seminar on pb-cam
TRANSCRIPT
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A LOW-POWER
PRECOMPUTATION BASEDCAM
ANSHUL VYAS
11EC62R02
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Overview
Introduction
Precomputation-Based CAM (PB-CAM)
Parameter extractor
PB-CAM Word Circuit
Parameter comparison
Ones Count Approach
Block-XOR Approach
Experimental Results
Future Scope Conclusion
References
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Introduction
Large number ofComparisons
Consumes most of CAMPower
Reducing Comparisonsto reduce power
Courtesy: Wai-Kai Chen, The VLSI Handbook, chap. 56,Content Addressable Memory.
Functional Block Diagram of CAM
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Architecture of PB-CAM
To reduce comparisonoperations betweeninput and stored data
Parameter Extractor,
Parameter memoryadded
For m words by n bits CAM,
Parallel CAM : m*n
PB-CAM:1st comparison: m*[log(n+2)]
2nd comparison: m*n/n+1
Total: m*{[log(n+2)]+1}
Courtesy: C.S. Lin, J.C. Chang, and B.D. Liu, A low-power Precomputation-based fully parallel content-addressable memory, IEEE J. Solid-State Circuits, vol. 38, no. 4, pp.654662, Apr. 2003.
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Ones Count PB-CAM
Courtesy: K. Pagiamtzis and A. Sheikholeslami, Content-addressable memory (CAM) circuits andarchitectures: A tutorial and survey,IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 712727, Mar. 2006.
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Ones count Parameter Extractor
Courtesy: C.S. Lin, J.C. Chang, and B.D. Liu, A low-power Precomputation-based fully parallelcontent-addressable memory, IEEE J. Solid-State Circuits, vol. 38, no. 4, pp.654662, Apr. 2003.
Block diagram Circuit design
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Traditional Dynamic CAM Word Circuit
Extra precharge time foreach data searchingoperation
Charge Sharing and NoiseProblems
Clock signal is necessaryfor the operation
Courtesy: C.S. Lin, J.C. Chang, and B.D. Liu, A low-power Precomputation-based fully parallel content-addressable memory, IEEE J. Solid-State Circuits, vol. 38, no. 4, pp.654662, Apr. 2003.
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Proposed Pseudo-nMOS CAM word circuit
V=1(Invalid Data)pM1 OFF and nM1 ONDataMatch = 0
V=0(Valid Data)
pM1 ON and nM1 OFFDataMatch signaldepends upon thecomparison results ofCAM cells
Disadvantage Static Power Dissipation m-1 words mismatch
and thus static powerdissipation is very high
Courtesy: C.S. Lin, J.C. Chang, and B.D. Liu, A low-power Precomputation-based fully parallelcontent-addressable memory, IEEE J. Solid-State Circuits, vol. 38, no. 4, pp.654662, Apr. 2003.
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Based on PB-CAM Architecture
Parameter comparisoncircuit used to controlpull-up pM1
Average number of
parameter match:m/(n+1)
Static power dissipationfor [m/(n+1)]-1
Courtesy: C.S. Lin, J.C. Chang, and B.D. Liu, A low-power Precomputation-based fully parallelcontent-addressable memory, IEEE J. Solid-State Circuits, vol. 38, no. 4, pp.654662, Apr. 2003.
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Traditional 9-T CAM Cell
6-T SRAM to store data
PTL-type XOR gate forcomparison
Courtesy: C.S. Lin, J.C. Chang, and B.D. Liu, A low-power Precomputation-based fully parallelcontent-addressable memory, IEEE J. Solid-State Circuits, vol. 38, no. 4, pp.654662, Apr. 2003.
FloatingZero(Mismatch)
BLi Qi CAMCell
0 0 Floating
0 1 0
1 0 0
1 1 Floating
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Proposed 7-T CAM Cell
Advantages
1. Searching time faster
2. Simplifies HardwareDesign
3. Reduces OperatingVoltage
Courtesy: C.S. Lin, J.C. Chang, and B.D. Liu, A low-power Precomputation-based fully parallelcontent-addressable memory, IEEE J. Solid-State Circuits, vol. 38, no. 4, pp.654662, Apr. 2003.
BLi Qi CAM Cell PB-CAM
0 0 Floating Floating
0 1 0 Floating
1 0 0 0
1 1 Floating Floating
Floating
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PB-CAM Word Structure
Courtesy: C.S. Lin, J.C. Chang, and B.D. Liu, A low-power Precomputation-based fully parallelcontent-addressable memory, IEEE J. Solid-State Circuits, vol. 38, no. 4, pp.654662, Apr. 2003.
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Parameter Comparison Circuit
Working Operations
1. Parameter set
2. Parameter write
3. Parameter Compare
Courtesy: C.S. Lin, J.C. Chang, and B.D. Liu, A low-power Precomputation-based fully parallelcontent-addressable memory, IEEE J. Solid-State Circuits, vol. 38, no. 4, pp.654662, Apr. 2003.
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Ones CountApproach Analysis
Courtesy: Shanq-Jang Ruan, Low Power Design of Precomputation Based Content Addressable
MemoryIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 3,pp. 331-335, March 2008.
Average Probability= 14Cn/214
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Block-XOR Approach
Courtesy: Shanq-Jang Ruan, Low Power Design of Precomputation Based Content Addressable
MemoryIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 3,pp.331-335, March 2008.
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Block-XOR Approach Analysis
Courtesy: Shanq-Jang Ruan, Low Power Design of Precomputation Based Content Addressable
MemoryIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 3,pp. 331-335, March 2008.
8 * 8 * 8 * 2
1024+ 1024/8
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Experimental Results
Courtesy: Shanq-Jang Ruan, Low Power Design of Precomputation Based Content AddressableMemoryIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 3,pp. 331-335, March 2008.
Summary ofPB-CAM Chip
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Future Scope
Development of newer and better Parameter Functions
Architectural and circuit inventions to implement CAMs withRAM like densities
To look beyond SRAM and implement CAM using
MRAM
Nano-RAM using Carbon nanotubes
Memristor based technology
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Conclusion
PB-CAM
Low Power
Low Cost
Low Voltage
Static Pseudo nMOS Logic word structure
Block XOR Approach better than Ones Count
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References
Shanq-Jang Ruan, Low Power Design of PrecomputationBased Content Addressable MemoryIEEE Transactions onVery Large Scale Integration (VLSI) Systems, vol. 16, no.3,pp. 331-335, Mar. 2008.
C.S. Lin, J.C. Chang, and B.D. Liu,A low-powerPrecomputation-based fully parallel content-addressablememory,IEEE J. Solid-State Circuits, vol. 38, no. 4,pp.654662, Apr. 2003.
K. Pagiamtzis and A. Sheikholeslami, Content-addressablememory (CAM) circuits and architectures: A tutorial andsurvey,IEEE J. Solid-State Circuits, vol. 41, no. 3, pp.712727, Mar. 2006.
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H. Miyatake, M. Tanaka, and Y. Mori, A design for high-speed-low power CMOS fully parallel content-addressablememory macros, IEEE J. Solid-State Circuits, vol. 36, no.6, pp. 956968, Jun. 2001.
K. J. Schultz, F. Shafai, G. F. R. Gibson, A. G. Bluschke, andD. E. Somppi, Fully parallel 25 MHz, 2.5-Mb CAM, in IEEEInt. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers,1998, pp. 332333.
Wai-Kai Chen, The VLSI Handbook, chap. 56,ContentAddressable Memory.
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BACKUP SLIDES
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NAND Gate Implementation
Static CMOS Logic Dynamic CMOS Logic
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Charge sharing
Qinit = CL * Vdd
When nmos with input A turns ON,
Qinit = Qfinal = CL * Vfinal + C1 * Vfinal
Vfinal = [CL/(CL+C1) ] * Vdd
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6T SRAM Cell
6T SRAM Cell Used in most commercial chips
Data stored in cross-coupled inverters
Read: Precharge bit, bit_b
Raise wordline
Write:
Drive data onto bit, bit_b Raise wordline
bit bit_b
word
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Static Logic vs. Pseudo-nMOS
Static Logic includes pull-up and pull-down networks - 2n transistors for n-input
function.
Pseudo-nMOS - n+1 transistors for n-input function
Requires pull-up transistor be weaker than pull-down network (5:1)
May eliminate p-transistors & possibly long pull-up chains
Static power dissipation
weak
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Advantages & Disadvantage
The big advantages of dynamic cmos type of logic is thatthe inputs are connected only to NMOS transistors so thatthe input load capacitance is much smaller. Therefore,dynamic logic is faster than static CMOS. Furthermore, forcomplex functions the transistor count is almost halved.
The big disadvantages of this type of logic is the need forrepeated charging and discharging even when the inputs donot change their state. Therefore, dynamic logic consumesmore power than static CMOS despite the lower transistorcount.
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Comparison of Parameter Extractors
Courtesy: Shanq-Jang Ruan, Low Power Design of Precomputation Based Content AddressableMemoryIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 3,pp.
331-335, March 2008.
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