Sept. 27,1966 C. G. BELLMULTISTABLE CIRCUITFiled Sept. 19, 196s

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United States Patent Office p_tiw~~~5f!.

8.P76.8484

hot krminak rod an ontwt termid wbcm <a)

5(2) developing a fourth-kvcl signal at its output

terminal wbcn a second-kvel sigual is prewntat at kast ooc of its input terminal

(a) when Mid Ant-kvel and third-kvcl sig-nak may be the sama and when said se&ond-kwt and fourth-level signals may be

(B) (n+l)?zm numbered in said o&wJ ~ICC-qucnce and each having 8a input terminal and anoutput tcrmirU&

(I ) each iawxkr havi~ a traushtor(a)tbebaYcofwhkhiac4xUMsdtotbc

invcrtcrinputtcmG4alEad(b) the colkctor of which b anmeckd to

the invertcr output ermina&(2) said traGstw in eadt innr~ being arrang d

(a) to ban a rchtiwly b colltior-emit-hrrc&tawzrt-~itrec&cssaidfourtb-kvctsignaiatitsbmeand

(b) to have a r;atin;y small colkctacmit-tertrwtxaitrcaivusailithird-kvelsignalmitrbae

6(3) developing said first-kvel rignal at ita out-

put terminal when one or more second-kwl sig-nab are applied to its input terminals, and

(4) having its output terminal connected to an5 input termhal of each of tb other logic cir-

cuiI*.(B) wwcc meam having a p&&y of output lines

C3CllOtWlliCb&- t o 8 If&rent One o fsaid multistabk ciraCt output terminals, and

10 (C) output neam ba* 8 plunlity of input Enc¶each of wtlii is oolllltcbcd .tO 8 difkfU&t OIX O fsaidmultistabkciradoutptte~ . .

(D)sot&twbennidsourcemca~coPdmocr,outputlinetbazfromtohars~ esoad&wl T*

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zs (B) Poauca said m si$lmlr&ntbetraD-rktcaOft&ioWftC?tbCfChiSiZl8CUOd~strk.

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Sept. 27,1966 C. G. BELLMULTISTABLE CIRCUITFiled Sept. 19. 1963

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United States Patent Office Patenti hp:ii5tsP

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descrii8bovc. Azmovoltpuluuaoyoftlmter-miws2&2dwilltkaruultiatlm--3voltkvelattba

8,976,8485

(2) developing a fourth-kvel signal at ita outputterminal when a secondkvel rignd is pmntat at kaat one of it:, input terminat

(a) where aaid Ant-kvet and third-kvel sig-nala may be the same and where said xc- 6ond-kvel and fourth-kvel signals may betbesaw.

(B) (n+l) inverten numbered in said ordered X-quence and each haCng an input terminal and anoutput terminal, 10

(1) each inverter having a tnnsistor(P)tbebWeofwhi&iaconnecWtotbe

iaverter input terminal nndfb) the colkctcr of which is conne&d to. &einvertero4rQuttermin4 16

(2) said tnmirtQ in each invertet being anxng d

6(3) developing said first-kvel rianal at its out-

put terminal when one or morc”&ond-keel sig-nab are applied to its inwt terminals. and

(4) having iU output ter&nsl amne&d to aninput termM of each of tba otbm lo& cir-cuit*.

(B) source means having a plurality of output lineseach of which is ColwEtcd tordi!Ymtoneofsaid rnultistabk circuit m terminab. and