sequential circuits · output values, depending on its previous state. * in other words, a...
TRANSCRIPT
Sequential circuits
* The digital circuits we have seen so far (gates, multiplexer, demultiplexer, encoders,decoders) are combinatorial in nature, i.e., the output(s) depends only on thepresent values of the inputs and not on their past values.
* In sequential circuits, the “state” of the circuit is crucial in determining the outputvalues. For a given input combination, a sequential circuit may produce differentoutput values, depending on its previous state.
* In other words, a sequential circuit has a memory (of its past state) whereas acombinatorial circuit has no memory.
* Sequential circuits (together with combinatorial circuits) make it possible to buildseveral useful applications, such as counters, registers, arithmetic/logic unit (ALU),all the way to microprocessors.
M. B. Patil, IIT Bombay
Sequential circuits
* The digital circuits we have seen so far (gates, multiplexer, demultiplexer, encoders,decoders) are combinatorial in nature, i.e., the output(s) depends only on thepresent values of the inputs and not on their past values.
* In sequential circuits, the “state” of the circuit is crucial in determining the outputvalues. For a given input combination, a sequential circuit may produce differentoutput values, depending on its previous state.
* In other words, a sequential circuit has a memory (of its past state) whereas acombinatorial circuit has no memory.
* Sequential circuits (together with combinatorial circuits) make it possible to buildseveral useful applications, such as counters, registers, arithmetic/logic unit (ALU),all the way to microprocessors.
M. B. Patil, IIT Bombay
Sequential circuits
* The digital circuits we have seen so far (gates, multiplexer, demultiplexer, encoders,decoders) are combinatorial in nature, i.e., the output(s) depends only on thepresent values of the inputs and not on their past values.
* In sequential circuits, the “state” of the circuit is crucial in determining the outputvalues. For a given input combination, a sequential circuit may produce differentoutput values, depending on its previous state.
* In other words, a sequential circuit has a memory (of its past state) whereas acombinatorial circuit has no memory.
* Sequential circuits (together with combinatorial circuits) make it possible to buildseveral useful applications, such as counters, registers, arithmetic/logic unit (ALU),all the way to microprocessors.
M. B. Patil, IIT Bombay
Sequential circuits
* The digital circuits we have seen so far (gates, multiplexer, demultiplexer, encoders,decoders) are combinatorial in nature, i.e., the output(s) depends only on thepresent values of the inputs and not on their past values.
* In sequential circuits, the “state” of the circuit is crucial in determining the outputvalues. For a given input combination, a sequential circuit may produce differentoutput values, depending on its previous state.
* In other words, a sequential circuit has a memory (of its past state) whereas acombinatorial circuit has no memory.
* Sequential circuits (together with combinatorial circuits) make it possible to buildseveral useful applications, such as counters, registers, arithmetic/logic unit (ALU),all the way to microprocessors.
M. B. Patil, IIT Bombay
Sequential circuits
* The digital circuits we have seen so far (gates, multiplexer, demultiplexer, encoders,decoders) are combinatorial in nature, i.e., the output(s) depends only on thepresent values of the inputs and not on their past values.
* In sequential circuits, the “state” of the circuit is crucial in determining the outputvalues. For a given input combination, a sequential circuit may produce differentoutput values, depending on its previous state.
* In other words, a sequential circuit has a memory (of its past state) whereas acombinatorial circuit has no memory.
* Sequential circuits (together with combinatorial circuits) make it possible to buildseveral useful applications, such as counters, registers, arithmetic/logic unit (ALU),all the way to microprocessors.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
01
0
10
0
10
1
1 0
1
1X1
X2
previous
0
01 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.
B = 0 ⇒ X2 = 1 ⇒ X1 =AX2 = 1 · 1 = 0.Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
0
1
0
10
0
10
1
1 0
1
1X1
X2
previous
0
01 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.
B = 0 ⇒ X2 = 1 ⇒ X1 =AX2 = 1 · 1 = 0.Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
0
1
0
10
0
10
1
1 0
1
1X1
X2
previous
0
01 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.B = 0 ⇒ X2 = 1
⇒ X1 =AX2 = 1 · 1 = 0.Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
01
0
10
0
10
1
1 0
1
1X1
X2
previous
0
01 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.B = 0 ⇒ X2 = 1
⇒ X1 =AX2 = 1 · 1 = 0.Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
01
0
10
0
10
1
1 0
1
1X1
X2
previous
0
01 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.B = 0 ⇒ X2 = 1 ⇒ X1 =AX2 = 1 · 1 = 0.
Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
01
0
10
0
10
1
1 0
1
1X1
X2
previous
0
01 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.B = 0 ⇒ X2 = 1 ⇒ X1 =AX2 = 1 · 1 = 0.
Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
01
0
10
0
10
1
1 0
1
1X1
X2
previous
0
01 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.B = 0 ⇒ X2 = 1 ⇒ X1 =AX2 = 1 · 1 = 0.Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
01
0
10
0
1
0
1
1 0
1
1X1
X2
previous
0
01 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.B = 0 ⇒ X2 = 1 ⇒ X1 =AX2 = 1 · 1 = 0.Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.
→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
01
0
10
0
10
1
1 0
1
1X1
X2
previous
0
01 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.B = 0 ⇒ X2 = 1 ⇒ X1 =AX2 = 1 · 1 = 0.Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
01
0
10
0
10
1
1 0
1
1
X1
X2
previous
0
01 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.B = 0 ⇒ X2 = 1 ⇒ X1 =AX2 = 1 · 1 = 0.Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
01
0
10
0
10
1
1 0
1
1
X1
X2
previous
0
01 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.B = 0 ⇒ X2 = 1 ⇒ X1 =AX2 = 1 · 1 = 0.Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
01
0
10
0
10
1
1 0
1
1X1
X2
previous
0
01 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.B = 0 ⇒ X2 = 1 ⇒ X1 =AX2 = 1 · 1 = 0.Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
01
0
10
0
10
1
1 0
1
1X1
X2
previous
0
01 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.B = 0 ⇒ X2 = 1 ⇒ X1 =AX2 = 1 · 1 = 0.Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.
Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
01
0
10
0
10
1
1 0
1
1X1
X2
previous
0
01 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.B = 0 ⇒ X2 = 1 ⇒ X1 =AX2 = 1 · 1 = 0.Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.
The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
01
0
10
0
10
1
1 0
1
1X1
X2
previous
0
01 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.B = 0 ⇒ X2 = 1 ⇒ X1 =AX2 = 1 · 1 = 0.Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
01
0
10
0
10
1
1 0
1
1X1
X2
previous
0
0
1 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.B = 0 ⇒ X2 = 1 ⇒ X1 =AX2 = 1 · 1 = 0.Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
X1
X2
1
01
0
10
0
10
1
1 0
1
1X1
X2
previous
0
01 1
* A, B: inputs, X1, X2: outputs
* Consider A= 1, B = 0.B = 0 ⇒ X2 = 1 ⇒ X1 =AX2 = 1 · 1 = 0.Overall, we have X1 = 0, X2 = 1.
* Consider A= 0, B = 1.→ X1 = 1, X2 = 0.
* Consider A=B = 1.
X1 =AX2 =X2, X2 =B X1 =X1 ⇒ X1 =X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.The circuit has “latched in” the previous state.
* For A=B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that willbecome clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
X1
X2
R
S
R S QQ
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
* The combination A= 1, B = 0 serves to reset X1 to 0 (irrespective of the previous state of the latch).
* The combination A= 0, B = 1 serves to set X1 to 1 (irrespective of the previous state of the latch).
* In other words,A= 1, B = 0 → latch gets reset to 0.A= 0, B = 1 → latch gets set to 1.
* The A input is therefore called the RESET (R) input, and B is called the SET (S) input of the latch.
* X1 is denoted by Q, and X2 (which is X1 in all cases except for A=B = 0) is denoted by Q.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
X1
X2
R
S
R S QQ
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
* The combination A= 1, B = 0 serves to reset X1 to 0 (irrespective of the previous state of the latch).
* The combination A= 0, B = 1 serves to set X1 to 1 (irrespective of the previous state of the latch).
* In other words,A= 1, B = 0 → latch gets reset to 0.A= 0, B = 1 → latch gets set to 1.
* The A input is therefore called the RESET (R) input, and B is called the SET (S) input of the latch.
* X1 is denoted by Q, and X2 (which is X1 in all cases except for A=B = 0) is denoted by Q.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
X1
X2
R
S
R S QQ
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
* The combination A= 1, B = 0 serves to reset X1 to 0 (irrespective of the previous state of the latch).
* The combination A= 0, B = 1 serves to set X1 to 1 (irrespective of the previous state of the latch).
* In other words,A= 1, B = 0 → latch gets reset to 0.A= 0, B = 1 → latch gets set to 1.
* The A input is therefore called the RESET (R) input, and B is called the SET (S) input of the latch.
* X1 is denoted by Q, and X2 (which is X1 in all cases except for A=B = 0) is denoted by Q.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
X1
X2
R
S
R S QQ
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
* The combination A= 1, B = 0 serves to reset X1 to 0 (irrespective of the previous state of the latch).
* The combination A= 0, B = 1 serves to set X1 to 1 (irrespective of the previous state of the latch).
* In other words,A= 1, B = 0 → latch gets reset to 0.A= 0, B = 1 → latch gets set to 1.
* The A input is therefore called the RESET (R) input, and B is called the SET (S) input of the latch.
* X1 is denoted by Q, and X2 (which is X1 in all cases except for A=B = 0) is denoted by Q.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
X1
X2
R
S
R S QQ
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
* The combination A= 1, B = 0 serves to reset X1 to 0 (irrespective of the previous state of the latch).
* The combination A= 0, B = 1 serves to set X1 to 1 (irrespective of the previous state of the latch).
* In other words,A= 1, B = 0 → latch gets reset to 0.A= 0, B = 1 → latch gets set to 1.
* The A input is therefore called the RESET (R) input, and B is called the SET (S) input of the latch.
* X1 is denoted by Q, and X2 (which is X1 in all cases except for A=B = 0) is denoted by Q.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
X1
X2
R
S
R S QQ
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
* The combination A= 1, B = 0 serves to reset X1 to 0 (irrespective of the previous state of the latch).
* The combination A= 0, B = 1 serves to set X1 to 1 (irrespective of the previous state of the latch).
* In other words,A= 1, B = 0 → latch gets reset to 0.A= 0, B = 1 → latch gets set to 1.
* The A input is therefore called the RESET (R) input, and B is called the SET (S) input of the latch.
* X1 is denoted by Q, and X2 (which is X1 in all cases except for A=B = 0) is denoted by Q.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A
B
A B X2X1
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
X1
X2
R
S
R S QQ
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
* The combination A= 1, B = 0 serves to reset X1 to 0 (irrespective of the previous state of the latch).
* The combination A= 0, B = 1 serves to set X1 to 1 (irrespective of the previous state of the latch).
* In other words,A= 1, B = 0 → latch gets reset to 0.A= 0, B = 1 → latch gets set to 1.
* The A input is therefore called the RESET (R) input, and B is called the SET (S) input of the latch.
* X1 is denoted by Q, and X2 (which is X1 in all cases except for A=B = 0) is denoted by Q.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
R
S
t
t
t
t
R S
t1 t2
Q
t3
Q
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
R
S
Q
Q
* Up to t = t1, R = 0, S = 1 → Q = 1.
* At t = t1, R goes high → R = S = 1, and the latch holds its previous state→ no change at the output.
* At t = t2, S goes low → R = 1, S = 0 → Q = 0.
* At t = t3, S goes high → R = S = 1, and the latch holds its previous state→ no change at the output.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
R
S
t
t
t
t
R S
t1 t2
Q
t3
Q
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
R
S
Q
Q
* Up to t = t1, R = 0, S = 1 → Q = 1.
* At t = t1, R goes high → R = S = 1, and the latch holds its previous state→ no change at the output.
* At t = t2, S goes low → R = 1, S = 0 → Q = 0.
* At t = t3, S goes high → R = S = 1, and the latch holds its previous state→ no change at the output.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
R
S
t
t
t
t
R S
t1 t2
Q
t3
Q
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
R
S
Q
Q
* Up to t = t1, R = 0, S = 1 → Q = 1.
* At t = t1, R goes high → R = S = 1, and the latch holds its previous state→ no change at the output.
* At t = t2, S goes low → R = 1, S = 0 → Q = 0.
* At t = t3, S goes high → R = S = 1, and the latch holds its previous state→ no change at the output.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
R
S
t
t
t
t
R S
t1 t2
Q
t3
Q
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
R
S
Q
Q
* Up to t = t1, R = 0, S = 1 → Q = 1.
* At t = t1, R goes high → R = S = 1, and the latch holds its previous state→ no change at the output.
* At t = t2, S goes low → R = 1, S = 0 → Q = 0.
* At t = t3, S goes high → R = S = 1, and the latch holds its previous state→ no change at the output.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
R
S
t
t
t
t
R S
t1 t2
Q
t3
Q
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
R
S
Q
Q
* Up to t = t1, R = 0, S = 1 → Q = 1.
* At t = t1, R goes high → R = S = 1, and the latch holds its previous state→ no change at the output.
* At t = t2, S goes low → R = 1, S = 0 → Q = 0.
* At t = t3, S goes high → R = S = 1, and the latch holds its previous state→ no change at the output.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
R
S
t
t
t
t
R S
t3t2
Q
t1
QR
S1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
Q
Q
t4 t5
?
?
Why not allow R = S = 0?
- It makes Q =Q = 1, i.e., Q and Q are not inverse of each other any more.
- More importantly, when R and S both become 1 simultaneously (starting from R =S = 0), the finaloutputs Q and Q cannot be uniquely determined. We could have Q = 0, Q = 1 or Q = 1, Q = 0,depending on the delays associated with the two NAND gates.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
R
S
t
t
t
t
R S
t3t2
Q
t1
QR
S1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
Q
Q
t4 t5
?
?
Why not allow R = S = 0?
- It makes Q =Q = 1, i.e., Q and Q are not inverse of each other any more.
- More importantly, when R and S both become 1 simultaneously (starting from R =S = 0), the finaloutputs Q and Q cannot be uniquely determined. We could have Q = 0, Q = 1 or Q = 1, Q = 0,depending on the delays associated with the two NAND gates.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
R
S
t
t
t
t
R S
t3t2
Q
t1
QR
S1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
Q
Q
t4 t5
?
?
Why not allow R = S = 0?
- It makes Q =Q = 1, i.e., Q and Q are not inverse of each other any more.
- More importantly, when R and S both become 1 simultaneously (starting from R =S = 0), the finaloutputs Q and Q cannot be uniquely determined. We could have Q = 0, Q = 1 or Q = 1, Q = 0,depending on the delays associated with the two NAND gates.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
R
S
t
t
t
t
R S
t3t2
Q
t1
QR
S1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
Q
Q
t4 t5
?
?
Why not allow R = S = 0?
- It makes Q =Q = 1, i.e., Q and Q are not inverse of each other any more.
- More importantly, when R and S both become 1 simultaneously (starting from R = S = 0), the finaloutputs Q and Q cannot be uniquely determined. We could have Q = 0, Q = 1 or Q = 1, Q = 0,depending on the delays associated with the two NAND gates.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
R
S
t
t
t
t
R S
t3t2
Q
t1
QR
S1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
Q
Q
t4
t5
?
?
Why not allow R = S = 0?
- It makes Q =Q = 1, i.e., Q and Q are not inverse of each other any more.
- More importantly, when R and S both become 1 simultaneously (starting from R = S = 0), the finaloutputs Q and Q cannot be uniquely determined. We could have Q = 0, Q = 1 or Q = 1, Q = 0,depending on the delays associated with the two NAND gates.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
R
S
t
t
t
t
R S
t3t2
Q
t1
QR
S1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
Q
Q
t4
t5
?
?
Why not allow R = S = 0?
- It makes Q =Q = 1, i.e., Q and Q are not inverse of each other any more.
- More importantly, when R and S both become 1 simultaneously (starting from R = S = 0), the finaloutputs Q and Q cannot be uniquely determined. We could have Q = 0, Q = 1 or Q = 1, Q = 0,depending on the delays associated with the two NAND gates.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
R
S
t
t
t
t
R S
t3t2
Q
t1
QR
S1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
Q
Q
t4 t5
?
?
Why not allow R = S = 0?
- It makes Q =Q = 1, i.e., Q and Q are not inverse of each other any more.
- More importantly, when R and S both become 1 simultaneously (starting from R = S = 0), the finaloutputs Q and Q cannot be uniquely determined. We could have Q = 0, Q = 1 or Q = 1, Q = 0,depending on the delays associated with the two NAND gates.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
R
S
t
t
t
t
R S
t3t2
Q
t1
QR
S1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
Q
Q
t4 t5
?
?
Why not allow R = S = 0?
- It makes Q =Q = 1, i.e., Q and Q are not inverse of each other any more.
- More importantly, when R and S both become 1 simultaneously (starting from R = S = 0), the finaloutputs Q and Q cannot be uniquely determined. We could have Q = 0, Q = 1 or Q = 1, Q = 0,depending on the delays associated with the two NAND gates.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
R
S
t
t
t
t
R S
t3t2
Q
t1
QR
S1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
Q
Q
t4 t5
?
?
Why not allow R = S = 0?
- It makes Q =Q = 1, i.e., Q and Q are not inverse of each other any more.
- More importantly, when R and S both become 1 simultaneously (starting from R = S = 0), the finaloutputs Q and Q cannot be uniquely determined. We could have Q = 0, Q = 1 or Q = 1, Q = 0,depending on the delays associated with the two NAND gates.
M. B. Patil, IIT Bombay
NOR latch (RS latch)
R
S
R S QQ
1
1
0 0
0
0
1 1
1
1 0
0
previous
invalid
Q
Q
* The NOR latch is similar to the NAND latch:When R = 1, S = 0, the latch gets reset to Q = 0.When R = 0, S = 1, the latch gets set to Q = 1.
* For R = S = 0, the latch retains its previous state (i.e., the previous values of Q and Q).
* R = S = 1 is not allowed for reasons similar to those discussed in the context of the NAND latch.
M. B. Patil, IIT Bombay
NOR latch (RS latch)
R
S
R S QQ
1
1
0 0
0
0
1 1
1
1 0
0
previous
invalid
Q
Q
* The NOR latch is similar to the NAND latch:When R = 1, S = 0, the latch gets reset to Q = 0.When R = 0, S = 1, the latch gets set to Q = 1.
* For R = S = 0, the latch retains its previous state (i.e., the previous values of Q and Q).
* R = S = 1 is not allowed for reasons similar to those discussed in the context of the NAND latch.
M. B. Patil, IIT Bombay
NOR latch (RS latch)
R
S
R S QQ
1
1
0 0
0
0
1 1
1
1 0
0
previous
invalid
Q
Q
* The NOR latch is similar to the NAND latch:When R = 1, S = 0, the latch gets reset to Q = 0.When R = 0, S = 1, the latch gets set to Q = 1.
* For R = S = 0, the latch retains its previous state (i.e., the previous values of Q and Q).
* R = S = 1 is not allowed for reasons similar to those discussed in the context of the NAND latch.
M. B. Patil, IIT Bombay
NOR latch (RS latch)
R
S
R S QQ
1
1
0 0
0
0
1 1
1
1 0
0
previous
invalid
Q
Q
* The NOR latch is similar to the NAND latch:When R = 1, S = 0, the latch gets reset to Q = 0.When R = 0, S = 1, the latch gets set to Q = 1.
* For R = S = 0, the latch retains its previous state (i.e., the previous values of Q and Q).
* R = S = 1 is not allowed for reasons similar to those discussed in the context of the NAND latch.
M. B. Patil, IIT Bombay
Comparison of NAND and NOR latches
R
S
R
S
R S
R S
Q
Q
Q
Q
1
1
0 0
0
0
1 1
1
1 0
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
0
previous
invalid
Q
Q
Q
Q
M. B. Patil, IIT Bombay
NAND latch: alternative node names
R
S
R S QQ
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
QQRSS
R
1
1
1 1
0
0
0 0
1
1 0
Active low input nodes:
0
previous
invalid
Q
Q
M. B. Patil, IIT Bombay
NAND latch: alternative node names
R
S
R S QQ
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
Q
Q
QQRSS
R
1
1
1 1
0
0
0 0
1
1 0
Active low input nodes:
0
previous
invalid
Q
Q
M. B. Patil, IIT Bombay
Chatter (bouncing) due to a mechanical switch
B
A
Vs VoR
expectedt
Vo
Vs
actualt
Vs
Vo
* When the switch is thrown from A to B, Vo is expected to go from 0V to Vs (say, 5V ).
* However, mechanical switches suffer from “chatter” or “bouncing,” i.e., the transition from A to B is not asingle, clean one. As a result, Vo oscillates between 0V and 5V before settling to its final value (5V ).
* In some applications, this chatter can cause malfunction → need a way to remove the chatter.
M. B. Patil, IIT Bombay
Chatter (bouncing) due to a mechanical switch
B
A
Vs VoR
expectedt
Vo
Vs
actualt
Vs
Vo
* When the switch is thrown from A to B, Vo is expected to go from 0V to Vs (say, 5V ).
* However, mechanical switches suffer from “chatter” or “bouncing,” i.e., the transition from A to B is not asingle, clean one. As a result, Vo oscillates between 0V and 5V before settling to its final value (5V ).
* In some applications, this chatter can cause malfunction → need a way to remove the chatter.
M. B. Patil, IIT Bombay
Chatter (bouncing) due to a mechanical switch
B
A
Vs VoR
expectedt
Vo
Vs
actualt
Vs
Vo
* When the switch is thrown from A to B, Vo is expected to go from 0V to Vs (say, 5V ).
* However, mechanical switches suffer from “chatter” or “bouncing,” i.e., the transition from A to B is not asingle, clean one. As a result, Vo oscillates between 0V and 5V before settling to its final value (5V ).
* In some applications, this chatter can cause malfunction → need a way to remove the chatter.
M. B. Patil, IIT Bombay
Chatter (bouncing) due to a mechanical switch
B
A
Vs VoR
expectedt
Vo
Vs
actualt
Vs
Vo
* When the switch is thrown from A to B, Vo is expected to go from 0V to Vs (say, 5V ).
* However, mechanical switches suffer from “chatter” or “bouncing,” i.e., the transition from A to B is not asingle, clean one. As a result, Vo oscillates between 0V and 5V before settling to its final value (5V ).
* In some applications, this chatter can cause malfunction → need a way to remove the chatter.
M. B. Patil, IIT Bombay
Chatter (bouncing) due to a mechanical switch
B
A
Vs VoR
expectedt
Vo
Vs
actualt
Vs
Vo
* When the switch is thrown from A to B, Vo is expected to go from 0V to Vs (say, 5V ).
* However, mechanical switches suffer from “chatter” or “bouncing,” i.e., the transition from A to B is not asingle, clean one. As a result, Vo oscillates between 0V and 5V before settling to its final value (5V ).
* In some applications, this chatter can cause malfunction → need a way to remove the chatter.
M. B. Patil, IIT Bombay
Chatter (bouncing) due to a mechanical switch
B
A
Vs VoR
expectedt
Vo
Vs
actualt
Vs
Vo
* When the switch is thrown from A to B, Vo is expected to go from 0V to Vs (say, 5V ).
* However, mechanical switches suffer from “chatter” or “bouncing,” i.e., the transition from A to B is not asingle, clean one. As a result, Vo oscillates between 0V and 5V before settling to its final value (5V ).
* In some applications, this chatter can cause malfunction → need a way to remove the chatter.
M. B. Patil, IIT Bombay
Chatter (bouncing) due to a mechanical switch
R St
t
t
A
B
S
R
5V
5V
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
R
S
Q
Q
* Because of the chatter, the S and R inputs may have multiple transitions when the switch is thrown fromA to B.
* However, for S =R = 1, the previous value of Q is retained, causing a single transition in Q, as desired.
M. B. Patil, IIT Bombay
Chatter (bouncing) due to a mechanical switch
R St
t
t
A
B
S
R
5V
5V
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
R
S
Q
Q
* Because of the chatter, the S and R inputs may have multiple transitions when the switch is thrown fromA to B.
* However, for S =R = 1, the previous value of Q is retained, causing a single transition in Q, as desired.
M. B. Patil, IIT Bombay
Chatter (bouncing) due to a mechanical switch
R St
t
t
A
B
S
R
5V
5V
1
1
1 1
0
0
0 0
1
1 0
0
previous
invalid
R
S
Q
Q
* Because of the chatter, the S and R inputs may have multiple transitions when the switch is thrown fromA to B.
* However, for S =R = 1, the previous value of Q is retained, causing a single transition in Q, as desired.
M. B. Patil, IIT Bombay
The “clock”
* Complex digital circuits are generally designed for synchronous operation, i.e., transitions in the varioussignals are synchronised with the clock.
* Synchronous circuits are easier to design and troubleshoot because the voltages at the nodes (both outputnodes and internal nodes) can change only at specific times.
* A clock is a periodic signal, with a positive-going transition and a negative-going transition.
positive edge negative edge
T
1
t0
* The clock frequency determines the overall speed of the circuit. For example, a processor that operateswith a 1 GHz clock is 10 times faster than one that operates with a 100 MHz clock.
Intel 80286 (IBM PC-AT): 6 MHzModern CPU chips: 2 to 3 GHz.
M. B. Patil, IIT Bombay
The “clock”
* Complex digital circuits are generally designed for synchronous operation, i.e., transitions in the varioussignals are synchronised with the clock.
* Synchronous circuits are easier to design and troubleshoot because the voltages at the nodes (both outputnodes and internal nodes) can change only at specific times.
* A clock is a periodic signal, with a positive-going transition and a negative-going transition.
positive edge negative edge
T
1
t0
* The clock frequency determines the overall speed of the circuit. For example, a processor that operateswith a 1 GHz clock is 10 times faster than one that operates with a 100 MHz clock.
Intel 80286 (IBM PC-AT): 6 MHzModern CPU chips: 2 to 3 GHz.
M. B. Patil, IIT Bombay
The “clock”
* Complex digital circuits are generally designed for synchronous operation, i.e., transitions in the varioussignals are synchronised with the clock.
* Synchronous circuits are easier to design and troubleshoot because the voltages at the nodes (both outputnodes and internal nodes) can change only at specific times.
* A clock is a periodic signal, with a positive-going transition and a negative-going transition.
positive edge negative edge
T
1
t0
* The clock frequency determines the overall speed of the circuit. For example, a processor that operateswith a 1 GHz clock is 10 times faster than one that operates with a 100 MHz clock.
Intel 80286 (IBM PC-AT): 6 MHzModern CPU chips: 2 to 3 GHz.
M. B. Patil, IIT Bombay
The “clock”
* Complex digital circuits are generally designed for synchronous operation, i.e., transitions in the varioussignals are synchronised with the clock.
* Synchronous circuits are easier to design and troubleshoot because the voltages at the nodes (both outputnodes and internal nodes) can change only at specific times.
* A clock is a periodic signal, with a positive-going transition and a negative-going transition.
positive edge negative edge
T
1
t0
* The clock frequency determines the overall speed of the circuit. For example, a processor that operateswith a 1 GHz clock is 10 times faster than one that operates with a 100 MHz clock.
Intel 80286 (IBM PC-AT): 6 MHzModern CPU chips: 2 to 3 GHz.
M. B. Patil, IIT Bombay
The “clock”
* Complex digital circuits are generally designed for synchronous operation, i.e., transitions in the varioussignals are synchronised with the clock.
* Synchronous circuits are easier to design and troubleshoot because the voltages at the nodes (both outputnodes and internal nodes) can change only at specific times.
* A clock is a periodic signal, with a positive-going transition and a negative-going transition.
positive edge negative edge
T
1
t0
* The clock frequency determines the overall speed of the circuit. For example, a processor that operateswith a 1 GHz clock is 10 times faster than one that operates with a 100 MHz clock.
Intel 80286 (IBM PC-AT): 6 MHzModern CPU chips: 2 to 3 GHz.
M. B. Patil, IIT Bombay
Clocked RS latch
0 1
01
0 1
01
B
CLK R SA B
Clocked RS latch NAND RS latch
invalid
previous
previous
previous
invalid
A
B
S
CLK
R
A QQ
1
1
0
0
0 0
11
1
1
1
1
0 X X1
1
1 1
0
0
0 0Q
Q
Q
Q
* When clock is inactive (0), A=B = 1, and the latch holds the previous state.
* When clock is active (1), A=S , B =R. Using the truth table for the NAND RS latch (right), we canconstruct the truth table for the clocked RS latch.
* Note that the above table is sensitive to the level of the clock (i.e., whether CLK is 0 or 1).
M. B. Patil, IIT Bombay
Clocked RS latch
0 1
01
0 1
01
B
CLK R SA B
Clocked RS latch NAND RS latch
invalid
previous
previous
previous
invalid
A
B
S
CLK
R
A QQ
1
1
0
0
0 0
11
1
1
1
1
0 X X1
1
1 1
0
0
0 0Q
Q
Q
Q
* When clock is inactive (0), A=B = 1, and the latch holds the previous state.
* When clock is active (1), A=S , B =R. Using the truth table for the NAND RS latch (right), we canconstruct the truth table for the clocked RS latch.
* Note that the above table is sensitive to the level of the clock (i.e., whether CLK is 0 or 1).
M. B. Patil, IIT Bombay
Clocked RS latch
0 1
01
0 1
01
B
CLK R SA B
Clocked RS latch NAND RS latch
invalid
previous
previous
previous
invalid
A
B
S
CLK
R
A QQ
1
1
0
0
0 0
11
1
1
1
1
0 X X1
1
1 1
0
0
0 0Q
Q
Q
Q
* When clock is inactive (0), A=B = 1, and the latch holds the previous state.
* When clock is active (1), A= S , B =R. Using the truth table for the NAND RS latch (right), we canconstruct the truth table for the clocked RS latch.
* Note that the above table is sensitive to the level of the clock (i.e., whether CLK is 0 or 1).
M. B. Patil, IIT Bombay
Clocked RS latch
0 1
01
0 1
01
B
CLK R SA B
Clocked RS latch NAND RS latch
invalid
previous
previous
previous
invalid
A
B
S
CLK
R
A QQ
1
1
0
0
0 0
11
1
1
1
1
0 X X1
1
1 1
0
0
0 0Q
Q
Q
Q
* When clock is inactive (0), A=B = 1, and the latch holds the previous state.
* When clock is active (1), A= S , B =R. Using the truth table for the NAND RS latch (right), we canconstruct the truth table for the clocked RS latch.
* Note that the above table is sensitive to the level of the clock (i.e., whether CLK is 0 or 1).
M. B. Patil, IIT Bombay
Clocked RS latch
R
S
Q
0 1
01
CLK
B
CLK R S
invalid
previous
previous
S
CLK
R
A
0.4 0.6 0.8 0.20
time (msec)
1
1
0
0
0 0
11
1
1
1
1
0 X X
SEQUEL file: ee101 rs 1.sqproj
Q
Q
M. B. Patil, IIT Bombay
Edge-triggered flip-flops
* The clocked RS latch seen previously is level-sensitive, i.e., if the clock is active (CLK = 1), the flip-flopoutput is allowed to change, depending on the R and S inputs.
* In an edge-sensitive flip-flop, the output can change only at the active clock edge (i.e., CLK transitionfrom 0 to 1 or from 1 to 0).
* Edge-sensitive flip-flops are denoted by the following symbols:
R
CLK
S
R
CLK
S
negative edge−triggered flip−floppositive edge−triggered flip−flop
Q
Q
Q
Q
M. B. Patil, IIT Bombay
Edge-triggered flip-flops
* The clocked RS latch seen previously is level-sensitive, i.e., if the clock is active (CLK = 1), the flip-flopoutput is allowed to change, depending on the R and S inputs.
* In an edge-sensitive flip-flop, the output can change only at the active clock edge (i.e., CLK transitionfrom 0 to 1 or from 1 to 0).
* Edge-sensitive flip-flops are denoted by the following symbols:
R
CLK
S
R
CLK
S
negative edge−triggered flip−floppositive edge−triggered flip−flop
Q
Q
Q
Q
M. B. Patil, IIT Bombay
Edge-triggered flip-flops
* The clocked RS latch seen previously is level-sensitive, i.e., if the clock is active (CLK = 1), the flip-flopoutput is allowed to change, depending on the R and S inputs.
* In an edge-sensitive flip-flop, the output can change only at the active clock edge (i.e., CLK transitionfrom 0 to 1 or from 1 to 0).
* Edge-sensitive flip-flops are denoted by the following symbols:
R
CLK
S
R
CLK
S
negative edge−triggered flip−floppositive edge−triggered flip−flop
Q
Q
Q
Q
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
1
1
1 1
0
0
0 0Q
Q
Truth table for JK flip−flop
CLK J K
0 XX previous (Qn)
Q (Qn+1)
1 0 0 previous (Qn)
1 10 0
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q. In other words, nothinghappens as long as CLK = 0.
* When CLK = 1:
- J =K = 0 → R = S = 1, RS latch holds previous Q, i.e., Qn+1 =Qn, where n denotes the nth clockpulse (This notation will become clear shortly).
- J = 0, K = 1 → R = 1, S =Qn.
Case (i): Qn = 0 → S = 1 (i.e., R =S = 1) → Qn+1 =Qn = 0.
Case (ii): Qn = 1 → S = 0 (i.e., R = 1, S = 0) → Qn+1 = 0.
In either case, Qn+1 = 0 → For J = 0, K = 1, Qn+1 = 0.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
1
1
1 1
0
0
0 0Q
Q
Truth table for JK flip−flop
CLK J K
0 XX previous (Qn)
Q (Qn+1)
1 0 0 previous (Qn)
1 10 0
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q. In other words, nothinghappens as long as CLK = 0.
* When CLK = 1:
- J =K = 0 → R = S = 1, RS latch holds previous Q, i.e., Qn+1 =Qn, where n denotes the nth clockpulse (This notation will become clear shortly).
- J = 0, K = 1 → R = 1, S =Qn.
Case (i): Qn = 0 → S = 1 (i.e., R =S = 1) → Qn+1 =Qn = 0.
Case (ii): Qn = 1 → S = 0 (i.e., R = 1, S = 0) → Qn+1 = 0.
In either case, Qn+1 = 0 → For J = 0, K = 1, Qn+1 = 0.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
1
1
1 1
0
0
0 0Q
Q
Truth table for JK flip−flop
CLK J K
0 XX previous (Qn)
Q (Qn+1)
1 0 0 previous (Qn)
1 10 0
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q. In other words, nothinghappens as long as CLK = 0.
* When CLK = 1:
- J =K = 0 → R = S = 1, RS latch holds previous Q, i.e., Qn+1 =Qn, where n denotes the nth clockpulse (This notation will become clear shortly).
- J = 0, K = 1 → R = 1, S =Qn.
Case (i): Qn = 0 → S = 1 (i.e., R =S = 1) → Qn+1 =Qn = 0.
Case (ii): Qn = 1 → S = 0 (i.e., R = 1, S = 0) → Qn+1 = 0.
In either case, Qn+1 = 0 → For J = 0, K = 1, Qn+1 = 0.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
1
1
1 1
0
0
0 0Q
Q
Truth table for JK flip−flop
CLK J K
0 XX previous (Qn)
Q (Qn+1)
1 0 0 previous (Qn)
1 10 0
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q. In other words, nothinghappens as long as CLK = 0.
* When CLK = 1:
- J =K = 0 → R = S = 1, RS latch holds previous Q, i.e., Qn+1 =Qn, where n denotes the nth clockpulse (This notation will become clear shortly).
- J = 0, K = 1 → R = 1, S =Qn.
Case (i): Qn = 0 → S = 1 (i.e., R =S = 1) → Qn+1 =Qn = 0.
Case (ii): Qn = 1 → S = 0 (i.e., R = 1, S = 0) → Qn+1 = 0.
In either case, Qn+1 = 0 → For J = 0, K = 1, Qn+1 = 0.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
1
1
1 1
0
0
0 0Q
Q
Truth table for JK flip−flop
CLK J K
0 XX previous (Qn)
Q (Qn+1)
1 0 0 previous (Qn)
1 10 0
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q. In other words, nothinghappens as long as CLK = 0.
* When CLK = 1:
- J =K = 0 → R = S = 1, RS latch holds previous Q, i.e., Qn+1 =Qn, where n denotes the nth clockpulse (This notation will become clear shortly).
- J = 0, K = 1 → R = 1, S =Qn.
Case (i): Qn = 0 → S = 1 (i.e., R =S = 1) → Qn+1 =Qn = 0.
Case (ii): Qn = 1 → S = 0 (i.e., R = 1, S = 0) → Qn+1 = 0.
In either case, Qn+1 = 0 → For J = 0, K = 1, Qn+1 = 0.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
1
1
1 1
0
0
0 0Q
Q
Truth table for JK flip−flop
CLK J K
0 XX previous (Qn)
Q (Qn+1)
1 0 0 previous (Qn)
1 10 0
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q. In other words, nothinghappens as long as CLK = 0.
* When CLK = 1:
- J =K = 0 → R = S = 1, RS latch holds previous Q, i.e., Qn+1 =Qn, where n denotes the nth clockpulse (This notation will become clear shortly).
- J = 0, K = 1 → R = 1, S =Qn.
Case (i): Qn = 0 → S = 1 (i.e., R =S = 1) → Qn+1 =Qn = 0.
Case (ii): Qn = 1 → S = 0 (i.e., R = 1, S = 0) → Qn+1 = 0.
In either case, Qn+1 = 0 → For J = 0, K = 1, Qn+1 = 0.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
1
1
1 1
0
0
0 0Q
Q
Truth table for JK flip−flop
CLK J K
0 XX previous (Qn)
Q (Qn+1)
1 0 0 previous (Qn)
1 10 0
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q. In other words, nothinghappens as long as CLK = 0.
* When CLK = 1:
- J =K = 0 → R = S = 1, RS latch holds previous Q, i.e., Qn+1 =Qn, where n denotes the nth clockpulse (This notation will become clear shortly).
- J = 0, K = 1 → R = 1, S =Qn.
Case (i): Qn = 0 → S = 1 (i.e., R =S = 1) → Qn+1 =Qn = 0.
Case (ii): Qn = 1 → S = 0 (i.e., R = 1, S = 0) → Qn+1 = 0.
In either case, Qn+1 = 0 → For J = 0, K = 1, Qn+1 = 0.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
1
1
1 1
0
0
0 0Q
Q
Truth table for JK flip−flop
CLK J K
0 XX previous (Qn)
Q (Qn+1)
1 0 0 previous (Qn)
1 10 0
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q. In other words, nothinghappens as long as CLK = 0.
* When CLK = 1:
- J =K = 0 → R = S = 1, RS latch holds previous Q, i.e., Qn+1 =Qn, where n denotes the nth clockpulse (This notation will become clear shortly).
- J = 0, K = 1 → R = 1, S =Qn.
Case (i): Qn = 0 → S = 1 (i.e., R = S = 1) → Qn+1 =Qn = 0.
Case (ii): Qn = 1 → S = 0 (i.e., R = 1, S = 0) → Qn+1 = 0.
In either case, Qn+1 = 0 → For J = 0, K = 1, Qn+1 = 0.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
1
1
1 1
0
0
0 0Q
Q
Truth table for JK flip−flop
CLK J K
0 XX previous (Qn)
Q (Qn+1)
1 0 0 previous (Qn)
1 10 0
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q. In other words, nothinghappens as long as CLK = 0.
* When CLK = 1:
- J =K = 0 → R = S = 1, RS latch holds previous Q, i.e., Qn+1 =Qn, where n denotes the nth clockpulse (This notation will become clear shortly).
- J = 0, K = 1 → R = 1, S =Qn.
Case (i): Qn = 0 → S = 1 (i.e., R = S = 1) → Qn+1 =Qn = 0.
Case (ii): Qn = 1 → S = 0 (i.e., R = 1, S = 0) → Qn+1 = 0.
In either case, Qn+1 = 0 → For J = 0, K = 1, Qn+1 = 0.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
1
1
1 1
0
0
0 0Q
Q
Truth table for JK flip−flop
CLK J K
0 XX previous (Qn)
Q (Qn+1)
1 0 0 previous (Qn)
1 10 0
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q. In other words, nothinghappens as long as CLK = 0.
* When CLK = 1:
- J =K = 0 → R = S = 1, RS latch holds previous Q, i.e., Qn+1 =Qn, where n denotes the nth clockpulse (This notation will become clear shortly).
- J = 0, K = 1 → R = 1, S =Qn.
Case (i): Qn = 0 → S = 1 (i.e., R = S = 1) → Qn+1 =Qn = 0.
Case (ii): Qn = 1 → S = 0 (i.e., R = 1, S = 0) → Qn+1 = 0.
In either case, Qn+1 = 0 → For J = 0, K = 1, Qn+1 = 0.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
1
1
1 1
0
0
0 0Q
Q
Truth table for JK flip−flop
CLK J K
0 XX previous (Qn)
Q (Qn+1)
1 0 0 previous (Qn)
1 10 0
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q. In other words, nothinghappens as long as CLK = 0.
* When CLK = 1:
- J =K = 0 → R = S = 1, RS latch holds previous Q, i.e., Qn+1 =Qn, where n denotes the nth clockpulse (This notation will become clear shortly).
- J = 0, K = 1 → R = 1, S =Qn.
Case (i): Qn = 0 → S = 1 (i.e., R = S = 1) → Qn+1 =Qn = 0.
Case (ii): Qn = 1 → S = 0 (i.e., R = 1, S = 0) → Qn+1 = 0.
In either case, Qn+1 = 0 → For J = 0, K = 1, Qn+1 = 0.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
Truth table for JK flip−flop
CLK J K
1
1
1 1
0
0
0 0
0 XX previous (Qn)
1 00
1 10
previous (Qn)
0
Q
Q
Q (Qn+1)
1 1 0 1
1 1 1 toggles (Qn)
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R =Qn =Qn.
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 =Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R =Qn, S =Qn.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 =Qn.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
Truth table for JK flip−flop
CLK J K
1
1
1 1
0
0
0 0
0 XX previous (Qn)
1 00
1 10
previous (Qn)
0
Q
Q
Q (Qn+1)
1 1 0 1
1 1 1 toggles (Qn)
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R =Qn =Qn.
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 =Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R =Qn, S =Qn.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 =Qn.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
Truth table for JK flip−flop
CLK J K
1
1
1 1
0
0
0 0
0 XX previous (Qn)
1 00
1 10
previous (Qn)
0
Q
Q
Q (Qn+1)
1 1 0 1
1 1 1 toggles (Qn)
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R =Qn =Qn.
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 =Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R =Qn, S =Qn.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 =Qn.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
Truth table for JK flip−flop
CLK J K
1
1
1 1
0
0
0 0
0 XX previous (Qn)
1 00
1 10
previous (Qn)
0
Q
Q
Q (Qn+1)
1 1 0 1
1 1 1 toggles (Qn)
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R =Qn =Qn.
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 =Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R =Qn, S =Qn.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 =Qn.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
Truth table for JK flip−flop
CLK J K
1
1
1 1
0
0
0 0
0 XX previous (Qn)
1 00
1 10
previous (Qn)
0
Q
Q
Q (Qn+1)
1 1 0 1
1 1 1 toggles (Qn)
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R =Qn =Qn.
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 =Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R =Qn, S =Qn.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 =Qn.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
Truth table for JK flip−flop
CLK J K
1
1
1 1
0
0
0 0
0 XX previous (Qn)
1 00
1 10
previous (Qn)
0
Q
Q
Q (Qn+1)
1 1 0 1
1 1 1 toggles (Qn)
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R =Qn =Qn.
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 =Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R =Qn, S =Qn.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 =Qn.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
Truth table for JK flip−flop
CLK J K
1
1
1 1
0
0
0 0
0 XX previous (Qn)
1 00
1 10
previous (Qn)
0
Q
Q
Q (Qn+1)
1 1 0 1
1 1 1 toggles (Qn)
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R =Qn =Qn.
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 =Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R =Qn, S =Qn.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 =Qn.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
Truth table for JK flip−flop
CLK J K
1
1
1 1
0
0
0 0
0 XX previous (Qn)
1 00
1 10
previous (Qn)
0
Q
Q
Q (Qn+1)
1 1 0 1
1 1 1 toggles (Qn)
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R =Qn =Qn.
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 =Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R =Qn, S =Qn.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 =Qn.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
Truth table for JK flip−flop
CLK J K
1
1
1 1
0
0
0 0
0 XX previous (Qn)
1 00
1 10
previous (Qn)
0
Q
Q
Q (Qn+1)
1 1 0 1
1 1 1 toggles (Qn)
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R =Qn =Qn.
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 =Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R =Qn, S =Qn.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 =Qn.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
Truth table for JK flip−flop
CLK J K
1
1
1 1
0
0
0 0
0 XX previous (Qn)
1 00
1 10
previous (Qn)
0
Q
Q
Q (Qn+1)
1 1 0 1
1 1 1 toggles (Qn)
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R =Qn =Qn.
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 =Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R =Qn, S =Qn.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 =Qn.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
1 0
10
Truth table for RS latch
invalid
previous
R S R
S
Truth table for JK flip−flop
CLK J K
1
1
1 1
0
0
0 0
0 XX previous (Qn)
1 00
1 10
previous (Qn)
0
Q
Q
Q (Qn+1)
1 1 0 1
1 1 1 toggles (Qn)
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R =Qn =Qn.
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 =Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R =Qn, S =Qn.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 =Qn.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
R
S
Truth table for JK flip−flop
CLK J K
1 00
1 10
1 1 1
1 1 0
0 XX
previous (Qn)
0
toggles (Qn)
1
previous (Qn)
Q
Q
Q (Qn+1)
Consider J =K = 1 and CLK = 1.
As long as CLK = 1, Q will keep toggling! (The frequency will depend on the delay values of the various gates).
→ Use the “Master-slave” configuration.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
R
S
Truth table for JK flip−flop
CLK J K
1 00
1 10
1 1 1
1 1 0
0 XX
previous (Qn)
0
toggles (Qn)
1
previous (Qn)
Q
Q
Q (Qn+1)
Consider J =K = 1 and CLK = 1.
As long as CLK = 1, Q will keep toggling! (The frequency will depend on the delay values of the various gates).
→ Use the “Master-slave” configuration.
M. B. Patil, IIT Bombay
JK flip-flop: introduction
J
CLK
K
RS latch
R
S
Truth table for JK flip−flop
CLK J K
1 00
1 10
1 1 1
1 1 0
0 XX
previous (Qn)
0
toggles (Qn)
1
previous (Qn)
Q
Q
Q (Qn+1)
Consider J =K = 1 and CLK = 1.
As long as CLK = 1, Q will keep toggling! (The frequency will depend on the delay values of the various gates).
→ Use the “Master-slave” configuration.
M. B. Patil, IIT Bombay
JK flip-flop (Master-Slave)
RS latch 2RS latch 1
J
K
Master Slave
Q1QR2
S2
R1
S1
CLKCLK
Q
J KCLK
0 0
0 1
1 0
1 1
1
Qn
Qn
0
Qn+1
* When CLK goes high, only the first latch is affected; the second latch retains its previous value (becauseCLK = 0 → R2 = S2 = 1).
* When CLK goes low, the output of the first latch (Q1) is retained (since R1 =S1 = 1), and Q1 can nowaffect Q.
* In other words, the effect of any changes in J and K appears at the output Q only when CLK makes atransition from 1 to 0.This is therefore a negative edge-triggered flip-flop.
* Note that the JK flip-flop allows all four input combinations.
M. B. Patil, IIT Bombay
JK flip-flop (Master-Slave)
RS latch 2RS latch 1
J
K
Master Slave
Q1QR2
S2
R1
S1
CLKCLK
Q
J KCLK
0 0
0 1
1 0
1 1
1
Qn
Qn
0
Qn+1
* When CLK goes high, only the first latch is affected; the second latch retains its previous value (becauseCLK = 0 → R2 = S2 = 1).
* When CLK goes low, the output of the first latch (Q1) is retained (since R1 =S1 = 1), and Q1 can nowaffect Q.
* In other words, the effect of any changes in J and K appears at the output Q only when CLK makes atransition from 1 to 0.This is therefore a negative edge-triggered flip-flop.
* Note that the JK flip-flop allows all four input combinations.
M. B. Patil, IIT Bombay
JK flip-flop (Master-Slave)
RS latch 2RS latch 1
J
K
Master Slave
Q1QR2
S2
R1
S1
CLKCLK
Q
J KCLK
0 0
0 1
1 0
1 1
1
Qn
Qn
0
Qn+1
* When CLK goes high, only the first latch is affected; the second latch retains its previous value (becauseCLK = 0 → R2 = S2 = 1).
* When CLK goes low, the output of the first latch (Q1) is retained (since R1 = S1 = 1), and Q1 can nowaffect Q.
* In other words, the effect of any changes in J and K appears at the output Q only when CLK makes atransition from 1 to 0.This is therefore a negative edge-triggered flip-flop.
* Note that the JK flip-flop allows all four input combinations.
M. B. Patil, IIT Bombay
JK flip-flop (Master-Slave)
RS latch 2RS latch 1
J
K
Master Slave
Q1QR2
S2
R1
S1
CLKCLK
Q
J KCLK
0 0
0 1
1 0
1 1
1
Qn
Qn
0
Qn+1
* When CLK goes high, only the first latch is affected; the second latch retains its previous value (becauseCLK = 0 → R2 = S2 = 1).
* When CLK goes low, the output of the first latch (Q1) is retained (since R1 = S1 = 1), and Q1 can nowaffect Q.
* In other words, the effect of any changes in J and K appears at the output Q only when CLK makes atransition from 1 to 0.This is therefore a negative edge-triggered flip-flop.
* Note that the JK flip-flop allows all four input combinations.
M. B. Patil, IIT Bombay
JK flip-flop (Master-Slave)
RS latch 2RS latch 1
J
K
Master Slave
Q1QR2
S2
R1
S1
CLKCLK
Q
J KCLK
0 0
0 1
1 0
1 1
1
Qn
Qn
0
Qn+1
* When CLK goes high, only the first latch is affected; the second latch retains its previous value (becauseCLK = 0 → R2 = S2 = 1).
* When CLK goes low, the output of the first latch (Q1) is retained (since R1 = S1 = 1), and Q1 can nowaffect Q.
* In other words, the effect of any changes in J and K appears at the output Q only when CLK makes atransition from 1 to 0.This is therefore a negative edge-triggered flip-flop.
* Note that the JK flip-flop allows all four input combinations.
M. B. Patil, IIT Bombay
JK flip-flop (Master-Slave)
RS latch 2RS latch 1
J
K
Master Slave
Q1QR2
S2
R1
S1
CLKCLK
Q
J KCLK
0 0
0 1
1 0
1 1
1
Qn
Qn
0
Qn+1
* When CLK goes high, only the first latch is affected; the second latch retains its previous value (becauseCLK = 0 → R2 = S2 = 1).
* When CLK goes low, the output of the first latch (Q1) is retained (since R1 = S1 = 1), and Q1 can nowaffect Q.
* In other words, the effect of any changes in J and K appears at the output Q only when CLK makes atransition from 1 to 0.This is therefore a negative edge-triggered flip-flop.
* Note that the JK flip-flop allows all four input combinations.
M. B. Patil, IIT Bombay
JK flip-flop (Master-Slave)
RS latch 2RS latch 1
J
K
Master Slave
J KCLK
t
t
t
t
t
t
t
t
t
CLK
Q1QR2
S2
R1
S1
Q1
R2
S2
Q
J
K
R1
S1
0 0
0 1
1 0
1 1
1
Qn
Qn
0
CLKCLK
Q
Qn+1
M. B. Patil, IIT Bombay
JK flip-flop (Master-Slave)
RS latch 2RS latch 1
J
K
Master Slave
J KCLK
t
t
t
t
t
t
t
t
t
CLK
Q1QR2
S2
R1
S1
Q1
R2
S2
Q
J
K
R1
S1
0 0
0 1
1 0
1 1
1
Qn
Qn
0
CLKCLK
Q
Qn+1
M. B. Patil, IIT Bombay
JK flip-flop (Master-Slave)
RS latch 2RS latch 1
J
K
Master Slave
J KCLK
t
t
t
t
t
t
t
t
t
CLK
Q1QR2
S2
R1
S1
Q1
R2
S2
Q
J
K
R1
S1
0 0
0 1
1 0
1 1
1
Qn
Qn
0
CLKCLK
Q
Qn+1
M. B. Patil, IIT Bombay
JK flip-flop (Master-Slave)
RS latch 2RS latch 1
J
K
Master Slave
J KCLK
t
t
t
t
t
t
t
t
t
CLK
Q1QR2
S2
R1
S1
Q1
R2
S2
Q
J
K
R1
S1
0 0
0 1
1 0
1 1
1
Qn
Qn
0
CLKCLK
Q
Qn+1
M. B. Patil, IIT Bombay
JK flip-flop (Master-Slave)
RS latch 2RS latch 1
J
K
Master Slave
J KCLK
t
t
t
t
t
t
t
t
t
CLK
Q1QR2
S2
R1
S1
Q1
R2
S2
Q
J
K
R1
S1
0 0
0 1
1 0
1 1
1
Qn
Qn
0
CLKCLK
Q
Qn+1
M. B. Patil, IIT Bombay
JK flip-flop (Master-Slave)
RS latch 2RS latch 1
J
K
Master Slave
J KCLK
t
t
t
t
t
t
t
t
t
CLK
Q1QR2
S2
R1
S1
Q1
R2
S2
Q
J
K
R1
S1
0 0
0 1
1 0
1 1
1
Qn
Qn
0
CLKCLK
Q
Qn+1
M. B. Patil, IIT Bombay
JK flip-flop (Master-Slave)
RS latch 2RS latch 1
J
K
Master Slave
J KCLK
t
t
t
t
t
t
t
t
t
CLK
Q1QR2
S2
R1
S1
Q1
R2
S2
Q
J
K
R1
S1
0 0
0 1
1 0
1 1
1
Qn
Qn
0
CLKCLK
Q
Qn+1
M. B. Patil, IIT Bombay
JK flip-flop (Master-Slave)
RS latch 2RS latch 1
J
K
Master Slave
J KCLK
t
t
t
t
t
t
t
t
t
CLK
Q1QR2
S2
R1
S1
Q1
R2
S2
Q
J
K
R1
S1
0 0
0 1
1 0
1 1
1
Qn
Qn
0
CLKCLK
Q
Qn+1
M. B. Patil, IIT Bombay
JK flip-flop (Master-Slave)
RS latch 2RS latch 1
J
K
Master Slave
J KCLK
t
t
t
t
t
t
t
t
t
CLK
Q1QR2
S2
R1
S1
Q1
R2
S2
Q
J
K
R1
S1
0 0
0 1
1 0
1 1
1
Qn
Qn
0
CLKCLK
Q
Qn+1
M. B. Patil, IIT Bombay
JK flip-flop
J
CLK
K
J
CLK
K
J K CLK J K
positive edge−triggered JK flip−flop
CLK
negative edge−triggered JK flip−flop
Q
Q
Q
Q
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0
1
Qn
0
Qn Qn
Qn
1
Qn+1 Qn+1
* Both negative (e.g., 74ALS112A, CD54ACT112) and positive (e.g., 74ALS109A, CD4027) edge-triggeredJK flip-flops are available as ICs.
M. B. Patil, IIT Bombay
JK flip-flop
J
CLK
K
J
CLK
K
J K CLK J K
positive edge−triggered JK flip−flop
CLK
negative edge−triggered JK flip−flop
Q
Q
Q
Q
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0
1
Qn
0
Qn Qn
Qn
1
Qn+1 Qn+1
* Both negative (e.g., 74ALS112A, CD54ACT112) and positive (e.g., 74ALS109A, CD4027) edge-triggeredJK flip-flops are available as ICs.
M. B. Patil, IIT Bombay
JK flip-flop
J
K
CLK
SlaveMaster
Q1
Q1
Q
CLK
Q
CLK
t2Bt2At1Bt1A
Consider a negative edge-triggered JK flip-flop.
* As seen earlier, when CLK is high (i.e., t1A < t < t1B , etc.), the input J and K determine the Masterlatch output Q1.During this time, no change is visible at the flip-flop output Q.
* When the clock goes low, the Slave flip-flop becomes active, making it possible for Q to change.
* In short, although the flip-flop output Q can only change after the active edge, (t1B , t2B , etc.), the new Qvalue is determined by J and K values just before the active edge.This is a very important point!
M. B. Patil, IIT Bombay
JK flip-flop
J
K
CLK
SlaveMaster
Q1
Q1
Q
CLK
Q
CLK
t2Bt2At1Bt1A
Consider a negative edge-triggered JK flip-flop.
* As seen earlier, when CLK is high (i.e., t1A < t < t1B , etc.), the input J and K determine the Masterlatch output Q1.During this time, no change is visible at the flip-flop output Q.
* When the clock goes low, the Slave flip-flop becomes active, making it possible for Q to change.
* In short, although the flip-flop output Q can only change after the active edge, (t1B , t2B , etc.), the new Qvalue is determined by J and K values just before the active edge.This is a very important point!
M. B. Patil, IIT Bombay
JK flip-flop
J
K
CLK
SlaveMaster
Q1
Q1
Q
CLK
Q
CLK
t2Bt2At1Bt1A
Consider a negative edge-triggered JK flip-flop.
* As seen earlier, when CLK is high (i.e., t1A < t < t1B , etc.), the input J and K determine the Masterlatch output Q1.During this time, no change is visible at the flip-flop output Q.
* When the clock goes low, the Slave flip-flop becomes active, making it possible for Q to change.
* In short, although the flip-flop output Q can only change after the active edge, (t1B , t2B , etc.), the new Qvalue is determined by J and K values just before the active edge.This is a very important point!
M. B. Patil, IIT Bombay
JK flip-flop
J
K
CLK
SlaveMaster
Q1
Q1
Q
CLK
Q
CLK
t2Bt2At1Bt1A
Consider a negative edge-triggered JK flip-flop.
* As seen earlier, when CLK is high (i.e., t1A < t < t1B , etc.), the input J and K determine the Masterlatch output Q1.During this time, no change is visible at the flip-flop output Q.
* When the clock goes low, the Slave flip-flop becomes active, making it possible for Q to change.
* In short, although the flip-flop output Q can only change after the active edge, (t1B , t2B , etc.), the new Qvalue is determined by J and K values just before the active edge.
This is a very important point!
M. B. Patil, IIT Bombay
JK flip-flop
J
K
CLK
SlaveMaster
Q1
Q1
Q
CLK
Q
CLK
t2Bt2At1Bt1A
Consider a negative edge-triggered JK flip-flop.
* As seen earlier, when CLK is high (i.e., t1A < t < t1B , etc.), the input J and K determine the Masterlatch output Q1.During this time, no change is visible at the flip-flop output Q.
* When the clock goes low, the Slave flip-flop becomes active, making it possible for Q to change.
* In short, although the flip-flop output Q can only change after the active edge, (t1B , t2B , etc.), the new Qvalue is determined by J and K values just before the active edge.This is a very important point!
M. B. Patil, IIT Bombay
JK flip-flop
J
CLK
K
J K
CLK
J
K
Q
positive edge−triggered JK flip−flop
CLK
0
time (msec)
0.1 0.2 0.3 0.4 0.5 0.6
Q
Q
0 0
0 1
1 0
1 1
Qn
0
Qn
1
Qn+1
J
CLK
K
CLK J K
CLK
J
K
Q
negative edge−triggered JK flip−flop
0
time (msec)
0.1 0.2 0.3 0.4 0.5 0.6
Q
Q0 0
0 1
1 0
1 1
0
1
Qn
Qn
Qn+1
M. B. Patil, IIT Bombay
JK flip-flop
J
CLK
K
J K
CLK
J
K
Q
positive edge−triggered JK flip−flop
CLK
0
time (msec)
0.1 0.2 0.3 0.4 0.5 0.6
Q
Q
0 0
0 1
1 0
1 1
Qn
0
Qn
1
Qn+1
J
CLK
K
CLK J K
CLK
J
K
Q
negative edge−triggered JK flip−flop
0
time (msec)
0.1 0.2 0.3 0.4 0.5 0.6
Q
Q0 0
0 1
1 0
1 1
0
1
Qn
Qn
Qn+1
M. B. Patil, IIT Bombay
JK flip-flop
1
CLK
t
t
t
J K
CLK
CLK
J2Q2
Q1
K2
J1
K1
Q2
QJ
QK
QJ
QK
t5t4t3t2t1
Q1
0 0
0 1
1 0
1 1
J1=K1=1. Assume Q1=Q2=0 initially.
Qn
0
Qn
1
Qn+1
t Q2 (t = t+k )K2 (t = t−k )J2 (t = t−k )
t2
t3
t4
t5
t1
1 0 1
0 1 0
1 0 1
1 00
1 00
* Since J1 = K1 = 1, Q1 toggles after every active clock edge.
* J2 = Q1, K2 = Q1. We need to look at J2 and K2 values just before the active edge, to determine the next value of Q2.
* It is convenient to construct a table listing J2 and K2 to figure out the next Q2 value.
M. B. Patil, IIT Bombay
JK flip-flop
1
CLK
t
t
t
J K
CLK
CLK
J2Q2
Q1
K2
J1
K1
Q2
QJ
QK
QJ
QK
t5t4t3t2t1
Q1
0 0
0 1
1 0
1 1
J1=K1=1. Assume Q1=Q2=0 initially.
Qn
0
Qn
1
Qn+1
t Q2 (t = t+k )K2 (t = t−k )J2 (t = t−k )
t2
t3
t4
t5
t1
1 0 1
0 1 0
1 0 1
1 00
1 00
* Since J1 = K1 = 1, Q1 toggles after every active clock edge.
* J2 = Q1, K2 = Q1. We need to look at J2 and K2 values just before the active edge, to determine the next value of Q2.
* It is convenient to construct a table listing J2 and K2 to figure out the next Q2 value.
M. B. Patil, IIT Bombay
JK flip-flop
1
CLK
t
t
t
J K
CLK
CLK
J2Q2
Q1
K2
J1
K1
Q2
QJ
QK
QJ
QK
t5t4t3t2t1
Q1
0 0
0 1
1 0
1 1
J1=K1=1. Assume Q1=Q2=0 initially.
Qn
0
Qn
1
Qn+1
t Q2 (t = t+k )K2 (t = t−k )J2 (t = t−k )
t2
t3
t4
t5
t1
1 0 1
0 1 0
1 0 1
1 00
1 00
* Since J1 = K1 = 1, Q1 toggles after every active clock edge.
* J2 = Q1, K2 = Q1. We need to look at J2 and K2 values just before the active edge, to determine the next value of Q2.
* It is convenient to construct a table listing J2 and K2 to figure out the next Q2 value.
M. B. Patil, IIT Bombay
JK flip-flop
1
CLK
t
t
t
J K
CLK
CLK
J2Q2
Q1
K2
J1
K1
Q2
QJ
QK
QJ
QK
t5t4t3t2t1
Q1
0 0
0 1
1 0
1 1
J1=K1=1. Assume Q1=Q2=0 initially.
Qn
0
Qn
1
Qn+1
t Q2 (t = t+k )K2 (t = t−k )J2 (t = t−k )
t2
t3
t4
t5
t1
1 0 1
0 1 0
1 0 1
1 00
1 00
* Since J1 = K1 = 1, Q1 toggles after every active clock edge.
* J2 = Q1, K2 = Q1. We need to look at J2 and K2 values just before the active edge, to determine the next value of Q2.
* It is convenient to construct a table listing J2 and K2 to figure out the next Q2 value.
M. B. Patil, IIT Bombay
JK flip-flop
1
CLK
t
t
t
J K
CLK
CLK
J2Q2
Q1
K2
J1
K1
Q2
QJ
QK
QJ
QK
t5t4t3t2t1
Q1
0 0
0 1
1 0
1 1
J1=K1=1. Assume Q1=Q2=0 initially.
Qn
0
Qn
1
Qn+1
t Q2 (t = t+k )K2 (t = t−k )J2 (t = t−k )
t2
t3
t4
t5
t1
1 0 1
0 1 0
1 0 1
1 00
1 00
* Since J1 = K1 = 1, Q1 toggles after every active clock edge.
* J2 = Q1, K2 = Q1. We need to look at J2 and K2 values just before the active edge, to determine the next value of Q2.
* It is convenient to construct a table listing J2 and K2 to figure out the next Q2 value.
M. B. Patil, IIT Bombay
JK flip-flop
1
CLK
t
t
t
J K
CLK
CLK
J2Q2
Q1
K2
J1
K1
Q2
QJ
QK
QJ
QK
t5t4t3t2t1
Q1
0 0
0 1
1 0
1 1
J1=K1=1. Assume Q1=Q2=0 initially.
Qn
0
Qn
1
Qn+1
t Q2 (t = t+k )K2 (t = t−k )J2 (t = t−k )
t2
t3
t4
t5
t1
1 0 1
0 1 0
1 0 1
1 00
1 00
* Since J1 = K1 = 1, Q1 toggles after every active clock edge.
* J2 = Q1, K2 = Q1. We need to look at J2 and K2 values just before the active edge, to determine the next value of Q2.
* It is convenient to construct a table listing J2 and K2 to figure out the next Q2 value.
M. B. Patil, IIT Bombay
JK flip-flop
1
CLK
t
t
t
J K
CLK
CLK
J2Q2
Q1
K2
J1
K1
Q2
QJ
QK
QJ
QK
t5t4t3t2t1
Q1
0 0
0 1
1 0
1 1
J1=K1=1. Assume Q1=Q2=0 initially.
Qn
0
Qn
1
Qn+1
t Q2 (t = t+k )K2 (t = t−k )J2 (t = t−k )
t2
t3
t4
t5
t1
1 0 1
0 1 0
1 0 1
1 00
1 00
* Since J1 = K1 = 1, Q1 toggles after every active clock edge.
* J2 = Q1, K2 = Q1. We need to look at J2 and K2 values just before the active edge, to determine the next value of Q2.
* It is convenient to construct a table listing J2 and K2 to figure out the next Q2 value.
M. B. Patil, IIT Bombay
1
J KCLK
t
t
t
CLK
t
CLK
0
1
0
1
0
1
t5t4t3t2t1
QJ
QK
QJ
QK
QJ
QK
Q0 Q1 Q2
0 0
0 1
1 0
1 1
Qn
0
Qn
1
Q0
Q1
Q2
Qn+1
t
t1
tk− tk
+
t2
t3
t4
t5
1 11 0 0 10 0 0
K2J2K1J1K0J0 Q2Q1 Q1Q0 Q0Q2
11 0
1
0 0
1
1
0
01 1 001 0 01 11 1
1
0 0
1
0
1
1 1 0 01 1 01 1 10 1
0
1 0
1
0
1
10 1 1 11 1 0 0 01 1
1
0 1
0
0
1
11 0 0 01 1 1 1 00 0
0
1 1
0
1
0
M. B. Patil, IIT Bombay
1
J KCLK
t
t
t
CLK
t
CLK
0
1
0
1
0
1
t5t4t3t2t1
QJ
QK
QJ
QK
QJ
QK
Q0 Q1 Q2
0 0
0 1
1 0
1 1
Qn
0
Qn
1
Q0
Q1
Q2
Qn+1
t
t1
tk− tk
+
t2
t3
t4
t5
1 11 0 0 10 0 0
K2J2K1J1K0J0 Q2Q1 Q1Q0 Q0Q2
11 0
1
0 0
1
1
0
01 1 001 0 01 11 1
1
0 0
1
0
1
1 1 0 01 1 01 1 10 1
0
1 0
1
0
1
10 1 1 11 1 0 0 01 1
1
0 1
0
0
1
11 0 0 01 1 1 1 00 0
0
1 1
0
1
0
M. B. Patil, IIT Bombay
1
J KCLK
t
t
t
CLK
t
CLK
0
1
0
1
0
1
t5t4t3t2t1
QJ
QK
QJ
QK
QJ
QK
Q0 Q1 Q2
0 0
0 1
1 0
1 1
Qn
0
Qn
1
Q0
Q1
Q2
Qn+1
t
t1
tk− tk
+
t2
t3
t4
t5
1 11 0 0 10 0 0
K2J2K1J1K0J0 Q2Q1 Q1Q0 Q0Q2
11 0
1
0 0
1
1
0
01 1 001 0 01 11 1
1
0 0
1
0
1
1 1 0 01 1 01 1 10 1
0
1 0
1
0
1
10 1 1 11 1 0 0 01 1
1
0 1
0
0
1
11 0 0 01 1 1 1 00 0
0
1 1
0
1
0
M. B. Patil, IIT Bombay
1
J KCLK
t
t
t
CLK
t
CLK
0
1
0
1
0
1
t5t4t3t2t1
QJ
QK
QJ
QK
QJ
QK
Q0 Q1 Q2
0 0
0 1
1 0
1 1
Qn
0
Qn
1
Q0
Q1
Q2
Qn+1
t
t1
tk− tk
+
t2
t3
t4
t5
1 11 0 0 10 0 0
K2J2K1J1K0J0 Q2Q1 Q1Q0 Q0Q2
11 0
1
0 0
1
1
0
01 1 001 0 01
11 1
1
0 0
1
0
1
1 1 0 01 1 01 1 10 1
0
1 0
1
0
1
10 1 1 11 1 0 0 01 1
1
0 1
0
0
1
11 0 0 01 1 1 1 00 0
0
1 1
0
1
0
M. B. Patil, IIT Bombay
1
J KCLK
t
t
t
CLK
t
CLK
0
1
0
1
0
1
t5t4t3t2t1
QJ
QK
QJ
QK
QJ
QK
Q0 Q1 Q2
0 0
0 1
1 0
1 1
Qn
0
Qn
1
Q0
Q1
Q2
Qn+1
t
t1
tk− tk
+
t2
t3
t4
t5
1 11 0 0 10 0 0
K2J2K1J1K0J0 Q2Q1 Q1Q0 Q0Q2
11 0
1
0 0
1
1
0
01 1 001 0 01 11 1
1
0 0
1
0
1
1 1 0 01 1 01 1 10 1
0
1 0
1
0
1
10 1 1 11 1 0 0 01 1
1
0 1
0
0
1
11 0 0 01 1 1 1 00 0
0
1 1
0
1
0
M. B. Patil, IIT Bombay
1
J KCLK
t
t
t
CLK
t
CLK
0
1
0
1
0
1
t5t4t3t2t1
QJ
QK
QJ
QK
QJ
QK
Q0 Q1 Q2
0 0
0 1
1 0
1 1
Qn
0
Qn
1
Q0
Q1
Q2
Qn+1
t
t1
tk− tk
+
t2
t3
t4
t5
1 11 0 0 10 0 0
K2J2K1J1K0J0 Q2Q1 Q1Q0 Q0Q2
11 0
1
0 0
1
1
0
01 1 001 0 01 11 1
1
0 0
1
0
1
1 1 0 01 1 01 1
10 1
0
1 0
1
0
1
10 1 1 11 1 0 0 01 1
1
0 1
0
0
1
11 0 0 01 1 1 1 00 0
0
1 1
0
1
0
M. B. Patil, IIT Bombay
1
J KCLK
t
t
t
CLK
t
CLK
0
1
0
1
0
1
t5t4t3t2t1
QJ
QK
QJ
QK
QJ
QK
Q0 Q1 Q2
0 0
0 1
1 0
1 1
Qn
0
Qn
1
Q0
Q1
Q2
Qn+1
t
t1
tk− tk
+
t2
t3
t4
t5
1 11 0 0 10 0 0
K2J2K1J1K0J0 Q2Q1 Q1Q0 Q0Q2
11 0
1
0 0
1
1
0
01 1 001 0 01 11 1
1
0 0
1
0
1
1 1 0 01 1 01 1 10 1
0
1 0
1
0
1
10 1 1 11 1 0 0 01 1
1
0 1
0
0
1
11 0 0 01 1 1 1 00 0
0
1 1
0
1
0
M. B. Patil, IIT Bombay
1
J KCLK
t
t
t
CLK
t
CLK
0
1
0
1
0
1
t5t4t3t2t1
QJ
QK
QJ
QK
QJ
QK
Q0 Q1 Q2
0 0
0 1
1 0
1 1
Qn
0
Qn
1
Q0
Q1
Q2
Qn+1
t
t1
tk− tk
+
t2
t3
t4
t5
1 11 0 0 10 0 0
K2J2K1J1K0J0 Q2Q1 Q1Q0 Q0Q2
11 0
1
0 0
1
1
0
01 1 001 0 01 11 1
1
0 0
1
0
1
1 1 0 01 1 01 1 10 1
0
1 0
1
0
1
10 1 1 11 1 0 0
01 1
1
0 1
0
0
1
11 0 0 01 1 1 1 00 0
0
1 1
0
1
0
M. B. Patil, IIT Bombay
1
J KCLK
t
t
t
CLK
t
CLK
0
1
0
1
0
1
t5t4t3t2t1
QJ
QK
QJ
QK
QJ
QK
Q0 Q1 Q2
0 0
0 1
1 0
1 1
Qn
0
Qn
1
Q0
Q1
Q2
Qn+1
t
t1
tk− tk
+
t2
t3
t4
t5
1 11 0 0 10 0 0
K2J2K1J1K0J0 Q2Q1 Q1Q0 Q0Q2
11 0
1
0 0
1
1
0
01 1 001 0 01 11 1
1
0 0
1
0
1
1 1 0 01 1 01 1 10 1
0
1 0
1
0
1
10 1 1 11 1 0 0 01 1
1
0 1
0
0
1
11 0 0 01 1 1 1 00 0
0
1 1
0
1
0
M. B. Patil, IIT Bombay
1
J KCLK
t
t
t
CLK
t
CLK
0
1
0
1
0
1
t5t4t3t2t1
QJ
QK
QJ
QK
QJ
QK
Q0 Q1 Q2
0 0
0 1
1 0
1 1
Qn
0
Qn
1
Q0
Q1
Q2
Qn+1
t
t1
tk− tk
+
t2
t3
t4
t5
1 11 0 0 10 0 0
K2J2K1J1K0J0 Q2Q1 Q1Q0 Q0Q2
11 0
1
0 0
1
1
0
01 1 001 0 01 11 1
1
0 0
1
0
1
1 1 0 01 1 01 1 10 1
0
1 0
1
0
1
10 1 1 11 1 0 0 01 1
1
0 1
0
0
1
11 0 0 01 1 1 1
00 0
0
1 1
0
1
0
M. B. Patil, IIT Bombay
1
J KCLK
t
t
t
CLK
t
CLK
0
1
0
1
0
1
t5t4t3t2t1
QJ
QK
QJ
QK
QJ
QK
Q0 Q1 Q2
0 0
0 1
1 0
1 1
Qn
0
Qn
1
Q0
Q1
Q2
Qn+1
t
t1
tk− tk
+
t2
t3
t4
t5
1 11 0 0 10 0 0
K2J2K1J1K0J0 Q2Q1 Q1Q0 Q0Q2
11 0
1
0 0
1
1
0
01 1 001 0 01 11 1
1
0 0
1
0
1
1 1 0 01 1 01 1 10 1
0
1 0
1
0
1
10 1 1 11 1 0 0 01 1
1
0 1
0
0
1
11 0 0 01 1 1 1 00 0
0
1 1
0
1
0
M. B. Patil, IIT Bombay
1
J KCLK
t
t
t
CLK
t
CLK
0
1
0
1
0
1
t5t4t3t2t1
QJ
QK
QJ
QK
QJ
QK
Q0 Q1 Q2
0 0
0 1
1 0
1 1
Qn
0
Qn
1
Q0
Q1
Q2
Qn+1
t
t1
tk− tk
+
t2
t3
t4
t5
1 11 0 0 10 0 0
K2J2K1J1K0J0 Q2Q1 Q1Q0 Q0Q2
11 0
1
0 0
1
1
0
01 1 001 0 01 11 1
1
0 0
1
0
1
1 1 0 01 1 01 1 10 1
0
1 0
1
0
1
10 1 1 11 1 0 0 01 1
1
0 1
0
0
1
11 0 0 01 1 1 1 00 0
0
1 1
0
1
0
M. B. Patil, IIT Bombay
JK flip-flop: asynchronous inputs
J KCLK
Rd
Sd
CLK
Rd
QJ
QK
Sd
Qn
Qn
0 0
0 1
1 0
1 1
X X X
X X X
X X X
0 1
1 0
1 1
0
0
0
0
0
0
0
0
1
invalid
0
1 operationnormal
0
Qn+1
* Clocked flip-flops are also provided with asynchronous or direct Set and Reset inputs, Sd and Rd , (alsocalled Preset and Clear, respectively) which override all other inputs (J, K, CLK).
* The Sd and Rd inputs may be active low; in that case, they are denoted by Sd and Rd .
* The asynchronous inputs are convenient for starting up a circuit in a known state.
M. B. Patil, IIT Bombay
JK flip-flop: asynchronous inputs
J KCLK
Rd
Sd
CLK
Rd
QJ
QK
Sd
Qn
Qn
0 0
0 1
1 0
1 1
X X X
X X X
X X X
0 1
1 0
1 1
0
0
0
0
0
0
0
0
1
invalid
0
1 operationnormal
0
Qn+1
* Clocked flip-flops are also provided with asynchronous or direct Set and Reset inputs, Sd and Rd , (alsocalled Preset and Clear, respectively) which override all other inputs (J, K, CLK).
* The Sd and Rd inputs may be active low; in that case, they are denoted by Sd and Rd .
* The asynchronous inputs are convenient for starting up a circuit in a known state.
M. B. Patil, IIT Bombay
JK flip-flop: asynchronous inputs
J KCLK
Rd
Sd
CLK
Rd
QJ
QK
Sd
Qn
Qn
0 0
0 1
1 0
1 1
X X X
X X X
X X X
0 1
1 0
1 1
0
0
0
0
0
0
0
0
1
invalid
0
1 operationnormal
0
Qn+1
* Clocked flip-flops are also provided with asynchronous or direct Set and Reset inputs, Sd and Rd , (alsocalled Preset and Clear, respectively) which override all other inputs (J, K, CLK).
* The Sd and Rd inputs may be active low; in that case, they are denoted by Sd and Rd .
* The asynchronous inputs are convenient for starting up a circuit in a known state.
M. B. Patil, IIT Bombay
JK flip-flop: asynchronous inputs
J KCLK
Rd
Sd
CLK
Rd
QJ
QK
Sd
Qn
Qn
0 0
0 1
1 0
1 1
X X X
X X X
X X X
0 1
1 0
1 1
0
0
0
0
0
0
0
0
1
invalid
0
1 operationnormal
0
Qn+1
* Clocked flip-flops are also provided with asynchronous or direct Set and Reset inputs, Sd and Rd , (alsocalled Preset and Clear, respectively) which override all other inputs (J, K, CLK).
* The Sd and Rd inputs may be active low; in that case, they are denoted by Sd and Rd .
* The asynchronous inputs are convenient for starting up a circuit in a known state.
M. B. Patil, IIT Bombay
D flip-flop
J
K
J
K
D
CLK
D
CLK
CLK
CLK D
D
Q
CLK
D
Q
t
t
t
t
t
t
positive edge−triggered D flip−flop
negative edge−triggered D flip−flop
DD
CLK
D
CLK
CLK
t5
t5
t4
t4
t3
t3
t2
t2
t1
t1
Q
Q
Q
Q
Q
Q
Q
Q
0
1
0
1
0
1
1
0
Qn+1
Qn+1
* The D flip-flop can be used to delay the Data (D) signal by one clock period.
* With J = D, K = D, we have either J = 0, K = 1 or J = 1, K = 0; the next Q is 0 in the first case, 1 in the second case.* Instead of a JK flip-flop, an RS flip-flop can also be used to make a D flip-flop, with S = D, R = D.
M. B. Patil, IIT Bombay
D flip-flop
J
K
J
K
D
CLK
D
CLK
CLK
CLK D
D
Q
CLK
D
Q
t
t
t
t
t
t
positive edge−triggered D flip−flop
negative edge−triggered D flip−flop
DD
CLK
D
CLK
CLK
t5
t5
t4
t4
t3
t3
t2
t2
t1
t1
Q
Q
Q
Q
Q
Q
Q
Q
0
1
0
1
0
1
1
0
Qn+1
Qn+1
* The D flip-flop can be used to delay the Data (D) signal by one clock period.
* With J = D, K = D, we have either J = 0, K = 1 or J = 1, K = 0; the next Q is 0 in the first case, 1 in the second case.* Instead of a JK flip-flop, an RS flip-flop can also be used to make a D flip-flop, with S = D, R = D.
M. B. Patil, IIT Bombay
D flip-flop
J
K
J
K
D
CLK
D
CLK
CLK
CLK D
D
Q
CLK
D
Q
t
t
t
t
t
t
positive edge−triggered D flip−flop
negative edge−triggered D flip−flop
DD
CLK
D
CLK
CLK
t5
t5
t4
t4
t3
t3
t2
t2
t1
t1
Q
Q
Q
Q
Q
Q
Q
Q
0
1
0
1
0
1
1
0
Qn+1
Qn+1
* The D flip-flop can be used to delay the Data (D) signal by one clock period.
* With J = D, K = D, we have either J = 0, K = 1 or J = 1, K = 0; the next Q is 0 in the first case, 1 in the second case.
* Instead of a JK flip-flop, an RS flip-flop can also be used to make a D flip-flop, with S = D, R = D.
M. B. Patil, IIT Bombay
D flip-flop
J
K
J
K
D
CLK
D
CLK
CLK
CLK D
D
Q
CLK
D
Q
t
t
t
t
t
t
positive edge−triggered D flip−flop
negative edge−triggered D flip−flop
DD
CLK
D
CLK
CLK
t5
t5
t4
t4
t3
t3
t2
t2
t1
t1
Q
Q
Q
Q
Q
Q
Q
Q
0
1
0
1
0
1
1
0
Qn+1
Qn+1
* The D flip-flop can be used to delay the Data (D) signal by one clock period.
* With J = D, K = D, we have either J = 0, K = 1 or J = 1, K = 0; the next Q is 0 in the first case, 1 in the second case.* Instead of a JK flip-flop, an RS flip-flop can also be used to make a D flip-flop, with S = D, R = D.
M. B. Patil, IIT Bombay
Shift register
CLK D
CLK
0 0 0 0
Q4
Q3Q2Q1D D D DD Q Q
Q Q QQ
0
1
0
1
Qn+1
CLK
D
Q1
Q2
Q3
Q4
1 0 0 01 1 0 00 1 1 01 0 1 10 1 0 10 0 1 00 0 0 10 0 0 00 0 0 0
SEQUEL file: ee101 shift reg 1.sqproj
M. B. Patil, IIT Bombay
Shift register
CLK D
CLK
0 0 0 0
Q4
Q3Q2Q1D D D DD Q Q
Q Q QQ
0
1
0
1
Qn+1
CLK
D
Q1
Q2
Q3
Q4
1 0 0 0
1 1 0 00 1 1 01 0 1 10 1 0 10 0 1 00 0 0 10 0 0 00 0 0 0
SEQUEL file: ee101 shift reg 1.sqproj
M. B. Patil, IIT Bombay
Shift register
CLK D
CLK
0 0 0 0
Q4
Q3Q2Q1D D D DD Q Q
Q Q QQ
0
1
0
1
Qn+1
CLK
D
Q1
Q2
Q3
Q4
1 0 0 01 1 0 0
0 1 1 01 0 1 10 1 0 10 0 1 00 0 0 10 0 0 00 0 0 0
SEQUEL file: ee101 shift reg 1.sqproj
M. B. Patil, IIT Bombay
Shift register
CLK D
CLK
0 0 0 0
Q4
Q3Q2Q1D D D DD Q Q
Q Q QQ
0
1
0
1
Qn+1
CLK
D
Q1
Q2
Q3
Q4
1 0 0 01 1 0 00 1 1 0
1 0 1 10 1 0 10 0 1 00 0 0 10 0 0 00 0 0 0
SEQUEL file: ee101 shift reg 1.sqproj
M. B. Patil, IIT Bombay
Shift register
CLK D
CLK
0 0 0 0
Q4
Q3Q2Q1D D D DD Q Q
Q Q QQ
0
1
0
1
Qn+1
CLK
D
Q1
Q2
Q3
Q4
1 0 0 01 1 0 00 1 1 01 0 1 1
0 1 0 10 0 1 00 0 0 10 0 0 00 0 0 0
SEQUEL file: ee101 shift reg 1.sqproj
M. B. Patil, IIT Bombay
Shift register
CLK D
CLK
0 0 0 0
Q4
Q3Q2Q1D D D DD Q Q
Q Q QQ
0
1
0
1
Qn+1
CLK
D
Q1
Q2
Q3
Q4
1 0 0 01 1 0 00 1 1 01 0 1 10 1 0 1
0 0 1 00 0 0 10 0 0 00 0 0 0
SEQUEL file: ee101 shift reg 1.sqproj
M. B. Patil, IIT Bombay
Shift register
CLK D
CLK
0 0 0 0
Q4
Q3Q2Q1D D D DD Q Q
Q Q QQ
0
1
0
1
Qn+1
CLK
D
Q1
Q2
Q3
Q4
1 0 0 01 1 0 00 1 1 01 0 1 10 1 0 10 0 1 0
0 0 0 10 0 0 00 0 0 0
SEQUEL file: ee101 shift reg 1.sqproj
M. B. Patil, IIT Bombay
Shift register
CLK D
CLK
0 0 0 0
Q4
Q3Q2Q1D D D DD Q Q
Q Q QQ
0
1
0
1
Qn+1
CLK
D
Q1
Q2
Q3
Q4
1 0 0 01 1 0 00 1 1 01 0 1 10 1 0 10 0 1 00 0 0 1
0 0 0 00 0 0 0
SEQUEL file: ee101 shift reg 1.sqproj
M. B. Patil, IIT Bombay
Shift register
CLK D
CLK
0 0 0 0
Q4
Q3Q2Q1D D D DD Q Q
Q Q QQ
0
1
0
1
Qn+1
CLK
D
Q1
Q2
Q3
Q4
1 0 0 01 1 0 00 1 1 01 0 1 10 1 0 10 0 1 00 0 0 10 0 0 0
0 0 0 0
SEQUEL file: ee101 shift reg 1.sqproj
M. B. Patil, IIT Bombay
Shift register
CLK D
CLK
0 0 0 0
Q4
Q3Q2Q1D D D DD Q Q
Q Q QQ
0
1
0
1
Qn+1
CLK
D
Q1
Q2
Q3
Q4
1 0 0 01 1 0 00 1 1 01 0 1 10 1 0 10 0 1 00 0 0 10 0 0 00 0 0 0
SEQUEL file: ee101 shift reg 1.sqproj
M. B. Patil, IIT Bombay
Parallel transfer between shift registers
Register B
Register A
CLK
D D D
D D D
D
D
B1B0B1B2B3B3
A3 A2 A1 A0
A3 A2 A1 A0
B2 B0
Q
Q
Q
Q
Q Q
Q
Q Q
Q Q
Q
Q
Q
* After the active clock edge, the contents of the A register (A3A2A1A0) are copied to the B register.
M. B. Patil, IIT Bombay
Parallel transfer between shift registers
Register B
Register A
CLK
D D D
D D D
D
D
B1B0B1B2B3B3
A3 A2 A1 A0
A3 A2 A1 A0
B2 B0
Q
Q
Q
Q
Q Q
Q
Q Q
Q Q
Q
Q
Q
* After the active clock edge, the contents of the A register (A3A2A1A0) are copied to the B register.
M. B. Patil, IIT Bombay
Bidirectional shift register
DDD D
CLK
D3D2D1D0 Q1 Q2 Q3Q0
DL
DR
Q
M
Q
Q Q Q
Q
Q
Q
M
* When the mode input (M) is 1, we haveD0 =DR , D1 =Q0, D2 =Q1, D3 =Q2.
* When the mode input (M) is 0, we haveD0 =Q1, D1 =Q2, D2 =Q3, D3 =DL.
* M = 1 → shift right operation.M = 0 → shift left operation.
M. B. Patil, IIT Bombay
Bidirectional shift register
DDD D
CLK
D3D2D1D0 Q1 Q2 Q3Q0
DL
DR
Q
M
Q
Q Q Q
Q
Q
Q
M
* When the mode input (M) is 1, we haveD0 =DR , D1 =Q0, D2 =Q1, D3 =Q2.
* When the mode input (M) is 0, we haveD0 =Q1, D1 =Q2, D2 =Q3, D3 =DL.
* M = 1 → shift right operation.M = 0 → shift left operation.
M. B. Patil, IIT Bombay
Bidirectional shift register
DDD D
CLK
D3D2D1D0 Q1 Q2 Q3Q0
DL
DR
Q
M
Q
Q Q Q
Q
Q
Q
M
* When the mode input (M) is 1, we haveD0 =DR , D1 =Q0, D2 =Q1, D3 =Q2.
* When the mode input (M) is 0, we haveD0 =Q1, D1 =Q2, D2 =Q3, D3 =DL.
* M = 1 → shift right operation.M = 0 → shift left operation.
M. B. Patil, IIT Bombay
Bidirectional shift register
DDD D
CLK
D3D2D1D0 Q1 Q2 Q3Q0
DL
DR
Q
M
Q
Q Q Q
Q
Q
Q
M
* When the mode input (M) is 1, we haveD0 =DR , D1 =Q0, D2 =Q1, D3 =Q2.
* When the mode input (M) is 0, we haveD0 =Q1, D1 =Q2, D2 =Q3, D3 =DL.
* M = 1 → shift right operation.M = 0 → shift left operation.
M. B. Patil, IIT Bombay
Shift left operation
0 1 0 110 0 0 0original
numberdec. 13
2021222324252627
1 0 11 00 0 0
after
shift leftdec. 26
Shift left → × 2
M. B. Patil, IIT Bombay
Shift left operation
0 1 0 110 0 0 0original
numberdec. 13
2021222324252627
1 0 11 00 0 0
after
shift leftdec. 26
Shift left → × 2
M. B. Patil, IIT Bombay
Shift left operation
0 1 0 110 0 0 0original
numberdec. 13
2021222324252627
1 0 11 00 0 0
after
shift leftdec. 26
Shift left → × 2
M. B. Patil, IIT Bombay
Multiplication using shift and add
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 1 10
0 0 00 Z
0
Z Z
1 1 1 1 10
ZZZ
11110001
B3B2B1B0
since B0 = 1
since B1 = 0
addition
since B2 = 1
addition
since B3 = 1
addition
Note that Z = 0. We use Z to denote 0s which areindependent of the numbers being multiplied.
(decimal 143)
(decimal 13)
A3A2A1A0 (decimal 11)
initializeZ Z Z Z Z Z Z Z
Register 2 Register 1
since B0 = 1load 10111 0 1 1
add1 0 1 1 Z Z Z Z
shift1 0 1 1Z Z Z Z
since B1 = 0load 00000 0 0 0
add0 1 0 1 1 Z Z Z
shiftZ 0 1 0 1 1 Z Z
since B2 = 1load 10111 0 1 1
add1 1 0 1 1 1 Z Z
shift1 1 0 1 1 1 ZZ
since B3 = 1load 10110 1 11
add1 0 0 0 1 1 1 1 Z
shiftZ 1 0 0 0 1 1 1 1
M. B. Patil, IIT Bombay
Multiplication using shift and add
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 1 10
0 0 00 Z
0
Z Z
1 1 1 1 10
ZZZ
11110001
B3B2B1B0
since B0 = 1
since B1 = 0
addition
since B2 = 1
addition
since B3 = 1
addition
Note that Z = 0. We use Z to denote 0s which areindependent of the numbers being multiplied.
(decimal 143)
(decimal 13)
A3A2A1A0 (decimal 11)
initializeZ Z Z Z Z Z Z Z
Register 2 Register 1
since B0 = 1load 10111 0 1 1
add1 0 1 1 Z Z Z Z
shift1 0 1 1Z Z Z Z
since B1 = 0load 00000 0 0 0
add0 1 0 1 1 Z Z Z
shiftZ 0 1 0 1 1 Z Z
since B2 = 1load 10111 0 1 1
add1 1 0 1 1 1 Z Z
shift1 1 0 1 1 1 ZZ
since B3 = 1load 10110 1 11
add1 0 0 0 1 1 1 1 Z
shiftZ 1 0 0 0 1 1 1 1
M. B. Patil, IIT Bombay
Multiplication using shift and add
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 1 10
0 0 00 Z
0
Z Z
1 1 1 1 10
ZZZ
11110001
B3B2B1B0
since B0 = 1
since B1 = 0
addition
since B2 = 1
addition
since B3 = 1
addition
Note that Z = 0. We use Z to denote 0s which areindependent of the numbers being multiplied.
(decimal 143)
(decimal 13)
A3A2A1A0 (decimal 11)
initializeZ Z Z Z Z Z Z Z
Register 2 Register 1
since B0 = 1load 10111 0 1 1
add1 0 1 1 Z Z Z Z
shift1 0 1 1Z Z Z Z
since B1 = 0load 00000 0 0 0
add0 1 0 1 1 Z Z Z
shiftZ 0 1 0 1 1 Z Z
since B2 = 1load 10111 0 1 1
add1 1 0 1 1 1 Z Z
shift1 1 0 1 1 1 ZZ
since B3 = 1load 10110 1 11
add1 0 0 0 1 1 1 1 Z
shiftZ 1 0 0 0 1 1 1 1
M. B. Patil, IIT Bombay
Multiplication using shift and add
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 1 10
0 0 00 Z
0
Z Z
1 1 1 1 10
ZZZ
11110001
B3B2B1B0
since B0 = 1
since B1 = 0
addition
since B2 = 1
addition
since B3 = 1
addition
Note that Z = 0. We use Z to denote 0s which areindependent of the numbers being multiplied.
(decimal 143)
(decimal 13)
A3A2A1A0 (decimal 11)
initializeZ Z Z Z Z Z Z Z
Register 2 Register 1
since B0 = 1load 10111 0 1 1
add1 0 1 1 Z Z Z Z
shift1 0 1 1Z Z Z Z
since B1 = 0load 00000 0 0 0
add0 1 0 1 1 Z Z Z
shiftZ 0 1 0 1 1 Z Z
since B2 = 1load 10111 0 1 1
add1 1 0 1 1 1 Z Z
shift1 1 0 1 1 1 ZZ
since B3 = 1load 10110 1 11
add1 0 0 0 1 1 1 1 Z
shiftZ 1 0 0 0 1 1 1 1
M. B. Patil, IIT Bombay
Multiplication using shift and add
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 1 10
0 0 00 Z
0
Z Z
1 1 1 1 10
ZZZ
11110001
B3B2B1B0
since B0 = 1
since B1 = 0
addition
since B2 = 1
addition
since B3 = 1
addition
Note that Z = 0. We use Z to denote 0s which areindependent of the numbers being multiplied.
(decimal 143)
(decimal 13)
A3A2A1A0 (decimal 11)
initializeZ Z Z Z Z Z Z Z
Register 2 Register 1
since B0 = 1load 10111 0 1 1
add1 0 1 1 Z Z Z Z
shift1 0 1 1Z Z Z Z
since B1 = 0load 00000 0 0 0
add0 1 0 1 1 Z Z Z
shiftZ 0 1 0 1 1 Z Z
since B2 = 1load 10111 0 1 1
add1 1 0 1 1 1 Z Z
shift1 1 0 1 1 1 ZZ
since B3 = 1load 10110 1 11
add1 0 0 0 1 1 1 1 Z
shiftZ 1 0 0 0 1 1 1 1
M. B. Patil, IIT Bombay
Multiplication using shift and add
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 1 10
0 0 00 Z
0
Z Z
1 1 1 1 10
ZZZ
11110001
B3B2B1B0
since B0 = 1
since B1 = 0
addition
since B2 = 1
addition
since B3 = 1
addition
Note that Z = 0. We use Z to denote 0s which areindependent of the numbers being multiplied.
(decimal 143)
(decimal 13)
A3A2A1A0 (decimal 11)
initializeZ Z Z Z Z Z Z Z
Register 2 Register 1
since B0 = 1load 10111 0 1 1
add1 0 1 1 Z Z Z Z
shift1 0 1 1Z Z Z Z
since B1 = 0load 00000 0 0 0
add0 1 0 1 1 Z Z Z
shiftZ 0 1 0 1 1 Z Z
since B2 = 1load 10111 0 1 1
add1 1 0 1 1 1 Z Z
shift1 1 0 1 1 1 ZZ
since B3 = 1load 10110 1 11
add1 0 0 0 1 1 1 1 Z
shiftZ 1 0 0 0 1 1 1 1
M. B. Patil, IIT Bombay
Multiplication using shift and add
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 1 10
0 0 00 Z
0
Z Z
1 1 1 1 10
ZZZ
11110001
B3B2B1B0
since B0 = 1
since B1 = 0
addition
since B2 = 1
addition
since B3 = 1
addition
Note that Z = 0. We use Z to denote 0s which areindependent of the numbers being multiplied.
(decimal 143)
(decimal 13)
A3A2A1A0 (decimal 11)
initializeZ Z Z Z Z Z Z Z
Register 2 Register 1
since B0 = 1load 10111 0 1 1
add1 0 1 1 Z Z Z Z
shift1 0 1 1Z Z Z Z
since B1 = 0load 00000 0 0 0
add0 1 0 1 1 Z Z Z
shiftZ 0 1 0 1 1 Z Z
since B2 = 1load 10111 0 1 1
add1 1 0 1 1 1 Z Z
shift1 1 0 1 1 1 ZZ
since B3 = 1load 10110 1 11
add1 0 0 0 1 1 1 1 Z
shiftZ 1 0 0 0 1 1 1 1
M. B. Patil, IIT Bombay
Multiplication using shift and add
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 1 10
0 0 00 Z
0
Z Z
1 1 1 1 10
ZZZ
11110001
B3B2B1B0
since B0 = 1
since B1 = 0
addition
since B2 = 1
addition
since B3 = 1
addition
Note that Z = 0. We use Z to denote 0s which areindependent of the numbers being multiplied.
(decimal 143)
(decimal 13)
A3A2A1A0 (decimal 11)
initializeZ Z Z Z Z Z Z Z
Register 2 Register 1
since B0 = 1load 10111 0 1 1
add1 0 1 1 Z Z Z Z
shift1 0 1 1Z Z Z Z
since B1 = 0load 00000 0 0 0
add0 1 0 1 1 Z Z Z
shiftZ 0 1 0 1 1 Z Z
since B2 = 1load 10111 0 1 1
add1 1 0 1 1 1 Z Z
shift1 1 0 1 1 1 ZZ
since B3 = 1load 10110 1 11
add1 0 0 0 1 1 1 1 Z
shiftZ 1 0 0 0 1 1 1 1
M. B. Patil, IIT Bombay
Multiplication using shift and add
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 1 10
0 0 00 Z
0
Z Z
1 1 1 1 10
ZZZ
11110001
B3B2B1B0
since B0 = 1
since B1 = 0
addition
since B2 = 1
addition
since B3 = 1
addition
Note that Z = 0. We use Z to denote 0s which areindependent of the numbers being multiplied.
(decimal 143)
(decimal 13)
A3A2A1A0 (decimal 11)
initializeZ Z Z Z Z Z Z Z
Register 2 Register 1
since B0 = 1load 10111 0 1 1
add1 0 1 1 Z Z Z Z
shift1 0 1 1Z Z Z Z
since B1 = 0load 00000 0 0 0
add0 1 0 1 1 Z Z Z
shiftZ 0 1 0 1 1 Z Z
since B2 = 1load 10111 0 1 1
add1 1 0 1 1 1 Z Z
shift1 1 0 1 1 1 ZZ
since B3 = 1load 10110 1 11
add1 0 0 0 1 1 1 1 Z
shiftZ 1 0 0 0 1 1 1 1
M. B. Patil, IIT Bombay
Multiplication using shift and add
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 1 10
0 0 00 Z
0
Z Z
1 1 1 1 10
ZZZ
11110001
B3B2B1B0
since B0 = 1
since B1 = 0
addition
since B2 = 1
addition
since B3 = 1
addition
Note that Z = 0. We use Z to denote 0s which areindependent of the numbers being multiplied.
(decimal 143)
(decimal 13)
A3A2A1A0 (decimal 11)
initializeZ Z Z Z Z Z Z Z
Register 2 Register 1
since B0 = 1load 10111 0 1 1
add1 0 1 1 Z Z Z Z
shift1 0 1 1Z Z Z Z
since B1 = 0load 00000 0 0 0
add0 1 0 1 1 Z Z Z
shiftZ 0 1 0 1 1 Z Z
since B2 = 1load 10111 0 1 1
add1 1 0 1 1 1 Z Z
shift1 1 0 1 1 1 ZZ
since B3 = 1load 10110 1 11
add1 0 0 0 1 1 1 1 Z
shiftZ 1 0 0 0 1 1 1 1
M. B. Patil, IIT Bombay
Multiplication using shift and add
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 1 10
0 0 00 Z
0
Z Z
1 1 1 1 10
ZZZ
11110001
B3B2B1B0
since B0 = 1
since B1 = 0
addition
since B2 = 1
addition
since B3 = 1
addition
Note that Z = 0. We use Z to denote 0s which areindependent of the numbers being multiplied.
(decimal 143)
(decimal 13)
A3A2A1A0 (decimal 11)
initializeZ Z Z Z Z Z Z Z
Register 2 Register 1
since B0 = 1load 10111 0 1 1
add1 0 1 1 Z Z Z Z
shift1 0 1 1Z Z Z Z
since B1 = 0load 00000 0 0 0
add0 1 0 1 1 Z Z Z
shiftZ 0 1 0 1 1 Z Z
since B2 = 1load 10111 0 1 1
add1 1 0 1 1 1 Z Z
shift1 1 0 1 1 1 ZZ
since B3 = 1load 10110 1 11
add1 0 0 0 1 1 1 1 Z
shiftZ 1 0 0 0 1 1 1 1
M. B. Patil, IIT Bombay
Multiplication using shift and add
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 1 10
0 0 00 Z
0
Z Z
1 1 1 1 10
ZZZ
11110001
B3B2B1B0
since B0 = 1
since B1 = 0
addition
since B2 = 1
addition
since B3 = 1
addition
Note that Z = 0. We use Z to denote 0s which areindependent of the numbers being multiplied.
(decimal 143)
(decimal 13)
A3A2A1A0 (decimal 11)
initializeZ Z Z Z Z Z Z Z
Register 2 Register 1
since B0 = 1load 10111 0 1 1
add1 0 1 1 Z Z Z Z
shift1 0 1 1Z Z Z Z
since B1 = 0load 00000 0 0 0
add0 1 0 1 1 Z Z Z
shiftZ 0 1 0 1 1 Z Z
since B2 = 1load 10111 0 1 1
add1 1 0 1 1 1 Z Z
shift1 1 0 1 1 1 ZZ
since B3 = 1load 10110 1 11
add1 0 0 0 1 1 1 1 Z
shiftZ 1 0 0 0 1 1 1 1
M. B. Patil, IIT Bombay
Multiplication using shift and add
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 1 10
0 0 00 Z
0
Z Z
1 1 1 1 10
ZZZ
11110001
B3B2B1B0
since B0 = 1
since B1 = 0
addition
since B2 = 1
addition
since B3 = 1
addition
Note that Z = 0. We use Z to denote 0s which areindependent of the numbers being multiplied.
(decimal 143)
(decimal 13)
A3A2A1A0 (decimal 11)
initializeZ Z Z Z Z Z Z Z
Register 2 Register 1
since B0 = 1load 10111 0 1 1
add1 0 1 1 Z Z Z Z
shift1 0 1 1Z Z Z Z
since B1 = 0load 00000 0 0 0
add0 1 0 1 1 Z Z Z
shiftZ 0 1 0 1 1 Z Z
since B2 = 1load 10111 0 1 1
add1 1 0 1 1 1 Z Z
shift1 1 0 1 1 1 ZZ
since B3 = 1load 10110 1 11
add1 0 0 0 1 1 1 1 Z
shiftZ 1 0 0 0 1 1 1 1
M. B. Patil, IIT Bombay
Multiplication using shift and add
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 1 10
0 0 00 Z
0
Z Z
1 1 1 1 10
ZZZ
11110001
B3B2B1B0
since B0 = 1
since B1 = 0
addition
since B2 = 1
addition
since B3 = 1
addition
Note that Z = 0. We use Z to denote 0s which areindependent of the numbers being multiplied.
(decimal 143)
(decimal 13)
A3A2A1A0 (decimal 11)
initializeZ Z Z Z Z Z Z Z
Register 2 Register 1
since B0 = 1load 10111 0 1 1
add1 0 1 1 Z Z Z Z
shift1 0 1 1Z Z Z Z
since B1 = 0load 00000 0 0 0
add0 1 0 1 1 Z Z Z
shiftZ 0 1 0 1 1 Z Z
since B2 = 1load 10111 0 1 1
add1 1 0 1 1 1 Z Z
shift1 1 0 1 1 1 ZZ
since B3 = 1load 10110 1 11
add1 0 0 0 1 1 1 1 Z
shiftZ 1 0 0 0 1 1 1 1M. B. Patil, IIT Bombay
K K K K
J0
1
J J J
CLK
Clear
t
t
t
Clear
Load
CLK
Load
RdRd
SdSd
Rd
Sd
Rd
SdQ3 Q0
Q0=A3
A3 A0A2 A1
Q0=A2
Q
Q0=A1Q0=A0
Q1Q
Q2Q
Q
Q
Q
00 000 0 00 0 0 0
* All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop.
* Subsequently, with every clock pulse, the data shifts right and appears serially at the output Q0.→ parallel in-serial out data movement
M. B. Patil, IIT Bombay
K K K K
J0
1
J J J
CLK
Clear
t
t
t
Clear
Load
CLK
Load
RdRd
SdSd
Rd
Sd
Rd
SdQ3 Q0
Q0=A3
A3 A0A2 A1
Q0=A2
Q
Q0=A1Q0=A0
Q1Q
Q2Q
Q
Q
Q
00 000 0 00 0 0 0
* All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop.
* Subsequently, with every clock pulse, the data shifts right and appears serially at the output Q0.→ parallel in-serial out data movement
M. B. Patil, IIT Bombay
K K K K
J0
1
J J J
CLK
Clear
t
t
t
Clear
Load
CLK
Load
RdRd
SdSd
Rd
Sd
Rd
SdQ3 Q0
Q0=A3
A3 A0A2 A1
Q0=A2
Q
Q0=A1Q0=A0
Q1Q
Q2Q
Q
Q
Q
00 000 0 00 0 0 0
* All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop.
* Subsequently, with every clock pulse, the data shifts right and appears serially at the output Q0.→ parallel in-serial out data movement
M. B. Patil, IIT Bombay
K K K K
J0
1
J J J
CLK
Clear
t
t
t
Clear
Load
CLK
Load
RdRd
SdSd
Rd
Sd
Rd
SdQ3 Q0
Q0=A3
A3 A0A2 A1
Q0=A2
Q
Q0=A1Q0=A0
Q1Q
Q2Q
Q
Q
Q
00 000 0 00 0 0 0
* All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop.
* Subsequently, with every clock pulse, the data shifts right and appears serially at the output Q0.→ parallel in-serial out data movement
M. B. Patil, IIT Bombay
K K K K
J0
1
J J J
CLK
Clear
t
t
t
Clear
Load
CLK
Load
RdRd
SdSd
Rd
Sd
Rd
SdQ3 Q0
Q0=A3
A3 A0A2 A1
Q0=A2
Q
Q0=A1Q0=A0
Q1Q
Q2Q
Q
Q
Q
00 000 0 00 0 0 0
* All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop.
* Subsequently, with every clock pulse, the data shifts right and appears serially at the output Q0.→ parallel in-serial out data movement
M. B. Patil, IIT Bombay
K K K K
J0
1
J J J
CLK
Clear
t
t
t
Clear
Load
CLK
Load
RdRd
SdSd
Rd
Sd
Rd
SdQ3 Q0
Q0=A3
A3 A0A2 A1
Q0=A2
Q
Q0=A1Q0=A0
Q1Q
Q2Q
Q
Q
Q
00 000 0 00 0 0 0
* All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop.
* Subsequently, with every clock pulse, the data shifts right and appears serially at the output Q0.→ parallel in-serial out data movement
M. B. Patil, IIT Bombay
K K K K
J0
1
J J J
CLK
Clear
t
t
t
Clear
Load
CLK
Load
RdRd
SdSd
Rd
Sd
Rd
SdQ3 Q0
Q0=A3
A3 A0A2 A1
Q0=A2
Q
Q0=A1Q0=A0
Q1Q
Q2Q
Q
Q
Q
00
000 0 00 0 0 0
* All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop.
* Subsequently, with every clock pulse, the data shifts right and appears serially at the output Q0.→ parallel in-serial out data movement
M. B. Patil, IIT Bombay
K K K K
J0
1
J J J
CLK
Clear
t
t
t
Clear
Load
CLK
Load
RdRd
SdSd
Rd
Sd
Rd
SdQ3 Q0
Q0=A3
A3 A0A2 A1
Q0=A2
Q
Q0=A1Q0=A0
Q1Q
Q2Q
Q
Q
Q
00 00
0 0 00 0 0 0
* All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop.
* Subsequently, with every clock pulse, the data shifts right and appears serially at the output Q0.→ parallel in-serial out data movement
M. B. Patil, IIT Bombay
K K K K
J0
1
J J J
CLK
Clear
t
t
t
Clear
Load
CLK
Load
RdRd
SdSd
Rd
Sd
Rd
SdQ3 Q0
Q0=A3
A3 A0A2 A1
Q0=A2
Q
Q0=A1Q0=A0
Q1Q
Q2Q
Q
Q
Q
00 000 0 0
0 0 0 0
* All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop.
* Subsequently, with every clock pulse, the data shifts right and appears serially at the output Q0.→ parallel in-serial out data movement
M. B. Patil, IIT Bombay
K K K K
J0
1
J J J
CLK
Clear
t
t
t
Clear
Load
CLK
Load
RdRd
SdSd
Rd
Sd
Rd
SdQ3 Q0
Q0=A3
A3 A0A2 A1
Q0=A2
Q
Q0=A1Q0=A0
Q1Q
Q2Q
Q
Q
Q
00 000 0 00 0 0 0
* All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop.
* Subsequently, with every clock pulse, the data shifts right and appears serially at the output Q0.→ parallel in-serial out data movement
M. B. Patil, IIT Bombay
Counters
Reset
State transition diagram General configuration
Clock Counter
Decodinglogic
k
1
2
3
4
Q0
Q1
Q2
QN−1
* A counter with k states is called a modulo-k (mod-k) counter.
* A counter can be made with flip-flops, each flip-flop serving as a memory element with two states (0 or 1).
* If there are N flip-flops in a counter, there are 2N possible states (since each flip-flop can have Q = 0 orQ = 1). It is possible to exclude some of these states.→ N flip-flops can be used to make a mod-k counter with k ≤ 2N .
* Typically, a reset facility is also provided, which can be used to force a certain state to initialize thecounter.
M. B. Patil, IIT Bombay
Counters
Reset
State transition diagram General configuration
Clock Counter
Decodinglogic
k
1
2
3
4
Q0
Q1
Q2
QN−1
* A counter with k states is called a modulo-k (mod-k) counter.
* A counter can be made with flip-flops, each flip-flop serving as a memory element with two states (0 or 1).
* If there are N flip-flops in a counter, there are 2N possible states (since each flip-flop can have Q = 0 orQ = 1). It is possible to exclude some of these states.→ N flip-flops can be used to make a mod-k counter with k ≤ 2N .
* Typically, a reset facility is also provided, which can be used to force a certain state to initialize thecounter.
M. B. Patil, IIT Bombay
Counters
Reset
State transition diagram General configuration
Clock Counter
Decodinglogic
k
1
2
3
4
Q0
Q1
Q2
QN−1
* A counter with k states is called a modulo-k (mod-k) counter.
* A counter can be made with flip-flops, each flip-flop serving as a memory element with two states (0 or 1).
* If there are N flip-flops in a counter, there are 2N possible states (since each flip-flop can have Q = 0 orQ = 1). It is possible to exclude some of these states.→ N flip-flops can be used to make a mod-k counter with k ≤ 2N .
* Typically, a reset facility is also provided, which can be used to force a certain state to initialize thecounter.
M. B. Patil, IIT Bombay
Counters
Reset
State transition diagram General configuration
Clock Counter
Decodinglogic
k
1
2
3
4
Q0
Q1
Q2
QN−1
* A counter with k states is called a modulo-k (mod-k) counter.
* A counter can be made with flip-flops, each flip-flop serving as a memory element with two states (0 or 1).
* If there are N flip-flops in a counter, there are 2N possible states (since each flip-flop can have Q = 0 orQ = 1). It is possible to exclude some of these states.→ N flip-flops can be used to make a mod-k counter with k ≤ 2N .
* Typically, a reset facility is also provided, which can be used to force a certain state to initialize thecounter.
M. B. Patil, IIT Bombay
Counters
Reset
State transition diagram General configuration
Clock Counter
Decodinglogic
k
1
2
3
4
Q0
Q1
Q2
QN−1
* A counter with k states is called a modulo-k (mod-k) counter.
* A counter can be made with flip-flops, each flip-flop serving as a memory element with two states (0 or 1).
* If there are N flip-flops in a counter, there are 2N possible states (since each flip-flop can have Q = 0 orQ = 1). It is possible to exclude some of these states.→ N flip-flops can be used to make a mod-k counter with k ≤ 2N .
* Typically, a reset facility is also provided, which can be used to force a certain state to initialize thecounter.
M. B. Patil, IIT Bombay
Counters: example
1
t
t
t
State transition diagram
k
1
2
3
4
CLK
CLK
t
state
0 1 1 0 1 0
0
01
01
11
110
0 0
0
1
0
1
0
1
t5t4t3t2t1
QJ
QK
QJ
QK
QJ
QK
Q0 Q1 Q2
01
2
3
4
5
1
Q0
Q1
Q2
1 1 0
1 1 1
0 1 1
1 0 1
0 0 0
0 0
Q1Q0 Q2
M. B. Patil, IIT Bombay
Counters
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1
CLK
X
8T
t
t
Reset
Clock Counter
Decodinglogic
k
1
2
3
4
Q0
Q1
Q2
QN−1
X is 1 for state 3; else, it is 0.
* The counter outputs (i.e., the flip-flop outputs, Q0, Q1, · · · QN−1) can be decoded using appropriate logic.* In particular, it is possible to have a decoder output (say, X ) which is 1 only for state i , and 0 otherwise.→ For k clock pulses, we get a single pulse at X , i.e., the clock frequency has been divided by k. For this reason, amod-k counter is also called a divide-by-k counter.
M. B. Patil, IIT Bombay
Counters
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1
CLK
X
8T
t
t
Reset
Clock Counter
Decodinglogic
k
1
2
3
4
Q0
Q1
Q2
QN−1
X is 1 for state 3; else, it is 0.
* The counter outputs (i.e., the flip-flop outputs, Q0, Q1, · · · QN−1) can be decoded using appropriate logic.
* In particular, it is possible to have a decoder output (say, X ) which is 1 only for state i , and 0 otherwise.→ For k clock pulses, we get a single pulse at X , i.e., the clock frequency has been divided by k. For this reason, amod-k counter is also called a divide-by-k counter.
M. B. Patil, IIT Bombay
Counters
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1
CLK
X
8T
t
t
Reset
Clock Counter
Decodinglogic
k
1
2
3
4
Q0
Q1
Q2
QN−1
X is 1 for state 3; else, it is 0.
* The counter outputs (i.e., the flip-flop outputs, Q0, Q1, · · · QN−1) can be decoded using appropriate logic.* In particular, it is possible to have a decoder output (say, X ) which is 1 only for state i , and 0 otherwise.→ For k clock pulses, we get a single pulse at X , i.e., the clock frequency has been divided by k. For this reason, amod-k counter is also called a divide-by-k counter.
M. B. Patil, IIT Bombay
A binary ripple counter
K
J
K K
J
t
t
t
t
CLK
J
FF0 FF1 FF2CLK
1
Q0
Q1 Q2Q0
Q1
Q2
Q Q
Q Q
Q
Q
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
1
1
00 repeats
Q2 Q1 Q0
* J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge arrives.* For FF1 and FF2, Q0 and Q1, respectively, provide the clock.* Note that the direct inputs Sd and Rd (not shown) are assumed to be Sd = Rd = 0 for all flip-flops, allowing normal
flip-flip operation.
M. B. Patil, IIT Bombay
A binary ripple counter
K
J
K K
J
t
t
t
t
CLK
J
FF0 FF1 FF2CLK
1
Q0
Q1 Q2Q0
Q1
Q2
Q Q
Q Q
Q
Q
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
1
1
00 repeats
Q2 Q1 Q0
* J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.
* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge arrives.* For FF1 and FF2, Q0 and Q1, respectively, provide the clock.* Note that the direct inputs Sd and Rd (not shown) are assumed to be Sd = Rd = 0 for all flip-flops, allowing normal
flip-flip operation.
M. B. Patil, IIT Bombay
A binary ripple counter
K
J
K K
J
t
t
t
t
CLK
J
FF0 FF1 FF2CLK
1
Q0
Q1 Q2Q0
Q1
Q2
Q Q
Q Q
Q
Q
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
1
1
00 repeats
Q2 Q1 Q0
* J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge arrives.
* For FF1 and FF2, Q0 and Q1, respectively, provide the clock.* Note that the direct inputs Sd and Rd (not shown) are assumed to be Sd = Rd = 0 for all flip-flops, allowing normal
flip-flip operation.
M. B. Patil, IIT Bombay
A binary ripple counter
K
J
K K
J
t
t
t
t
CLK
J
FF0 FF1 FF2CLK
1
Q0
Q1 Q2Q0
Q1
Q2
Q Q
Q Q
Q
Q
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
1
1
00 repeats
Q2 Q1 Q0
* J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge arrives.* For FF1 and FF2, Q0 and Q1, respectively, provide the clock.
* Note that the direct inputs Sd and Rd (not shown) are assumed to be Sd = Rd = 0 for all flip-flops, allowing normalflip-flip operation.
M. B. Patil, IIT Bombay
A binary ripple counter
K
J
K K
J
t
t
t
t
CLK
J
FF0 FF1 FF2CLK
1
Q0
Q1 Q2Q0
Q1
Q2
Q Q
Q Q
Q
Q
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
1
1
00 repeats
Q2 Q1 Q0
* J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge arrives.* For FF1 and FF2, Q0 and Q1, respectively, provide the clock.
* Note that the direct inputs Sd and Rd (not shown) are assumed to be Sd = Rd = 0 for all flip-flops, allowing normalflip-flip operation.
M. B. Patil, IIT Bombay
A binary ripple counter
K
J
K K
J
t
t
t
t
CLK
J
FF0 FF1 FF2CLK
1
Q0
Q1 Q2Q0
Q1
Q2
Q Q
Q Q
Q
Q
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
1
1
00 repeats
Q2 Q1 Q0
* J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge arrives.* For FF1 and FF2, Q0 and Q1, respectively, provide the clock.
* Note that the direct inputs Sd and Rd (not shown) are assumed to be Sd = Rd = 0 for all flip-flops, allowing normalflip-flip operation.
M. B. Patil, IIT Bombay
A binary ripple counter
K
J
K K
J
t
t
t
t
CLK
J
FF0 FF1 FF2CLK
1
Q0
Q1 Q2Q0
Q1
Q2
Q Q
Q Q
Q
Q
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
1
1
00 repeats
Q2 Q1 Q0
* J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge arrives.* For FF1 and FF2, Q0 and Q1, respectively, provide the clock.
* Note that the direct inputs Sd and Rd (not shown) are assumed to be Sd = Rd = 0 for all flip-flops, allowing normalflip-flip operation.
M. B. Patil, IIT Bombay
A binary ripple counter
K
J
K K
J
t
t
t
t
CLK
J
FF0 FF1 FF2CLK
1
Q0
Q1 Q2Q0
Q1
Q2
Q Q
Q Q
Q
Q
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
1
1
00 repeats
Q2 Q1 Q0
* J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge arrives.* For FF1 and FF2, Q0 and Q1, respectively, provide the clock.
* Note that the direct inputs Sd and Rd (not shown) are assumed to be Sd = Rd = 0 for all flip-flops, allowing normalflip-flip operation.
M. B. Patil, IIT Bombay
A binary ripple counter
K
J
K K
J
t
t
t
t
CLK
J
FF0 FF1 FF2CLK
1
Q0
Q1 Q2Q0
Q1
Q2
Q Q
Q Q
Q
Q
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
1
1
00 repeats
Q2 Q1 Q0
* J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge arrives.* For FF1 and FF2, Q0 and Q1, respectively, provide the clock.* Note that the direct inputs Sd and Rd (not shown) are assumed to be Sd = Rd = 0 for all flip-flops, allowing normal
flip-flip operation. M. B. Patil, IIT Bombay
A binary ripple counter
K
J
K K
J
t
t
t
t
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
0
1
1
0
CLK
J
FF0 FF1 FF2CLK
1
00 repeats
Q2 Q1
Q0
Q1 Q2Q0
Q1
Q2
Q0
Q Q
Q Q
Q
Q
* The counter has 8 states, Q2Q1Q0 = 000, 001, 010, 011, 100, 101, 110, 111.→ it is a mod-8 counter. In particular, it is a binary, mod-8, up counter (since it counts up from 000 to 111).
* If the clock frequency is fc , the frequency at the Q0, Q1, Q2 outputs is fc/2, fc/4, fc/8, respectively. For this counter,therefore, div-by-2, div-by-4, div-by-8 outputs are already available, without requiring decoding logic.
* This type of counter is called a “ripple” counter since the clock transitions ripple through the flip-flops.
M. B. Patil, IIT Bombay
A binary ripple counter
K
J
K K
J
t
t
t
t
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
0
1
1
0
CLK
J
FF0 FF1 FF2CLK
1
00 repeats
Q2 Q1
Q0
Q1 Q2Q0
Q1
Q2
Q0
Q Q
Q Q
Q
Q
* The counter has 8 states, Q2Q1Q0 = 000, 001, 010, 011, 100, 101, 110, 111.→ it is a mod-8 counter. In particular, it is a binary, mod-8, up counter (since it counts up from 000 to 111).
* If the clock frequency is fc , the frequency at the Q0, Q1, Q2 outputs is fc/2, fc/4, fc/8, respectively. For this counter,therefore, div-by-2, div-by-4, div-by-8 outputs are already available, without requiring decoding logic.
* This type of counter is called a “ripple” counter since the clock transitions ripple through the flip-flops.
M. B. Patil, IIT Bombay
A binary ripple counter
K
J
K K
J
t
t
t
t
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
0
1
1
0
CLK
J
FF0 FF1 FF2CLK
1
00 repeats
Q2 Q1
Q0
Q1 Q2Q0
Q1
Q2
Q0
Q Q
Q Q
Q
Q
* The counter has 8 states, Q2Q1Q0 = 000, 001, 010, 011, 100, 101, 110, 111.→ it is a mod-8 counter. In particular, it is a binary, mod-8, up counter (since it counts up from 000 to 111).
* If the clock frequency is fc , the frequency at the Q0, Q1, Q2 outputs is fc/2, fc/4, fc/8, respectively. For this counter,therefore, div-by-2, div-by-4, div-by-8 outputs are already available, without requiring decoding logic.
* This type of counter is called a “ripple” counter since the clock transitions ripple through the flip-flops.
M. B. Patil, IIT Bombay
A binary ripple counter
K
J
K K
J
t
t
t
t
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
0
1
1
0
CLK
J
FF0 FF1 FF2CLK
1
00 repeats
Q2 Q1
Q0
Q1 Q2Q0
Q1
Q2
Q0
Q Q
Q Q
Q
Q
* The counter has 8 states, Q2Q1Q0 = 000, 001, 010, 011, 100, 101, 110, 111.→ it is a mod-8 counter. In particular, it is a binary, mod-8, up counter (since it counts up from 000 to 111).
* If the clock frequency is fc , the frequency at the Q0, Q1, Q2 outputs is fc/2, fc/4, fc/8, respectively. For this counter,therefore, div-by-2, div-by-4, div-by-8 outputs are already available, without requiring decoding logic.
* This type of counter is called a “ripple” counter since the clock transitions ripple through the flip-flops. M. B. Patil, IIT Bombay
A binary ripple counter
K
J
K K
J
t
t
t
t
0
1
1
0
0
1
1
0
0
0
1
1
1
1
0
0
0
0
1
0
1
0
0
1
1
0
CLK
J
FF0 FF1 FF2CLK
1
00 repeats
Q2 Q1
Q0
Q1 Q2Q0
Q1
Q2
Q0
Q Q
Q Q
Q
Q
* If positive edge-triggered flip-flops are used, we get a binary down counter (counting down from 111 to 000).
M. B. Patil, IIT Bombay
A binary ripple counter
K
J
K K
J
t
t
t
t
0
1
1
0
0
1
1
0
0
0
1
1
1
1
0
0
0
0
1
0
1
0
0
1
1
0
CLK
J
FF0 FF1 FF2CLK
1
00 repeats
Q2 Q1
Q0
Q1 Q2Q0
Q1
Q2
Q0
Q Q
Q Q
Q
Q
* If positive edge-triggered flip-flops are used, we get a binary down counter (counting down from 111 to 000).
M. B. Patil, IIT Bombay
Binary ripple counters
1
J
K
J
K
J
K K
J
KK
J J
1
FF0 FF1 FF2
FF0 FF1 FF2
CLK
CLK
Q0
Q0
Q1
Q1
Q2
Q2
Q
Q
Q
Q
Q
Q
Q
Q Q
Q
Q
Q
* Home work: Sketch the waveforms (CLK, Q0, Q1, Q2), and tabulate the counter states in each case.
M. B. Patil, IIT Bombay
Up-down binary ripple counters
CLK
K K
J
K
JJ
FF0 FF1 FF2CLK
1
t
t
t
t
CLK
t
t
t
t
M=1 M=0
Q0 Q1 Q2
Q0
Q1
Q2
Q0
Q1
Q2
Q Q
Q Q
Q
Q
M
M
* When Mode (M) = 1, the counter counts up; else, it counts down. (SEQUEL file: ee101 counter 3.sqproj)
M. B. Patil, IIT Bombay
Up-down binary ripple counters
CLK
K K
J
K
JJ
FF0 FF1 FF2CLK
1
t
t
t
t
CLK
t
t
t
t
M=1 M=0
Q0 Q1 Q2
Q0
Q1
Q2
Q0
Q1
Q2
Q Q
Q Q
Q
Q
M
M
* When Mode (M) = 1, the counter counts up; else, it counts down. (SEQUEL file: ee101 counter 3.sqproj)
M. B. Patil, IIT Bombay
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0 01 1
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
K K
J J
K
J
K
0
J
FF0 FF1 FF2 FF3CLK
1
0 0 0 0 repeats
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
time (msec)
Q2Q3
Q3
Q2
Q1
Q0
Q1
Q3Q2Q1Q0
Q0
Q
Q
Q
Q
Q
Q Q
Q
Rd Rd
Sd Sd Sd
Rd Rd
Sd
SEQUEL file: ee101 counter 5.sqproj
Decade counter using direct inputs
* When the counter reachesQ3Q2Q1Q0 = 1010 (i.e., decimal 10),Q3Q1 = 1, and the flip-flops arecleared to Q3Q2Q1Q0 = 0000.
* The counter counts from 0000(decimal 0) to 1001 (decimal 9)→ “decade counter.”
M. B. Patil, IIT Bombay
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0 01 1
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
K K
J J
K
J
K
0
J
FF0 FF1 FF2 FF3CLK
1
0 0 0 0 repeats
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
time (msec)
Q2Q3
Q3
Q2
Q1
Q0
Q1
Q3Q2Q1Q0
Q0
Q
Q
Q
Q
Q
Q Q
Q
Rd Rd
Sd Sd Sd
Rd Rd
Sd
SEQUEL file: ee101 counter 5.sqproj
Decade counter using direct inputs
* When the counter reachesQ3Q2Q1Q0 = 1010 (i.e., decimal 10),Q3Q1 = 1, and the flip-flops arecleared to Q3Q2Q1Q0 = 0000.
* The counter counts from 0000(decimal 0) to 1001 (decimal 9)→ “decade counter.”
M. B. Patil, IIT Bombay
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0 01 1
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
K K
J J
K
J
K
0
J
FF0 FF1 FF2 FF3CLK
1
0 0 0 0 repeats
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
time (msec)
Q2Q3
Q3
Q2
Q1
Q0
Q1
Q3Q2Q1Q0
Q0
Q
Q
Q
Q
Q
Q Q
Q
Rd Rd
Sd Sd Sd
Rd Rd
Sd
SEQUEL file: ee101 counter 5.sqproj
Decade counter using direct inputs
* When the counter reachesQ3Q2Q1Q0 = 1010 (i.e., decimal 10),Q3Q1 = 1, and the flip-flops arecleared to Q3Q2Q1Q0 = 0000.
* The counter counts from 0000(decimal 0) to 1001 (decimal 9)→ “decade counter.”
M. B. Patil, IIT Bombay
A synchronous counter
K
J
K
J
K
J
K
1
t
t
t
t
t
J
FF0 FF1 FF2 FF3
CLK
CLK
Q0 Q1 Q2 Q3
Q0
Q1
Q2
Q3
Q
Q
Q
Q
Q
Q
Q
Q
* Since all flip-flops are driven by the same clock, the counter is called a “synchronous” counter.* J0 = K0 = 1, J1 = K1 = Q0, J2 = K2 = Q1Q0, J3 = K3 = Q2Q1Q0.* FF0 toggles after every active edge.
FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state. (Similarly, for FF2 and FF3)* From the waveforms, we see that it is a binary up counter.
M. B. Patil, IIT Bombay
A synchronous counter
K
J
K
J
K
J
K
1
t
t
t
t
t
J
FF0 FF1 FF2 FF3
CLK
CLK
Q0 Q1 Q2 Q3
Q0
Q1
Q2
Q3
Q
Q
Q
Q
Q
Q
Q
Q
* Since all flip-flops are driven by the same clock, the counter is called a “synchronous” counter.
* J0 = K0 = 1, J1 = K1 = Q0, J2 = K2 = Q1Q0, J3 = K3 = Q2Q1Q0.* FF0 toggles after every active edge.
FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state. (Similarly, for FF2 and FF3)* From the waveforms, we see that it is a binary up counter.
M. B. Patil, IIT Bombay
A synchronous counter
K
J
K
J
K
J
K
1
t
t
t
t
t
J
FF0 FF1 FF2 FF3
CLK
CLK
Q0 Q1 Q2 Q3
Q0
Q1
Q2
Q3
Q
Q
Q
Q
Q
Q
Q
Q
* Since all flip-flops are driven by the same clock, the counter is called a “synchronous” counter.* J0 = K0 = 1, J1 = K1 = Q0, J2 = K2 = Q1Q0, J3 = K3 = Q2Q1Q0.
* FF0 toggles after every active edge.FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state. (Similarly, for FF2 and FF3)
* From the waveforms, we see that it is a binary up counter.
M. B. Patil, IIT Bombay
A synchronous counter
K
J
K
J
K
J
K
1
t
t
t
t
t
J
FF0 FF1 FF2 FF3
CLK
CLK
Q0 Q1 Q2 Q3
Q0
Q1
Q2
Q3
Q
Q
Q
Q
Q
Q
Q
Q
* Since all flip-flops are driven by the same clock, the counter is called a “synchronous” counter.* J0 = K0 = 1, J1 = K1 = Q0, J2 = K2 = Q1Q0, J3 = K3 = Q2Q1Q0.* FF0 toggles after every active edge.
FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state. (Similarly, for FF2 and FF3)
* From the waveforms, we see that it is a binary up counter.
M. B. Patil, IIT Bombay
A synchronous counter
K
J
K
J
K
J
K
1
t
t
t
t
t
J
FF0 FF1 FF2 FF3
CLK
CLK
Q0 Q1 Q2 Q3
Q0
Q1
Q2
Q3
Q
Q
Q
Q
Q
Q
Q
Q
* Since all flip-flops are driven by the same clock, the counter is called a “synchronous” counter.* J0 = K0 = 1, J1 = K1 = Q0, J2 = K2 = Q1Q0, J3 = K3 = Q2Q1Q0.* FF0 toggles after every active edge.
FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state. (Similarly, for FF2 and FF3)
* From the waveforms, we see that it is a binary up counter.
M. B. Patil, IIT Bombay
A synchronous counter
K
J
K
J
K
J
K
1
t
t
t
t
t
J
FF0 FF1 FF2 FF3
CLK
CLK
Q0 Q1 Q2 Q3
Q0
Q1
Q2
Q3
Q
Q
Q
Q
Q
Q
Q
Q
* Since all flip-flops are driven by the same clock, the counter is called a “synchronous” counter.* J0 = K0 = 1, J1 = K1 = Q0, J2 = K2 = Q1Q0, J3 = K3 = Q2Q1Q0.* FF0 toggles after every active edge.
FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state. (Similarly, for FF2 and FF3)
* From the waveforms, we see that it is a binary up counter.
M. B. Patil, IIT Bombay
A synchronous counter
K
J
K
J
K
J
K
1
t
t
t
t
t
J
FF0 FF1 FF2 FF3
CLK
CLK
Q0 Q1 Q2 Q3
Q0
Q1
Q2
Q3
Q
Q
Q
Q
Q
Q
Q
Q
* Since all flip-flops are driven by the same clock, the counter is called a “synchronous” counter.* J0 = K0 = 1, J1 = K1 = Q0, J2 = K2 = Q1Q0, J3 = K3 = Q2Q1Q0.* FF0 toggles after every active edge.
FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state. (Similarly, for FF2 and FF3)
* From the waveforms, we see that it is a binary up counter.
M. B. Patil, IIT Bombay
A synchronous counter
K
J
K
J
K
J
K
1
t
t
t
t
t
J
FF0 FF1 FF2 FF3
CLK
CLK
Q0 Q1 Q2 Q3
Q0
Q1
Q2
Q3
Q
Q
Q
Q
Q
Q
Q
Q
* Since all flip-flops are driven by the same clock, the counter is called a “synchronous” counter.* J0 = K0 = 1, J1 = K1 = Q0, J2 = K2 = Q1Q0, J3 = K3 = Q2Q1Q0.* FF0 toggles after every active edge.
FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state. (Similarly, for FF2 and FF3)
* From the waveforms, we see that it is a binary up counter.
M. B. Patil, IIT Bombay
A synchronous counter
K
J
K
J
K
J
K
1
t
t
t
t
t
J
FF0 FF1 FF2 FF3
CLK
CLK
Q0 Q1 Q2 Q3
Q0
Q1
Q2
Q3
Q
Q
Q
Q
Q
Q
Q
Q
* Since all flip-flops are driven by the same clock, the counter is called a “synchronous” counter.* J0 = K0 = 1, J1 = K1 = Q0, J2 = K2 = Q1Q0, J3 = K3 = Q2Q1Q0.* FF0 toggles after every active edge.
FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state. (Similarly, for FF2 and FF3)* From the waveforms, we see that it is a binary up counter.
M. B. Patil, IIT Bombay
Design of synchronous counters
CLK J K
CLK
K
J Qn
Qn
Q
Q
0
0 1
1 0
1 1
0
0
1
Qn+1
KCLK JQn+1Qn
0 0 X0
10 1 X
01 X 1
1 1 X 0
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1). What should J and K be in order tomake that happen?
* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn by making J = 0, K = 0.
→ J = 0, K = X (i.e., K can be 0 or 1).
* Similarly, work out the other entries in the table.
* The table for a negative edge-triggered flip-flop would be identical except for the active edge.
M. B. Patil, IIT Bombay
Design of synchronous counters
CLK J K
CLK
K
J Qn
Qn
Q
Q
0
0 1
1 0
1 1
0
0
1
Qn+1 KCLK JQn+1Qn
0 0 X0
10 1 X
01 X 1
1 1 X 0
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1). What should J and K be in order tomake that happen?
* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn by making J = 0, K = 0.
→ J = 0, K = X (i.e., K can be 0 or 1).
* Similarly, work out the other entries in the table.
* The table for a negative edge-triggered flip-flop would be identical except for the active edge.
M. B. Patil, IIT Bombay
Design of synchronous counters
CLK J K
CLK
K
J Qn
Qn
Q
Q
0
0 1
1 0
1 1
0
0
1
Qn+1 KCLK JQn+1Qn
0 0 X0
10 1 X
01 X 1
1 1 X 0
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1). What should J and K be in order tomake that happen?
* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn by making J = 0, K = 0.
→ J = 0, K = X (i.e., K can be 0 or 1).
* Similarly, work out the other entries in the table.
* The table for a negative edge-triggered flip-flop would be identical except for the active edge.
M. B. Patil, IIT Bombay
Design of synchronous counters
CLK J K
CLK
K
J Qn
Qn
Q
Q
0
0 1
1 0
1 1
0
0
1
Qn+1 KCLK JQn+1Qn
0 0 X0
10 1 X
01 X 1
1 1 X 0
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1). What should J and K be in order tomake that happen?
* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn by making J = 0, K = 0.→ J = 0, K = X (i.e., K can be 0 or 1).
* Similarly, work out the other entries in the table.
* The table for a negative edge-triggered flip-flop would be identical except for the active edge.
M. B. Patil, IIT Bombay
Design of synchronous counters
CLK J K
CLK
K
J Qn
Qn
Q
Q
0
0 1
1 0
1 1
0
0
1
Qn+1 KCLK JQn+1Qn
0 0 X0
10 1 X
01 X 1
1 1 X 0
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1). What should J and K be in order tomake that happen?
* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn by making J = 0, K = 0.→ J = 0, K = X (i.e., K can be 0 or 1).
* Similarly, work out the other entries in the table.
* The table for a negative edge-triggered flip-flop would be identical except for the active edge.
M. B. Patil, IIT Bombay
Design of synchronous counters
CLK J K
CLK
K
J Qn
Qn
Q
Q
0
0 1
1 0
1 1
0
0
1
Qn+1 KCLK JQn+1Qn
0 0 X0
10 1 X
01 X 1
1 1 X 0
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1). What should J and K be in order tomake that happen?
* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn by making J = 0, K = 0.→ J = 0, K = X (i.e., K can be 0 or 1).
* Similarly, work out the other entries in the table.
* The table for a negative edge-triggered flip-flop would be identical except for the active edge.
M. B. Patil, IIT Bombay
Design of synchronous counters
CLK J K
CLK
K
J Qn
Qn
Q
Q
0
0 1
1 0
1 1
0
0
1
Qn+1 KCLK JQn+1Qn
0 0 X0
10
1 X
01 X 1
1 1 X 0
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1). What should J and K be in order tomake that happen?
* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn by making J = 0, K = 0.→ J = 0, K = X (i.e., K can be 0 or 1).
* Similarly, work out the other entries in the table.
* The table for a negative edge-triggered flip-flop would be identical except for the active edge.
M. B. Patil, IIT Bombay
Design of synchronous counters
CLK J K
CLK
K
J Qn
Qn
Q
Q
0
0 1
1 0
1 1
0
0
1
Qn+1 KCLK JQn+1Qn
0 0 X0
10 1 X
01 X 1
1 1 X 0
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1). What should J and K be in order tomake that happen?
* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn by making J = 0, K = 0.→ J = 0, K = X (i.e., K can be 0 or 1).
* Similarly, work out the other entries in the table.
* The table for a negative edge-triggered flip-flop would be identical except for the active edge.
M. B. Patil, IIT Bombay
Design of synchronous counters
CLK J K
CLK
K
J Qn
Qn
Q
Q
0
0 1
1 0
1 1
0
0
1
Qn+1 KCLK JQn+1Qn
0 0 X0
10 1 X
01
X 1
1 1 X 0
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1). What should J and K be in order tomake that happen?
* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn by making J = 0, K = 0.→ J = 0, K = X (i.e., K can be 0 or 1).
* Similarly, work out the other entries in the table.
* The table for a negative edge-triggered flip-flop would be identical except for the active edge.
M. B. Patil, IIT Bombay
Design of synchronous counters
CLK J K
CLK
K
J Qn
Qn
Q
Q
0
0 1
1 0
1 1
0
0
1
Qn+1 KCLK JQn+1Qn
0 0 X0
10 1 X
01 X 1
1 1 X 0
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1). What should J and K be in order tomake that happen?
* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn by making J = 0, K = 0.→ J = 0, K = X (i.e., K can be 0 or 1).
* Similarly, work out the other entries in the table.
* The table for a negative edge-triggered flip-flop would be identical except for the active edge.
M. B. Patil, IIT Bombay
Design of synchronous counters
CLK J K
CLK
K
J Qn
Qn
Q
Q
0
0 1
1 0
1 1
0
0
1
Qn+1 KCLK JQn+1Qn
0 0 X0
10 1 X
01 X 1
1 1
X 0
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1). What should J and K be in order tomake that happen?
* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn by making J = 0, K = 0.→ J = 0, K = X (i.e., K can be 0 or 1).
* Similarly, work out the other entries in the table.
* The table for a negative edge-triggered flip-flop would be identical except for the active edge.
M. B. Patil, IIT Bombay
Design of synchronous counters
CLK J K
CLK
K
J Qn
Qn
Q
Q
0
0 1
1 0
1 1
0
0
1
Qn+1 KCLK JQn+1Qn
0 0 X0
10 1 X
01 X 1
1 1 X 0
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1). What should J and K be in order tomake that happen?
* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn by making J = 0, K = 0.→ J = 0, K = X (i.e., K can be 0 or 1).
* Similarly, work out the other entries in the table.
* The table for a negative edge-triggered flip-flop would be identical except for the active edge.
M. B. Patil, IIT Bombay
Design of synchronous counters
CLK J K
CLK
K
J Qn
Qn
Q
Q
0
0 1
1 0
1 1
0
0
1
Qn+1 KCLK JQn+1Qn
0 0 X0
10 1 X
01 X 1
1 1 X 0
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1). What should J and K be in order tomake that happen?
* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn by making J = 0, K = 0.→ J = 0, K = X (i.e., K can be 0 or 1).
* Similarly, work out the other entries in the table.
* The table for a negative edge-triggered flip-flop would be identical except for the active edge.
M. B. Patil, IIT Bombay
Design of synchronous counters
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
1
2
3
4
5
K K K
CLK
J
J Kstate
1 0 0 0CLK
J J
repeats
Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn Qn+1
K2 K1 K0
J2 J1 J0Q
Q2
Q
Q
Q
Q1Q
Q
Q0
Design a synchronous mod-5 counter with the given state transition table.
Outline of method:
* State 1 → State 2 meansQ2: 0→ 0,Q1: 0→ 0,Q0: 0→ 1.
* Refer to the right table. For Q2: 0→ 0, we must have J2 = 0, K2 = X , and so on.
* When we cover all transitions in the left table, we have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2.
* The last step is to come up with suitable functions for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. This can be donewith K-maps. (If the number of flip-flops is more than 4, other techniques can be employed.)
M. B. Patil, IIT Bombay
Design of synchronous counters
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
1
2
3
4
5
K K K
CLK
J
J Kstate
1 0 0 0CLK
J J
repeats
Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn Qn+1
K2 K1 K0
J2 J1 J0Q
Q2
Q
Q
Q
Q1Q
Q
Q0
Design a synchronous mod-5 counter with the given state transition table.
Outline of method:
* State 1 → State 2 meansQ2: 0→ 0,Q1: 0→ 0,Q0: 0→ 1.
* Refer to the right table. For Q2: 0→ 0, we must have J2 = 0, K2 = X , and so on.
* When we cover all transitions in the left table, we have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2.
* The last step is to come up with suitable functions for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. This can be donewith K-maps. (If the number of flip-flops is more than 4, other techniques can be employed.)
M. B. Patil, IIT Bombay
Design of synchronous counters
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
1
2
3
4
5
K K K
CLK
J
J Kstate
1 0 0 0CLK
J J
repeats
Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn Qn+1
K2 K1 K0
J2 J1 J0Q
Q2
Q
Q
Q
Q1Q
Q
Q0
Design a synchronous mod-5 counter with the given state transition table.
Outline of method:
* State 1 → State 2 meansQ2: 0→ 0,Q1: 0→ 0,Q0: 0→ 1.
* Refer to the right table. For Q2: 0→ 0, we must have J2 = 0, K2 = X , and so on.
* When we cover all transitions in the left table, we have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2.
* The last step is to come up with suitable functions for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. This can be donewith K-maps. (If the number of flip-flops is more than 4, other techniques can be employed.)
M. B. Patil, IIT Bombay
Design of synchronous counters
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
1
2
3
4
5
K K K
CLK
J
J Kstate
1 0 0 0CLK
J J
repeats
Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn Qn+1
K2 K1 K0
J2 J1 J0Q
Q2
Q
Q
Q
Q1Q
Q
Q0
Design a synchronous mod-5 counter with the given state transition table.
Outline of method:
* State 1 → State 2 meansQ2: 0→ 0,Q1: 0→ 0,Q0: 0→ 1.
* Refer to the right table. For Q2: 0→ 0, we must have J2 = 0, K2 = X , and so on.
* When we cover all transitions in the left table, we have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2.
* The last step is to come up with suitable functions for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. This can be donewith K-maps. (If the number of flip-flops is more than 4, other techniques can be employed.)
M. B. Patil, IIT Bombay
Design of synchronous counters
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
1
2
3
4
5
K K K
CLK
J
J Kstate
1 0 0 0CLK
J J
repeats
Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn Qn+1
K2 K1 K0
J2 J1 J0Q
Q2
Q
Q
Q
Q1Q
Q
Q0
Design a synchronous mod-5 counter with the given state transition table.
Outline of method:
* State 1 → State 2 meansQ2: 0→ 0,Q1: 0→ 0,Q0: 0→ 1.
* Refer to the right table. For Q2: 0→ 0, we must have J2 = 0, K2 = X , and so on.
* When we cover all transitions in the left table, we have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2.
* The last step is to come up with suitable functions for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. This can be donewith K-maps. (If the number of flip-flops is more than 4, other techniques can be employed.)
M. B. Patil, IIT Bombay
Design of synchronous counters
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
1
2
3
4
5
K K K
CLK
J
J Kstate
1 0 0 0CLK
J J
repeats
Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn Qn+1
K2 K1 K0
J2 J1 J0Q
Q2
Q
Q
Q
Q1Q
Q
Q0
Design a synchronous mod-5 counter with the given state transition table.
Outline of method:
* State 1 → State 2 meansQ2: 0→ 0,Q1: 0→ 0,Q0: 0→ 1.
* Refer to the right table. For Q2: 0→ 0, we must have J2 = 0, K2 = X , and so on.
* When we cover all transitions in the left table, we have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2.
* The last step is to come up with suitable functions for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. This can be donewith K-maps. (If the number of flip-flops is more than 4, other techniques can be employed.)
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn
0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn
0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X
0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X
1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X
1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X
X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X
X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X X 0
1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X
X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1
X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1
0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X
0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
CLK J K
K0J0K1J1K2J2Q2 Q1 Q0
0 0
0
0
1
1
1 1
X
1 X
X 1
X 0
0
Qn+1Qn0 X 0 X 1 X
0 X 1 X X 1
0 X X 0 1 X
1 X X 1 X 1
X 1 0 X 0 X
* We now have the truth tables for J0, K0, J1, K1, J2, K2 in terms of Q0, Q1, Q2. The next step is to findlogical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0, Q1, Q2 which do notoccur in the state transition table (such as Q2Q1Q0 = 110). We treat these as don’t care conditions.
M. B. Patil, IIT Bombay
Design of synchronous counters
0 0X X X1
0 X 1 X X 1
0 X X 0 1 X
1 X X X1 1
1 0 X 0 XX
X0 0
0 11
0
00 01 11 10
0
1
X 0
1 X
00 01 11 10
0
1 X X
011
1
0
00 01 11 10
X X
1 1
X
0
1
X 0 X
X 1
00 01 11 10
00 01 11 10
0
1
X X 1
X X
00 01 11 10
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
0
Q2Q1 Q2Q1
Q0Q0
Q2Q1 Q2Q1
Q0Q0
Q2Q1
Q0
Q2Q1
Q0
K0
K0
J0
J0
K1
K1
J1
J1
K2
K2
J2
J2
Q2 Q1 Q0
X
X X
X
X X
X
X X X X
X
X X
X
X X
X
* We treat the unused states (Q2Q1Q0 = 101, 110, 111) as (additional) don’t care conditions. Since these are differentfrom the don’t care conditions arising from the state transition table, we mark them with a different colour.
* We will assume that a suitable initialization facility is provided to ensure that the counter starts up in one of the fiveallowed states (say, Q2Q1Q0 = 000).
* From the K-maps, J2 = Q1Q0, K2 = 1, J1 = Q0, K1 = Q0, J0 = Q2, K0 = 1.
M. B. Patil, IIT Bombay
Design of synchronous counters
0 0X X X1
0 X 1 X X 1
0 X X 0 1 X
1 X X X1 1
1 0 X 0 XX
X0 0
0 11
0
00 01 11 10
0
1
X 0
1 X
00 01 11 10
0
1 X X
011
1
0
00 01 11 10
X X
1 1
X
0
1
X 0 X
X 1
00 01 11 10
00 01 11 10
0
1
X X 1
X X
00 01 11 10
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
0
Q2Q1 Q2Q1
Q0Q0
Q2Q1 Q2Q1
Q0Q0
Q2Q1
Q0
Q2Q1
Q0
K0
K0
J0
J0
K1
K1
J1
J1
K2
K2
J2
J2
Q2 Q1 Q0
X
X X
X
X X
X
X X X X
X
X X
X
X X
X
* We treat the unused states (Q2Q1Q0 = 101, 110, 111) as (additional) don’t care conditions. Since these are differentfrom the don’t care conditions arising from the state transition table, we mark them with a different colour.
* We will assume that a suitable initialization facility is provided to ensure that the counter starts up in one of the fiveallowed states (say, Q2Q1Q0 = 000).
* From the K-maps, J2 = Q1Q0, K2 = 1, J1 = Q0, K1 = Q0, J0 = Q2, K0 = 1.
M. B. Patil, IIT Bombay
Design of synchronous counters
0 0X X X1
0 X 1 X X 1
0 X X 0 1 X
1 X X X1 1
1 0 X 0 XX
X0 0
0 11
0
00 01 11 10
0
1
X 0
1 X
00 01 11 10
0
1 X X
011
1
0
00 01 11 10
X X
1 1
X
0
1
X 0 X
X 1
00 01 11 10
00 01 11 10
0
1
X X 1
X X
00 01 11 10
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
0
Q2Q1 Q2Q1
Q0Q0
Q2Q1 Q2Q1
Q0Q0
Q2Q1
Q0
Q2Q1
Q0
K0
K0
J0
J0
K1
K1
J1
J1
K2
K2
J2
J2
Q2 Q1 Q0
X
X X
X
X X
X
X X X X
X
X X
X
X X
X
* We treat the unused states (Q2Q1Q0 = 101, 110, 111) as (additional) don’t care conditions. Since these are differentfrom the don’t care conditions arising from the state transition table, we mark them with a different colour.
* We will assume that a suitable initialization facility is provided to ensure that the counter starts up in one of the fiveallowed states (say, Q2Q1Q0 = 000).
* From the K-maps, J2 = Q1Q0, K2 = 1, J1 = Q0, K1 = Q0, J0 = Q2, K0 = 1.
M. B. Patil, IIT Bombay
Design of synchronous counters
0 0X X X1
0 X 1 X X 1
0 X X 0 1 X
1 X X X1 1
1 0 X 0 XX
X0 0
0 11
0
00 01 11 10
0
1
X 0
1 X
00 01 11 10
0
1 X X
011
1
0
00 01 11 10
X X
1 1
X
0
1
X 0 X
X 1
00 01 11 10
00 01 11 10
0
1
X X 1
X X
00 01 11 10
state
0
12
3
4
5
1 0 0
00
0 1 0
0 1 1
1 0 0
1 0 0 0
0
Q2Q1 Q2Q1
Q0Q0
Q2Q1 Q2Q1
Q0Q0
Q2Q1
Q0
Q2Q1
Q0
K0
K0
J0
J0
K1
K1
J1
J1
K2
K2
J2
J2
Q2 Q1 Q0
X
X X
X
X X
X
X X X X
X
X X
X
X X
X
* We treat the unused states (Q2Q1Q0 = 101, 110, 111) as (additional) don’t care conditions. Since these are differentfrom the don’t care conditions arising from the state transition table, we mark them with a different colour.
* We will assume that a suitable initialization facility is provided to ensure that the counter starts up in one of the fiveallowed states (say, Q2Q1Q0 = 000).
* From the K-maps, J2 = Q1Q0, K2 = 1, J1 = Q0, K1 = Q0, J0 = Q2, K0 = 1.
M. B. Patil, IIT Bombay
Design of synchronous counters: verification
K K K
J J J
CLK
1
CLK
0.04 0.14 0.24 0.34
time (msec)
SEQUEL file: ee101 counter 6.sqproj
K2 K1 K0
J0Q
Q Q
Q2Q
Q1
Q
QQ0J2 J1
Q0
Q1
Q2
* J2 =Q1Q0,
K2 = 1,
J1 =Q0,
K1 =Q0,
J0 =Q2,
K0 = 1.
* Note that the design is independentof whether positive or negativeedge-triggered flip-flops are used.
M. B. Patil, IIT Bombay
Design of synchronous counters: verification
K K K
J J J
CLK
1
CLK
0.04 0.14 0.24 0.34
time (msec)
SEQUEL file: ee101 counter 6.sqproj
K2 K1 K0
J0Q
Q Q
Q2Q
Q1
Q
QQ0J2 J1
Q0
Q1
Q2
* J2 =Q1Q0,
K2 = 1,
J1 =Q0,
K1 =Q0,
J0 =Q2,
K0 = 1.
* Note that the design is independentof whether positive or negativeedge-triggered flip-flops are used.
M. B. Patil, IIT Bombay
Design of synchronous counters: verification
K K K
J J J
CLK
1
CLK
0.04 0.14 0.24 0.34
time (msec)
SEQUEL file: ee101 counter 6.sqproj
K2 K1 K0
J0Q
Q Q
Q2Q
Q1
Q
QQ0J2 J1
Q0
Q1
Q2
* J2 =Q1Q0,
K2 = 1,
J1 =Q0,
K1 =Q0,
J0 =Q2,
K0 = 1.
* Note that the design is independentof whether positive or negativeedge-triggered flip-flops are used.
M. B. Patil, IIT Bombay
Combination of counters: Approach 1
Counter 1
Counter 2
A1
A2
AN1
B1
B2
BN2
mod-k1
mod-k2
Clock 1
Clock 2
k1=4
k2=3
Counter 1
mod-k1
Clock 1
Counter 1 state
Clock 1
4 2 3 41 2 3 41 2 3 41 2 3 41 1
Decoding
Logic
Counter 2
mod-k2
Clock 2
Clock 2
Counter 2 state 1 2 3 1
Combined state2 3 41 2 3 41 2 3 41 2 3 41 14
13 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1 2
→ the combined counter is a mod-k1k2 counter.
M. B. Patil, IIT Bombay
Combination of counters: Approach 1
Counter 1
Counter 2
A1
A2
AN1
B1
B2
BN2
mod-k1
mod-k2
Clock 1
Clock 2
k1=4
k2=3
Counter 1
mod-k1
Clock 1
Counter 1 state
Clock 1
4 2 3 41 2 3 41 2 3 41 2 3 41 1
Decoding
Logic
Counter 2
mod-k2
Clock 2
Clock 2
Counter 2 state 1 2 3 1
Combined state2 3 41 2 3 41 2 3 41 2 3 41 14
13 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1 2
→ the combined counter is a mod-k1k2 counter.
M. B. Patil, IIT Bombay
Combination of counters: Approach 1
Counter 1
Counter 2
A1
A2
AN1
B1
B2
BN2
mod-k1
mod-k2
Clock 1
Clock 2
k1=4
k2=3
Counter 1
mod-k1
Clock 1
Counter 1 state
Clock 1
4 2 3 41 2 3 41 2 3 41 2 3 41 1
Decoding
Logic
Counter 2
mod-k2
Clock 2
Clock 2
Counter 2 state 1 2 3 1
Combined state2 3 41 2 3 41 2 3 41 2 3 41 14
13 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1 2
→ the combined counter is a mod-k1k2 counter.
M. B. Patil, IIT Bombay
Combination of counters: Approach 1
Counter 1
Counter 2
A1
A2
AN1
B1
B2
BN2
mod-k1
mod-k2
Clock 1
Clock 2
k1=4
k2=3
Counter 1
mod-k1
Clock 1
Counter 1 state
Clock 1
4 2 3 41 2 3 41 2 3 41 2 3 41 1
Decoding
Logic
Counter 2
mod-k2
Clock 2
Clock 2
Counter 2 state 1 2 3 1
Combined state2 3 41 2 3 41 2 3 41 2 3 41 14
13 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1 2
→ the combined counter is a mod-k1k2 counter.
M. B. Patil, IIT Bombay
Combination of counters: Approach 1
Counter 1
Counter 2
A1
A2
AN1
B1
B2
BN2
mod-k1
mod-k2
Clock 1
Clock 2
k1=4
k2=3
Counter 1
mod-k1
Clock 1
Counter 1 state
Clock 1
4 2 3 41 2 3 41 2 3 41 2 3 41 1
Decoding
Logic
Counter 2
mod-k2
Clock 2
Clock 2
Counter 2 state 1 2 3 1
Combined state2 3 41 2 3 41 2 3 41 2 3 41 14
13 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1 2
→ the combined counter is a mod-k1k2 counter.
M. B. Patil, IIT Bombay
Combination of counters: Approach 1
Counter 1
Counter 2
A1
A2
AN1
B1
B2
BN2
mod-k1
mod-k2
Clock 1
Clock 2
k1=4
k2=3
Counter 1
mod-k1
Clock 1
Counter 1 state
Clock 1
4 2 3 41 2 3 41 2 3 41 2 3 41 1
Decoding
Logic
Counter 2
mod-k2
Clock 2
Clock 2
Counter 2 state 1 2 3 1
Combined state2 3 41 2 3 41 2 3 41 2 3 41 14
13 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1 2
→ the combined counter is a mod-k1k2 counter.
M. B. Patil, IIT Bombay
Combination of counters: example
K K K K
t t
CLK
t t
t
t
mod−2 counter mod−5 counter
J
CLK
1
CLK
1
J JJ
CLK
Q0 Q0
Q1
Q2
J0
K0
Q
QQ0 J2
K2
Q
Q Q
Q0Q
K0
Q
QK1
Q2 J0Q1J1
M. B. Patil, IIT Bombay
Combination of counters: example
K K KK
J
CLK
1
t
t
t
t
t
CLK
1
J JJ
51 2 3 4 5 6 7 8 9 10 1 2 3 4 6 7 8 9 10
QA
Q0
Q1
Q2
SEQUEL file: ee101 counter 7.sqproj
JA
KA
Q
QQA
J2
K2
Q
Q Q
Q0Q
K0
Q
QK1
Q2 J0Q1J1
M. B. Patil, IIT Bombay
Combination of counters: Approach 2
Counter 1
Counter 2
A1
A2
AN1
B1
B2
BN2
mod-k1
mod-k2
Clock 1
Clock 2
k1=4
k2=3
Counter 1
mod-k1
Clock 1
Counter 1 state
Clock 1
4 2 3 41 2 3 41 2 3 41 2 3 41 1
Counter 2
mod-k2
Clock 2
Clock 2
Counter 2 state 13 2 13 3 3 3 31 1 1 12 2 2 2 2
Combined state2 3 41 2 3 41 2 3 41 2 3 41 14
13 2 3 1 2 2 2 2 23 1 3 1 3 1 13
→ the combined counter is a mod-k1k2 counter.
M. B. Patil, IIT Bombay
Combination of counters: Approach 2
Counter 1
Counter 2
A1
A2
AN1
B1
B2
BN2
mod-k1
mod-k2
Clock 1
Clock 2
k1=4
k2=3
Counter 1
mod-k1
Clock 1
Counter 1 state
Clock 1
4 2 3 41 2 3 41 2 3 41 2 3 41 1
Counter 2
mod-k2
Clock 2
Clock 2
Counter 2 state 13 2 13 3 3 3 31 1 1 12 2 2 2 2
Combined state2 3 41 2 3 41 2 3 41 2 3 41 14
13 2 3 1 2 2 2 2 23 1 3 1 3 1 13
→ the combined counter is a mod-k1k2 counter.
M. B. Patil, IIT Bombay
Combination of counters: Approach 2
Counter 1
Counter 2
A1
A2
AN1
B1
B2
BN2
mod-k1
mod-k2
Clock 1
Clock 2
k1=4
k2=3
Counter 1
mod-k1
Clock 1
Counter 1 state
Clock 1
4 2 3 41 2 3 41 2 3 41 2 3 41 1
Counter 2
mod-k2
Clock 2
Clock 2
Counter 2 state 13 2 13 3 3 3 31 1 1 12 2 2 2 2
Combined state2 3 41 2 3 41 2 3 41 2 3 41 14
13 2 3 1 2 2 2 2 23 1 3 1 3 1 13
→ the combined counter is a mod-k1k2 counter.
M. B. Patil, IIT Bombay
Combination of counters: Approach 2
Counter 1
Counter 2
A1
A2
AN1
B1
B2
BN2
mod-k1
mod-k2
Clock 1
Clock 2
k1=4
k2=3
Counter 1
mod-k1
Clock 1
Counter 1 state
Clock 1
4 2 3 41 2 3 41 2 3 41 2 3 41 1
Counter 2
mod-k2
Clock 2
Clock 2
Counter 2 state 13 2 13 3 3 3 31 1 1 12 2 2 2 2
Combined state2 3 41 2 3 41 2 3 41 2 3 41 14
13 2 3 1 2 2 2 2 23 1 3 1 3 1 13
→ the combined counter is a mod-k1k2 counter.
M. B. Patil, IIT Bombay
Combination of counters: Approach 2
Counter 1
Counter 2
A1
A2
AN1
B1
B2
BN2
mod-k1
mod-k2
Clock 1
Clock 2
k1=4
k2=3
Counter 1
mod-k1
Clock 1
Counter 1 state
Clock 1
4 2 3 41 2 3 41 2 3 41 2 3 41 1
Counter 2
mod-k2
Clock 2
Clock 2
Counter 2 state 13 2 13 3 3 3 31 1 1 12 2 2 2 2
Combined state2 3 41 2 3 41 2 3 41 2 3 41 14
13 2 3 1 2 2 2 2 23 1 3 1 3 1 13
→ the combined counter is a mod-k1k2 counter.
M. B. Patil, IIT Bombay
Combination of counters: Approach 2
Counter 1
Counter 2
A1
A2
AN1
B1
B2
BN2
mod-k1
mod-k2
Clock 1
Clock 2
k1=4
k2=3
Counter 1
mod-k1
Clock 1
Counter 1 state
Clock 1
4 2 3 41 2 3 41 2 3 41 2 3 41 1
Counter 2
mod-k2
Clock 2
Clock 2
Counter 2 state 13 2 13 3 3 3 31 1 1 12 2 2 2 2
Combined state2 3 41 2 3 41 2 3 41 2 3 41 14
13 2 3 1 2 2 2 2 23 1 3 1 3 1 13
→ the combined counter is a mod-k1k2 counter.
M. B. Patil, IIT Bombay
Combination of counters: Approach 2
Counter 1
Counter 2
A1
A2
AN1
B1
B2
BN2
mod-k1
mod-k2
Clock 1
Clock 2
k1=4
k2=3
Counter 1
mod-k1
Clock 1
Counter 1 state
Clock 1
4 2 3 41 2 3 41 2 3 41 2 3 41 1
Counter 2
mod-k2
Clock 2
Clock 2
Counter 2 state 13 2 13 3 3 3 31 1 1 12 2 2 2 2
Combined state2 3 41 2 3 41 2 3 41 2 3 41 14
13 2 3 1 2 2 2 2 23 1 3 1 3 1 13
→ the combined counter is a mod-k1k2 counter.
M. B. Patil, IIT Bombay
Combination of counters: example (same as before)
K K K K
t t
CLK
t t
t
t
mod−2 counter mod−5 counter
J
CLK
1
CLK
1
J JJ
CLK
Q0 Q0
Q1
Q2
J0
K0
Q
QQ0 J2
K2
Q
Q Q
Q0Q
K0
Q
QK1
Q2 J0Q1J1
M. B. Patil, IIT Bombay
Combination of counters: example
K K K
t
t
t
t
t
CLK
K
1
J JJJ
1
CLK
51 2 3 4 5 6 7 8 9 10 1 2 3 4 6 7 8 9 10
QA
Q0
Q1
Q2
SEQUEL file: ee101 counter 8.sqproj
J2
K2
Q
Q Q
Q0Q
K0
Q
QK1
Q2 J0Q1J1JA
KA
Q
QQA
M. B. Patil, IIT Bombay
555 timer IC
The 555 timer is useful in timer, pulse generation, and oscillator applications. We will look at two commonapplications.
* Monostable multivibrator
t
t
T
Vout
Vtrigger
* Astable multivibrator
t
T
Vout
M. B. Patil, IIT Bombay
555 timer IC
The 555 timer is useful in timer, pulse generation, and oscillator applications. We will look at two commonapplications.
* Monostable multivibrator
t
t
T
Vout
Vtrigger
* Astable multivibrator
t
T
Vout
M. B. Patil, IIT Bombay
555 timer IC
The 555 timer is useful in timer, pulse generation, and oscillator applications. We will look at two commonapplications.
* Monostable multivibrator
t
t
T
Vout
Vtrigger
* Astable multivibrator
t
T
Vout
M. B. Patil, IIT Bombay
555 timer
R S
Threshold
Trigger
Discharge
Outbuffer
Q
R
R
R
Q
Q
Q
R
S
1
1
0 0
0
0
1
1 0
0
previous
VCC
OutThreshold
Trigger
Discharge
2VCC
3
VCC
3
Q
Q
R
S
STOP
M. B. Patil, IIT Bombay
555 timer
R S
Threshold
Trigger
Discharge
Outbuffer
Q
R
R
R
Q
Q
Q
R
S
1
1
0 0
0
0
1
1 0
0
previous
VCC
OutThreshold
Trigger
Discharge
2VCC
3
VCC
3
Q
Q
R
S
STOP
M. B. Patil, IIT Bombay
555 timer
R S
Threshold
Trigger
Discharge
Outbuffer
Q
R
R
R
Q
Q
Q
R
S
1
1
0 0
0
0
1
1 0
0
previous
VCC
OutThreshold
Trigger
Discharge
2VCC
3
VCC
3
Q
Q
R
S
STOP
M. B. Patil, IIT Bombay
555 monostable multivibrator
VC C
R
OutThreshold
Discharge
Trigger
2VCC
3
VCC
3
Q
Q
R
S
VCC
t
t
t
t
t
Trigger
S
R
Q
VC
to VCC
2VCC
3
T
VC (t) = VCC
(1− e−t/τ
)→ 2VCC
3= VCC
(1− e−T/τ
)→ e−T/τ =
1
3→ T = τ log 3 ≈ 1.1 τ
SEQUEL file: ic555 mono 1.sqproj
M. B. Patil, IIT Bombay
555 monostable multivibrator
VC C
R
OutThreshold
Discharge
Trigger
2VCC
3
VCC
3
Q
Q
R
S
VCC
t
t
t
t
t
Trigger
S
R
Q
VC
to VCC
2VCC
3
T
VC (t) = VCC
(1− e−t/τ
)→ 2VCC
3= VCC
(1− e−T/τ
)→ e−T/τ =
1
3→ T = τ log 3 ≈ 1.1 τ
SEQUEL file: ic555 mono 1.sqproj
M. B. Patil, IIT Bombay
555 monostable multivibrator
VC C
R
OutThreshold
Discharge
Trigger
2VCC
3
VCC
3
Q
Q
R
S
VCC
t
t
t
t
t
Trigger
S
R
Q
VC
to VCC
2VCC
3
T
VC (t) = VCC
(1− e−t/τ
)→ 2VCC
3= VCC
(1− e−T/τ
)→ e−T/τ =
1
3→ T = τ log 3 ≈ 1.1 τ
SEQUEL file: ic555 mono 1.sqproj
M. B. Patil, IIT Bombay
555 monostable multivibrator
VC C
R
OutThreshold
Discharge
Trigger
2VCC
3
VCC
3
Q
Q
R
S
VCC
t
t
t
t
t
Trigger
S
R
Q
VC
to VCC
2VCC
3
T
VC (t) = VCC
(1− e−t/τ
)→ 2VCC
3= VCC
(1− e−T/τ
)→ e−T/τ =
1
3→ T = τ log 3 ≈ 1.1 τ
SEQUEL file: ic555 mono 1.sqproj
M. B. Patil, IIT Bombay
555 monostable multivibrator
VC C
R
OutThreshold
Discharge
Trigger
2VCC
3
VCC
3
Q
Q
R
S
VCC
t
t
t
t
t
Trigger
S
R
Q
VC
to VCC
2VCC
3
TVC (t) = VCC
(1− e−t/τ
)
→ 2VCC
3= VCC
(1− e−T/τ
)→ e−T/τ =
1
3→ T = τ log 3 ≈ 1.1 τ
SEQUEL file: ic555 mono 1.sqproj
M. B. Patil, IIT Bombay
555 monostable multivibrator
VC C
R
OutThreshold
Discharge
Trigger
2VCC
3
VCC
3
Q
Q
R
S
VCC
t
t
t
t
t
Trigger
S
R
Q
VC
to VCC
2VCC
3
TVC (t) = VCC
(1− e−t/τ
)→ 2VCC
3= VCC
(1− e−T/τ
)
→ e−T/τ =1
3→ T = τ log 3 ≈ 1.1 τ
SEQUEL file: ic555 mono 1.sqproj
M. B. Patil, IIT Bombay
555 monostable multivibrator
VC C
R
OutThreshold
Discharge
Trigger
2VCC
3
VCC
3
Q
Q
R
S
VCC
t
t
t
t
t
Trigger
S
R
Q
VC
to VCC
2VCC
3
TVC (t) = VCC
(1− e−t/τ
)→ 2VCC
3= VCC
(1− e−T/τ
)→ e−T/τ =
1
3→ T = τ log 3 ≈ 1.1 τ
SEQUEL file: ic555 mono 1.sqproj
M. B. Patil, IIT Bombay
555 monostable multivibrator
VC C
R
OutThreshold
Discharge
Trigger
2VCC
3
VCC
3
Q
Q
R
S
VCC
t
t
t
t
t
Trigger
S
R
Q
VC
to VCC
2VCC
3
TVC (t) = VCC
(1− e−t/τ
)→ 2VCC
3= VCC
(1− e−T/τ
)→ e−T/τ =
1
3→ T = τ log 3 ≈ 1.1 τ
SEQUEL file: ic555 mono 1.sqproj
M. B. Patil, IIT Bombay
555 astable multivibrator
VC C
Ra
Rb
Out
Discharge
Trigger
Threshold
VCC
3
2VCC
3
Q
Q
R
S
VCC
t
t
t
t
TH TL
S
R
Q
VC
VCC
3
2VCC
3
VCC
0
Charging:
VC (0) =VCC
3, VC (∞) = VCC .
Let VC (t) = Ae−t/τ1 + B
→ B = VCC , A = −2VCC
32VCC
3= −2VCC
3e−TH/τ1 + VCC
→ TH = τ1 log 2, with τ1 = (Ra + Rb)C .
M. B. Patil, IIT Bombay
555 astable multivibrator
VC C
Ra
Rb
Out
Discharge
Trigger
Threshold
VCC
3
2VCC
3
Q
Q
R
S
VCC
t
t
t
t
TH TL
S
R
Q
VC
VCC
3
2VCC
3
VCC
0
Charging:
VC (0) =VCC
3, VC (∞) = VCC .
Let VC (t) = Ae−t/τ1 + B
→ B = VCC , A = −2VCC
32VCC
3= −2VCC
3e−TH/τ1 + VCC
→ TH = τ1 log 2, with τ1 = (Ra + Rb)C .
M. B. Patil, IIT Bombay
555 astable multivibrator
VC C
Ra
Rb
Out
Discharge
Trigger
Threshold
VCC
3
2VCC
3
Q
Q
R
S
VCC
t
t
t
t
TH TL
S
R
Q
VC
VCC
3
2VCC
3
VCC
0
Charging:
VC (0) =VCC
3, VC (∞) = VCC .
Let VC (t) = Ae−t/τ1 + B
→ B = VCC , A = −2VCC
32VCC
3= −2VCC
3e−TH/τ1 + VCC
→ TH = τ1 log 2, with τ1 = (Ra + Rb)C .
M. B. Patil, IIT Bombay
555 astable multivibrator
VC C
Ra
Rb
Out
Discharge
Trigger
Threshold
VCC
3
2VCC
3
Q
Q
R
S
VCC
t
t
t
t
TH TL
S
R
Q
VC
VCC
3
2VCC
3
VCC
0
Charging:
VC (0) =VCC
3, VC (∞) = VCC .
Let VC (t) = Ae−t/τ1 + B
→ B = VCC , A = −2VCC
3
2VCC
3= −2VCC
3e−TH/τ1 + VCC
→ TH = τ1 log 2, with τ1 = (Ra + Rb)C .
M. B. Patil, IIT Bombay
555 astable multivibrator
VC C
Ra
Rb
Out
Discharge
Trigger
Threshold
VCC
3
2VCC
3
Q
Q
R
S
VCC
t
t
t
t
TH TL
S
R
Q
VC
VCC
3
2VCC
3
VCC
0
Charging:
VC (0) =VCC
3, VC (∞) = VCC .
Let VC (t) = Ae−t/τ1 + B
→ B = VCC , A = −2VCC
32VCC
3= −2VCC
3e−TH/τ1 + VCC
→ TH = τ1 log 2, with τ1 = (Ra + Rb)C .
M. B. Patil, IIT Bombay
555 astable multivibrator
VC C
Ra
Rb
Out
Discharge
Trigger
Threshold
VCC
3
2VCC
3
Q
Q
R
S
VCC
t
t
t
t
TH TL
S
R
Q
VC
VCC
3
2VCC
3
VCC
0
Charging:
VC (0) =VCC
3, VC (∞) = VCC .
Let VC (t) = Ae−t/τ1 + B
→ B = VCC , A = −2VCC
32VCC
3= −2VCC
3e−TH/τ1 + VCC
→ TH = τ1 log 2, with τ1 = (Ra + Rb)C .
M. B. Patil, IIT Bombay
555 astable multivibrator
VC C
Ra
Rb
Out
Discharge
Trigger
Threshold
VCC
3
2VCC
3
Q
Q
R
S
VCC
t
t
t
t
TH TL
S
R
Q
VC
VCC
3
2VCC
3
VCC
0
Discharging: VC (0) =2VCC
3, VC (∞) = 0.
→ VC (t) =2VCC
3e−t/τ2
VCC
3=
2VCC
3e−TL/τ2
→ TL = τ2 log 2, with τ2 = RbC .
SEQUEL file: ic555 astable 1.sqproj
M. B. Patil, IIT Bombay
555 astable multivibrator
VC C
Ra
Rb
Out
Discharge
Trigger
Threshold
VCC
3
2VCC
3
Q
Q
R
S
VCC
t
t
t
t
TH TL
S
R
Q
VC
VCC
3
2VCC
3
VCC
0
Discharging: VC (0) =2VCC
3, VC (∞) = 0.
→ VC (t) =2VCC
3e−t/τ2
VCC
3=
2VCC
3e−TL/τ2
→ TL = τ2 log 2, with τ2 = RbC .
SEQUEL file: ic555 astable 1.sqproj
M. B. Patil, IIT Bombay
555 astable multivibrator
VC C
Ra
Rb
Out
Discharge
Trigger
Threshold
VCC
3
2VCC
3
Q
Q
R
S
VCC
t
t
t
t
TH TL
S
R
Q
VC
VCC
3
2VCC
3
VCC
0
Discharging: VC (0) =2VCC
3, VC (∞) = 0.
→ VC (t) =2VCC
3e−t/τ2
VCC
3=
2VCC
3e−TL/τ2
→ TL = τ2 log 2, with τ2 = RbC .
SEQUEL file: ic555 astable 1.sqproj
M. B. Patil, IIT Bombay
555 astable multivibrator
VC C
Ra
Rb
Out
Discharge
Trigger
Threshold
VCC
3
2VCC
3
Q
Q
R
S
VCC
t
t
t
t
TH TL
S
R
Q
VC
VCC
3
2VCC
3
VCC
0
Discharging: VC (0) =2VCC
3, VC (∞) = 0.
→ VC (t) =2VCC
3e−t/τ2
VCC
3=
2VCC
3e−TL/τ2
→ TL = τ2 log 2, with τ2 = RbC .
SEQUEL file: ic555 astable 1.sqproj
M. B. Patil, IIT Bombay
555 astable multivibrator
VC C
Ra
Rb
Out
Discharge
Trigger
Threshold
VCC
3
2VCC
3
Q
Q
R
S
VCC
t
t
t
t
TH TL
S
R
Q
VC
VCC
3
2VCC
3
VCC
0
Discharging: VC (0) =2VCC
3, VC (∞) = 0.
→ VC (t) =2VCC
3e−t/τ2
VCC
3=
2VCC
3e−TL/τ2
→ TL = τ2 log 2, with τ2 = RbC .
SEQUEL file: ic555 astable 1.sqproj
M. B. Patil, IIT Bombay
555 astable multivibrator
VC C
Ra
Rb
Out
Discharge
Trigger
Threshold
VCC
3
2VCC
3
Q
Q
R
S
VCC
t
t
t
t
TH TL
S
R
Q
VC
VCC
3
2VCC
3
VCC
0
Discharging: VC (0) =2VCC
3, VC (∞) = 0.
→ VC (t) =2VCC
3e−t/τ2
VCC
3=
2VCC
3e−TL/τ2
→ TL = τ2 log 2, with τ2 = RbC .
SEQUEL file: ic555 astable 1.sqproj
M. B. Patil, IIT Bombay