sequential design motivation sequential processing often more tractable than parallel example...
TRANSCRIPT
Sequential DesignMotivation
Sequential processing often more tractable than parallel
Example
Sequential processing sometimes only method that works
Example (generalization of parity)
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
W XY Z
0 0 0 1 1 1 1 0
0 0
0 1
1 1
1 0
0
1
2
3
4
5
6
7
1 2
1 3
1 4
1 5
8
9
1 0
1 1
1
1
1
1 1
1
1
1
p
F A
A 0 B 0
F A
A 1 B 1
F A
A 2 B 2
F A
A 3 B 3
S 0S 1 S 2 S 3
C 0C 1 C 2 C 3 C 4
Sequential DesignFinite State Machines
Elements
states
transitions
output(s)
Example
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
e v e n
0 01
1
o d d
Sequential DesignFinite State Machines
Sequence recognition1) Create machine to recognize sequence
2) Fill in other states
Example (“abac”)
Note: Must handle cases whereby non-initial substring is target sequence
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
a b a cI NI T a a b a ba a ba c
b ,c
ac b
a
b , c
b , c
a
a b a cI NI T a a b a ba a ba c
Sequential DesignMealy and Moore Machines
Mooreoutput function of current state only
Mealyoutput function of current state and current inputs
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
in p u ts
o u tp u tsN ex t-s ta telog ic
S ta tem em ory
O utp u tlog ic
C L O C K
M ea ly m a ch in e o n ly
Sequential Design
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
i) Derive the transition equations from the next state logic
iii) Construct a transition/output table from the equations produced in i) and ii)
ii) Derive the output equation from the output logic
iv) Construct a state/output table by labeling the states in iii)
v) Derive a DFSM from the table in iv)
vi) State in ordinary language what the machine is doing
Sequential Design
Sequential Machine AnalysisExample
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
D
C L K
Q
D
C L K
Q
Q N
Q N
I1
C L K
O U T
n ext s ta te lo g ic
o u tp u t lo g ic
I0
Q 0D 0
D 1 Q 1
Sequential DesignSequential Machine Analysis
Examplei) Derivation of transition equations
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
D
C L K
Q
D
C L K
Q
Q N
Q N
I1
C L K
O U T
n ext s ta te lo g ic
o u tp u t lo g ic
I0
Q 0D 0
D 1 Q 1
Q0+ = Q0I0'I1' + Q0Q1'I0' + Q0Q1'I1' + Q0'Q1I1 + Q0'Q1I0 + Q0'I0I1
Q1+ = Q1I0'I1' + Q1'I0'I1 + Q1I0I1 + Q1'I0I1'
Sequential DesignSequential Machine Analysis
Exampleii) Derivation of output equation
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
D
C L K
Q
D
C L K
Q
Q N
Q N
I1
C L K
O U T
n ext s ta te lo g ic
o u tp u t lo g ic
I0
Q 0D 0
D 1 Q 1
OUT = Q0'Q1'
Sequential DesignSequential Machine Analysis
Exampleiii) Construction of the transition/output table
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
Q0+ = Q0I0'I1' + Q0Q1'I0' + Q0Q1'I1' + Q0'Q1I1 + Q0'Q1I0 + Q0'I0I1
Q1+ = Q1I0'I1' + Q1'I0'I1 + Q1I0I1 + Q1'I0I1'
I0I1
Q0Q1 00 01 10 11 OUT
00 00 01 01 10 1
01 01 10 10 11 0
10 10 11 11 00 0
11 11 00 00 01 0
Q0+Q1
+
Sequential DesignSequential Machine Analysis
Exampleiv) Construction of the state/output table
A = 00B = 01C = 10D = 11
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
I0I1
Q0Q1 00 01 10 11 OUT
A A B B C 1
B B C C D 0
C C D D A 0
D D A A B 0
Q0+Q1
+
Sequential Design
Sequential Machine AnalysisExample
v) Derivation of the finite state machine
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
I0I1
Q0Q1 00 01 10 11 OUT
A A B B C 1
B B C C D 0
C C D D A 0
D D A A B 0
Q0+Q1
+
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 01 1
1 1 1 1
1 1
0 1 ,1 0
Sequential DesignSequential Machine Analysis
Examplevi) Ordinary language description?
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 01 1
1 1 1 1
1 1
0 1 ,1 0
Sequential DesignSequential Machine Synthesis
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
i) Finite state diagram construction
ii) State/output table construction
iii) State-variable assignment
iv) Substitution of state-assignments into the state/output table
v) Construct an excitation table
vii) Derive output equations from the transition/output table
vi) Derive excitation equations from this table
viii) Draw a circuit diagram that realizes the excitation and output
ix) Verification
Sequential DesignSequential Machine Synthesis
Example 1 (parity)i) State diagram construction
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
e v e n
0 01
1
o d d
Sequential DesignSequential Machine Synthesis
Example 1 (parity)ii) Construction of the state/output table
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
e v e n
0 01
1
o d d
I
Q0 0 1 OUT
even even odd 0
odd odd even 1
Q0+
Sequential DesignSequential Machine Synthesis
Example 1 (parity)iii) State variable assignment
0 = even1 = odd
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
I
Q0 0 1 OUT
even even odd 0
odd odd even 1
Q0+
Sequential DesignSequential Machine Synthesis
Example 1 (parity)iv) Transition/output table construction
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
I
Q0 0 1 OUT
0 0 1 0
1 1 0 1
Q0+
Sequential DesignSequential Machine Synthesis
Example 1 (parity)v) Excitation/output table construction
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
I
Q0 0 1 OUT
0 0 1 0
1 1 0 1
D0
Sequential DesignSequential Machine Synthesis
Example 1 (parity)vi) Excitation equation derivation
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
I
Q0 0 1 OUT
0 0 1 0
1 1 0 1
D0
D0 = Q0I' + Q0'I
Sequential DesignSequential Machine Synthesis
Example 1 (parity)vii) Output equation derivation
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
I
Q0 0 1 OUT
0 0 1 0
1 1 0 1
D0
OUT = Q0
Sequential DesignSequential Machine Synthesis
Example 1 (parity)viii) Circuit realization
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
OUT = Q0 D0 = Q0I' + Q0'I
D
C L K
Q
Q N
C L K
I
O UT
Sequential DesignSequential Machine Synthesis
Example 1 (parity)ix) Verification
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
D
C L K
Q
Q N
C L K
I
O UT
I 0 1 1 0 0 1 1 1 0 1 0
Q 0 1 0 0 0 1 0 1 1 0 0
OUT 0 1 0 0 0 1 0 1 1 0 0
Sequential DesignSequential Machine Synthesis
Example 2 (sequence recognition)i) Convert DFSM into binary
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
a b a cI NI T a a b a ba a ba c
b ,c
ac b
a
b , c
b , c
a
0 0 0 1 0 0 1 00 0 0 0 0 1 0 1 0 0 11 1 0 0
0 1 ,1 0
0 01 0 0 1
0 0
0 1 ,1 0
0 1 ,1 0
0 0
Sequential DesignSequential Machine Synthesis
Example 2 (sequence recognition)ii) Construct excitation/output table
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
0 0 0 1 0 0 1 00 0 0 0 0 1 0 1 0 0 11 1 0 0
0 1 ,1 0
0 01 0 0 1
0 0
0 1 ,1 0
0 1 ,1 0
0 0
I0I1
Q0Q1Q2 00 01 10 OUT
000 001 000 000 0
001 001 010 000 0
010 011 000 000 0
011 001 010 100 0
100 001 000 000 1
D0D1D2
Sequential DesignSequential Machine Synthesis
Example 2 (sequence recognition)iii) Derive minimized excitation and output equations
Note: x’s represent don’tcare conditions
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
I 0I 1
Q 1Q 20 0 0 1 1 0
0 0
0 1
1 1
1 0
1 1
Q 0 = 0
I 0I 1
Q 1Q 20 0 0 1 1 0
0 0
0 1
1 1
1 0
1 1
Q 0 = 1
D 0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
I 0 Q 1 Q 2
I 0I 1
Q 1Q 20 0 0 1 1 0
0 0
0 1
1 1
1 0
1 1
Q 0 = 0
I 0I 1
Q 1Q 20 0 0 1 1 0
0 0
0 1
1 1
1 0
1 1
Q 0 = 1
D 1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x1
1
1
I 1 Q 2I 0 ' I 1 'Q 1 Q 2 '
Q 1Q 2
Q 00 0 0 1 1 0
0
1
1 1
O UT
x x1 x
Q 1Q 20 1 1 0
0 0
0 1
1 1
1 0
1 1Q 1Q 2
0 0 0 1 1 0
0 0
0 1
1 1
1 0
1 1
D 2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
1
1
Q 0 = 0
I 0I 10 0
Q 0 = 1
I 0I 1 0 0
1
I 0 ' I 1 '
Sequential DesignSequential Machine Synthesis
Example 2 (sequence recognition)iv) All equations and circuit
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
D0 = I0Q1Q2 D1 = I1Q2 + I0'I1'Q1Q2'
D2 = I0'I1'OUT = Q0
D
C L K
Q
Q N
C L K
O UT
D
C L K
Q
Q N
D
C L K
Q
Q N
I 0
I 1
D 0
D 1
D 2
Q 0
Q 1
Q 2
Sequential DesignSequential Machine Synthesis
Example 2 (sequence recognition)v) Verification
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
I0 0 0 0 0 0 0 1 0 0 0 1 1
I1 1 0 1 0 1 0 0 0 1 0 0 0
input b a b a b a c a b a c c
Q0 0 0 0 0 0 0 1 0 0 0 1 0
Q1 0 0 1 1 1 1 0 0 1 1 0 0
Q2 0 1 0 1 0 1 0 1 0 1 0 0
state INIT a ab aba ab aba abac a ab aba abac INIT
OUT 0 0 0 0 0 0 1 0 0 0 1 0
Sequential DesignSequential Machine Synthesis
Example 3 (JK flip-flop design)Setting states
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
Q Q+ J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
Q+ ≡ QN J + QK'
Sequential DesignSequential Machine Synthesis
Example 3 (JK flip-flop design)Mod 4 example
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
I0I1
Q0Q1 00 01 10 11 OUT
00 00 01 01 11 1
01 01 11 11 10 0
11 11 10 10 00 0
10 10 00 00 01 0
Q0+Q1
+
Sequential DesignSequential Machine Synthesis
Example 3 (JK flip-flop design)Mod 4 example, excitation table
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
I0I1
Q0Q1 00 01 10 11
00 0x,0x 0x,1x 0x,1x 1x,1x
01 0x,x0 1x,x0 1x,x0 1x,x1
11 x0,x0 x0,x1 x0,x1 x1,x1
10 x0,0x x1,0x x1,0x x1,1x
J0 K0, J1 K1
Sequential DesignSequential Machine Synthesis
Example 3 (JK flip-flop design)Mod 4 example, excitation equations
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
I 0I 1
Q 0Q 10 0 0 1 1 0
0 0
0 1
1 1
1 0
1 1I 0I 1
Q 0Q 10 0
0 0
0 1
1 1
1 0
J 0
I 0I 1
Q 0Q 10 0 0 1 1 0
0 0
0 1
1 1
1 0
1 1I 0I 1
Q 0Q 10 0 0 1 1 0
0 0
0 1
1 1
1 0
1 1
J 1 K 1
K 0
x x1 x x
x1 x1 x1 x
x x x 1x
x x 1x 1x 1
0 1 1 01 1
x1 1 1 x x x
x x xx 1
x x 1x x 1 1
x x x1 x
J0 = I0I1 + I1Q1 + I0Q1
K0 = I0I1 + I0Q1' + I1Q1'
J1 = I0I1 + + I1Q0' + I0Q0'
K1 = I0I1 + I1Q0 + I0Q0
Sequential DesignSequential Machine Synthesis
Example 3 (JK flip-flop design)Mod 4 example, realization
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0
D
C L K
Q
Q N
C L K
O UT
I 0
I 1
Q 0
K
D
C L K
Q
Q N
Q 1
K
Sequential DesignSummary of Topics
Finite state machinesSequential machine analysisSequential machine synthesis
D flip-flopsJK flip-flops
0 1 ,1 0B
D C
0 0A
0 1 ,1 0
0 0
0 1 ,1 0
0 0
0 011
11 11
11
0 1 ,1 0