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Digital Logic Design Ch1-1
Sequential Logic Circuits
ByDr. M. Hebaishy
Digital Logic Design Ch1-2
Rem.!) Types of Logic Circuits
Combinational Logic
Memoryless
Outputs determined by current values of inputs
Sequential Logic
Has memory
Outputs determined by previous and current values of
inputs
inputs outputsfunctional spec
timing spec
Digital Logic Design Ch1-3
Outlines
Introduction
Sequential Circuits
Storage Elements: Latches
Storage Elements: Flip‐Flops
Analysis of Clocked Sequential Circuits
State Reduction and Assignment
Design Procedure
Digital Logic Design Ch1-4
Introduction
Asynchronous
Synchronous
Combinational
Circuit
Flip-flops
Inputs Outputs
Clock
Combinational
CircuitMemory
Elements
Inputs Outputs
Digital Logic Design Ch1-5
There are two main types of sequential circuits :
• A synchronous sequential circuit is a system whose behavior can be defined from the
knowledge of its signals at discrete instants of time.
• An asynchronous sequential circuit depends upon the input signals at any instant of time
and the order in which the inputs change.
The storage elements (memory) used in clocked sequential circuits are called flipflops.
A flip-flop is a binary storage device capable of storing one bit of information. In a stable
state, the output of a flip-flop is either 0 or 1.
A sequential circuit may use many flip-flops to store as many bits as necessary.
Sequential Circuits
Digital Logic Design Ch1-6
Outputs of sequential logic depend on current and prior input
values – it has memory.
Some definitions:
State: all the information about a circuit necessary to explain its future
behavior
Latches and flip-flops: state elements that store one bit of state
Sequential Circuits
• Give sequence to events
• Have memory (short-term)
• Use feedback from output to input to store information
Digital Logic Design Ch1-7
State Elements
• The state of a circuit influences its future behavior
• State elements store state
– Bistable circuit
– SR Latch
– SR Flip Flop
– D Flip Flop (Controlled Latch)
– J k Flip Flop
Digital Logic Design Ch1-8
Bistable Circuit
QQQ
Q
I1
I2
I2 I1
• Fundamental building block of other state elements
• Two outputs: Q, Q’
• No inputs
Digital Logic Design Ch1-9
• Consider the two possible cases:
– Q = 0:
then Q’ = 1, Q = 0 (consistent)
– Q = 1:
then Q’ = 0, Q = 1 (consistent)
• Stores 1 bit of state in the state variable, Q (or Q)
• But there are no inputs to control the state
Bistable Circuit Analysis
Q
Q
I1
I2
0
1
1
0
Q
Q
I1
I2
1
0
0
1
Digital Logic Design Ch1-10
S R Latch
SR Latch
• The SR latch is a circuit with two cross-coupled NOR gates or two
cross-coupled NAND gates, and two inputs labeled S for set and R for
reset.
SR latch with NOR gates
Digital Logic Design Ch1-11
SR latch with NAND gates
Digital Logic Design Ch1-1212
SR Latch
R
S
Q
Q
S R Q0 Q Q’
0 0 0
0
1
0
0
0 1 Q = Q0
Initial Value
Digital Logic Design Ch1-1313
Latches
SR Latch
R
S
Q
Q
S R Q0 Q Q’
0 0 0 0 1
0 0 1
1
0
0
0
1 0 Q = Q0
Q = Q0
Digital Logic Design Ch1-1414
Latches
SR Latch
R
S
Q
Q
S R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0
0
1
1
0
1 Q = 0
Q = Q0
Digital Logic Design Ch1-1515
SR Latch
R
S
Q
Q
S R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 11
0
1
0
0 1
Q = 0
Q = Q0
Q = 0
Digital Logic Design Ch1-1616
Latches
SR Latch
R
S
Q
Q
S R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 0 1
1 0 0
0
1
0
1
1 0
Q = 0
Q = Q0
Q = 1
Digital Logic Design Ch1-1717
SR Latch
R
S
Q
Q
S R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 0 1
1 0 0 1 0
1 0 1
1
0
0
1
1 0
Q = 0
Q = Q0
Q = 1
Q = 1
Digital Logic Design Ch1-1818
SR Latch
R
S
Q
Q
S R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 0 1
1 0 0 1 0
1 0 1 1 0
1 1 0
0
1
1
1
0 0
Q = 0
Q = Q0
Q = 1
Q = Q’
0
Digital Logic Design Ch1-1919
SR Latch
R
S
Q
Q
S R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 0 1
1 0 0 1 0
1 0 1 1 0
1 1 0 0 0
1 1 1
1
0
1
1
0 0
Q = 0
Q = Q0
Q = 1
Q = Q’
0
Q = Q’
Digital Logic Design Ch1-20
SR Latch
R
S
Q
Q
S R Q
0 0 Q0
0 1 0
1 0 1
1 1 Q=Q’=0
No change
Reset
Set
Invalid
S’ R’ Q
0 0 Q=Q’=1
0 1 1
1 0 0
1 1 Q0
Invalid
Set
Reset
No change
S
R
Q
Q
Digital Logic Design Ch1-21
SR Latch
• SR stands for Set/Reset Latch
– Stores one bit of state (Q)
• Control what value is being stored with S, R inputs
– Set: Make the output 1
(S = 1, R = 0, Q = 1)
– Reset: Make the output 0
(S = 0, R = 1, Q = 0)
• Must do something to avoid
invalid state (when S = R = 1) S
R Q
Q
SR Latch
Symbol
Digital Logic Design Ch1-22
S – R Flip Flop
S - R F F (Controlled Latch)
C S R Q
0 x x Q0
1 0 0 Q0
1 0 1 0
1 1 0 1
1 1 1 Q =Q’
No change
No change
Reset
Set
Invalid
S
R
Q
Q
S
R
C
S
RQ
QS
R
C
Digital Logic Design Ch1-23
Draw the Time diagram for the output Q for Clocked S-R Flip Flop if the
Pulses of Inputs (CK, S, R ) as shown below , Let the initial output Q=0.
Digital Logic Design Ch1-24
D – Type Flip Flop (D = Data)
One way to eliminate the undesirable condition of the indeterminate
state in the SR latch is to ensure that inputs S and R are never equal to 1
at the same time. This is done in the D latch, shown in Fig
Flip Flop CircuitModes of operationSymbol
CK D Q
0 x Q0
1 0 0
1 1 1
No change
Reset
Set
D -Flip Flop
Digital Logic Design Ch1-25
D – Type Latch Time Diagram
CK
Timing Diagram
D
Q
t
Output may change
Digital Logic Design Ch1-26
Latch VS Flip-Flops
Controlled latches are level-triggered
Flip-Flops are edge-triggered
C
CLK Positive Edge
CLK Negative Edge
Digital Logic Design Ch1-27
Master-Slave D Flip-Flop
D Latch
(Master)
D
C
QD Latch
(Slave)
D
C
Q QD
CLK
CLK
D
QMaster
QSlave
Looks like it is negative edge-
triggered
Master Slave
Digital Logic Design Ch1-28
J-K Flip Flop
Circuit DiagramTable CharacteristicsSymbol
• JK flip-flop has two inputs and performs all three operations. The circuit diagram of a
JK flip-flop constructed as shown in Fig.
• gates is shown in Fig. The J input sets the flip-flop to 1, the K input resets it to 0,
and when both inputs are enabled, the output is complemented (Toggle)
ModeOutputInputs
QCKKJ
No Change
𝑄0000
Reset0110
Set1101
Toggle𝑄111
J-K Flip Flop
Digital Logic Design Ch1-29
Digital Logic Design Ch1-30
T Flip-Flop
J Q
QK
T D Q
Q
T
T Q
Q
T Q (t+1)
0 Q (t)
1 Q’(t)
No change
Toggle
T - Flip Flop
Digital Logic Design Ch1-31
D Q (t +1)
0 0
1 1
Reset
Set
J K Q (t +1)
0 0 Q (t)
0 1 0
1 0 1
1 1 Q’(t)
No change
Reset
Set
Toggle
T Q (t +1)
0 Q (t)
1 Q’(t)
No change
Toggle
Flip-Flop Characteristic Tables
Q(t+1) = D
Q(t +1) = T Q
𝑸 𝒕 + 𝟏 = 𝑱𝑸+ 𝑲Q
Digital Logic Design Ch1-32
Analysis / Derivation
J K Q(t ) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
J Q
QK
0 1 0 0
1 1 0 1
J
J
K Q K Q KQ QK
𝑸 𝒕 + 𝟏 = 𝑱𝑸+ 𝑲Q
After Minimization
Using K-Map to Minimize The table
No change
Reset
Set
Toggle
Digital Logic Design Ch1-33
Analysis of Clocked Sequential Circuits
The Steps of Analysis are summarized into:
Circuit diagram Equation State table State diagram
The State
State = Values of all Flip-Flops
Example
Initial values: A B = 0 0
D Q
Q
CLK
D Q
Q
A
B
y
x
Digital Logic Design Ch1-34
D Q
Q
CLK
D Q
Q
A
B
y
xA(t+1) = DA
= A(t) x(t)+B(t) x(t)
= A x + B x
B(t+1) = DB
= A’(t) x(t)
= A’ x
y(t) = [A(t)+ B(t)] x’(t)
= (A + B) x’
State Equations
Digital Logic Design Ch1-3535
Analysis of Clocked Sequential Circuits
State Table (Transition Table)
D Q
Q
CLK
D Q
Q
A
B
y
x
A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
Present
StateInput
Next
StateOutput
A B x A B y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
t+1 tt
0 0 0
0 1 0
0 0 1
1 1 0
0 0 1
1 0 0
0 0 1
1 0 0
Digital Logic Design Ch1-3636
Analysis of Clocked Sequential Circuits
State Table (Transition Table)
D Q
Q
CLK
D Q
Q
A
B
y
x
A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
Present
State
Next State Output
x = 0 x = 1 x = 0 x = 1
A B A B A B y y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0
t+1 tt
Digital Logic Design Ch1-37
Analysis of Clocked Sequential Circuits
State Diagram
D Q
Q
CLK
D Q
Q
A
B
y
x
0 0 1 0
0 1 1 1
0/0
0/1
1/0
1/0
1/0
1/0 0/1
0/1
AB input/output
Present
State
Next State Output
x = 0 x = 1 x = 0 x = 1
A B A B A B y y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0
Digital Logic Design Ch1-38
D Flip-Flops
Example:
D Q
Q
x
CLK
yA
Present
StateInput
Next
State
A x y A
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
0 100,11 00,11
01,10
01,10
A(t+1) = DA = A x y
Digital Logic Design Ch1-39
JK Flip-Flops
Example :
J Q
QK
CLK
J Q
QK
x
A
BPresent
StateI/P
Next
State
Flip-Flop
Inputs
A B x A B JA KA JB KB
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 1 0
0 0 0 1
1 1 1 0
1 0 0 1
0 0 1 1
0 0 0 0
1 1 1 1
1 0 0 0
0 1
0 0
1 1
1 0
1 1
1 0
0 0
1 1
JA = B KA = B x’
JB = x’ KB = A x
A(t+1) = JA Q’A + K’A QA
= A’B + AB’ + Ax
B(t+1) = JB Q’B + K’B QB
= B’x’ + ABx + A’Bx’
Digital Logic Design Ch1-40
JK Flip-Flops
Example:
J Q
QK
CLK
J Q
QK
x
A
BPresent
StateI/P
Next
State
Flip-Flop
Inputs
A B x A B JA KA JB KB
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 1 0
0 0 0 1
1 1 1 0
1 0 0 1
0 0 1 1
0 0 0 0
1 1 1 1
1 0 0 0
0 1
0 0
1 1
1 0
1 1
1 0
0 0
1 1
0 0 1 1
0 1 1 0
1 0 1
0
1
00
1
Digital Logic Design Ch1-41
T Flip-Flops
Example:
TA = B x TB = x
y = A B
A(t+1) = TA Q’A + T’A QA
= AB’ + Ax’ + A’Bx
B(t+1) = TB Q’B + T’B QB
= x B
A
B
T Q
QR
T Q
QR
CLK Reset
xy
Present
StateI/P
Next
State
F.F
InputsO/P
A B x A B TA TB y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0
0 1
0 0
1 1
0 0
0 1
0 0
1 1
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0
0
0
0
0
0
1
1
Digital Logic Design Ch1-42
T Flip-Flops
Example:
A
B
T Q
QR
T Q
QR
CLK Reset
xy
Present
StateI/P
Next
State
F.F
InputsO/P
A B x A B TA TB y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0
0 1
0 0
1 1
0 0
0 1
0 0
1 1
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0
0
0
0
0
0
1
1
0 0 0 1
1 1 1 0
0/0
1/0
0/0
1/0
1/0
1/1
0/00/1
Digital Logic Design Ch1-43
Mealy and Moore Models
The Mealy model: the outputs are functions of both the
present state and inputs .
The outputs may change if the inputs change during the clock pulse
period.
» The outputs may have momentary false values unless the inputs are
synchronized with the clocks.
The Moore model: the outputs are functions of the present
state only .
The outputs are synchronous with the clocks.
Digital Logic Design Ch1-44
Present
StateI/P
Next
StateO/P
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
Mealy
For the same state,
the output changes with the input
Present
StateI/P
Next
StateO/P
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 1 0
0 1 1 1 0 0
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 1
Moore
For the same state,
the output does not change with the input
Digital Logic Design Ch1-45
Moore State Diagram
State / Output
0 0 / 0 0 1 / 0
1 1 / 1 1 0 / 0
0
1
1
1
00
0
1
Digital Logic Design Ch1-46
State Reduction and Assignment
State Reduction Reductions on
the number of flip-flops and
the number of gates.
A reduction in the number of
states may result in a reduction in
the number of flip-flops.
An example state diagram
showing in Fig.
Digital Logic Design Ch1-47
Only the input-output sequences
are important.
Two circuits are equivalent
» Have identical outputs for all
input sequences;
» The number of states is not
important.
State: a a b c d e f f g f g a
Input: 0 1 0 1 0 1 1 0 1 0 0
Output: 0 0 0 0 0 1 1 0 1 0 0
Digital Logic Design Ch1-48
Equivalent states
Two states are said to be equivalent
» For each member of the set of inputs, they give exactly the same output and
send the circuit to the same state or to an equivalent state.
» One of them can be removed.
Digital Logic Design Ch1-49
Reducing the state table
e = g (remove g);
d = f (remove f);
Digital Logic Design Ch1-50
The reduced finite state machine
State: a a b c d e d d e d e a
Input: 0 1 0 1 0 1 1 0 1 0 0
Output: 0 0 0 0 0 1 1 0 1 0 0
Digital Logic Design Ch1-51
The checking of each pair of
states for possible
equivalence can be done
systematically using
Implication Table.
The unused states are treated
as don't-care condition
fewer combinational gates.
Reduced State diagram
Digital Logic Design Ch1-52
Design Procedure
Design Procedure for sequential circuit
The word description of the circuit behavior to get a state diagram;
State reduction if necessary;
Assign binary values to the states;
Obtain the binary-coded state table;
Choose the type of flip-flops;
Derive the simplified flip-flop input equations and output equations;
Draw the logic diagram;
Digital Logic Design Ch1-53
Design of Clocked Sequential Circuits with D F.F.
Example.:
Detect 3 or more consecutive 1’s
Synthesis using D Flip-Flops
DA (A, B, x) = ∑ (3, 5, 7)
= A x + B x
DB (A, B, x) = ∑ (1, 5, 7)
= A x + B’ x
y (A, B, x) = ∑ (6, 7)
= A B
B
0 0 1 0
A 0 1 1 0
x B
0 1 0 0
A 0 1 1 0
xB
0 0 0 0
A 0 0 1 1
x
Digital Logic Design Ch1-54
Example:
Detect 3 or more consecutive 1’s
DA = A x + B x
DB = A x + B’ x
y = A B
Synthesis using D Flip-Flops
D Q
Q
A
CLK
x
BD Q
Q
y
Digital Logic Design Ch1-55
Quiz
1-The D latch constructed with four NAND gates and an inverter. Consider the following three other
ways for obtaining a D latch. In each case, draw the logic diagram and verify the circuit operation.
(a) Use NOR gates for the SR latch part and AND gates for the other two. An inverter may be needed.
(b) Use NOR gates for all four gates. Inverters may be needed.
(c) Use four NAND gates only (without an inverter). This can be done by connecting the output of the
upper gate (the gate that goes to the SR latch) to the input of the lower gate (instead of the
inverter output).
2- Construct a JK flip-flop, Show that the characteristic equation for the complement output of a JK flip-flop is
Q’ (t + 1) = J’ Q’ + KQ
3- A PN flip-flop has four operations: clear to 0, no change, complement, and set to 1, when inputs P
and N are 00, 01, 10,
and 11, respectively.
(a) Tabulate the characteristic table. (b) * Derive the characteristic equation.
(c) Show how the PN flip-flop can be converted to a D flip-flop
4- A sequential circuit with two D flip-flops A and B, two inputs, x and y ; and one output z is specified
by the following next-state and output equations
A(t + 1) = xy’ + xBB(t + 1) = xA + xB’
z = A(a) Draw the logic diagram of the circuit.
(b) List the state table for the sequential circuit.
(c) Draw the corresponding state diagram.
Digital Logic Design Ch1-56
Sol: 1
A
B
C
Digital Logic Design Ch1-57
Sol : 2
Digital Logic Design Ch1-58
(C)
Ans(3)
Digital Logic Design Ch1-59
Sol. 4
Digital Logic Design Ch1-60
Digital Logic Design Ch1-61
5- A sequential circuit has one flip-flop Q, two inputs x and y, and one output S . It consists of a full-adder circuit connected to a D flip-flop, as shown in Fig. Derive the
state table and state diagram of the sequential circuit.
Digital Logic Design Ch1-62
Digital Logic Design Ch1-63
6- A sequential circuit has two JK flip-flops A and B and one input x The circuit is described by the
following flip-flop input equations :
𝑱𝑨 = 𝒙 𝑲𝑨 = 𝑩
𝑱𝑩 = 𝒙 𝑲𝑩 = 𝑨
a) Derive the equations A(t+1) and B(t+1) by substituting the input equations for the J and K variables.
b) Draw the state diagram of the circuit.
Sol:
Digital Logic Design Ch1-64
7- A sequential circuit has two JK flip-flops A and B , two inputs x and y, and one output z.
The flip flop input equations and circuit output equation are :
𝑱𝑨 = 𝑩𝒙 + 𝑩 𝒚 𝑲𝑨 = 𝑩 x 𝒚
𝑱𝑩 = 𝑨𝒙 𝑲𝑩 = 𝑨 + x 𝒚𝒛 = 𝑨𝒙 𝒚 + B𝒙 𝒚
a) Draw the logic diagram of the circuit.
b) Tabulate the state table
c) Derive the state equations for A and B.
Digital Logic Design Ch1-65
Digital Logic Design Ch1-66
Digital Logic Design Ch1-67
8- Design a sequential circuit with two D flip flops A and B, and one input x_in.
a)When x_in =0 , the state of the circuit remains the same.
When x_in =1, the circuit goes through the state transitions from 00 to 01, to11, to 10, back to 00
and repeat.
b) When x_in =0, the state of the circuit remains the same .
When x_in=1, the circuit goes through the state transition from 00 to 11, to 01, to 10 back to 00,
and repeats
Digital Logic Design Ch1-68
Digital Logic Design Ch1-69
9- List State table for the JK flip-flop using Q as the present and next state and J and K as inputs .
Design the sequential circuit specified by the state table using D- Flip Flop.
Sol.
Digital Logic Design Ch1-70
END