sequential logic materials taken from: digital design and computer architecture by david and sarah...

Sequential Logic

Materials taken from: Digital Design and Computer Architecture by David and Sarah

Harris &The Essentials of Computer Organization and

Architecture by L. Null & J. Lobur

2

3.6 Sequential Circuits• Combinational logic circuits are perfect for

situations when we require the immediate application of a Boolean function to a set of inputs.

• There are other times, however, when we need a circuit to change its value with consideration to its current state as well as its inputs.

– These circuits have to “remember” their current state.

• Sequential logic circuits provide this functionality for us.

3

• As the name implies, sequential logic circuits require a means by which events can be sequenced.

• State changes are controlled by clocks.– A “clock” is a special circuit that sends electrical pulses

through a circuit.• Clocks produce electrical waveforms such as the

one shown below.

3.6 Sequential Circuits

4

• State changes occur in sequential circuits only when the clock ticks.

• Circuits can change state on the rising edge, falling edge, or when the clock pulse reaches its highest voltage.


5

• Circuits that change state on the rising edge, or falling edge of the clock pulse are called edge-triggered.

• Level-triggered circuits change state when the clock voltage reaches its highest or lowest level.


6

• To retain their state values, sequential circuits rely on feedback.

• Feedback in digital circuits occurs when an output is looped back to the input.

• A simple example of this concept is shown below.– If Q is 0 it will always be 0, if it is 1, it will always be 1.

Why?


Copyright © 2007 Elsevier 3-<7>

A Bistable Feedback CircuitQ

Q

I1

I2

0

1

1

0

• Consider the two possible cases:– Q = 0: then Q = 1 and Q = 0 (consistent)

– Q = 1: then Q = 0 and Q = 1 (consistent)

• Bistable circuit stores 1 bit of state in the state variable, Q (or Q )

• But there are no inputs to control the state

Q

Q

I1

I2

1

0

0

1


SR (Set/Reset) LatchR

S

Q

Q

N1

N2

• SR Latch

• Consider the four possible cases:– S = 1, R = 0

– S = 0, R = 1

– S = 0, R = 0

– S = 1, R = 1


SR Latch Analysis– S = 1, R = 0: then Q = 1 and Q = 0

– S = 0, R = 1: then Q = 0 and Q = 1

R

S

Q

Q

N1

N2

0

1

R

S

Q

Q

N1

N2

1

0


SR Latch Analysis– S = 1, R = 0: then Q = 1 and Q = 0

– S = 0, R = 1: then Q = 0 and Q = 1

R

S

Q

Q

N1

N2

0

1

1

00

0

R

S

Q

Q

N1

N2

1

0

0

10

1


SR Latch Analysis– S = 0, R = 0: then Q = Qprev

– S = 1, R = 1: then Q = 0 and Q = 0

R

S

Q

Q

N1

N2

1

1

R

S

Q

Q

N1

N2

0

0

R

S

Q

Q

N1

N2

0

0

0

Qprev = 0 Qprev = 1


SR Latch Analysis– S = 0, R = 0: then Q = Qprev and Q = Qprev (memory!)

– S = 1, R = 1: then Q = 0 and Q = 0 (invalid state: Q ≠ NOT Q)

R

S

Q

Q

N1

N2

1

1

0

00

0

R

S

Q

Q

N1

N2

0

0

1

01

0

R

S

Q

Q

N1

N2

0

0

0

10

1

Qprev = 0 Qprev = 1

13

• The SR latch actually has three inputs: S, R, and its current output, Q.

• Thus, we can construct a truth table for this circuit, as shown at the right.

• Notice the two undefined values. When both S and R are 1, the SR latch is unstable.



D Latch

D LatchSymbol

CLK

D Q

Q

• Two inputs: CLK, D– CLK: controls when the output changes

– D (the data input): controls what the output changes to

• Function– When CLK = 1, D passes through to Q (the latch is transparent)

– When CLK = 0, Q holds its previous value (the latch is opaque)

• Avoids invalid case when Q ≠ NOT Q


D Latch Internal Circuit

S

R Q

Q

Q

QD

CLKD

R

S

CLK

D Q

Q

S R Q QCLK D

0 X1 01 1

D


D Latch Internal Circuit

S

R Q

Q

Q

QD

CLKD

R

S

CLK

D Q

Q

S R Q

0 0 Qprev0 1 01 0 1

Q

10

CLK D

0 X1 01 1

D

X10

Qprev


D Flip-Flop• Two inputs: CLK, D

• Function– The flip-flop “samples” D on the rising edge of CLK

• When CLK rises from 0 to 1, D passes through to Q

• Otherwise, Q holds its previous value

– Q changes only on the rising edge of CLK

• A flip-flop is called an edge-triggered device because it is activated on the clock edge D Flip-Flop

Symbols

D Q

Q


D Flip-Flop Internal Circuit

CLK

D Q

Q

CLK

D Q

Q

Q

Q

DN1

CLK

L1 L2

• Two back-to-back latches (L1 and L2) controlled by complementary clocks

• When CLK = 0– L1 is transparent

– L2 is opaque

– D passes through to N1

• When CLK = 1– L2 is transparent

– L1 is opaque

– N1 passes through to Q

• Thus, on the edge of the clock (when CLK rises from 0 1)– D passes through to Q

19

• If we can be sure that the inputs to an SR flip-flop will never both be 1, we will never have an unstable circuit. This may not always be the case.

• The SR flip-flop can be modified to provide a stable state when both inputs are 1.

• This modified flip-flop is called a JK flip-flop, shown at the right.- The “JK” is in honor of

Jack Kilby.


20

• At the right, we see how an SR flip-flop can be modified to create a JK flip-flop.

• The characteristic table indicates that the flip-flop is stable for all inputs.



Enabled Flip-Flops

InternalCircuit

D Q

CLKEN

DQ

0

1D Q

EN

Symbol

• Inputs: CLK, D, EN– The enable input (EN) controls when new data (D) is stored

• Function– EN = 1

• D passes through to Q on the clock edge

– EN = 0• the flip-flop retains its previous state


Resettable Flip-Flops• Inputs: CLK, D, Reset

• Function:– Reset = 1

• Q is forced to 0

– Reset = 0• the flip-flop behaves like an ordinary D flip-flop

Symbols

D Q

Resetr

23

• This illustration shows a 4-bit register consisting of D flip-flops. You will usually see its block diagram (below) instead.

A larger memory configuration is shown on the next slide.


24


25

• A binary counter is another example of a sequential circuit.

• The low-order bit is complemented at each clock pulse.

• Whenever it changes from 0 to 1, the next bit is complemented, and so on through the other flip-flops.



Synchronous Sequential Logic Design• Breaks cyclic paths by inserting registers

• These registers contain the state of the system

• The state changes at the clock edge, so we say the system is synchronized to the clock

• Rules of synchronous sequential circuit composition:– Every circuit element is either a register or a combinational circuit

– At least one circuit element is a register

– All registers receive the same clock signal

– Every cyclic path contains at least one register

• Common synchronous sequential circuits– Finite State Machines (FSMs)

– Pipelines

– memory


Finite State Machine (FSM)• Consists of:

– State register that• Store the current state and

• Load the next state at the clock edge

– Combinational logic that• Computes the next state

• Computes the outputs

NextState

CurrentState

S’ S

CLK

CL

Next StateLogic

NextState

CL

OutputLogic

Outputs

28

• The behavior of sequential circuits can be expressed using characteristic tables or finite state machines (FSMs).– FSMs consist of a set of nodes that hold the states of the

machine and a set of arcs that connect the states.• Moore and Mealy machines are two types of FSMs

that are equivalent.– They differ only in how they express the outputs of the

machine.• Moore machines place outputs on each node, while

Mealy machines present their outputs on the transitions.



Finite State Machines (FSMs)• Next state is determined by the current state and the inputs

• Two types of finite state machines differ in the output logic:– Moore FSM: outputs depend only on the current state

– Mealy FSM: outputs depend on the current state and the inputs

CLKM Nk knext

statelogic

outputlogic

Moore FSM

CLKM Nk knext

statelogic

outputlogic

inputs

inputs

outputs

outputsstate

statenextstate

nextstate

Mealy FSM

30

• The behavior of a JK flop-flop is depicted below by a Moore machine (left) and a Mealy machine (right).


31

• Although the behavior of Moore and Mealy machines is identical, their implementations differ.

This is our Moore machine.


32

• Although the behavior of Moore and Mealy machines is identical, their implementations differ.

This is our Mealy machine.



Finite State Machine Example• Traffic light controller

– Traffic sensors: TA, TB (TRUE when there’s traffic)

– Lights: LA, LB

TA

LA

TA

LB

TB

TB

LA

LB

Academic Ave.B

ravadoB

lvd.Dorms

Fields

DiningHall

Labs


FSM Black Box• Inputs: CLK, Reset, TA, TB

• Outputs: LA, LB

TA

TB

LA

LB

CLK

Reset

TrafficLight

Controller


FSM State Transition Diagram• Moore FSM: outputs labeled in each state

• States: Circles

• Transitions: ArcsS0

LA: greenLB: red

Reset


FSM State Transition Diagram• Moore FSM: outputs labeled in each state

• States: Circles

• Transitions: ArcsS0

LA: greenLB: red

S1LA: yellow

LB: red

S3LA: red

LB: yellow

S2LA: red

LB: green

TA

TA

TB

TB

Reset


FSM State Transition Table

Current State Inputs

Next State

S TA TB S'

S0 0 X

S0 1 X

S1 X X

S2 X 0

S2 X 1

S3 X X


FSM State Transition Table

Current State Inputs

Next State

S TA TB S'

S0 0 X S1

S0 1 X S0

S1 X X S2

S2 X 0 S3

S2 X 1 S2

S3 X X S0


FSM Encoded State Transition TableCurrent State Inputs Next State

S1 S0 TA TB S'1 S'0

0 0 0 X

0 0 1 X

0 1 X X

1 0 X 0

1 0 X 1

1 1 X X

State Encoding

S0 00

S1 01

S2 10

S3 11


FSM Encoded State Transition TableCurrent State Inputs Next State

S1 S0 TA TB S'1 S'0

0 0 0 X 0 1

0 0 1 X 0 0

0 1 X X 1 0

1 0 X 0 1 1

1 0 X 1 1 0

1 1 X X 0 0

State Encoding

S0 00

S1 01

S2 10

S3 11

S'1 = S1 S0

S'0 = S1S0TA + S1S0TB


FSM Output TableCurrent State Outputs

S1 S0 LA1 LA0 LB1 LB0

0 0

0 1

1 0

1 1

Output Encoding

green 00

yellow 01

red 10


FSM Output TableCurrent State Outputs

S1 S0 LA1 LA0 LB1 LB0

0 0 0 0 1 0

0 1 0 1 1 0

1 0 1 0 0 0

1 1 1 0 0 1

Output Encoding

green 00

yellow 01

red 10

LA1 = S1

LA0 = S1S0

LB1 = S1

LB0 = S1S0


FSM Schematic: State Register

S1

S0

S'1

S'0

CLK

state register

Reset

r


FSM Schematic: Next State Logic

S1

S0

S'1

S'0

CLK

next state logic state register

Reset

TA

TB

inputs

S1 S0

r


FSM Schematic: Output Logic

S1

S0

S'1

S'0

CLK

next state logic output logicstate register

Reset

LA1

LB1

LB0

LA0

TA

TB

inputs outputs

S1 S0

r


FSM Timing Diagram

CLK

Reset

TA

TB

S'1:0

S1:0

LA1:0

LB1:0

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

S1 (01) S2 (10) S3 (11) S0 (00)

t (sec)

??

??

S0 (00)

S0 (00) S1 (01) S2 (10) S3 (11) S1 (01)

??

??

0 5 10 15 20 25 30 35 40 45

Green (00)

Red (10)

S0 (00)

Yellow (01) Red (10) Green (00)

Green (00) Red (10)Yellow (01)

S0LA: greenLB: red

S1LA: yellow

LB: red

S3LA: red

LB: yellow

S2LA: red

LB: green

TA

TA

TB

TB

Reset


FSM State Encoding• Binary encoding: i.e., for four states, 00, 01, 10, 11

• One-hot encoding– One state bit per state

– Only one state bit is HIGH at once

– I.e., for four states, 0001, 0010, 0100, 1000

– Requires more flip-flops

– Often next state and output logic is simpler


Moore vs. Mealy FSM• Alyssa P. Hacker has a snail that crawls down a paper tape

with 1’s and 0’s on it. The snail smiles whenever the last four digits it has crawled over are 1101. Design Moore and Mealy FSMs of the snail’s brain.


State Transition Diagramsreset

Moore FSM

S00

S10

S20

S30

S41

0

1 1 0 1

1

01 00

reset

S0 S1 S2 S3

0/0

1/0 1/0 0/01/1

0/01/0

0/0

Mealy FSM

Mealy FSM: arcs indicate input/output


Moore FSM State Transition TableCurrent State Inputs Next StateS2 S1 S0 A S'2 S'1 S'0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

State Encoding

S0 000

S1 001

S2 010

S3 011

S4 100


Moore FSM State Transition TableCurrent State Inputs Next StateS2 S1 S0 A S'2 S'1 S'0

0 0 0 0 0 0 0

0 0 0 1 0 0 1

0 0 1 0 0 0 0

0 0 1 1 0 1 0

0 1 0 0 0 1 1

0 1 0 1 0 1 0

0 1 1 0 0 0 0

0 1 1 1 1 0 0

1 0 0 0 0 0 0

1 0 0 1 0 1 0

State Encoding

S0 000

S1 001

S2 010

S3 011

S4 100


Moore FSM Output Table

Current State Output

S2 S1 S0 Y

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0


Moore FSM Output Table

Current State Output

S2 S1 S0 Y

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 0

1 0 0 1

Y = S2


Mealy FSM State Transition and Output Table

Current State Input Next State Output

S1 S0 A S'1 S'0 Y

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

State Encoding

S0 00

S1 01

S2 10

S3 11


Mealy FSM State Transition and Output Table

Current State Input Next State Output

S1 S0 A S'1 S'0 Y

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 0

0 1 1 1 0 0

1 0 0 1 1 0

1 0 1 1 0 0

1 1 0 0 0 0

1 1 1 0 1 1

State Encoding

S0 00

S1 01

S2 10

S3 11


Moore FSM SchematicS2

S1

S0

S'2

S'1

S'0

Y

CLK

Reset

A

S2

S1

S0


Mealy FSM Schematic

S'1

S'0

CLK

Reset

S1

S0

A

Y

S0S1


Moore and Mealy Timing Diagram

Mealy Machine

Moore Machine

CLK

Reset

A

S

Y

S

Y

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

S0 S3?? S1 S2 S4 S4S2 S3 S0

1 1 0 1 1 0 1 01

S2

S0 S3?? S1 S2 S1 S1S2 S3 S0S2


FSM Design Procedure• Identify the inputs and outputs

• Sketch a state transition diagram

• Write a state transition table

• Select state encodings

• For a Moore machine:– Rewrite the state transition table with the selected state encodings

– Write the output table

• For a Mealy machine:– Rewrite the combined state transition and output table with the selected

state encodings

• Write Boolean equations for the next state and output logic

• Sketch the circuit schematic

sequential logic materials taken from: digital design and computer architecture by david and sarah...

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