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E&CE 223 Digital Circuits and Systems (A. Kennings) Page 1
Sequential Logic
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 2
Sequential Circuits
Have considered only combinational circuits in which circuit outputs are determined entirely by current circuit inputs.
We can include storage elements into a circuit that act like memory and store a system state.
inputs outputscombinatorial
circuit
memory
elements
state
Outputs are then a function of both the current circuit inputs and the system state.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 3
Types of Sequential Circuits
Two main types of sequential circuits (classification depends on how timing happens):
Synchronous Sequential Circuits – circuit behavior is determined from the knowledge of signal values at discrete instances in time.
Asynchronous Sequential Circuits - circuit behavior is determined by signals at any instant in time and the order in which input signals change.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 4
Synchronous Sequential Circuits
To control the behavior of a circuit at discrete instances in time, we will need to introduce the concept of a clock.
It’s a periodic signal consisting of a sequence of pulses. It is used to control the times at which the storage elements in the circuit change their values.
The storage elements used can be latches or flip-flops.
inputs outputscombinatorial
circuit
storage
elements
state
clock/
control
clock/
control
The clock/control connects to the storage elements which are latches or flip-flops.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 5
Clocks
Clocks are periodic.
They can control when things happen because their transition from 0 ! 1 and from 1 ! 0 occur at discrete instances in time.
The 0 ! 1 transition is often called the rising edge of the clock.
The 1 ! 0 transition is often called the falling edge of the clock.
clock1
0
rising edge (0->1
transition)
falling edge (1->0
transition)
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 6
Latches
Latches are level sensitive storage elements;
They operate based on whether signals are at logic levels 0 or 1, not on logic transitions from 0 ! 1 or 1 ! 0.
Latches are not really too useful for synchronous sequential circuits (they are for asynchronous circuits), but form the basis from which flip-flops are built.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 7
SR Latch (NOR Implementation) Illustrated
Consider the operation of the following circuit:
Q
!Q
R (reset)
S (set)
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 8
SR Latch (NOR Implementation) Explained
In general (one exception, see below), the outputs are complements of each other (this is why they are labeled Q and :Q):
When S=1, R=0 the output is Q=1, :Q=0 and the circuit in the set state.
When S=0, R=1 the output is Q=0, :Q=1 and the circuit in the reset state.
So, S=1 (active high) implies set (Q=1) and R=1 (active high) implies reset (Q=0).
When S=0, R=0 the output holds at its previous value (storage).
When S=1, R=1 the output is Q=:Q=0 which is not desirable.
We want to avoid this combination of inputs.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 9
S’R’ Latch (NAND Implementation) Illustrated
Consider the operation of the following circuit:
Q
!Q
S (set)
R (reset)
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 10
S’R’ Latch (NAND Implementation) Explained
In general (one exception, see below), the outputs are complements of each other (this is why they are labeled Q and :Q):
When S=0, R=1 the output is Q=1, :Q=0 and the circuit in the set state.
When S=1, R=0 the output is Q=0, :Q=1 and the circuit in the reset state.
So, S=0 (active low) implies set (Q=1) and R=0 (active low) implies reset (Q=0).
When S=1, R=1 the output holds at its previous value (storage).
When S=0, R=0 the output is Q=:Q=1 which is not desirable.
We want to avoid this combination of inputs.
So, it works similar to the NOR implementation, but the input values are reversed for each of the different cases.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 11
Latch With Control Input (i.e., Gated Latch)
We can add an additional control input that acts as an enable signal.
Consider adding some extra NAND gates in front of an S’R’ Latch.
This gives us a SR Latch with control input.
Q
!Q
S
R
C
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 12
Latch With Control Input Explained
Q
!Q
S
R
C
When the control input C=0,
The inputs to the latch are both 1 which puts the SR latch into hold state.
The latch outputs will not change regardless of S and R values.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 13
Latch With Control Input (NAND Implementation)
Q
!Q
S
R
C
When the control input C=1,
The S and R inputs will reach the latch and we can analyze the behavior.
The NAND gates at the input to the latchresult in active high inputs:
S=1 (and R=0) causes a set (Q=1).
R=1 (and S=0) causes a reset (Q=0).
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 14
D Latch
We must avoid the undesirable situation in which we cannot determine what the output of the latch will be…
i.e., we never want S=1, R=1 when C=1 (bad!)
The solution is to construct a latch where S and R can never have the same value.
Q
!Q
D
C
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 15
D Latch Illustrated
We still have a hold state when the control input C=0.
The output Q follows input D when the control input C=1.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 16
Schematic Symbol for SR Latch (With and Without Control Input)
S Q
R
S Q
R
C
Note: as illustrated, this means the inputs are active high; i.e., we set when S=1 (and R=0) and we reset with R=1 (and S=0).
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 17
Schematic Symbol for S’R’ Latch (With and Without Control Input)
Note: as illustrated, this means the inputs are active low; i.e., we set when S=0 (and R=1) and we reset with R=0 (and S=1).
S Q
R
S Q
R
C
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 18
Schematic Symbol for D Latch (With Control Input)
Note: For a D Latch, the control input is required, since it is via the control input that we have the hold state.
D Q
C
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 19
Textbook Sections
Information on Sequential Circuits, Synchronous Sequential Circuits and Latches can be found in the course textbook in Chapter 5, Sections 5.1 and 5.2.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 20
Problem With Latches
Latches do not allow for precise control because they are level sensitive.
Consider a D-Latch with the clock signal connected to the control input.
Output of the latch can change anytime while the clock is at its active level.
This creates an interval in time over which the state, or output, of the memory element can change rather that an instant in time at which the state, or output, of the memory element can change.
It would be better to only allow the output to change when the clock edge makes a transition from 0 ! 1 (rising edge triggering) or 1 ! 0 (falling edge triggering). This gives even more precise control!
Flip-flops give more precise control by being edge-triggered.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 21
Triggering Illustrated
Response to positive level (a latch) – large window of time for output to change.
Positive Edge Triggering. The input to the flip-flop just before the clock changes from 0 ! 1 causes the output to change just after the clock changes from 0 ! 1.
Negative Edge Triggering. The input to the flip-flop just before the clock changes from 1 ! 0 causes the output to change just after the clock changes from 1 ! 0.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 22
Negative Edge Triggered D Flip-Flop (Master-Slave)
We can make a negative edge triggered D-type flip-flop (DFF) using two D latches.
We connect the clock input to the control input of the first latch (master),and the inversion of the clock input to the control input of the second latch (slave).
D Q
C
D Q
C
D Q
CLOCK
D Latch
(master)
D Latch
(slave)Y
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 23
Operation of Negative Edge Triggered D Flip-Flop (Master-Slave)
While CLK=1, Y will follow input D via the master latch, but Q will not follow Y (it is in hold state) and will hold its current value.
When CLK=0 (at the moment of change), Y will be disconnected from D and will hold its current value. Q will follow Y via the master latch.
The effect is that the value of D just prior to the falling edge of the clock will get “transferred” to the output Q just after the falling edge of the clock.
D Q
C
D Q
C
D Q
CLOCK
D Latch
(master)
D Latch
(slave)Y
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 24
Positive Edge Triggered D Flip-Flop (Master-Slave)
We can make a positive edge triggered DFF simply by changing the inversion of the clock signal
Output of master latch, Y, follows D when clock is low (slave in hold).
Output of slave latch, Q, follows Y when clock is high (master in hold).
D Q
C
D Q
C
D Q
CLOCK
D Latch
(master)
D Latch
(slave)Y
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 25
Schematic Symbols for DFFs
We can introduce schematic symbols for DFFs.
Note the indication of the clock input and the change to the symbols (vs. a D latch) to indicate edge-triggering.
D Q
D Q
Positive Edge-Triggered DFF:
Negative Edge-Triggered DFF:
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 26
More Efficient Design of a DFF
Master-Slave is not the most efficient way to build an edge-triggered DFF.
The circuit below acts as a positive edge-triggered DFF:
Q
!Q
S
R
D
CLK
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 27
More Efficient Design of a DFF Explained (CLK=0)
When CLK=0, both S=1 and R=1 and the output latch will hold its state.
Q
!Q
S
R
D
CLK
0
1
1
hold
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 28
More Efficient Design of a DFF Explained (D=0 when CLK=0 ! 1)
When D=0 and CLK = 0 ! 1, R = 1 ! 0 and the output latch goes into its reset state (Q=0).
Further changes in D while CLK=1 cannot change R and Q=D just after clock changes.
Q
!Q
S
R
D
CLK
0->1
1
1->0
reset
0 1
Q->0
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 29
More Efficient Design of a DFF Explained (D=1 when CLK=0 ! 1)
When D=1 and CLK = 0 ! 1, S = 1 ! 0 and the output latch goes into its set state (Q=1).
Further changes in D while CLK=1 cannot change S and Q=D just after clock changes.
Q
!Q
S
R
D
CLK
0->1
1->0
1
set
1 0
Q->1
1
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 30
Sets and Resets
Sometimes flip-flops will have additional, asynchronous control inputs that force the output Q to a particular value.
An asynchronous signal that forces Q=1 is called an asynchronous set or preset.
The output will remain 1 as long as the set input is active (changes in D and CLK are ignored).
An asynchronous signal that forces Q=0 is called an asynchronous clear or reset.
The output will remain 0 as long as the reset input is active (changes in D and CLK are ignored).
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 31
Reset Illustrated
The following circuit has an (active low) asynchronous reset.
Q
!Q
S
R
D
CLK
RESET 01
1
1
0
0/1
reset/
hold
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 32
Schematic Symbols for DSRFFs (DFF With Resets and Sets)
Active low set and reset signals.
Active high set and reset signals.
D Q
R
S
D Q
R
S
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 33
Characteristic Tables and Equations
We can describe the behavior of a flip-flop via a characteristic table.
The characteristic table shows what the next flip-flop output value will be given the current flip-flop input value after the clock makes its active edge transition.
The characteristic table for a DFF is:
We can also write this as a characteristic equation:
For a DFF, the output value becomes the input value when the clock makes its active edge transition.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 34
Toggle Flip-Flops (TFF)
Another type of flip-flop that has a different behavior when compared to a DFF.
Symbol for a positive edge-triggered TFF:
T Q
T Q
Symbol for a negative edge-triggered TFF:
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 35
Behavior of a TFF
The characteristic table for the TFF:
The characteristic equation for the TFF:
So with a TFF, the output toggles (or flips) its value if the input is T=1, otherwise it remains the same.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 36
Construction Of A TFF Using a DFF
D QT
Q
CLOCK
T Q
We can actually build a TFF using a DFF and a 2-input XOR gate.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 37
JK Flip-Flops (JKFF)
J Q
K
Again, another type of flip-flop that has different behavior compared to a DFF or to a TFF.
Positive edge-triggered JKFF:
J Q
K
Negative edge-triggered JKFF:
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 38
Behavior of a JKFF
The characteristic table for the JKFF:
We can derive the characteristic equation for the JKFF (I find it easy to explain via a K-Map):
JK
Q(t)
0
1
00 01 11 10
0
1
0
0
1
1
1
0
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 39
Construction Of A JKFF Using a DFF
We can actually build a JKFF using a DFF and some other gates.
J Q
K
D Q
J
Q
CLOCKK
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 40
Circuit Timing With Flip-Flops
There are some important things to understand when we go to actually make and implement a circuit with flip-flops.
In reality, it takes time for gates to change their output values according to the input values – i.e., there are propagation delays due to resistance, capacitance, etc.
Changes in flip-flop outputs occur at the active clock edge.
There are three timing parameters that are especially important:
Setup Time (TSU).
Hold Time (TH).
Clock-To-Output Time (TCO).
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 41
Definitions
Setup Time (TSU):
The setup time of a flip-flop is the amount of time that the data inputs need to be held stable (not changing) PRIOR to the arrival of the active clock edge.
Hold Time (TH):
The hold time of a flip-flop is the amount of time that the data inputs need to be held stable (not changing) AFTER the arrival of the active clock edge.
Clock-To-Output (TCO):
The clock-to-output time of a flip-flop is the amount of time it takes for the output to become stable (at its new value) AFTER the arrival of the active clock edge.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 42
Comments
If these timing specifications are not met, then it is possible that the flip-flop will not behave as expected.
That is, if we don’t observe setup and hold times at the data inputs, then our output might not change as expected.
That is, if we don’t wait long enough (clock-to-output time) for the output to change, then we might use an incorrect value.
If we violate any of these timing parameters, then we have a timing violation.
These timing parameters (as we will see later) have an influence on how fast we can clock a circuit.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 43
Timing Parameters Illustrated (Using A DFF)
CLOCK
D
Q
TSU TH
D should not change in this interval
TCO
Q not stable (trustworthy) until this interval ends
D Q
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 44
Textbook Sections
Information on Flip-Flops can be found in the course textbook in Chapter 5, Section 5.3.