serena project: the kick off

SERENA Progress Santa Fe, May 14th 2008 AMDL - Andrea M. Di Lellis

SERENA Project: the kick offSERENA Project: the kick off


SERENA Current scheduleSERENA Current schedule


SERENA LONG TERM PLANSERENA LONG TERM PLAN


SERENA DOCUMENTATIONSERENA DOCUMENTATION

(see Released_doc annex)


SERENA SYSTEM AIVSERENA SYSTEM AIV

(see AIV_program_0.3 annex)


Outlook

SERENA SCU / SYSTEMSERENA SCU / SYSTEM

• I/Fs developing status• DHSU Architecture• System Budgets


S pW 10 / (50) Mb/s LVDS Link

2Mb/s RS-422 Link

Unit 5

NPA-IS SCU NPA-IS SCU ElectronicsElectronics

Unit- 1Unit- 1(ELENA box(ELENA box)

STROFIO20° 20° FOV

NPA-IS System

S/C SpacewireSERENA Bus

S/C fixation platforms

S/COBDH Unit

3/4

ELENA / MIPA1.8° x 76°/9°x 180°

Unit 2

PICAM 90°x 360°

Redu SpW Bus

SCU Limited PWR Bus28 VDC

SCU Limited Power Bus28 VDC

Main S/C Power Bus +28VDC

Redu S/C Power Bus +28 VDC

SCU L. PWR +28VDC

SERENA SCU / SYSTEMSERENA SCU / SYSTEM


S/C Power

J01

S/C Main SpW

J02

S/C Redu SpW

J03

PICAM PWR I/F

J04

SCU

PICAM SpW I/F

J05

GND STUD

J07

STROFIO I/F

J06

ELENA MAIN

J301

ELE/MIP HV DISABLE

MIPA ELECTRONICs

MIPA SENSOR I/F

J401

ELENA BOX

SERENA SCU / SYSTEM I/FsSERENA SCU / SYSTEM I/Fs


DHSU Block Diagram

3-EEPROM3-EEPROM

Leon-3 FT core courtesy By Gaisler Research TM

Reset Circuitry

SURVSURVPROMPROM8kx168kx16

SURVSURVPROMPROM8kx168kx16

ACTEL RTAX2000S

[A0..A16]

[D0..D24]

2-SRAM2-SRAM512kx8512kx8

with EDACwith EDAC


with EDACwith EDAC

2-EEPROM2-EEPROMEEPROM

Power Switch

Transceiver

3-Cube 3-Cube CompressorCompressor

3-Cube 3-Cube CompressorCompressor

3-CubePower Switch

Transceiver

SPACEWIRESPACEWIREkernelkernel

ECSS-E-50-12 A

SPACEWIRESPACEWIREkernelkernel

ECSS-E-50-12 A

TM/TCLVDS

Transceivers

S/C SPACEWIRE TC/TM I/FBP-MPO DHSU DPU, AMD - V1.0 Rev. C


with EDACwith EDAC


with EDACwith EDAC

1-EEPROM1-EEPROM128kx8128kx8

with EDACwith EDAC

1-EEPROM1-EEPROM128kx8128kx8

with EDACwith EDAC

EDAC 2x12 to16

Recon-structor


with EDACwith EDAC


with EDACwith EDAC

STROFIOSTROFIOI/F I/F

STROFIOSTROFIOI/F I/F

POWERPOWERControl I/F Control I/F

POWERPOWERControl I/F Control I/F

PW

R E

N/D

IS L

INE

sELENAELENA

I/F I/F

ELENAELENAI/F I/F

MIPAMIPAI/F I/F

MIPAMIPAI/F I/F

Developing& Testing I/F

EMCFILTER

+3.3VDC / DC

Converter

50 MHz OSC

S/C POWER I/F

EMCFILTER

PICAMPICAMI/F I/F

PICAMPICAMI/F I/F

LocTM/LocTC Serial 2Mb/s I/F

Drivers


Drivers


Drivers

LocTM/LocTC Serial SpW I/F

Drivers


AHBController

MemoryController

ToSRAM

I/F

TOEEPROM

I/F

AHB/APBBridge

Timers

UARTs

IrqCtrl

I/O Ports

LEONCORE

AHB Interface

AMBA AHB

AMBA APB

APB/SwitchBridge

CFGPort

Main S/C SpW IF

Redu S/C SpW IF

ToCOMPR

I/F

SERENA I/Fs architectureSERENA I/Fs architecture

SCU SpW I/F

ELE Ser IF

MIP Ser IF

STR Ser IF

Legend: 2Mb/s I/F

PIC SpW IF


SERENA Grounding schemeSERENA Grounding scheme


DATA HANDLING: Main DPUs inheritanceDATA HANDLING: Main DPUs inheritance

FORMER AMDL’s related experiences:

• CLUSTER CIS-2: DPU Designing & On-Board S/W (MAS281)

• DARA-NASA EQUATOR-S ESIC: On-Board S/W (MAS281)

• DMARS-96 &ESA MARS EXPRESS PFS: FFT DPU Design & On-Board S/W (AD21000)

• DOUBLE STAR HIA: Composition Experiment OnBoard S/W (MAS281)

• ESA SMART-1 AMIE: Microcamera - Power supply & S/C I/F board

• NASA/JPL DAWN: VIR On board compression S/W & GSE

CURRENT AMDL’s related experiences:

ESA BEPICOLOMBO SERENA: PM and Design Manager

ESA EXOMARS IRAS: Electronics Design Manager


Full representativeSCU board 100% mastered

SCU H/W demonstration mdel

DHSU Developing


SERENA ELE/SCU CPPASERENA ELE/SCU CPPA


SCU SENSORS I/Fs: SCU SENSORS I/Fs: MIPA #1/2MIPA #1/2

MIPA I/F Timing (from SARA, CHA- SARA-DS-0005, Issue 2 Rev 5, Date 2006-10-09 )

where:Sclk- 2 MHz continuous running clock generated by the SCUSin - Frame sync from SCU to MIPA, which goes high between every byte Din - Three byte command from SCU to MIPA Sout - Frame sync from MIPAto SCU, which goes high between every byte Dout - Data from MIPA to SCU. Number of bytes depends on command.


SCU SENSORS I/Fs: SCU SENSORS I/Fs: MIPA #2/2MIPA #2/2

The sensor has an auto-sync feature which requires that the three command bytes arereceived within a certain time. If not, a time out will be generated and the sensor will startwaiting for the first command byte again. In this respect a complete command can not belonger than 15 μs.

MIPA Command Categories

All software and pre-programmed command sequences are re-programmable from ground.All commands, which are sent from the SCU to MIPA during normal operation, will alsohave a corresponding tele-command (TC), which can be used to explicitly set switches andreference MIPA voltages.

MIPA Command syntax

A MIPA command consists of three bytes, sent on the synchronous serial line with thefollowing organisation:

MIPA Commands bit structure (from SARA, CHA-SARA-DS-0005, Issue 2 Rev 5, Date 2006-10-09 )


SCU SENSORS I/Fs: ELE-STROFIOSCU SENSORS I/Fs: ELE-STROFIO #1/2 #1/2

As MIPA I/F, but exchanged data are organized as 16 bit words:

ELENA & STROFIO I/F Timing

where:

Clk - 2 MHz continuous running clock generated by the DPU Din- Two word command from SCU to ELENA Sin - Frame sync from SCU to ELENA, which goes high between every byte Dout- Data from ELENA to SCU. Number of words depends on command.Sout- Frame sync from ELENA to SCU , which goes high between every byte

The interface is synchronous to Sclk. With 2 MHz clock frequency, one word (17 bit) takes8.5 μs to be transmited and a command with two words, 17 μs.


SCU SENSORS I/Fs: ELE-STROFIOSCU SENSORS I/Fs: ELE-STROFIO #2/2 #2/2

Sensors have to implement an auto-sync feature which requires that the twocommand words are received within a certain time. If not, a time out will be generatedand the sensor will start waiting for the first command byte again. In this respect acomplete command can not be longer than 18 μs.

ELENA / STROFIO Command syntax

An ELENA or STROFIO command consists of two words, sent on the synchronousserial line with the following organisation:

WORD1 (PARAM) WORD2 (COMMAND)

Bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Val

X X X X X X X X X X X X X X X X Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y

ELENA STROFIO Commands bit structure.


SENSORS I/F implementation: e.g.MIPASENSORS I/F implementation: e.g.MIPA


SpW Testing ConfigurationSpW Testing Configuration

SCU SIM:PENDER’s GR-XC3S-1500 FPGA

based LEON3

LVDS I/F

PICAM & S/C SIM I/F &

HOST USB I/F


DHSU description

The DHSU unit consists of the following functional blocks housed on a 100x160mm2 Eurocard board:

- Hi Rel FPGA based Control Unit ( Leon3 FT) -Hi Rel SRAM 512x2 kB EDAC Protected- HI Rel local power converter and power distribution switches- Rad Tolerant EEPROM 128x2 kB EDAC Protected

Optionally on a second 100x100 mm2 mezzanine board:- Rad Tolerant 200 MIPS DSP Based DPU Compressor and glue logic

Main DHSU tasks are:- To receive and to distribute command to Sub-sys- to acquire data from active Sub-Sys- to download science and H/K data through the S/C interface ;- to control and manages the IRAS suite functions- to control and distributes primary power to Sub-Sys


EDAC

Faulty Case: corrupted bus:- Above: 1 err detected & recovered- Bottom: 2 err detected


DHSU: LEON 3

H/W STATUS:•Updating developing configuration of PENDER’s GR-XC3S-1500 FPGA based LEON3 development/prototyping board XCONFIG & XGRLIB and uploading procedures via IMPACT tool (Xilinx) tested and running for customized Leon3 configuration. For ACTEL developing procured A3PE3000 complete developing platform

•Boot PROMs prepared.•Received directly from Gaisler a customized .MCS version which encloses the optional GR SpW core.

S/W STATUS:•Updating S/W Development tools GRMON, GRSIM, BCC, GDB/DDD integrated on Cygwin and Win XP platforms. S/W development controlled under ECLIPSE 3.2.

DOC Status Preliminary definition of the internal I/Fs to Sub-Subsystem communication protocol issued. Provided a 2nd issue of Communication Interface Control Document BC-SRN-0045-00-01_.Doc

OPEN ISSUES:• no major issues


BUDGETSBUDGETS

InstrumentInterface

Nominal

(EOL/BOL) [W]

Calibration

(EOL/BOL) [W]

Burst

(EOL/BOL) [W]

Diagnostic

(EOL/BOL) [W]

ELENA with SCU 10.3 / 9.4 11.6 / 9.7 12.1 / 10.1 6.6 / 5.5

STROFIO 5 / 4.2 5 / 4.2 5 / 4.2 5 / 4.2

MIPA 3.5 / 2.9 3.5 / 2.9 3.5 / 2.9 3.5 / 2.9

PICAM 4.9 / 4.1 7.8 / 6.5 7.8 / 6.5 4.9 / 4.1

*Total 23.7 / 20.6 27.9 / 23.3 28.4 / 23.7 20.0 / 16.7

SCU 2.9 / 2.4 2.9 / 2.4 3.7 / 3.1 2.0 / 1,7

Power

Mass

TC Budget refined according to BC-SRN-0045-00-01Communication Interface Control Document

TM BUDGETSRef BC-EST-RS-02522 Draft 2

U N IT/M OD E N OR M AL

b/sC ALIB R ATION

b/sH IGH R E S .

b/sH /Kb/s

E LE N A 1092 150 4324 128S TR OFIO 200M IP A 64 512P IC A M 495 (S -S c i/B ) 3715 (D iag-A ) 3715 (P eak ) 68.3

serena project: the kick off

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