serial ata technology_final_9!27!06 (3)

8/3/2019 Serial ATA Technology_Final_9!27!06 (3)

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An Overview ofSerial ATA Technology

Chris EricksonGraduate Student

Department of Electrical and Computer EngineeringAuburn University, Auburn, AL [email protected]
mailto:[email protected]:[email protected]


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Objectives

Why SATA was invented

The differences between PATA and SATA

How the hardware is structured to transmitand receive SATA

Protocol of SATA transmission


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What is PATA?

All of the below synonyms refer to a modern dayPATA drive

PATA Parallel Advanced Technology Attachment

UDMA Ultra Direct Memory Access

IDE Integrated Device Electronics

EIDE Enhanced IDE


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More on PATA

40 & 80 wire cable option

40 wire limited to UDMA 33 MB/s and below

80 wire allowed for UDMA 66, 100, 133 MB/s

Required by ATA spec to be 5v tolerant(3.3v has been the norm for several years)

Must support Master/Slave/Cable Select


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SATA Basics

New Connector

Saves space

More reliable

More air flow

Connector has 4 transmission wires

Tx differential pair

Rx differential pair


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SATA Basics

SATA I for 1.5Gbps ~ 150MB/s

SATA II for 3.0Gbps ~ 300MB/s

Provides support for legacy command set

Includes new commands for SATA BISTand power management


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Connectivity

Serial ATA is point-to-point topology

Hosts can support multiple devices but

requires multiple links

100% available link bandwidth

Failure of one device or link does not affectother links


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Link Characteristics

SATA uses full-duplex links

Protocol only permits frame transfer in onedirection at a time

Each link consists of a transmit and a receivepair

SATA uses low voltage levels

Nominal voltage +/-250mV differential


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Power Management

SATA has Phy Ready Capable of sending and receiving data.

Main phase locked loop are on and active Partial Physical layer is powered but in a reduced

state. Must be able to return to Phy Ready within 10us. Slumber Physical layer is powered but in a reduced

state. Must be able to return to Phy Ready within 10ms.

ATA also defines IDLE, STANDBY, and SLEEP

Necessary for newer laptop & mobile devices


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SATA Architectural ModelDevice Control Software

Buffer Memory

DMA management

Serial digital transportcontrol

Serial digital link control

Serial physical interface

Device Layers

Host Control Software

Buffer Memory

DMA management

Host Layers




Application

Transport

Link

Physical


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Physical Layer

Transmission (Tx) and Reception (Rx) of a1.5Gb/s serial stream

Perform power on sequencing

Perform speed negotiation

Provide status to link layer

Support power management requestsOut-of-Band (OOB) signal generation anddetection


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Out of Band

Part of normal power on sequence

Allows host to issue a device hard reset

Allows device to request a hard reset

Brings device out of low power state


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Out of Band Signals

COMRESET

Always originated by the host

Forces a hard reset in the device

Used to start link initialization

COMINIT

Always originated by the device

Requests a link reset

Issued by device in response to COMRESET


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Out of Band Signals (cont.)

COMWAKE

Can be originated by either host or device

Used as final phase of OOB initialization

Used to bring out of low power & test states

Exit Partial

Exit Slumber

Exit BIST


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Out of Band Signal Forms

COMRESET / COMINIT

COMWAKE

106.7 ns

106.7 ns 106.7 ns

320 ns


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Out of Band Signaling Protocol

Host Device


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SATA Port Model

Clock & DataRecovery

Serializer

Deserializer

Analog

FrontEnd

OOB Detect

COMRESET /COMINIT

COMWAKE

Data Out

RX Clock

Port Control

Logic

Tx Clock

Align Generator

Data In

Phy ResetPhy Ready

SlumberPartial

SPD ModeSystem Clock

SPD Select

Tx +

Tx -

Rx -

Rx +


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Buffer Memory

DMA management




Device Layers


Buffer Memory

DMA management

Host Layers




Application

Transport

Link

Physical


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Link Layer

8b / 10b encoding

Scrambles and descrambles data andcontrol words

Converts data from transport layer intoframes

Conduct CRC generation and checkingProvides frame flow control


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Encoding Concepts

All 32 bit Dwords are encoded for SATA 32 bits data = 40 bits of transmission

Provides sufficient transition density Guarantees transition (0s and 1s) even if data

is 0x00 or 0xFF

Provides an easy way to detecttransmission error


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Current Running Disparity (CRD)

As each character is encoded a count ismaintained of the number of 0s and 1s being

transmitted

More 1s than 0s give positive disparity More 0s than 1s gives negative disparity

Same number gives neutral disparity

Only valid values of CRD are -1 and 1

Any other value indicates that a transmission errorhas occurred


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CRD+ & CRD- Encoded Characters

0 0 1 1 1 1 1 1

1 0 1 0 1 1 1 0 0 1 0 1 0 1 0 0 1 0 0 1

8b Character 0x3F

This 10b Character transmittedwhen CRD negative

This 10b Character transmittedwhen CRD positive

This character

6 ones

4 zeros

Disparity +2

This character

4 ones

6 zeros

Disparity -2


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SATA Primitives

Convey real-time state information

Control transfer of information betweenhost and device

Provide host/device coordination


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SATA Primitives

ALIGN Speed negotiation and at leastevery 256 Dword

SYNC Used when in idle to maintain bitsynchronization

CONT Used to suppress repeatedprimitives


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SATA Primitives

X_RDY

R_RDY

R_IP

R_OK

R_ERR

SOF

EOF

HOLD

HOLDA


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SATA Frame Structure

All SATA frames consist of:

A start of frame (SOF) delimiter

A payload transport layer information

A Cyclic Redundancy Check (CRC)

An end of frame (EOF) delimiter

SOF CRC EOFPayload Data


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Link Layer Protocol (1)

SYNCSYNCSYNCSYNCSYNCSYNC

SYNC SYNCSYNCSYNCSYNCSYNC

Host Device


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SYNCSYNCX_RDYX_RDYX_RDYX_RDY

SYNC SYNCSYNCSYNCSYNCSYNC

Host Device


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X_RDYX_RDYX_RDYX_RDYX_RDYX_RDY

SYNC R_RDYR_RDYR_RDYR_RDYSYNC

Host Device


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X_RDYX_RDYSOFDATADATADATA

R_RDY R_RDYR_RDYR_RDYR_RDYR_RDY

Host Device


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DATADATADATADATADATADATA

R_RDY R_IPR_IPR_IPR_IPR_RDY

Host Device


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DATADATACRCEOFWTRMWTRM

R_IP R_IPR_IPR_IPR_IPR_IP

Host Device


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CRCEOFWTRMWTRMWTRMWTRM

R_IP R_IPR_IPR_IPR_IPR_IP

Host Device


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WTRMWTRMWTRMWTRMWTRMWTRM

R_IP R_OKR_OKR_OKR_OKR_IP

Host Device


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WTRMWTRMSYNCSYNCSYNCSYNC

R_OK R_OKR_OKR_OKR_OKR_OK

Host Device


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Link Layer Protocol (last)

SYNCSYNCSYNCSYNCSYNCSYNC

R_OK SYNCSYNCSYNCSYNCR_OK

Host Device

SATA A hit t l M d l


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Buffer Memory

DMA management




Device Layers


Buffer Memory

DMA management

Host Layers




Application

Transport

Link

Physical


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Transport Layer

Responsible for the management ofFrame Information Structures (FIS)

At the command of Application layer: Format the FIS

Make frame transmission request to Link layer

Pass FIS contents to Link layer Receive transmission status from Link layer

and reports to Application layer


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Frame Information Structure (FIS)

A FIS is a mechanism to transfer informationbetween host and device application layers

Shadow Register Block contents ATA commands

Data movement setup information

Read and write data

Self test activation

Unique FIS Type Code


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FIS types

FIS TYPECODE Description Direction

27h Register transfer host to device H D

34h Register transfer device to host D H

A1h Set Device bits D H

39h DMA Activate D H

41h DMA Setup D H

58h BIST Activate D H

5Fh PIO Setup D H

46h Data D H


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Register Host to Device FIS

Byte 3 Byte 2 Byte 1 Byte 0

Dword 0 Features Command Reserved FIS TYPE(27h)

Dword 1 Dev/Head Cyl High Cyl Low SectorNumber

Dword 2 Features(exp)

Cyl High(exp)

Cyl Low(exp)

SectorNumber

Dword 3 Control Reserved SectorCount SectorCount

Dword 4 Reserved Reserved Reserved Reserved


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BIST Activate FIS


0 Reserved [ TASLFPRV ] Reserved FIS Type 58h

1 Data [31:24] Data [23:16] Data [15:8] Data [7:0]

2 Data [31:24] Data [23:16] Data [15:8] Data [7:0]

T - Far end transmit only transmit Dwords defined in words 1 & 2A - No ALIGN transmission (valid only with T)

S - Bypass scrambling (valid only with T)L - Far end retimed loopback with ALIGN insertionF - Far end analog loopbackP - Transmit primitives defined in words 1 & 2 of the FISR - ReservedV - Vendor Unique Test Mode other bits undefined


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Data FIS


Dword 0 Reserved Reserved Reserved FIS TYPE(46h)

Dword 1

N Dwords of Data

Minimum 1 Dword

Maximum 2048 Dwords

Dword 2

. . .

Dword N

SATA Architectural Model


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Buffer Memory

DMA management




Device Layers


Buffer Memory

DMA management

Host Layers




Application

Transport

Link

Physical


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Command / Application Layer

Defined using a series of state diagrams

Register H D

Register D H

DMA data in

DMA data out

Host command layer may be the same butmay only support legacy commands


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Completed !!

Any Question? Comments?

serial ata technology_final_9!27!06 (3)

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