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S1, 2006 COMP9032 Week13 1

Serial Input/Output

Lecturer: Annie Guo

S1, 2006 COMP9032 Week13 2

Lecture overview

• Serial communication

– Concepts

– Standards

• USART in AVR

S1, 2006 COMP9032 Week13 3

Why Serial I/O?

• Problems with Parallel I/O:

– Needs a wire for each bit.

– When the source and destination are more than a

few feet the parallel cable can be bulky and

expensive.

– Susceptible to reflections and induced noises for

long distance communication.

• Serial I/O overcomes these problems.

S1, 2006 COMP9032 Week13 4

Transmit Data

Buffer

Parallel In/Serial

Out Shift Register

Data From

Source

Received Data

Buffer

Serial In/Parallel

Out Shift Register

Data To Destination

Serial Data Tclock Rclock

TRANSMITTER RECEIVER

n n

Serial Communication System

Structure

S1, 2006 COMP9032 Week13 5


Structure (cont.)

• At the communication source:

– The parallel interface transfers data from the

source to the transmit data buffer.

– The data is loaded into the Parallel In Serial Out

(PISO) register and Tclock shifts the data bits out

from the shift register to the receiver.

S1, 2006 COMP9032 Week13 6


Structure (cont.)

• At the communication destination:

– Rclock shifts each bit received into the Serial In

Parallel Out (SIPO) register.

– After all data bits have been shifted, they are

transferred to the received data buffer.

– The data in the received data buffer can be read

by an input operation via the parallel interface.

S1, 2006 COMP9032 Week13 7

Serial Communication

• There are two basic types of serial

communications

– synchronous

– asynchronous

S1, 2006 COMP9032 Week13 8

Synchronous VS Asynchronous

• Synchronous

– Transmitter and receiver are synchronized

• Need extra hardware for clock synchronization

– Having faster data transfer rate

• Asynchronous

– Transmitter and receiver use different clocks. No

clock synchronization is required.

– Used in many applications such as keyboards,

mice, modems

– The rest of this lecture focuses on Asynchronous

communication

S1, 2006 COMP9032 Week13 9

UART

• The device that implements both transmitter and

receiver in a single integrated circuit is called a UART

(Universal Asynchronous Receiver/Transmitter).

• UART uses least significant first order

– The least significant bit of data is transferred first

• Data are transmitted asynchronously.

– Clocks on both sides are not synchronized

– But receivers have a way to synchronise the data receiving

operation with data transmission operation

• UART is the basis for most serial communication

hardware.

S1, 2006 COMP9032 Week13 10

UART Structure

Transmitter

Receiver

UART

Receiver

Transmitter

UART

Tclock1

Rclock1 Tclock2

Rclock2

Data Bus Data Bus

S1, 2006 COMP9032 Week13 11

UART Data Formats

• Before transmission, data should be encoded

– Many encoding schemes, such as ASCII

• Each encoded data is encapsulated with two bits

– Start bit and stop bit

• Mark and space: the logic one and zero levels are

called mark and space.

– When the transmitter is not sending anything, it holds the

line at mark level, also called idle level.

Least Significant

Bit

Optional

Parity Bit

Stop

Bit

Start

Bit

Data Bits

Mark

Space

S1, 2006 COMP9032 Week13 12

UART Data Formats (cont.)

• Typical bits in data transmission: – Start bit: When the transmitter has data to send, it first

changes the line from the mark to the space level for one bit time. This synchronises the receiver with transmitter. When the receiver detects the start bit, it knows to start clocking in the serial data bits.

– Data bits: representing a data, such as a character

– Parity bit: used to detect errors in the data

• For odd parity: the bit makes the total number of 1s in the data odd

• For even parity: the bit makes the total number of 1s in the data even.

– Stop bit: added at the end of data bits. It gives one bit-time between successive data. Some systems require more than one stop bit.

S1, 2006 COMP9032 Week13 13

Data Transmission Rate

• The rate at which bits are transmitted is called

baud rate.

• It is given in bits per second

• Standard data rates – Baud:

110, 150, 300, 600, 900, 1200, 2400, 4800, 9600,

14400, 19200, 38400, 57800

S1, 2006 COMP9032 Week13 14

Communication System Types

• Three ways that data can be sent in serial

communication system:

– Simplex system

– Full-duplex (FDX) system

– Half-duplex (HDX) system

S1, 2006 COMP9032 Week13 15

Simplex System

– Data are sent in one direction only

• For example, computer to a serial printer.

– Simple

• If the computer does not send data faster than the printer

can accept it, no handshaking signals are required.

– Two signal wires are needed for this system.

Computer Printer

S1, 2006 COMP9032 Week13 16

Full-Duplex (FDX) System

– Data are transmitted in two directions.

– It is called four-wire system, although only two

signal wires and a common ground are sufficient.

Terminal Computer

S1, 2006 COMP9032 Week13 17

Half-Duplex (HDX) System

– Data are transmitted in two directions with only

one pair of signal lines.

– Additional hardware and handshaking signals

must be added to an HDX system.

Computer Computer

S1, 2006 COMP9032 Week13 18

DTE & DCE

• There are two typical devices in

communications

• DCE

– Data Communications Equipment

• Provides a path for communication

• DTE

– Data Terminal Equipment

• Connects to a communication line

S1, 2006 COMP9032 Week13 19

DTE & DCE – example

• A communication system for internet access

– PC and Internet provider server are DTEs

– Two modems are DCEs

modem PC modem Provider

server

phone line

S1, 2006 COMP9032 Week13 20

Modem

• A modulator/demodulator

– It converts logic levels into tones to be sent over a

telephone line.

– At the other end of the telephone line, a

demodulator converts the tones back to logic

levels.

S1, 2006 COMP9032 Week13 21

Standards for the Serial I/O

Interface • Interface standards are needed to allow

different manufacturers’ equipment to be

interconnected

• Must define the following elements:

– Handshaking signals

– Direction of data flow

– Types of communication devices.

– Connectors and interface mechanical

considerations.

– Electrical signal levels.

S1, 2006 COMP9032 Week13 22

Standards for the Serial I/O

Interface (cont.) • Popular standards include RS-232-C, RS-

422, RS-423 and RS-485. – RS-232-C standard is used in most serial

interface.

– If the signals must be transmitted farther than 50 feet or greater than 20 Kbits/second, another electrical interface standard such as RS-422, RS-423 or RS-485 should be chosen.

– For RS-422, RS-423 and RS-485, handshaking, direction of signal flow, and the types of communication devices are based on the RS-232-C standard.

S1, 2006 COMP9032 Week13 23

Two RS232-C Connectors

DE9 pin assignments

DB25 pin assignments

S1, 2006 COMP9032 Week13 24

DE9 DB25 Signal Purpose

1 PG Protective ground: this is actually the shield

in a shielded cable. It is designed to be

connected to the equipment frame and may

be connected to external grounds.

3 2 TxD Transmitted data: Sourced by DTE and

received by DCE. Data terminal equipment

cannot send unless RTS, CTS, DSR and

DTR are asserted.

2 3 RxD Received data: Received by DTE, sourced

by DCE.

7 4 RTS Request to send: Sourced by DTE, received

by DCE. RTS is asserted by the DTE when

it wants to send data. The DCE responds by

asserting CTS.

RS-232-C Signal Definitions

S1, 2006 COMP9032 Week13 25


8 5 CTS Clear to send: Sourced by DCE, received

by DTE. CTS must be asserted before the

DTE can transmit data.

6 6 DSR Data set ready: Sourced by DCE and

received by DTE. Indicates that the DCE

has made a connection on the telephone

line and is ready to receive data from the

terminal. The DTE must see this asserted

before it can transmit data.

5 7 SG Signal ground: Ground reference for this

signal is separate from pin 1, protective

ground.

RS-232-C Signal Definitions (cont.)

S1, 2006 COMP9032 Week13 26


1 8 DCD Data carrier detect: Sourced by DCE,

received by DTE. Indicates that a DCE has

detected the carrier on the telephone line.

Originally it was used in half-duplex

systems but can be used in full-duplex

systems, too.

4 20 DTR

9 22 RI Ring indicator: Sourced by DCE and

received by DTE. Indicates that a ringing

signal is detected.

Data terminal ready: Sourced by DTE and

received by DCE. Indicates that DTE is

ready to send or receive data.

RS-232-C Signal Definitions (cont.)

S1, 2006 COMP9032 Week13 27

RS-232-C Interconnections

• When two serial ports are connected, the data rate,

the number of data bits, whether parity is used, the

type of parity, and the number of stop bits must be

set properly and identically on each UART.

• Proper cables must be used. There are four kinds of

cables from which to choose, depending on the types

of devices to be interconnected.

– Full DTE – DCE cable

– Minimal DTE – DCE cable

– DTE – DTE null modem cable

– Minimal null modem cable

S1, 2006 COMP9032 Week13 28

TxD 3 2 2 3 TxD

RxD 2 3 3 2 RxD

SG 5 7 7 5 SG

RTS 7 4 4 7 RTS

CTS 8 5 5 8 CTS

DCD 1 8 8 1 DCD

DSR 6 6 6 6 DSR

DTR 4 20 20 4 DTR

DTE DTE DCE DCE

DE9 DB25 DB25 DE9

Full DTE – DCE cable

RS-232-C Interconnections (cont.)

S1, 2006 COMP9032 Week13 29

TxD 3 2 2 3 TxD

RxD 2 3 3 2 RxD

SG 5 7 7 5 SG

RTS 7 4 4 7 RTS

CTS 8 5 5 8 CTS

DCD 1 8 8 1 DCD

DSR 6 6 6 6 DSR

DTR 4 20 20 4 DTR

DTE DTE DCE DCE

DE9 DB25 DB25 DE9

Minimal DTE-DCE cable


S1, 2006 COMP9032 Week13 30

TxD 3 2 2 3 TxD

RxD 2 3 3 2 RxD

SG 5 7 7 5 SG

RTS 7 4 4 7 RTS

CTS 8 5 5 8 CTS

DCD 1 8 8 1 DCD

DSR 6 6 6 6 DSR

DTR 4 20 20 4 DTR

DTE DTE DTE DTE

DE9 DB25 DB25 DE9

DTE – DTE null modem cable


S1, 2006 COMP9032 Week13 31

TxD 3 2 2 3 TxD

RxD 2 3 3 2 RxD

SG 5 7 7 5 SG

RTS 7 4 4 7 RTS

CTS 8 5 5 8 CTS

DCD 1 8 8 1 DCD

DSR 6 6 6 6 DSR

DTR 4 20 20 4 DTR

DTE DTE DTE DTE

DE9 DB25 DB25 DE9

Minimal null modem cable


S1, 2006 COMP9032 Week13 32

RS-232-C Logic levels:

Mark -25 to –3 volts

Space +25 to +3 volts

D R

RS-232-C

Logic levels TTL Logic

levels

TTL Logic

levels

RS-232-C Interface

S1, 2006 COMP9032 Week13 33

RS-423 Standard

• Also a single ended system.

• Allows longer distance and higher data rates than

RS-232-C.

• Allows a driver to broadcast data to 10 receivers.

D R

R

Up to 10

receivers

RS-423 Interface

S1, 2006 COMP9032 Week13 34

RS-422 Standard

• RS-422 line drivers and receivers operates

with differential amplifier.

– These drivers eliminate much of the common-

mode noise experienced with long transmission

lines, thus allowing the longer distances and

higher data rates.

D R

R

Up to 10

receivers

RS-422 Interface

S1, 2006 COMP9032 Week13 35

RS-485 Standard

• Similar to RS-422 in that it uses differential line

drivers and receivers.

• Unlike RS-422, RS-485 provides for multiple drivers

and receivers in a bussed environment.

– Up to 32 drivers/receivers pairs can be used together.

D R

R

Up to 32

receivers

RS-485 Interface

D

Up to 32

drivers

USB

• http://www.jaycar.com.au/images_uploaded/u

sbbus.pdf

S1, 2006 COMP9032 Week13 36

In the latest PCs, many of the peripherals such as thekeyboard, mouse, scanners, printers, modem and evenexternal CD-ROM drives and CD-writers connect to thecomputer itself via a USB cable � either directly or viaa �hub� expander unit. Here�s a brief introduction to theUniversal Serial Bus or USB, which was developedexpressly for this job.

As personal computers became more and more powerful and began to be used to handle photographicimages, audio, video and other �bulky� data, it becameevident that existing communications buses were notgoing to be good enough to carry the data back andforth between the computers and their growing array ofperipherals � especially as users wanted the data to bemoved around faster, rather than more slowly. So agroup of leading computer and telecom firms includingIBM, Intel, Microsoft, Compaq, Digital Equipment, NECand Northern Telecom got together and developed USB.

The USB is a medium-speed serial data bus designedto carry relatively large amounts of data over relativelyshort cables: up to about five metres long. It can support data rates of up to 12Mb/s (megabits per second), which is fast enough for most PC peripheralssuch as scanners, printers, keyboards, mice, joysticks,graphics tablets, low-res digital cameras, modems, digitalspeakers, low speed CD-ROM and CD-writer drives,external Zip disc drives and so on.

The USB is an addressible bus system, with a seven-bitaddress code so it can support up to 127 differentdevices or �nodes� at once (the �all zeroes� code is not avalid address). However it can have only one �host�: thePC itself. So a PC with its peripherals connected via theUSB forms a �star� local area network (LAN).

On the other hand any device connected to the USBcan have a number of other nodes connected to it indaisy-chain fashion, so it can also form the �hub� for amini-star subnetwork. Similarly you can have a device

which purely functions as a hub for other node devices,with no separate function of its own. This expansion viahubs is because the USB supports a tiered star topology,as shown in Fig.1. Each USB hub acts as a kind of �trafficcop� for its part of the network, routing data from thehost to its correct address and preventing �bus contention� clashes between devices trying to send dataat the same time.

On a USB hub device, the single port used to connectto the host PC � either directly or via another hub �is known as the �upstream� port, while the ports usedfor connecting other devices to the USB are known asthe �downstream� ports. This is illustrated in Fig.2.

USB hubs work �transparently� as far as the host PCand its operating system are concerned. Most hubs provide either four or seven downstream ports, or lessif they already include a USB device of their own.

Another important feature of the USB is that it�sdesigned to allow �hot swapping�: devices can be pluggedinto and unplugged from the bus without having to turnthe power off and on again, re-boot the PC or evenmanually start a driver program. A new device can simply be connected to the USB, and the PC�s operatingsystem should recognise it and automatically set up thenecessary driver to service it. Windows 98 and laterversions of Windows 95 do this, as do the latestMacintosh operating systems.

Power and dataUSB cables consist of two twisted pairs of wires, one

pair used to carry the bidirectional serial data and theother pair 5V DC power. This makes it possible for low-powered peripherals such as a mouse, joystick ormodem to be powered directly from the USB � orstrictly from the host PC (or the nearest hub) upstream,via the USB.

Most modern PCs have two USB ports, and eachcan provide up to 500mA of 5V DC power for bus-powered peripherals. Individual peripheral devices(including hubs) can draw a maximum of 100mAfrom their upstream USB port, so if they requireless than this figure for operation they can be buspowered. If they need more, they have to use theirown power supply such as a plug-pack adaptor. Hubsshould be able to supply up to 500mA at 5V from

Electus Distribution Reference Data Sheet: USBBUS.PDF (1)

Fig.1: The USB is a medium speed serial bus used totransfer data between a PC and its peripherals. Ituses a �tiered star� configuration, with expansion viahubs (either separate, or in USB devices).

The USB or Universal Serial Bus

Fig.2: The port on a USB device or hub whichconnects to the PC host (either directly or viaanother hub) is known as the �upstream� port,while hub ports which connect to additionalUSB devices are �downstream� ports.Downstream ports use Type A sockets, whileupstream ports use Type B sockets.

each downstream port, if they�re not bus powered.Serial data is sent along the USB in differential or

�push-pull� mode, with opposite polarities on the twosignal lines. This improves the signal-to-noise ratio(SNR), by doubling the effective signal amplitude andalso allowing the cancellation of any common-modenoise induced into the cable. The data is sent in non-return-to-zero (NRTZ) format, with signal levels of3.3V peak (i.e., 6.6V peak differential).

USB cables use two different types of connector:�Type A� plugs for the upstream end, and �Type B� plugsfor the downstream end. Hence the USB ports of PCsare provided with matching Type A sockets, as are the

downstream ports of hubs, while the upstream ports ofUSB devices (including hubs) have Type B sockets. TypeA plugs and sockets are flat in shape and have the fourconnections in line, while Type B plugs and sockets aremuch squarer in shape and have two connections oneither side of the centre spigot. (Fig.3)

Both types of connector are polarised so they cannotbe inserted the wrong way around. Fig.3 shows the pinconnections for both type of connector, with socketsshown and viewed from the front.

Note that although USB cables having a Type A plug ateach end are available, they should never be used toconnect two PCs together, via their USB ports. This isbecause a USB network can only have one host, andboth would try to claim that role. In any case, the cablewould also short their 5V power rails together, whichcould cause a damaging current to flow. USB is notdesigned for direct data transfer between PCs.

All normal USB connections should be made using

cables with a Type A plug at one end and a Type B plugat the other, although extension cables with a Type Aplug at one end and a Type A socket at the other canalso be used, providing the total extended length of acable doesn�t exceed 5m.

By the way, USB cables are usually easy to identify asthe plugs have a distinctive symbol moulded into them� see Fig.4.

Data formatsUSB data transfer is essentially in the form of

�packets� of data, sent back and forth between the hostand peripheral devices. However because USB isdesigned to handle many different types of data, it canuse four different data formats as appropriate.

One of the two main formats is bulk asynchronousmode, which is used for transferring data that isn�t timecritical. This is the format used to transmit data from ascanner or digital scanner for example, or to a printer.The packets can be interleaved on the USB with othersbeing sent to or from other devices.

The other main format is isochronous mode, used totransfer data that iiss time critical � such as audio datato digital speakers, or to/from a modem. These packetsmust not be delayed by those from other devices.

The two other data formats are interrupt format,used by devices to request servicing from the PC/host,and control format, used by the PC/host to send tokenpackets to control bus operation, and by all devices tosend handshake packets to indicate whether the datathey have just just received was OK (�ACK�) or haderrors (�NAK�).

Some of the data formats are illustrated in Fig.5.Note that all data packets begin with a �sync� byte(01hex), used to synchronise the PLL (phase-lockedloop) in the receiving device�s USB controller. This isfollowed by the packet identifier (PID), containing afour-bit nibble (sent in both normal and inverted form)which indicates the type of data and the direction it�sgoing in (i.e., to or from the host). Token packets thenhave the 7-bit address of the destination device and a4-bit �end point� field to indicate which of that device�sregisters it�s to be sent to.On the other hand data packets have a data field of up

to 1023 bytes of data following the PID field, while�Start of Frame� (SOF) packets have an 11-bit frameidentifier instead and handshake packets have no otherfield. Most packets end with a cyclic redundancy check(CRC) field of either five or 16 bits, for error checking,except handshake packets which rely on the redundancyin the PID field. All USB data is sent serially, of course,and least-significant-bit (LSB) first.

Luckily all of the fine details of USB handshaking anddata transfer are looked after by the driver software inthe PC and the firmware built into the USB controllerinside each USB peripheral device and hub � so normally all you have to do is hook it all together andperhaps supply a driver for a new device, when the PC�soperating system can�t find it. Most USB peripheralscome with their driver on a floppy disk or CD-ROM.

(Copyright © Electus Distribution, 2001)

Electus Distribution Reference Data Sheet: USBBUS.PDF (2)

Fig.3: Pin connections for the two differenttypes of USB socket, as viewed from the front.

Fig.4: Most USBplugs have thisdistinctivemarking symbol.

Fig.5: Examples ofthe various kindsof USB signallingand data packets.

Firewire

• http://www.jaycar.com.au/images_uploaded/fi

rewire.pdf

S1, 2006 COMP9032 Week13 37

Around 1986, Apple Computer Inc developed a veryfast but relatively low cost serial interface for distributing digital audio and other bulk data betweenpersonal computers, and between computers and theirperipherals. The new high speed serial interface wasdesigned to replace the relatively expensive SCSI parallelinterface, and Apple dubbed it FireWire (which is stillan Apple trademark).

Firewire was so successful that other manufacturerssoon began using it under licence. In 1995 Sony releasedits DCR-VX1000 digital video camcorder, which featuredessentially the same interface for input and output ofdigital video. Sony dubbed the interface iLink, and hasgradually provided the interfaces on all of its digitalcamcorders and VCRs. (iLink is a Sony trademark.)

It was soon realised that the FireWire/iLink interfacewas ideal not just for conveying digital video and audio,but for fast transfer of large amounts of any kind of digital data. Because of this the IEEE (Institution ofElectrical and Electronics Engineers) established it in1995 as an industry standard data interface, known asIEEE 1394-1995 � or �IEEE 1394� for short.

Nowadays IEEE 1394 interfaces are used on a verywide range of digital equipment, both in the computerand entertainment electronics industries. They�re standard on the majority of digital camcorders andVCRs, as well as on video editing workstations andadvanced computer graphics systems, and will probablybe standard on the new DVD-RW and DVD-RAM videorecorders. They�re increasingly found even inside largeworkstations and servers, to interface peripherals likelarge hard disk drives and arrays, CD-writers and scanners.

In fact it looks very much as if IEEE 1394 could wellbecome the standard high speed interface for the coming era of digital convergence � the merging ofcomputers, communications and entertainment technology.

Note that although there are some similaritiesbetween IEEE 1394 and the USB, there are quite a fewdifferences. USB is slower and essentially designed fornetworks with a single host (the PC), whereas IEEE 1394

can be used for peer-to-peer communication. A digitalcamcorder can stream video and audio data to both adigital VCR and a DVD-RAM recorder simultaneously viaan IEEE 1394 network, for example, with no need forassistance from a PC or other network controller device(after it has been allocated an isochronous channel forthe transfer � see later).

Fast & powerfulIEEE 1394 can transmit data at three rates: 98.304,

196.608 and 393.216Mb/s (megabits per second), whichare usually rounded to 100Mb/s, 200Mb/s and 400Mb/s� and officially labelled �S100�, �S200� and �S400� respectively. As you can see even the lowest rate isnearly 10 times that of USB.

Most consumer equipment like digital camcorders,VCRs and DVD-RAM recorders use the S100 rate,which is more than capable of handling a compressedvideo-and-audio data stream. The majority of PCI/IEEE1394 interface adaptor cards for PCs will also supportS200, while some can also support S400.

Like USB, IEEE 1394 is designed to allow �hot swapping�. Devices can be connected and/or disconnected without turning off the power or resetting,etc. The device which is performing the bus managerrole constantly monitors bus status, and reconfigures itdynamically whenever nodes are added or disconnected.

Data is transferred on the IEEE 1394 bus in addressedpackets, and is transaction-based. The transfers can beasynchronous or isochronous. Asynchronous transfersare used mainly for bus configuration, setting up transfers and handshaking, but are also used for bulkdata transfer to and from hard disk drives, etc.Isochronous transfers are used for transporting time-sensitive data like digital video and audio.

IEEE 1394 data packets have a 64-bit address header,which is divided into a 10-bit network address, a 6-bitnode address and the remaining 48 bits for data (ormode control) memory addresses at the receiving node.This gives IEEE 1394 the ability to address 1023 networks of 63 nodes, each with up to 281TB (terabytes) of data addresses.

In practical terms this tends to mean up to 63 devicescan be hooked up via IEEE 1394 cables as a network,with each device able to have tens or even hundreds of

Jaycar Electronics Reference Data Sheet: FIREWIRE.PDF (1)

Fig.1: A fairly typical IEEE 1394 network used ina digital video editing studio. The PC would generally take the role of bus manager andisochronous resource manager.

IEEE 1394 (AKA �FireWire� & �iLink�)

Fig.2: How the DS coding works. The Strobe signal is produced at the transmitting port, byexclsuive-ORing the Data and Clock. Then at thereceiving end the Clock is reconstructed by exclusive-ORing the Data and Strobe signals.

gigabytes of memory � and plenty of room for more!Typically devices have three IEEE 1394 ports, but they

can have up to 27. This allows networks to be as simpleas a DV camcorder connected to a digital VCR, or morecomplicated like the setup shown in Fig.1. As you cansee this shows a �tree� topology, taking advantage of theability of each device to act as a bus repeater or �minihub�.

One device on the bus acts as bus manager, and canalso act as isochronous resource manager. The latterallocates bus bandwidth for isochronous data transferswhen devices request them. When there�s a PC in thenetwork, it usually performs the roles of bus managerand isochronous resource manager.

As the IEEE 1394 bus uses time-domain multiplexing(TDM), the isochronous resource manager allocateseach isochronous transfer a �channel� consisting of somany �bandwidth allocation units� (i.e., a guaranteed proportion of the total time slots). A bandwidth allocation unit is 20.3ns, so there are 6144 of them in aIEEE 1394 �basic cycle� of 125us. However 25us of everycycle is always reserved for asynchronous control datatransfers, so a maximum of 4195 units is available forisochronous transfers. Typically a stream from a DVcamcorder to a PC or digital VCR might need to beallocated a channel of say 1800 bandwidth units, forabout 30Mb/s.

Only one data packet can occur every basic cycle for aparticular isochronous transfer channel, using that channel�s allocated bandwidth units. However multipleisochronous transfers can take place at the same time,providing there�s enough bandwidth available. The transfers can even be at different rates � say one atS100 and another at S200. If there isn�t enough bandwidth available when a device requests it, it waitsuntil the bandwidth does become available.

Asynchronous transfers can have multiple data packetsper basic cycle, within the 25us reserved for this type ofsignalling.

Data-Strobe codingAll data is sent along the IEEE 1394 bus in serial four

byte (32-bit) words, called quadlets. And the quadletsare encoded together with their clock signal onto twoNRZ (non return to zero) bus signals, using a techniqueknown as Data-Strobe (DS) coding. This improves transmission reliability by ensuring that only one of thetwo signals changes in each data bit period.

Fig.2 shows how DS coding works. The top waveformshows the Data bits being sent, while the bottom waveform shows the Clock signal. At the transmittingnode these two are fed to an exclusive-OR gate to generate the Strobe signal, shown in the centre. It�s thissignal and the Data signal which are sent along the bus,

and as you can see there�s only one change in the pairevery bit period.

At the receiving device, though, the Data and Strobesignals are again fed to an exclusive-OR gate. The output of this gate effectively reconstructs the Clocksignal again, with its timing still accurately locked to theData. The DS coding therefore avoids the need for IEEE1394 receivers to have a PLL (phase-locked loop).

Twisted pairsThe IEEE 1394 Data and Strobe signals are sent on

cables with two separately shielded twisted-wire pairs,called TPA (twisted pair A) and TPB (twisted pair B).Transfers in one direction have the Strobe signal on TPAand the Data signal on TPB, while those in the oppositedirection have the Data signal on TPA and the Strobesignal on TPB. Fig.3 shows the idea.

There are two different kinds of IEEE 1394 cable, withmatching connectors. The primary type of cable has notonly the two separately shielded wire pairs TPA andTPB, but also two DC power conductors � the negativebeing grounded. A cross-section of this type of cable isshown in Fig.4, and as you can see there�s also an outershield and sleeve.

The IEEE 1394 standard allows nodes to be suppliedwith DC power via the two power conductors. Thepower can be supplied at a voltage between 8V and 33V,and the current can be up to 1.5 amps.

The type of cable shown in Fig.4 is used for most�mainstream� IEEE 1394 applications, such as interfacinglarge hard disk arrays to DV editing workstations.

The second type of cable used for IEEE 1394 has onlythe two shielded twisted pairs TPA and TPB, and cantherefore only be used for signal transfer. This is thetype of cable first used in Sony�s iLink, and is now commonly used for digital video applications. Most DVcamcorders and VCRs use this type of cable.

Due to the high speed at which IEEE 1394 works,cables between device nodes should be no longer than5m long to limit signal attenuation. There should also beno more than 16 cable �hops� separating any two nodesin an IEEE 1394 network.

ConnectorsJust as there are two types of cable, there are two

types of IEEE 1394 connector to match. Not surprisinglyone type provides six connections and the other onlyfour. Both of the plugs are shown in Fig.5, together with


Fig.3: The Strobe and Data signals are sent alongthe IEEE 1394 bus via two shielded twisted-wirepairs, TPA and TPB.

Fig.4: The primary type of IEEE 1394 cable hasa pair of power conductors as well as the twoshielded signal pairs TPA and TPB.

their pinouts. The corresponding sockets and theirpinouts are complementary, of course.

As you can see both plugs are polarised and fairlycompact. But the inserting section of the primary 6-pin plug is much larger (11.3 x 6.2mm) than thatof the 4-pin plug, which is very small indeed (6.45 x3.5mm). The larger plug is polarised by a pair ofchamfers at one narrow end, while the smaller onehas an indent in the centre of one side.

Normally all devices with IEEE 1394 ports are fitted with sockets, and the cables have plugs ateach end. Adapter cables are available to allow datatransfer between devices with 6-pin and 4-pin sockets, with appropriate plugs at each end. (Thereare also short adaptor cables with a plug and asocket, to mate with a standard like-to-like cable.)

NNOOTTEE tthhaatt iinn aall ll ssttaannddaarrdd IIEEEEEE 11339944 ccaabblleess,,tthhee ccoonnnneeccttiioonnss ttoo tthhee ttwwoo ssiiggnnaall ��ttwwiisstteedd ppaaiirrss��aarree ttrraannssppoosseedd bbeettwweeeenn tthhee ttwwoo eennddss.. TThhaatt iiss,, iinnaa 66--ppiinn ttoo 66--ppiinn ccaabbllee ppiinnss 44 aanndd 33 aatt eeaacchh eennddccoonnnneecctt ttoo ppiinnss 66 aanndd 55 aatt tthhee ootthheerr,, rreessppeeccttiivveellyy.. SSiimmiillaarrllyy iinn aa 44--ppiinn ttoo 44--ppiinn ccaabblleeppiinnss 22 aanndd 11 aatt eeaacchh eenndd ccoonnnneecctt ttoo ppiinnss 44 aanndd 33aatt tthhee ootthheerr,, rreessppeeccttiivveellyy..

Because of their complex construction and thesmall size and precision of their connectors, IEEE1394 cables can be quite expensive. Because of thisand the tiny size of the 4-pin connectors in particular, they should be treated with care toensure that they provide reliable communication atthe fast data rates involved.

(Copyright © Jaycar Electronics, 2002)


Fig.5: The two different types of IEEE 1394 plug,and their basic pin connections. But note thatthe TPA and TPB connections are transposed inall standard IEEE 1394 cables.

IEEE 1394/FireWire Cables stocked by JaycarA range of standard IEEE 1394/Firewire/i.Link cables are now stocked by Jaycar Electronics stores and

authorised dealers. Here�s a quick rundown on the cables available and their catalogue numbers:

FFoorr mmoorree iinnffoorrmmaattiioonn,, pplleeaassee rreeffeerr ttoo tthhee llaatteesstt JJaayyccaarr EEnnggiinneeeerriinngg CCaattaalloogguuee oorr vviissiitt wwwwww..jjaayyccaarr..ccoomm..aauu

44--ppiinn ttoo 44--ppiinn CCaabblleess2m long Cat No. WC-76405m long Cat No. WC-7641



S1, 2006 COMP9032 Week13 38

AVR USARTs

• Two USART units

– Unit 0

– Unit 1

• Each unit can be configured for synchronous

or asynchronous serial communication

• USART unit 0 is used on our lab board to

receive program code downloaded from the

PC host via USB

S1, 2006 COMP9032 Week13 39

AVR USARTs (cont.)

• Support many serial frames.

• Have transmission error detection

– Odd or even parity error

– Framing error

• Three interrupts on

– TX Complete

– TX Data Register Empty

– RX Complete.

S1, 2006 COMP9032 Week13 40

USART

Block

Diagram

S1, 2006 COMP9032 Week13 41

AVR USART Structure

• The USART consists of three components:

clock generator, transmitter and receiver

• Clock generator

– consists of synchronization logic for external clock

input used by synchronous slave operation, and

the baud rate generator.

• Transmitter

– consists of a single write buffer, a serial Shift

Register, Parity Generator and Control Logic for

handling different serial frame formats.

S1, 2006 COMP9032 Week13 42

AVR USART Structure (cont.)

• Receiver

– The Receiver is the most complex part of the

USART module due to its clock and data recovery

units.

• The recovery units are used for asynchronous data

reception.

– In addition to the recovery units, the Receiver

includes a Parity Checker, Control Logic, a Shift

Register and a Receive Buffer (UDR).

– The Receiver supports the same frame formats as

the Transmitter, and can detect Frame Error, Data

Over Run and Parity Error.

S1, 2006 COMP9032 Week13 43

Frame Formats

• Up to 30 formats

– combinations of

• 1 start bit (St)

• 5, 6, 7, 8, or 9 data bits

• no, even or odd parity bit (P)

• 1 or 2 stop bits (Sp)

• Example

S1, 2006 COMP9032 Week13 44

Parity Bit

• Used to check whether the received data is different from the sending data

• Two forms of the parity bit – Even parity

– Odd parity

– Where di in the two formulas is a data bit, n is the

number of data bits.

0ddddP011nneven

1ddddP011nnodd

S1, 2006 COMP9032 Week13 45

Control Registers

• Three control registers are used in USART

operation:

– UCSRA

• for storing the status flags of USART

• for controlling transmission speed and use of multiple

processors

– UCSRB

• for enabling interrupts, transmission operations

• for setting frame formats

• for bit extension

– UCSRC

• For operation configuration

S1, 2006 COMP9032 Week13 46

UCSRA

• USART Control and Status Register A

S1, 2006 COMP9032 Week13 47

UCSRA Bit Descriptions

• Bit 7 – RXC: USART Receive Complete

– Set when the receive buffer is not empty

– The RXC flag can be used to generate a Receive

Complete interrupt

• Bit 6 – TXC: USART Transmit Complete

– Set when the entire frame in the Transmit Shift

Register has been shifted out and there are no

new data present in the transmit butter

– TXC is automatically cleared when a transmit

complete interrupt is executed.

– TXC can generate a Transmit Complete interrupt

S1, 2006 COMP9032 Week13 48

UCSRA Bit Descriptions (cont.)

• Bit 5 – UDRE: USART Data Register Empty – Set when the transmit buffer (UDR) is empty

– Can be used to generate a Data Register Empty interrupt

• Bit 4 – FE: Frame Error – Set when the next character in the receive buffer

had a Frame Error when received.

• Bit 3 – DOR: Data OverRun – Set when a Data OverRun condition is detected.

– A Data OverRun occurs when the receive buffers are all full and a new start bit is detected.

S1, 2006 COMP9032 Week13 49

UCSRA Bit Descriptions (cont.)

• Bit 2 – UPE: USART Parity Error

– Set when the next character in the receive buffer had a

Parity Error when received and the Parity Checking was

enabled

• Bit 1 – U2X: Double the USART Transmission Speed

– Set for doubling the transfer rate for asynchronous

communication

• Bit 0 – MPCM: Multi-processor Communication Mode

– If set, all the incoming frames received by the USART

Receiver that do not contain address information will be

ignored.

S1, 2006 COMP9032 Week13 50

UCSRB

• USART Control and Status Register B

S1, 2006 COMP9032 Week13 51

UCSRB Bit Descriptions

• Bit 7 – RXCIE: RX Complete Interrupt Enable

– Set to enable interrupt on the RXC flag

• Bit 6 – TXCIE: TX Complete Interrupt Enable

– Set to enable interrupt on the TXC flag

• Bit 5 – UDRIE: USART Data Register Empty

Interrupt Enable

– Set to enable interrupt on the UDRE flag.

S1, 2006 COMP9032 Week13 52

UCSRB Bit Descriptions (cont.)

• Bit 4 – RXEN: Receiver Enable – Set the enable the USART receiver.

– The Receiver will override normal port operation for the RxD pin when enabled. Disable the Receiver will flush the receive buffer invalidating the FE, DOR and UPE flags.

• Bit 3 – TXEN: Transmitter Enable – Set to enable the USART Transmitter

– The Transmitter will override normal port operations for the TxD pin when enabled. The disabling of the Transmitter will not become effective until transmissions are complete.

S1, 2006 COMP9032 Week13 53

UCSRB Bit Descriptions (cont.)

• Bit 2 – UCSZ2: Character Size

– The bit combined with the UCSZ1:0 bits in UCSRC sets the

number of data bits in a frame.

• Bit 1 – RXB8: Receive Data Bit 8

– The ninth data bit of the received character when operating

with serial frames with nine data bits. Must be read before

reading the low bits from UDR

• Bit 0 – TXB8: Transmit Data Bit 8

– The ninth data bit in the character to be transmitted when

operating with serial frames with nine data bits. Must be

written before writing the low bits to UDR

S1, 2006 COMP9032 Week13 54

UCSRC

• USART Control and Status Register C

S1, 2006 COMP9032 Week13 55

UCSRC Bit Descriptions

• Bit 6 – UMSEL: USART Mode Select

– 0: Asynchronous Operation

– 1: Synchronous Operation

• Bit 5:4 – UPM1:0: Parity Mode

– Set to enable Parity bit operation

UPM1 UPM0 Parity Mode

0 0 Disabled

0 1 Reserved

1 0 Enabled, Even Parity

1 1 Enabled, Odd Parity

S1, 2006 COMP9032 Week13 56

UCSRC Bit Descriptions (cont.)

• Bit 3 – USBS: Stop Bit Select

– 0: 1-bit

– 1: 2-bit

• Bit 2:1 – UCSZ1:0: Character Size

– Together with UCSZ2 to determine the number of

bits for a character

UCSZ2 UCSZ1 UCSZ0 Character Size

0 0 0 5-bit

0 0 1 6-bit

0 1 0 7-bit

0 1 1 8-bit

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Reserved

1 1 1 9-bit

S1, 2006 COMP9032 Week13 57

UCSRC Bit Descriptions (cont.)

• Bit 0 – UCPOL: Clock Polarity

UCPOL Transmitted Data Changed Received Data

Sampled

(Output of TxD Pin) (Input on RxD Pin)

0 Rising XCK Edge Failing XCK Edge

1 Failing XCK Edge Rising XCK Edge

S1, 2006 COMP9032 Week13 58

USART Initialization

• Initialization process consists of

– Setting the baud rate,

– Setting the frame format; and

– Enabling the Transmitter or the Receiver

• For interrupt driven USART operation, the

Global Interrupt Flag should be cleared when

doing the initialization

S1, 2006 COMP9032 Week13 59

Sample Code

• Initialize USART 1

USART_Init:

; Set baud rate, which is stored in r17:r16

sts UBRR1H, r17

sts UBRR1L, r16

; Enable receiver and transmitter

ldi r16, (1<<RXEN1)|(1<<TXEN1)

sts UCSR1B,r16

; Set frame format: 8 bit data, 2 stop bits

ldi r16, (1<<USBS1)|(3<<UCSZ10)

sts UCSR1C,r16

S1, 2006 COMP9032 Week13 60

Data Transmission

• The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. – A data transmission is initiated by loading the

transmit buffer with the data to be transmitted. • The CPU can load the transmit buffer by writing to the

UDR I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame.

– The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is loaded with new data, it will transfer one complete frame at the rate given by the baud register, U2X bit or by XCK depending on mode of operation.

S1, 2006 COMP9032 Week13 61

Sample code

• Data Transmission

– The code below uses polling of the Data Register

Empty (UDRE) flag.

• When using frames with less than eight bits, the most

significant bits written to the UDR are ignored.

USART_Transmit:

; Wait for empty transmit buffer

lds r15, UCSR1A

sbrs r15,UDRE1

rjmp USART_Transmit

; Put data (r16) into buffer, sends the data

sts UDR1,r16

S1, 2006 COMP9032 Week13 62

Status of Data Transmission

• The USART Transmitter has two flags that indicate

its state:

– USART Data Register Empty (UDRE)

• Set: when the transmit buffer is empty and ready to receiver

new data

• Clear: when the transmit butter contains data to be moved into

the shift register

– Transmit Complete (TXC)

• Set: when data in the Transmit Shift Register has been shifted

out and there are no new data currently present in the transmit

buffer

• Clear: otherwise

• Both flags can be used for generating interrupts.

S1, 2006 COMP9032 Week13 63

Data Reception

• The USART Receiver is enabled by writing

the Receive Enable (RXEN) bit in the UCSRB

Register

– The baud rate, mode of operation and frame

format must be set up once before doing any

transmissions. If synchronous operation is used,

the clock on the XCK pin will be overridden and

used as transmission clock.

S1, 2006 COMP9032 Week13 64

Sample code

• Data reception

USART_Receive:

; Wait for data to be received

lds r10, UCSR1A

sbrs r10, RXC1

rjmp USART_Receive

; Get and return received data from buffer

lds r16, UDR1

S1, 2006 COMP9032 Week13 65

Status of Data Reception

• The Receive Complete (RXC) flag indicates if

there are unread data present in the receive

buffer.

– Set: when unread data exist in the receive buffer

– Clear: otherwise

• If the receiver is disabled (RXEN = 0), the

receive buffer will be flushed and

consequently the RXC bit will become zero.

S1, 2006 COMP9032 Week13 66

Error Detection

• Three errors are checked on the receiver

side:

– Frame error

• By checking whether the first stop bit is corrected

received

– Parity error

• By checking whether the data received has the same

(odd or even) number of 1’s as in the data from the

tranmistter.

– Data OveRun error

• By checking if any data is yet read but is overwritten by

incoming data frame.

S1, 2006 COMP9032 Week13 67

Error Recovery

• Main sources of errors in asynchronous data

transmission

– Data reception is “out sync” with transmission

– Noise added to the data

S1, 2006 COMP9032 Week13 68

Error Recovery (cont.)

• AVR includes a clock recovery and a data recovery unit for handling errors in asynchronous transmission. – The clock recovery logic is used for synchronizing

the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin.

• Based on the start bit

– The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver

• Based on multiple sampling and majority policy for each incoming bit

S1, 2006 COMP9032 Week13 69


• The following figure gives an illustration

– The sample rate is 16 times the baud rate

– When the Clock Recovery logic detects a high

(idle) to low (start) transition on the RxD line, it

uses the samples 8, 9 and 10 to decide if it is a

valid bit (namely, 0)

• If the majority of the three bits are 0, the bit is valid; data

recovery is followed.

• If the majority of the three bits are 1, the bit is invalid; the

circuit looks for next start bit.

S1, 2006 COMP9032 Week13 70


– When the receiver clock is synchronized to the

start bit, the data recovery can begin for each

subsequent data bit.

– The decision of the logic level of the received bit is

taken by doing a majority voting of the logic value

to the three samples in the center of the received

bit.

S1, 2006 COMP9032 Week13 71

Reading Material

• Chapter 7: Computer Buses and Parallel

Input and Output. Microcontrollers and

Microcomputers by Fredrick M. Cady.

• Mega64 Data Sheet

– USART

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