session 04 v.3

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D i g i ta l D e s i g n u s i n g V H D L

Session Four

Introduced by

Cairo-Egypt

Version 03 – June 2012 1


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about Start Group

2

Mahmoud Abdellatif Alaa Salah Shehata Mohamed Salah Mohamed Talaat [email protected] www.slideshare.net/StartGroup www.facebook.com/groups/start.group www.startgroup.weebly.com [email protected] + 02 0122-4504158 M.A www.youtube.com/StartGroup2011 + 02 0128-0090250 A.S

Session Four


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mini-Project Discussion

Session Four 3

Sel Operation

0000 Y<= a

0001 Y<= a+1

0010 Y<= a-1

0011 Y<= b

0100 Y<= b+1

0101 Y<= b-1

0110 Y<= a+b

0111 Y<= a+b+cin

1000 Y<= not a

1001 Y<= not b

1010 Y<= a AND b

1011 Y<= a OR b

1100 Y<= a NAND b

1101 Y<= a NOR b

1110 Y<= a XOR b

1111 Y<= a XNOR b

Logic Unit

Arithmetic Unit

A(7:0)

B(7:0)

Cin

SEL(3:0)

C(7:0)

Synchronous ALU Using transcript & Pretty waveform


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Outline

Session Four 4

Data Operators - Concatenation - Aggregation - Attributes Counters and Shifting registers

4


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Outline

Session Four 5



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Data Operators [Concatenation]

Session Four 6

Used to merge two operands together using the concatenation operator ( & ). This result is an array in which length is the sum of lengths of both operands.

C <= A & B

A B

C


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Example 18

Session Four 7

Shift Registers

A <= 0 & A(7 downto 1);

--Shift right

A <= A(6 downto 0) & 0;

--Shift left

0

A7 A0

A7 A1

A7 A0

A6 A0

0


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Example 19

Session Four 8

Division/ Multiplication by 2^n

A <= A(7) & A(7 downto 1);

--Shift right

-- devision by 2

A <= A(6 downto 0) & A(0);

--Shift left

-- Multiplication by 2

-- Note (multiplication need

one more bit for each shift)

A7 A0

A7 A1 A7

A7 A1 A7

A7


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Example 20

Session Four 9

Rotate Registers

A <= A(0) & A(7 downto 1);

--Rotate right

A <= A(6 downto 0) & A(7);

-- Rotate left

A7 A0

A7 A1

A7 A0

A6 A0 A7 A0


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Data Operators [Aggregation]

Session Four 10

Provides an easy way of assigning objects of composite types The aggregate assigns values to a selected elements of an array or a record. Keyword ‘others’ is used here

data : std_logic_vector(15 downto 0); data <= (15 downto 8 => '0' , others => '1'); -- data = 0000000011111111

data <= (1 | 4 | 7 => '1', 2 | 3 => '0', others => 'Z'); -- data = ZZZZZZZZ1ZZ1001Z data <= (others => ‘1');

-- fill data with ones


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Data Operators [Attributes]

Session Four 11

Attributes can be used to poll characteristics/information of objects (e.g. signals). The general form of an attribute name is name'attribute_identifier.

The most commonly used attribute is 'EVENT, used to detect and trigger activity at a certain clock edge (for example rising edge) only.

Examples of attributes : ‘left, ‘right, ‘high, ‘length, ’range, ‘event, … Note Pronounce the apostrophe as “tick “

if (clk’event and clk = ‘1’) then


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Outline

Session Four 12



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Lab 04

Session Four 13

Title: COUNTERS in VHDL Goal:

Be familiar with implementations of different counter schemes


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Lab 04

Session Four 14

4-bit Free binary counter

Library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_signed.all;

Entity counter is

Port( clk, rst : in std_logic;

count : out std_logic_vector(3 downto 0));

end entity;

Architecture behav of d_ff is

Signal count_i : std_logic_vector(7 downto 0);

Begin

process(clk, rst)

begin

If (rst = '1') then

count_i <= "00000000";

elsif rising_edge(clk) then

count_i <= count_i + '1';

end if;

end process;

count <= count_i;

end behav;


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Lab 04

Session Four 15

4-Bit binary Counter with Synchronous/Asynchronous load

Assignment


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Lab 04

Session Four 16

4-Bit binary UP-Down Counter

Assignment


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Lab 05

Session Four 17

Title: Rotating LEDs Goal:

Be familiar with Shift registers


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Lab 05

Session Four 18

One way rotating LEDs

Assignment


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Lab 05

Session Four 19

Two ways rotating LEDs

Assignment


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Session Four 20

Start Notes [Synthesis Notes]

Area Optimization During writing a code for implementation you must save your resources, many ways maybe used to reduce area used from your FPGA. Here, we will introduce an example of thinking how to reduce your area in your design.

Example : Write a code describing this Adder Note that the selector can select one addition at a time, the operators are mutually exclusive

OpSel Function

00 A+B

01 C+D

10 E+F

11 G+H


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Session Four 21


It is better to write a code that describe the circuit on the right as adders take much bigger area than multiplexers his transformation of operators is called Resource Sharing


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Session Four 22


Possible Solutions Solution 1 Here the code is Tool Driven Resource Sharing, the tool understand that we don’t need to make four adders and one Adder is implemented. General Note To ensure resource sharing, operators must be coded in the same process, and same code (case or if) structure.

process (OpSel,A,B,C,D,E,F,G,H)

begin

case OpSel is

when "00" => Z <= A + B ;

when "01" => Z <= C + D ;

when "10" => Z <= E + F ;

when "11" => Z <= G + H ;

when others => Z <= ‘0’ ;

end case ;

end process ;


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Session Four 23


Possible Solutions Solution 2 Here the code is Code Driven Resource Sharing, You forced the tool to use only one Adder. Solution 3 Bad Code that may defeat Resource Sharing. Synthesis tool may create a separate resource for each adder. Don’t do that!

X <= Mux4(OpSel, A, C, E, G) ; -- 4x1 MUX in vhdl

Y <= Mux4(OpSel, B, D, F, H) ;

Z <= X + Y ;

Process (OpSel, A, B, C, D, E, F, G, H)

begin

if (OpSel = "00") then Z <= A + B; end if;

if (OpSel = "01") then Z <= C + D; end if;

if (OpSel = "10") then Z <= E + F; end if;

if (OpSel = "11") then Z <= G + H; end if;

end process ;


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Summary

Session Four 24

- Counters are essential in most of design blocks. - Different types of counters can be implemented using vhdl

- Free Counters - UP-DOWN Counters - BDC Counters - Counters with external LOAD signals

- Shift Registers are also important for Dividing and Multiplying by 2 and also for Parallel to Serial and Serial to Parallel conversion.

Examples Exercises Labs

18-20 - 4-5


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Time for Your Questions

Session Four 25


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Download Session 04 Files

Session Four 26

Attributes www.startgroup.weebly.com/vhdl-examples.html

Example on Do file www.startgroup.weebly.com/vhdl-examples.htm

http://www.startgroup.weebly.com/vhdl-examples.html







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Take Your Notes

Print the slides and take your notes here

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See You Next Session .. Don’t miss

Thank You

session 04 v.3

Business

level fourthg

salah mohamed talaat

bycairoegypt version

ssession four2