session 2 overview: power amplifiers

30 • 2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 ©2017 IEEE

ISSCC 2017 / SESSION 2 / POWER AMPLIFIERS / OVERVIEW

Session 2 Overview: Power AmplifiersRF SUBCOMMITTEE

1:30 PM2.1 A 28GHz/37GHz/39GHz Multiband Linear Doherty Power Amplifier for 5G Massive MIMO Applications

S. Hu, Georgia Institute of Technology, Atlanta, GAIn Paper 2.1, Georgia Institute of Technology presents a transformer-based Doherty combiner to enhance theefficiency and bandwidth of a PA. A power-dependent uneven-feeding scheme is introduced to further improveback-off efficiency. The Doherty PA achieves a maximum 1.92× PA efficiency improvement at 6dB power back-off over a Class-B PA at 37GHz.

2:00 PM2.2 A Fully Integrated Reconfigurable Wideband Envelope-Tracking SoC for High-Bandwidth WLAN

Applications in a 28nm CMOS TechnologyD. Chowdhury, Broadcom, San Diego, CA

In Paper 2.2, Broadcom describes a current-mode hysteresis comparator and a combination of core devicescascoded with high-voltage LDMOS transistors to enable a wide-bandwidth supply modulator. Efficiencyimprovements for a 20MHz signal at 2GHz and a 40MHz signal at 5GHz are 28% and 34%.

2:30 PM2.3 A Single-Inductor Dual-Output Converter with Linear-Amplifier-Driven Cross Regulation for Prioritized

Energy-Distribution Control of Envelope-Tracking Supply ModulatorS-H. Yang, National Chiao Tung University, Hsinchu, Taiwan

In Paper 2.3, National Chiao Tung University and Realtek Semiconductor describe a single-inductor dual-outputsupply modulator with cross regulation. The modulator achieves 86% efficiency and delivers up to 2W of outputpower with a bandwidth of 20MHz.

Subcommittee Chair: Piet Wambacq, imec, Leuven, Belgium

Improving efficiency at back-off power levels has become an active area of research to support spectrally efficient modulationschemes with high peak-to-average power ratios. Doherty power-amplifier topology and envelope-tracking supply modulation arekey enablers to improve the back-off efficiency of transmitters. Increasing signal bandwidths for applications such as carrier-aggregation LTE and WiFi 802.11ac poses challenges for supply modulation. Implementing the Doherty topology for 5G applicationsoperating at mm-wave frequencies is an active area of research.

Session Chair: Kohei Onizuka, Toshiba, Kawasaki, Japan

Session Co-Chair: Abbas Komijani, Qualcomm, San Jose, CA

31DIGEST OF TECHNICAL PAPERS •

ISSCC 2017 / February 6, 2017 / 1:30 PM

3:15 PM2.4 A 2.4V 23.9dBm 35.7%-PAE -32.1dBc-ACLR LTE-20MHz Envelope-Shaping-and-Tracking System

with a Multiloop-Controlled AC-Coupling Supply Modulator and a Mode-Switching PAX. Liu, Hong Kong University of Science and Technology, Hong Kong, China

In Paper 2.4, the Hong Kong University of Science and Technology presents an envelope-tracking system thatachieves high efficiency for 20MHz LTE at supply voltages as low as 2.4V. The envelope tracking and the PAsystem achieve 24dBm of output power, 36% PAE and -32dBc ACLR for a 20MHz signal at 2.4GHz.

3:45 PM2.5 A High-Efficiency Multiband Class-F Power Amplifier in 0.153μm Bulk CMOS for WCDMA/LTE

ApplicationsJ. Ko, MediaTek, Austin, TX

In Paper 2.5, MediaTek presents two CMOS LTE PAs with Class-F matching network. The Class-F matchingnetwork allows for high efficiency and high linearity for these PAs with 2.2dB/3.9dB power back-off for aWCDMA/LTE signal. The PAs achieve 37%/34% PAE, 27.5dBm/28.1dBm output power with E-UTRAACLR1 of -32dB at 0.83GHz/1.88GHz band for a 20MHz LTE 16-QAM signal.

4:00 PM2.6 A SiGe BiCMOS E-Band Power Amplifier with 22% PAE at 18dBm OP1dB and 8.5% at 6dB Back-Off

Leveraging Current Clamping in a Common-Base StageJ. Zhao, University of Pavia, Pavia, Italy; now with HiSilicon-Technologies, Milan, Italy

In Paper 2.6, Huawei and the University of Pavia present a SiGe power amplifier at 80GHz. A common-baseoutput stage causes the DC current to track the signal current and improve efficiency at back-off power. Realizedprototype shows OP1dB of 18dBm with Psat of 19dBm. The efficiency at OP1dB and at 6dB are 22% and 8.5%,respectively.

4:15 PM2.7 A Wideband 28GHz Power Amplifier Supporting 8×100MHz Carrier Aggregation for 5G in 40nm CMOS

S. Shakib, Texas A&M University, College Station, TXIn Paper 2.7, Texas A&M University and Qualcomm describe a 28GHz CMOS PA that supports 8×100MHz 64-QAM OFDM carrier aggregation at 6.7dBm Pout with 11% PAE. The PA uses a dual-resonance transformermatching network to increase the bandwidth.

4:30 PM2.8 A Class-G Voltage-Mode Doherty Power Amplifier

V. Vorapipat, University of California, San Diego, CAIn Paper 2.8, the University of California, San Diego, combines voltage-mode Doherty and Class-G switched-capacitor techniques to improve the efficiency of a PA at both 6dB and 12dB back-off. The CMOS PA achieves25dBm Psat with 30%/24%/17% PAE at peak power and 6dB/12dB back-off at 3.6GHz.

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32 • 2017 IEEE International Solid-State Circuits Conference

ISSCC 2017 / SESSION 2 / POWER AMPLIFIERS / 2.1

2.1 A 28GHz/37GHz/39GHz Multiband Linear Doherty Power Amplifier for 5G Massive MIMO Applications

Song Hu, Fei Wang, Hua Wang

Georgia Institute of Technology, Atlanta, GA

Millimeter-wave fifth-generation (5G) systems will extensively leverage massivemultiple-input multiple-output (MIMO) architectures to improve their linkperformance. These array systems will employ many power amplifiers (PAs)operating at moderate output power (Pout), e.g., 16 PAs each with +7dBm Pout [1].The PA energy efficiency is of paramount importance in MIMO systems forimproved battery life and thermal management. Due to spectrum-efficientmodulations with high peak-to-average power ratios, both PA peak efficiency andpower back-off (PBO) efficiency are critical. To achieve 5G Gb/s data-rates withcomplex modulations, envelope tracking PAs require high-speed/high-precisionsupply modulators, and outphasing PAs need high-speed baseband computation,both of which pose substantial challenges in practice. Although Doherty PAssupport high data-rates, existing silicon mm-wave Doherty PAs exhibit verylimited PBO efficiency enhancement, mainly due to inefficient Doherty powercombiners and imperfect main/auxiliary PA cooperation [2,3].

In addition, multiple mm-wave frequency bands, including spectra around 28, 37,and 39GHz, have been opened for 5G development. Multiband operations willgreatly facilitate MIMO frequency diversity and future cross-network/internationalroaming. Together with existing wideband antennas, a single multiband PA willenable future ultra-compact multiband massive MIMO 5G systems. However, thecarrier bandwidth of a conventional Doherty PA is often limited by the Dohertypower combiner.

To address these unmet challenges, we propose a fully integrated 28/37/39GHzmultiband Doherty PA for 5G massive MIMO applications. Both PA PBO efficiencyand carrier bandwidth are significantly enhanced by a transformer-based Dohertypower combiner. Moreover, a power-aware adaptive uneven-feeding schemeprovides optimum main/auxiliary PA cooperation. A prototype is implemented in0.13μm SiGe BiCMOS. It achieves +16.8/+17.1/+17dBm peak Pout,18.2/17.1/16.6dB peak power gain, 29.4/27.6/28.2% peak collector efficiency(CE), and 20.3/22.6/21.4% peak PAE at 28/37/39GHz. Its Doherty operationachieves 1.72/1.92/1.62× and 3.39/3.86/3.51× efficiency enhancement at5.9/6/6.7dB PBO over Class-B and Class-A PAs at 28/37/39GHz, respectively.Amplifying 3Gb/s 64-QAM with high efficiency and linearity is demonstrated inall these three 5G bands.

Figure 2.1.1 shows conventional and proposed Doherty output networks. Mostsilicon Doherty PAs employ the conventional design with either transmission lines(TLs) [2] or lump elements [4]. Series combining transformer is also used, which,however, exhibits compromised Doherty load modulation and requires additionalpassive overhead [3]. We propose a transformer-based Doherty output network.It significantly reduces the impedance transformation ratios (ITRs) in PBO whileachieving the same peak Pout. This directly improves the PBO passive efficiencyand enhances the Doherty PA PBO efficiency. Moreover, the reduced ITR broadensthe Doherty PA carrier bandwidth due to the decreased loaded quality factor ofthe passive network [5]. The proposed Doherty output network is designed usingon-chip transformers to achieve compactness. Transmission lines TL1, TL2, andTL3 are first approximated by low-, low-, and high-pass π-networks, respectively.Then, the four inductors are absorbed into two on-chip transformers. The twoshunt inductors from TL3 form magnetization inductors, and the series inductorsfrom TL1 and TL2 are incorporated as leakage inductors. Three λ/4 TLs are thusrealized in a two-transformer footprint. Capacitors C1, C2, and C3 absorb PA deviceor pad parasitics. 3D EM simulations verify the Doherty load modulation behaviorwith enhanced PBO passive efficiency and carrier bandwidth (Fig. 2.1.2).

For optimum Doherty operation, the auxiliary PA should provide a rapidlyincreasing current after it is turned on. Conventionally, this is achieved byadaptively biasing the auxiliary PA [3,4]. However, adaptive biasing circuit canbecome challenging for 5G applications, since it is loaded by large PA transistors,and it needs to track the real-time envelope that has ~3× bandwidth expansionover the modulated signal. We propose a power-aware adaptive uneven-feedingscheme (Fig. 2.1.3). The input conductance of the Class-C auxiliary PA increasesnoticeably for increased input power (Pin), while that of the Class-AB main PA

remains almost the same. This effect is leveraged to dynamically modulate theauxiliary driver load and achieve enhanced power gain when Pin increases. Thus,compared with the main path, the auxiliary PA final stage is fed by a larger Pin inthe high-power region. This facilitates the rapid increase of auxiliary PA outputcurrent and achieves an optimum Doherty operation without hardware overheador modulation-rate limitation.

Figure 2.1.4 shows the schematic of the PA. An on-chip differential quadraturehybrid first performs input power split and 90° phase shift. The relative phase ofmain/auxiliary paths is adjusted using 9-section varactor-loaded TLs to furtherextend the Doherty PA carrier bandwidth (Fig. 2.1.2) [6]. Different varactorsettings are used for 28GHz and 37/39GHz (Fig. 2.1.4). The high-order networksformed by varactor-loaded TLs also ensure wideband input matching for differentsettings. Each PA path comprises a driver stage and a PA stage. The interstagematching is designed to realize the proposed adaptive feeding scheme.

The PA chip occupies 1.76mm2 (Fig. 2.1.7). Measured small-signal S-parameters,saturated Pout (PSAT), and P1dB for the two settings show broadband performance(Fig. 2.1.4). The PA achieves a −3dB S21 bandwidth of 23.3 to 39.7GHz (52.1%).The −1dB PSAT bandwidth is 27.7% and 33.3% for the two settings, and collectivelycovers 28-to-42GHz (40%) band. Figure 2.1.5 shows large-signal continuous-wave test results. Owing to the proposed Doherty output network and adaptivefeeding scheme, superior PBO efficiency improvements are achieved over Class-B and Class-A PAs in all three 5G bands. Excellent amplitude/phase linearity isalso observed. The PA is measured using 500MSym/s 64-QAM (3Gb/s) signals(Fig. 2.1.5). Without predistortion, the EVM and ACPR are better than −27dB and−28.2dBc with average Pout>+9.2dBm in all three 5G bands. These 64-QAM testsshow substantial PA average efficiency improvements over normalized Class-Band Class-A PAs in all three bands, verifying the multiband Doherty performancein high-speed dynamic operations. The PA also supports 1GSym/s 64-QAM(6Gb/s) at 28GHz as the state-of-the-art demonstrated data-rate for 28GHz siliconPAs. Our PA advances the state of the art for Doherty, wideband, and 5G siliconPAs in mm-wave bands (Fig. 2.1.6).

Acknowledgements:We thank GlobalFoundries for chip fabrication.

References:[1] S. Shakib, et al., “A 28GHz Efficient Linear Power Amplifier for 5G PhasedArrays in 28nm Bulk CMOS,” ISSCC, pp. 352–353, Feb. 2016.[2] A. Agah, et al., “Active Millimeter-Wave Phase-Shift Doherty Power Amplifierin 45nm SOI CMOS,” IEEE JSSC, vol. 48, no. 10, pp. 2338–2350, Oct. 2013.[3] E. Kaymaksut, et al., “Transformer-Based Doherty Power Amplifiers for Mm-Wave Applications in 40nm CMOS,” IEEE TMTT, vol. 63, no. 4, pp. 1186–1192,Apr. 2015.[4] K. Onizuka, et al., “A 2.4GHz CMOS Doherty Power Amplifier with DynamicBiasing Scheme,” IEEE ASSCC, pp. 93–96, Nov. 2012.[5] A. Grebennikov, et al., “A Dual-Band Parallel Doherty Power Amplifier forWireless Applications,” IEEE TMTT, vol. 60, no. 10, pp. 3214–3222, Oct. 2012.[6] R. Darraji, et al., “Mitigation of Bandwidth Limitation in Wireless DohertyAmplifiers with Substantial Bandwidth Enhancement Using Digital Techniques,”IEEE TMTT, vol. 60, no. 9, pp. 2875–2885, Sept. 2012.

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Figure 2.1.1: Proposed transformer-based Doherty power combiner achievingreduced ITRs in PBO with the same peak Pout (Ropt=41.3Ω).

Figure 2.1.2: Compact layout and 3D EM simulation results of the proposedtransformer-based Doherty power combiner.

Figure 2.1.3: Proposed power-aware adaptive uneven Doherty PA input feedingscheme.

Figure 2.1.5: Continuous-wave and 500MSym/s 64-QAM (3Gb/s) measurementresults for the three 5G bands at 28, 37, and 39GHz. Figure 2.1.6: Comparison table.

Figure 2.1.4: Schematic together with measured small-signal S-parametersand large-signal PSAT/P1dB results.

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• 2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 ©2017 IEEE

ISSCC 2017 PAPER CONTINUATIONS

Figure 2.1.7: Die micrograph.



2.2 A Fully Integrated Reconfigurable Wideband Envelope-Tracking SoC for High-Bandwidth WLAN Applications in a 28nm CMOS Technology

Debopriyo Chowdhury, Sraavan R. Mundlapudi, Ali Afsahi

Broadcom, San Diego, CA

Envelope tracking (ET) has become popular for enhancing battery life in mobilecommunication devices that employ high peak-to-average power ratio (PAPR)signals. Most of the published ET systems have focused either on narrow-bandwidth standards, 20MHz WLAN, or LTE [1–3]. However, as the demand forhigher bandwidths and data-rates increases, so does the need for wideband ETsolutions. Furthermore, to support modulations with different PAPR and transmitpowers, the PA will likely require seamless switching between a continuous ETmode and a fixed-supply mode (as with a low drop-out regulator, i.e. a LDO).Hence, fast reconfigurability is needed, which most published ET systems lack.This paper describes a fully integrated, reconfigurable WLAN ET system withdigital baseband in a 28nm CMOS technology for bandwidths up to 40MHz. TheET modulator directly interfaces with a battery (Vbat) and is fully integrated withina complete WLAN transceiver with RF, digital, and frequency synthesizer circuitry.

Figure 2.2.1 shows the hybrid ET modulator [1], where a fast linear regulator (LR)operates in parallel with an efficient switching regulator (SWR), with the currenthand-off controlled by a hysteresis comparator (HC). Simulations show that forhigh bandwidth applications, a fast, low-delay HC is required. However, traditionalHCs use voltage sensing across a series resistor [1], which increases the ET loopdelay and output impedance. We employ a fully current-mode HC that employslow-impedance nodes and low delay (Fig. 2.2.1). A scaled replica of the linearregulator sourcing or sinking current (created by devices Mr1–Mr8) is comparedwith programmable threshold currents (Ithrsh_src/Ithrsh_sink) and an up or down signalis generated using an SR latch to create hysteresis. This fast comparator enablesthe switching regulator to source current in sync with the PA transientrequirements while decreasing current ripple.

The modulator can interface directly to Vbat (up to 5.5V) without the aid of anadditional voltage regulator. Meanwhile, since I/O devices can handle a maximumvoltage of only 1.8V in a standard 28nm technology, the SWR employs customlaterally diffused MOS (LDMOS) transistors with extended drain to handle highVds. The maximum Vgs is still limited to 1.8V, which required the implementationof high-side drive circuits (Fig. 2.2.1). The output of the hysteresis comparator(0-to-1.8V) is level-shifted to swing from (Vbat – 1.8V) to Vbat for the gate driveof the PMOS (MP1 in Fig. 2.2.1). A low-output-impedance Class-AB op-ampgenerates the (Vbat – 1.8V) sliding voltage reference. Since this voltage servesas an artificial ground for the inverters connected to the PMOS gate, very lowimpedance is required to avoid disturbing the PWM signal and any consequentdistortion in the envelope waveform.

The high frequency content of the envelope signal is handled primarily by the LR.The LR must have a 3dB bandwidth covering at least 3× to 4× of the signalbandwidth as well as a high slew rate and low total harmonic distortion. Theserequirements are in direct conflict with the Vbat interface requirement, whichnecessitates the use of LDMOS devices that have longer channel lengths. In orderto circumvent this issue, we use a thin-oxide 28nm core device with a minimumchannel length as the output transistor (MPL1/MNL1, Fig. 2.2.2) in cascode withan LDMOS transistor (MPL2/MNL2, Fig. 2.2.2). This extends the dominant poleof the LR and helps achieve a wide large-signal bandwidth. The gate of the p-sideLDMOS (MPL2) is biased using a sliding voltage (Vbat – 1.8V) to ensure that theVds across the core device never exceeds its reliability limits. A current mirror-based architecture is employed in the first stage to avoid unwantedhigh-impedance nodes. A floating voltage source generates the Class-AB biasneeded for the output stage of the linear regulator [3], which needs to source andsink dynamic currents.

In addition to high PAPR and higher-order modulation schemes, WLAN systemsmay transmit low-PAPR BPSK or QPSK modulated signals at high power levels.Unfortunately, low PAPR at higher power levels reduces ET current savings andmay also lower the maximum transmit power due to spectral regrowth arisingfrom drain modulation. Although switching to a fixed-supply mode is preferredfor such low-PAPR signals, adding a separate PA LDO adds area and current

overhead. We describe an ET system in this paper that can be reconfigured as aPA LDO dynamically with a low settling time. Based on a control bit setting, theSWR is turned off when the LDO mode is enabled, and the LR is configured tooutput a fixed 3.4V. A large off-chip capacitor (CL, Fig. 2.2.2) is switched in atthe ET output only when the LDO mode is enabled. However, because CL istypically large in value (e.g., 1μF), simply switching in a capacitor at the ET outputincreases the transition time significantly. To avoid this, we introduce a pre-charging technique where the capacitor CL is kept pre-charged to Vbat through asmall transistor PC1 (PC2 is off). In the LDO mode transmit cycle, PC1 is turnedoff and PC2 connects the pre-charged CL to the ET output, resulting in fasttransition between the modes.

The wideband ET is integrated with the digital baseband circuitry that performsenvelope generation and conditioning (Fig. 2.2.3). A Coordinate Rotation DigitalComputer (CORDIC) processor generates the envelope signals while aprogrammable farrow-based fractional-delay filter aligns the envelope and RFpaths. A look-up table (LUT1) performs envelope shaping (detroughing, scaling,etc.). A second LUT adjusts the envelope magnitude based on power control anddigital pre-distortion (DPD). The digital envelope is fed to a 12b D/A converter,and, finally, to the analog modulator. The ET system is integrated on the samedie with a complete 802.11n WLAN transceiver.

The chip is fabricated in 28nm CMOS. The ET section measures 0.6mm2 (Fig.2.2.7). While the digital baseband is designed for a 20MHz operation, an analog-only version of the above SoC has been fabricated to allow measurements up to40MHz. With a resistor load, the modulator measures peak efficiency of 94% andan average efficiency of 75% (with the WLAN envelope) from a 3.6V supply. Notethat this design used only one external inductor, unlike other ET designs [2–4].

The ET SoC is measured with a 2GHz WiFi PA using a 20MHz 802.11n 64-QAM72Mb/s OFDM WLAN signal and provides an efficiency enhancement of 28% (PAaverage drain efficiency improves from 29% to 38%) at 19dBm (Psat=26dBm),while meeting –33dB EVM and –45dBr spectral mask requirements with on-chipDPD (Fig. 2.2.4). When transmitting a BPSK-modulated low-PAPR MCS0 signal,the modulator is switched dynamically into the LDO mode and improves spectral-compliant transmission power to 21dBm, proving the effectiveness of the fastreconfigurable design. The analog ET section is also measured with an external5GHz WiFi PA using a 40MHz 802.11n 64-QAM 150Mb/s WLAN signal, providingan efficiency enhancement of 34% (PA average drain efficiency improves from22 to 30%) at 19dBm with an EVM of –34dB (with DPD) (Fig. 2.2.5). This showsthe effectiveness of the wideband design techniques used in what is a state-of-the-art reconfigurable WLAN ET SoC solution for 20MHz and 40MHz modes (Fig.2.2.6).

Acknowledgements:The authors would like to thank Rethnakaran Pulikkoonattu, Chuan Wang, StephenAu, Mike DeGennaro, Michael Irvin, Akira Ito, Navid Lashkarian, Oliver Hsu,Andrew Adams, Keith Carter and Arya Behzad for their help.

References:[1] F. Wang, et al., “A Monolithic High-Efficiency 2.4-GHz 20-dBm SiGe BiCMOSEnvelope-Tracking OFDM Power Amplifier”, IEEE JSSC, vol. 42, no 6., pp. 1271-1281, June 2007.[2] P. Riehl, et al., “An AC-Coupled Hybrid Envelope Modulator for HSUPATransmitters with 80% Modulator Efficiency”, ISSCC, pp. 364-365, Feb. 2013.[3] M. Hassan, et al., “A CMOS Dual-Switching Power-Supply Modulator with 8%efficiency improvement for 20MHz LTE Envelope Tracking RF Power Amplifiers”,ISSCC, pp. 366-367, Feb. 2013.[4] J.-S. Paek, et al., “An RF-PA Supply Modulator Achieving 83% Efficiency and-136dBm/Hz Noise for LTE-40MHz and GSM 35dBm Applications.”, ISSCC, pp.354-355, Feb. 2016.[5] K. Moon, et al., “Highly Linear Envelope Tracking Power Amplifier with SimpleCorrection Circuit”, IEEE RFIC, pp. 127-130, June 2015.

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Figure 2.2.1: Block diagram of a hybrid ET modulator with current modehysteretic comparator.

Figure 2.2.2: Wideband linear regulator that can be reconfigured to operate asan LDO.

Figure 2.2.3: Block diagram of the WLAN transmitter with integrated envelopetracking.

Figure 2.2.5: Measured EVM and PA current consumption (including ET) at5500MHz in fixed 3.4V (LDO) and ET modes for 40MHz 802.11n WLAN andmeasured spectrum at 19dBm Pout for 40MHz WLAN in ET mode. Figure 2.2.6: Performance comparison to published work.

Figure 2.2.4: Measured EVM and spectrum (at 19dBm) with WLAN SoC at2442MHz for 20MHz 802.11n in fixed 3.4V (LDO) and ET Modes.

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Figure 2.2.7: Die micrograph (the ET section is marked).



2.3 A Single-Inductor Dual-Output Converter with Linear-Amplifier-Driven Cross Regulation for Prioritized Energy-Distribution Control of Envelope-Tracking Supply Modulator

Shang-Hsien Yang1, Yen-Ting Lin1, Yu-Sheng Ma1, Hung-Wei Chen1, Ke-Horng Chen1, Chin-Long Wey1, Ying-Hsi Lin2, Shian-Ru Lin2, Tsung-Yen Tsai2

1National Chiao Tung University, Hsinchu, Taiwan, 2Realtek Semiconductor, Hsinchu, Taiwan

RF-PAs in 4G LTE mobile devices handle modulated signals with high peak-to-average power ratios (PAPRs) while maintaining linearity and power efficiency.Envelope-tracking technology increases the efficiency of an RF-PA by modulatingits supply voltage proportionally to the RF signals. The function of an envelope-tracking supply modulator (ETSM) is to track the envelope information andprovide the same output voltage to the RF-PA. Figure 2.3.1 shows a conventionalhybrid ETSM, which is comprised of a linear amplifier (LA) and a hysteresis-controlled switching regulator (SWR). Since the ETSM is mainly battery-powered,an additional SWR is required. This paper presents a single-inductor dual-output(SIDO) converter that removes both SWRs, as illustrated in Fig. 2.3.2, to speedup the performance of the ETSM. In the past, a cross-regulation (CR) effect wasrecognized as one the most critical drawbacks in the conventional design withsingle-inductor multiple-output (SIMO) converters, and numerous researchpapers have attempted to suppress CR [1,2]. In this paper, however, the proposedETSM design, driven by the LA, makes effective use of the CR effect for achievingfaster and efficient envelope tracking. Results show that, at a switching frequencyof 2MHz, the proposed ETSM can deliver up to 2W of average output power withan efficiency of 82%.

The conventional ETSM in Fig. 2.3.1 contains a SWRH and a SWRR. Thehysteresis-controlled SWR (SWRH) is responsible for supplying the averagepower, whereas the LA adds or removes power with a positive or a negative outputcurrent IENV,LA, while the SWRR supplies the regulated voltage VREG to the LA. Asense resistor RSENSE is connected in series with the LA for detecting the amountof current IENV,LA flowing out/into the LA. A hysteresis comparator CMPH is usedto provide power when the voltage across RSENSE reaches the upper/lowerhysteresis level. The significant phase lag on the SWRH greatly decreases overallefficiency. To improve performance, [3] uses an additional variable referencedirectly for the SWRH rather than sensing from the LA. However, such an approachdoes not account for the way the power is distributed, and the fast regulator (i.e.LA) may have to supply a higher proportion of power than intended, which maylead to lower efficiency. On the other hand, [4] uses a high-switching-frequencyWR to replace the LA, but it suffers from a high switching loss and high-frequencyin-band switching noise.

Both SWRs can be replaced by a compact-size SIDO converter, though it suffersfrom the poor CR effect. When transient occurs at one input while the others arein steady state, the victim steady-state outputs experience overshoot/undershoot.Thus, when IENV,LA suddenly varies, intentionally increasing the CR effect of IREG

on IL,AVG, it can instantaneously change the average power, because it is not limitedby the loop bandwidth. Consequently, CR can be manipulated to speed up theenvelope tracking performance.

Figure 2.3.2 illustrates the proposed ETSM with the prioritized energy-distribution(PED) technique. The energy, stored in the inductor of the SIDO converter isdelivered either to VREG or VDD,PA depending on VENV,I. When VENV,I is near the valley,MREG and MAVG are turned on and off, respectively, and IL charges the capacitorCREG maintaining VREG. VDD,PA is solely supplied by the LA. As VENV,I increases, bothMREG and MAVG are then turned off and on, respectively, where VDD,PA is suppliedby both the LA and IL. In Fig. 2.3.1, the LA is forced to dissipate power suppliedby SWRH to modulate VDD,PA. However, the proposed method reduces thedissipated power, because the LA is supplying a positive IENV,LA to VDDPA withoutdissipating power delivered by IL. In order for the LA to modulate VDD,PA and trackVENV,I in the entire process, VREG must be regulated to a reference voltage, VREF,REG.Hence, the SIDO converter prioritizes the power of IL to VREG and directly controlsthe duty cycle of VGP/VGN based on the feedback information of VREG.

The PED controller is responsible of the energy distribution between VREG andVDD,PA. When VENV,I increases, the LA immediately pulls charge from CREG, causingVREG to drop. Once the drop of VREG is sensed, an error signal increases the duty

cycle of VGP (or VGN) to increase IL. Finally, when VREG is settled to VREF,REG, IL isalso adjusted to the correct value.

Figure 2.3.3 show the schematics of the PED controller. The amount of IL flowinginto the RF-PA is monitored by an IL sensor, which extracts the voltage acrossMAVG using MAVG’, the current mirror, MCS, and loading resistor. The generated VL

is monitored by a peak detector to obtain the peak value VLPD. A voltage subtractordeducts a current-sense information VENV,LA with VLPD, and an error amplifier EA1

is responsible of regulating this value to VREF,LA. A simple PID compensatorregulates VREG to VREF,REG. According to PWM control, the duty cycle of VGP (orVGN) is determined. To maximize CR, energy-distribution operation should yieldto the regulation of VREG. The output current of the operational amplifier, OP2, ismonitored by the hysteresis comparators. In a steady state, the hysteresiscomparators remain idle, and an edge detector enables EA1 to charge CPED. Whena significant transient occurs at the VREG, the OP2 charges/discharges the PIDnetwork and the hysteresis comparators are triggered. The edge detectortemporarily disconnects EA1 from CPED to prioritize the energy distribution to VREG

and intentionally maximize the effect of CR.

Figure 2.3.4 shows the proposed LA circuit. The error amplifier drives thetransistor MSF, a source follower, and a power MOSFET MPWR,P, with the flipped-voltage technique, to source a current to the RF-PA and regulate VDD,PA. In a steadystate, the LA does not sink any current from the RF-PA load. However, during thebrief transition time when VENV,I decreases rapidly, the pulling stage prevents VDD,PA

from being overshot. A Gm-C filter constructed as a replica of the power stage isused to sense the average IENV,LA and convert it into VENV,LA.

Figure 2.3.5 shows the measurement results of the proposed SIDO converter inthe ETSM. The setup uses a 4μH inductor and a 22μF CREG. A 1nF capacitor isused at the VDD,PA. When the average of VDD,PA steps up from 2 to 3V, the transitiontime trise is 1.8μs, in which case IL steps from 450 to 700mA. When the VDD,PA

steps down back to 2V, the transition time tfall is 1μs, in which case IL steps from1 to 0.5A. The LA is capable of supplying a VDD,PA up to 4V.

Figure 2.3.6 shows the comparison table with available ETSMs. The proposedETSM is capable of delivering an average output power up to 2W whilemaintaining an efficiency of 68 to 82% with VREG is also generated within the SIDOconverter. Furthermore, since MP and MN are modulated using a Type-III PID andPWM control, the switching frequency of VLX is maintained at 2MHz regardlessof loading conditions to prevent undesired interference to the LTE communicationsystem. The LA is capable of regulating VDD,PA with high linearity, with asuppression of harmonics up to -42dB. Finally, the intrinsic efficiency of the SIDOconverter is 81 to 86%, allowing the overall ETSM to achieve a peak efficiency upto 82% at 2W of average output power. The test chip was fabricated in a 0.5μmCMOS process with the die micrograph shown in Fig. 2.3.7.

Acknowledgements:The authors would like to thank Hsiao-Hui Tai, Chiao-Li Fang and Ying-Zong Juangfor useful discussions. This work was supported by the National ChipImplementation Center (CIC) and Ministry of Science and Technology (MOST).

References:[1] H.-A. Yang, et al., "A 96%-Efficiency and 0.5%-Current-Cross-RegulationSingle-Inductor Multiple Floating-Output LED Driver with 24b Color Resolution,"ISSCC, pp. 230-231, Feb. 2016.[2] H. Chen, et al., "Minimized Transient and Steady-State Cross Regulation in 55-nm CMOS Single-Inductor Dual-Output (SIDO) Step-Down DC-DC Converter,"IEEE JSSC, vol. 46, no. 11, pp. 2488-2499, Jan. 2011.[3] J.-S. Paek, et al., "An RF-PA Supply Modulator Achieving 83% Efficiency and-136dBm/Hz Noise for LTE-40MHz and GSM 35dBm Applications," ISSCC,pp. 354-355, Feb. 2016.[4] P. Amò, et al., "Envelope Modulator for Multimode Transmitters with AC-Coupled Multilevel Regulators," ISSCC, pp. 296-297, Feb. 2014.[5] M. Hassan, et al., "A CMOS Dual-Switching Power-Supply Modulator with 8%Efficiency Improvement for 20MHz LTE Envelope Tracking RF power Amplifiers,"ISSCC, pp. 366-367, Feb. 2013.[6] S.-C. Lee, et al., "A Hybrid Supply Modulator with 10dB ET Operation DynamicRange Achieving a PAE of 42.6% at 27.0dBm PA Output Power," ISSCC, pp. 42-43, Feb. 2015.[7] P. Riehl, et al., "An AC-Coupled Hybrid Envelope Modulator for HSUPATransmitters with 80% Modulator Efficiency," ISSCC, pp. 364-365, Feb. 2013.

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Figure 2.3.1: Problems with a conventional envelope-tracking supplymodulator.

Figure 2.3.2: Proposed envelope-tracking supply modulator with a prioritizedenergy-distribution technique.

Figure 2.3.3: Proposed PED controller.

Figure 2.3.5: Measurement results. Figure 2.3.6: Comparison table and statistical data.

Figure 2.3.4: Proposed LA circuit.

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2.4 A 2.4V 23.9dBm 35.7%-PAE -32.1dBc-ACLR LTE-20MHz Envelope-Shaping-and-Tracking System with a Multiloop-Controlled AC-Coupling Supply Modulator and a Mode-Switching PA

Xun Liu, Heng Zhang, Min Zhao, Xuan Chen, Philip K. T. Mok, Howard C. Luong

Hong Kong University of Science and Technology, Hong Kong, China

Long-term-evolution (LTE) communication enables high data-rates but degradesthe efficiency of the power amplifiers (PAs) due to high peak-to-average powerratios of transmitted signals. Envelope tracking (ET) and envelope-elimination-and-restoration (EER) techniques have been proposed to improve the PAefficiency by adapting the PA supply voltage to the envelope. Linear PAs in ETsystems are mostly implemented in non-CMOS technologies for high efficiency[1]. However, the growing demand for low-cost integrated systems has motivatedthe use of CMOS PAs [2]. The main drawback of this is that linear CMOS PAshave poor efficiency.The high efficiency of switching PAs makes them a promisingcandidate in CMOS [3]. In EER systems, where switching PAs are used, the supplymodulator must satisfy stringent noise and bandwidth specifications in order torecover the amplitude information of the LTE signal. Thus, it is a challenge forsupply modulators to maintain high efficiency. Recently, a number of methodshave been adopted to improve supply-modulator efficiency. In [1], a dual-switching topology is proposed, but it requires an additional inductor and resultsin an unpredictable noise spectrum. In [4], an AC-coupling topology is adoptedto reduce the supply voltage of the linear amplifier. However, due to the slowresponse of the switching amplifier, the efficiency is still low.

This paper proposes an envelope-shaping-and-tracking (EST) system consistingof a high-efficiency supply modulator and a fully integrated CMOS PA. The ESTarchitecture is designed to improve the supply-modulator efficiency. As shownin Fig. 2.4.1, for the EST system, the mode-switching PA is directly driven by theoriginal RF signal. The envelope is shaped by clipping the low-voltage partaccording the switching and linear transition region of the PA. The EST systemconsists of two modes in accordance with the input power level. In the high-powermode, the PA works in the switching region, and the supply modulator tracks theenvelope. In the low-power mode, the PA is in the linear region, and the supplymodulator provides a constant supply voltage. The envelope-shaping scheme thusreduces the supply-modulator output range. Multiloop control with an AC-coupling structure is proposed for the supply modulator to improve its efficiency.A reference high-frequency path (HFP) is also proposed to extend the supply-modulator bandwidth.

For the supply modulator, a 25MHz 3-level switching amplifier is adopted with amuch-reduced inductor value to achieve a fast response. The 3-level topology,based on stacked 1.2V thin-oxide devices, allows the operation at up to 2.4Vsupply voltage and reduces the switching loss [5]. The topology also reduces theswitching noise by pushing it to 50MHz, which also helps to effectively attenuatethe PA in-band noise. An AC-coupling topology is adopted to take advantage ofthe reduced output range. As VO_LIN is shifted up by the DC voltage stored in CAC,the supply voltage of linear amplifier is reduced. CAC also eliminates the DC currentof the linear amplifier. These two methods help reduce the power consumption.Conventionally, with the AC-coupling topology, VAC is sensed to control theswitching amplifier [4], which slows down the switching-amplifier response. Thisproblem is solved in this work by a multiloop control as shown in Fig. 2.4.1.Intuitively, a high-efficiency switching amplifier provides the low-frequency power,while a low-efficiency linear amplifier provides the high-frequency power. Theratio of id over ia indicates the power distribution. Therefore, the efficiency isproportional to the gain and unity-gain frequency (UGF) of id/ia(s). As shown inFig. 2.4.2, the 2 terminals of CAC are sensed and compared with the referencevoltages by a differential difference amplifier (DDA). At the same time, the sensedcurrent signal VC is coupled to the output of the DDA through CML. VEA is used tocontrol id. By sensing VAC, VEA integrates ia, with an infinite gain at DC but lags ia,while, by sensing current, VC is proportional to ia. CML works as a high-pass filter,so that VEA is composed of both sensed signals. As a result, the UGF of id/ia isextended from 650kHz to 3.3MHz while inheriting the high gain. Moreover, withthis method, VAC can be regulated to be close to the shaping level, rather than arandom value in the free-running case.

In the EST system, the PA linearity at high power highly depends on the supply-modulator bandwidth, which is defined as the -3dB frequency of the transferfunction VPA/VELP. The circuitry implementation of the linear amplifier with thehigh-frequency path is shown in Fig. 2.4.2. The high-frequency path, which iscomposed of 2 resistors and a high-pass capacitor, is proposed to enhance thebandwidth without increasing current. As can be observed from the measuredBode plots of in Fig. 2.4.2, the bandwidth is increased from 33.9 to 69.2MHz withthe high-frequency path. The 2 peaks are due to the switching noise and can beignored.

The mode-switching PA has a single power stage, in which 1.2V thin-oxide and2.5V thick-oxide transistors are stacked to protect against breakdown, as shownin Fig. 2.4.3. To maximize efficiency, the common-gate voltage VBCG of thecascode device is dynamically biased to the optimized value with respect to theinstantaneous supply voltage with up to 4% efficiency improvement. Thecapacitive-charging-acceleration technique CCAT is also adopted [6]. The outputseries-power-combining matching network is designed based on the finite DC-feed-inductor Class-E operation to increase the output power. In existingsolutions, the center tap for the output transformer is floating, and the second-harmonic switching current appears at the PA supply [7]. In this work, thecenter-tap is shorted to ground to provide a low-impedance path to help steeraway and thus suppress around 50% of the second-harmonic switching currentto ground, which improves the ACLR by 2dBc.

The whole EST system is fabricated in 65nm CMOS with 3.5mm2 used for thesupply modulator with a 7nF on-chip flying capacitor CF and 1.9mm2 used for thePA. The off-chip inductor and CAC are 206nH and 1μF, respectively. 20MHz LTE16-QAM signal is used for all measurements. Figure 2.4.4 shows the measuredVELP, VPA, VAC and VX waveforms during tracking. VAC is always constant while VX

is 2.4V, 1.2V and 0V as expected. The efficiencies of the supply modulator with a3.9Ω resistive load, achieved with the proposed multiloop control or with theconventional sensing VAC control, are also shown in Fig. 2.4.4, demonstrating amaximum efficiency of 88.7%. 6-to-10% improvement is achieved with envelopeshaping and multiloop control compared with unshaped envelope with a VAC

control. From Fig. 2.4.5, the EST system measures a PAE of 35.7% with a 2%improvement by envelope shaping and ACLR of -32.1dBc with a 2dBcimprovement by shorting the center-tap to ground. The comparison of the supplymodulator in Fig. 2.4.6 to prior art demonstrates its high efficiency, largebandwidth, and low noise. From the system-comparison table, the EST systemachieves both high efficiency and linearity at the supply voltage as low as 2.4V.Figure 2.4.7 shows the overall die micrograph.

Acknowledgment:This project was funded by the Hong Kong Innovation Technology Funding(ITS/119/13FP), SANA Semiconductors Limited, and Richtek USA Incorporated.We would also like to acknowledge technical support from Keysight TechnologiesHong Kong Limited and consultation from Andrew Ko on testing equipment.

References:[1] M. Hassan, et al., “A CMOS Dual-Switching Power-Supply Modulator with 8%Efficiency Improvement for 20MHz LTE Envelope Tracking RF Power Amplifiers,”ISSCC, pp. 366-367, Feb. 2013.[2] K. Onizuka, et al., “A 1.8GHz Linear CMOS Power Amplifier with Supply-PathSwitching Scheme for WCDMA/LTE Applications,” ISSCC, pp. 90-91, Feb. 2013.[3] K. Oishi, et al., “A 1.95GHz Fully Integrated Envelope Elimination andRestoration CMOS Power Amplifier with Envelope/Phase Generator and TimingAligner for WCDMA and LTE,” ISSCC, pp. 60-61, Feb. 2014.[4] P. Riehl, et al., “An AC-Coupled Hybrid Envelope Modulator for HSUPATransmitters with 80% Modulator Efficiency,” ISSCC, pp. 364-365, Feb. 2013.[5] X. Liu, et al., “A 50MHz 5V 3W 90% Efficiency 3-Level Buck Converter withReal-Time Calibration and Wide Output Range for Fast-DVS in 65nm CMOS,” IEEESymp. VLSI Circuits, pp. 1-2, June 2016.[6] O. Lee, et al., "A Charging Acceleration Technique for Highly Efficient CascodeClass-E CMOS Power Amplifiers," IEEE JSSC, vol. 45, no. 10, pp. 2184-2197, Oct.2010.[7] O. Lee, et al., "Analysis and Design of Fully Integrated High-Power Parallel-Circuit Class-E CMOS Power Amplifiers," IEEE TCAS-I, vol. 57, no. 3, pp. 725-734,Mar. 2010.[8] S.-C. Lee, et al., “A Hybrid Supply Modulator with 10dB ET Operation DynamicRange Achieving a PAE of 42.6% at 27.0dBm PA Output Power” ISSCC, pp. 42-43, Feb. 2015.

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Figure 2.4.1: Block diagram of proposed EST system and the supply modulator.Figure 2.4.2: Circuitry implementation of multiloop control and the linearamplifier with high-frequency path. Bode plots of id/ia and VPA/VELP.

Figure 2.4.3: Circuitry implementation of the mode-switching PA and VBCG andefficiency improvement with dynamic biasing.

Figure 2.4.5: Measured performance of the proposed EST system: efficiency,ACLR and output spectrums.

Figure 2.4.6: Comparison with prior supply modulators and on-chip PA systemswith dynamic supply voltages.

Figure 2.4.4: Supply-modulator tracking waveform and efficiency with a 20 MHzLTE envelope.

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2.5 A High-Efficiency Multiband Class-F Power Amplifier in 0.153μm Bulk CMOS for WCDMA/LTE Applications

Jenwei Ko, Xiaochuan Guo, Changhua Cao, Saravanan Rajapandian, Solti Peng, Jing Li, Wenchang Lee, Narayanan Baskaran, Caiyi Wang

MediaTek, Austin, TX

Rapid growth in LTE smart phones has increased the demand for multiband poweramplifiers (PAs) that have low cost and high efficiency. This paper describes amultiband WCDMA/LTE PA fabricated in a low-cost 0.153μm (85% shrink of0.18μm) bulk CMOS process that has the highest PAE among published CMOSWCDMA/LTE PAs in [1-6]. Notably, the PA implemented a Class-F outputmatching network (MN) that maximizes Psat and PAE at Psat and improves linearity.

Figure 2.5.1 shows the block diagram of the multiband CMOS PA for 824 to849MHz (B5), 880 to 915MHz (B8), 1850 to 1910MHz (B2), and 1920 to1980MHz (B1). B5 and B8 share a low-band (LB) path, while B1 and B2 share ahigh-band (HB) path. Each path consists of a single-ended-to-differential inputMN, a driver-stage amplifier, an inter-stage MN, an output-stage amplifier, and adifferential-to-single-ended output MN. Directional couplers at the output of LBand HB paths are daisy-chained for power detection. All circuit blocks arecontrolled through a MIPI interface.

The output-stage amplifier uses a cascode structure with a high-voltage MOStransistor (M2) to improve the drain breakdown voltage and to reduce the voltageswing at the drain of the NMOS transistor (M1). This decreases the Miller effecton gate-to-drain capacitance (Cgd). In addition, a cross-coupled capacitor C1

neutralizes the Cgd. Non-linearity from gate-to-source capacitance (Cgs) and anyun-neutralized Cgd of M1 is linearized by a PMOS varactor (M3) biased in themoderate-inversion region [1]. The overall amplifier size, gate bias voltages, andload impedance are optimized for maximum efficiency at 28dBm output power.

The PA implements a Class-F output MN that not only limits the maximum drainvoltage swing but also improves the drain efficiency, Psat, and output-stagelinearity. The MN terminates the fundamental and the 3rd-harmonic impedancesat the drain to values determined from a load-pull analysis. It is easier to realizespecific impedance at the 3rd harmonic at LB compared to HB due to the significantnon-linear drain capacitance (Cdd) observed in the CMOS process. The MN realizesa short for the 2nd harmonic. This limits the drain voltage swing to 2×VDD at thematched condition and also reduces the device breakdown-voltage requirementunder VSWR conditions. Realizing specific impedances at harmonics higher thanthe 3rd gives marginal improvement in efficiency at the expense of area andcomplexity.

In Fig. 2.5.2, C2H(C2L), L2H(L2L), and L2CM are used to realize the 2nd-harmonic trap.Optimal values for C1H(C1L), C3H(C3L) and the transformer inductance inconjunction with the 2nd-harmonic trap help realize specific impedances at thefundamental and 3rd harmonic with minimal loss. Large frequency differencebetween HB and LB leads to different MN implementations.

The driver-stage-amplifier (driver) design along with inter-stage matching networkis critical for overall PA linearity and to drive the output-stage amplifier to itsfullest. Increasing the ratio (n) of the step-down inter-stage transformer in Fig.2.5.3 improves the driver efficiency at the expense of driver linearity. This PAimplements a 3:1 inter-stage transformer to optimize the efficiency-and-linearitytrade-off. As a result, the driver is very efficient and consumes only 3% of theoutput-stage quiescent current. The driver uses a cascode structure for goodlinearity and isolation with the input. Furthermore, a 2nd-harmonic short isimplemented at the driver output to improve its linearity.

The input matching network matches the PA to 50Ω using a 1:3 transformer,which provides an additional 9.5dB voltage gain. A tuning capacitor at the primaryis used to keep S11 < -10 dB across the various frequency bands.

Although the Class-F operation and the HVMOS improve reliability significantly,real-time voltage-stress monitoring (VSM) is implemented on each of the output-stage amplifier drains to indicate the voltage stress and to protect the PA undersevere conditions. The VSM circuit in Fig. 2.5.3 comprises of series diodes, acapacitor, and a resistor divider. The diodes and the capacitor track the peak drainvoltage. The divided voltage is compared with the reference voltage (Vref) to signalthe stress on the device.

Figure 2.5.7 shows the micrograph of the 0.153μm CMOS die and the 0.18μmIPD die in a 3.0×4.2×0.6mm3 LGA package. The performance of the packaged PAis measured on an evaluation board. Figure 2.5.4 shows linearity, PAE, and gainversus output power for an LTE 20MHz 100RB 16-QAM signal with VDD=3.4V.Measured LB (HB) PAE are 37.3% (34.7%) at 27.5dBm (28.1dBm) linear outputpower (Pmax) while meeting the 3GPP specification with a 2dB margin. LoweringVDD and the bias voltage enhances PAE at the mid- and low-power outputs (Fig.2.5.5). At 19dBm and 9dBm output power, HB PAEs are 21% and 8%, which arehigher than the Doherty PA in [6]. The high temperature operation life (HTOL)test is performed with 16 samples in each band at 85°C and 28dBm modulatedsignal for 520 hours. The ruggedness test is carried out under a VSWR of 10:1for various phases. No performance degradation is observed after the HTOL andthe ruggedness tests. The PA passes both HBM 2kV and machine-model (MM)300V ESD tests.

Figure 2.5.6 shows a summary of the performance comparison of this PA withthe state-of-the-art CMOS PAs for the WCDMA and LTE 20MHz 16-QAM signals.This Class-F linear PA has the best efficiency and the least power back-off (Psat -Pmax), compared to other PA architectures in [2-6]. The lower power back-off demonstrates the high linearity of this PA.

In conclusion, this Class-F PA achieves the highest efficiency among the publishedCMOS PAs in Fig. 2.5.6 and closes the performance gap between CMOS and GaAsPAs, especially, at LB frequencies.

Acknowledgements:The authors thank PY Chiang, Samny Huang, Jennifer Hsiao, Alex Liu, BigchougHung, Ying He, Marlon Teodosio and Paul Ko for their support of this work.

References:[1] C. Wang, et al., “A Capacitance-Compensation Technique for ImprovedLinearity in CMOS Class-AB Power Amplifier,” IEEE JSSC, vol.39, no.11, pp. 1927-1937, Nov. 2004.[2] B. Koo, et al., “A Fully Integrated Dual-Mode CMOS Power Amplifier forWCDMA Applications,” ISSCC, pp. 82-83, Feb. 2012.[3] K. Kanda, et al., “A Fully Integrated Triple-Band CMOS Power Amplifier forWCDMA Mobile Handsets,” ISSCC, pp. 86-87, Feb. 2012.[4] B. Park, et al., “A 31.5 %, 26 dBm LTE CMOS power amplifier with harmoniccontrol,” EuMIC, pp. 341-344, Oct. 2012.[5] E. Kaymaksut, et al., “A Dual-Mode Transformer-Based Doherty LTE PowerAmplifier in 40nm CMOS,” ISSCC, pp. 64-65, Feb. 2014.[6] A. Farouk, et al., “Class-O: A Highly Linear Class of Power Amplifiers in 0.13μmCMOS for WCDMA/LTE Applications,” ISSCC, pp. 40-41, Feb. 2015.

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Figure 2.5.1: Top block diagram and unit PA schematic. Figure 2.5.2: LB and HB Class-F output matching networks.

Figure 2.5.3: Inter-stage matching network and voltage-stress-monitoringcircuit.

Figure 2.5.5: LTE 20MHz, 100RB, 16-QAM measurement results at powermodes.

Figure 2.5.6: Performance comparison with the state-of-the-art WCDMA/LTECMOS PAs.

Figure 2.5.4: LTE 20MHz, 100RB, 16-QAM measurement results withVDD=3.4V.

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Figure 2.5.7: CMOS and IPD die micrograph.



2.6 A SiGe BiCMOS E-Band Power Amplifier with 22% PAE at 18dBm OP1dB and 8.5% at 6dB Back-Off Leveraging Current Clamping in a Common-Base Stage

Junlei Zhao1,2, Elham Rahimi1, Francesco Svelto1, Andrea Mazzanti1

1University of Pavia, Pavia, Italy 2now with HiSilicon-Technologies, Milan, Italy

Several spectrum portions at mm-waves are considered for Gb/s data-rates in 5Gcellular wireless backhaul and access networks, further motivating innovation incircuits and systems for efficient transceivers [1,2]. Small or pico-cell networksare required for spatial diversity and propagation-loss compensation, suggestingsilicon solutions also for backhauling where the E-band is a candidate. Techniquesfor spectral and power efficiency are being investigated, key for capacityimprovements over LTE and deployment of the large number of required cells. Atransmitter power amplifier (PA), delivering near 20dBm, is a key block for powersaving. With the high peak-to-average ratio of QAM modulations, PAs are operatedat 5-to-8dB back-off [2], where the efficiency of reported silicon E-band PAs is inthe order of a few percent only [3-5].

Techniques adopted at RF, such as supply modulation for envelop tracking andlinearization of switch-mode PAs, do not lend themselves to high-rate mm-wavecommunications, suggesting further investigation of basic amplifier topologies.Most of the reported E-band PAs are based on common-source/emitter stagesand suffer from soft saturation with output power at 1dB gain compression(OP1dB) remarkably lower than PSAT, where efficiency peaks. Class-A biasingyields maximum gain, but efficiency drops quickly at back-off. Class-AB allowscurrent saving at low output power, but still suffering from soft saturation. In thiswork, we exploit the intrinsically linear common-base stage to achieve OP1dBclose to PSAT. Furthermore, the power stage implements the current-mode versionof the well-known diode voltage clamper [6], so that the DC current tracks thesignal current yielding a remarkable improvement of efficiency at back-off.

The schematic of the differential amplifier including a cascode driver, output stage,and matching networks is shown in Fig. 2.6.1. Realized prototypes, designed foran 80GHz center frequency, show OP1dB=18dBm with PSAT=19dBm. Theefficiency at OP1dB and 6dB back-off is 22% and 8.5%, respectively, at least ~2×higher than for reported E-band silicon amplifiers.

The principle of current clamping is illustrated in Fig. 2.6.2. First, let us assumethe parasitic capacitance CBE=0. If Vb is set for low quiescent current in Q1 (ideallyzero), the transistor is off during the first-half negative cycle of IIN(t) and LE

charges up to Ipk. Then, the DC current through Q1 and LE equals Ipk. Q1 turns-onwith its emitter current IE(t)=Ipk+Ipksin(ω0t). Assuming LE ideally infinite, Q1 neverswitches off and operates in Class-A. With LE large but finite, the inductordischarges in each cycle due to the non-zero transistor emitter resistance. Arelatively small ripple appears in IL(t), but still the average current is proportionalto Ipk. Leveraging current-clamping, the DC current of Q1 scales linearly with theenvelope of the signal current, similar to an ideal Class-B common emitter stage,but without compromising gain.

At high frequency, CBE plays a key role. First, with ideally infinite LE, CBE absorbsall the signal current in the initial transient when Q1 is off and the chargingtransient becomes indefinitely long. With large LE, though not infinite, the transientis still unacceptably long. Second, CBE provides a low-impedance path at ω0 andforms a current divider with the equivalent resistance at the emitter. The latterkeeps reducing when the input current rises, and this mechanism causesunwanted expansion in the amplifier gain.

The two issues are solved by sizing LE to resonate with CBE at ω0. IL(t) rises quicklywith an overshoot of ~1.7Ipk, and reaches steady state in two cycles of IIN(t) only.Moreover, the high impedance of LE-CBE at ω0 forces the fundamental componentof the collector current to be equal to IIN, thus achieving a constant current gainup to amplifier saturation. CBE also sets low impedance at the emitter above ω0,thus allowing harmonics of IIN in the collector current, but the latter are easilyfiltered out by the output matching network of the amplifier.

The E-band PA has been designed in a SiGe BiCMOS technology featuring eightcopper metal layers, AluCap and high-speed NPN transistors withfT/fMAX=320/370GHz. Transistors in the common-base differential output stage,Q1a,b, are supplied from a VCC1=1.8V source and sized with the emitter area ofAe=5×2.4μm2. With a quiescent current set to 2×13mA, the emitter resistance ismuch lower than the driving impedance, not impairing the small-signal gain. TheDC current in Q1a,b rises with the delivered output power above 100mA. Atransformer T1, inductors L1a,b (modeling the metal paths toward the GSG pad),and the pad capacitance realize the output matching network.

The driver adopts a cascode configuration, with Q2a,b and Q3a,b of Ae=3×2μm2, forhigh output impedance. For maximum gain and best linearity, transistors arebiased in Class-A with 2×24mA from a VCC2=2.3V supply. An inter-stage matchingnetwork, realized with a transformer T2 and transistors parasitic capacitances,introduces a current gain of ~3. The input impedance of the amplifier is matchedto 50Ω with a transformer T3, L3a,b, and capacitance of the input pad, whileresistors R1a,b ensure unconditional stability also at low frequency.

Measured and simulated scattering parameters in the 50-to-100GHz frequencyrange are shown in Fig. 2.6.3. The peak of S21 is 21dB at 80GHz with -3dBbandwidth from 71 to 86GHz. S12 is below -30dB in the whole frequency rangewhile input reflection (S11) is below -10dB from 60 to 100GHz.

Large-signal measurements at 80GHz are reported in Fig. 2.6.4. OP1dB is 18dBm,only 1dB lower than PSAT=19dBm. The bottom plot shows the power consumptionand PAE versus POUT. Maximum PAE is 23% near PSAT and 22% at OP1dB. Currentclamping in the output stage allows significant power saving at back-off and PAE6dB below OP1dB is still 8.5%.

Figure 2.6.5 shows large-signal measurements versus frequency. PSAT rangesfrom 20dBm at 70GHz to 17.5dBm at 90GHz with OP1dB ~1dB less. Peak PAE isalways higher than 20% and at 6dB back-off from OP1dB above 7%. Experimentalresults are summarized in Fig. 2.6.6, together with the performances of recentlyreported silicon E-band PAs. The comparison with state of the art in Fig. 2.6.6shows at least ~2× higher efficiency, both at OP1dB and 6dB back-off. A diemicrograph is shown in Fig. 2.6.7.

Acknowledgements:Authors thank the RF Department of HiSilicon for technical and financial supportand the Huawei team of Milan, Italy, for the assistance with measurements.

References:[1] X. Ge, et al., "5G Wireless Backhaul Networks: Challenges and ResearchAdvances," IEEE Network, vol. 28, no. 6, pp. 6-11, Nov.-Dec. 2014.[2] C. Dehos, et al., “Millimeter-Wave Access and Backhauling: The Solution tothe Exponential Data Traffic Increase in 5G Mobile Communications Systems?”,IEEE Comm. Magazine, vol. 52, no. 9, pp. 88-95, Sept. 2014.[3] Y. Zhao and J. Long, “ A Wideband, Dual-Path, Millimeter-Wave PowerAmplifier With 20 dBm Output Power and PAE Above 15% in 130 nm SiGeBiCMOS,” IEEE JSSC, vol. 47, no. 9, pp. 1981-1997, Sept. 2012. [4] A. Chen, et al., “An 83-GHz High-Gain SiGe BiCMOS Power Amplifier UsingTransmission-Line Current-Combining Technique,” IEEE TMTT, vol. 61, no. 4, pp.1557-1569, Apr. 2013. [5] D. Zhao and P. Reynaert, “A 0.9V 20.9dBm 22.3%-PAE E-Band PowerAmplifier with Broadband Parallel-Series Power Combiner in 40nm CMOS,”ISSCC, pp. 248–249, Feb. 2014.[6] A. Sedra and K. Smith, Microelectronic Circuits, 6th edition, Oxford UniversityPress, USA, pp. 210-212, Dec. 2009.

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Figure 2.6.1: Schematic of the E-band power amplifier. Figure 2.6.2: Principle of current clamping in a common-base amplifier.

Figure 2.6.3: Measured and simulated scattering parameters.

Figure 2.6.5: POUT and PAE versus frequency. Figure 2.6.6: Performance summary and comparison.

Figure 2.6.4: Large-signal measurements at 80GHz.

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2.7 A Wideband 28GHz Power Amplifier Supporting 8×100MHz Carrier Aggregation for 5G in 40nm CMOS

Sherif Shakib1, Mohamed Elkholy1, Jeremy Dunworth2, Vladimir Aparin2, Kamran Entesari1

1Texas A&M University, College Station TX2Qualcomm, San Diego, CA

To meet rising demand, broadband-cellular-data providers are racing to deployfifth generation (5G) mm-wave technology, e.g., rollout of some 28GHz-bandservices is intended in 2017 in the USA with ~5/1Gb/s downlink/uplink targets.Even with 64-QAM signaling, this translates to an RF bandwidth (RFBW) as largeas ~800MHz. With ~100m cells and a dense network of 5G access points (APs),potential manufacturing volumes make low-cost CMOS technology attractive forboth user equipment (UE) and AP devices. However, the poor Pout and linearity ofCMOS power amplifiers (PAs) are a bottleneck, as ~10dB back-off is typical formeeting error-vector-magnitude (EVM) specifications. This limits communicationrange and PA power added efficiency (PAE), with wider RFBWs accentuating theseissues further. On the other hand, sufficient element counts in the envisaged 5Gphased-array modules can overcome path loss despite low Pout per PA, e.g., bycombining RFICs in an AP. CMOS PAs with wideband linearity/PAE can thereforeenable economical UE/AP devices to deliver 5G data-rates.

Silicon 28GHz-band PAs with state-of-the-art PAE were recently reported [1-3].Despite these advances, linearity is not sufficiently broadband for 5G speeds, e.g.,a maximum RFBW of 250MHz at 28GHz [1]. Relevant state-of-the-art CMOS PAsfor 802.11ad [4-6] are similar to their 28GHz counterparts in a normalized RFBWsense, e.g., 500MHz RFBW at 60GHz [4]. This paper reports a 28GHz CMOS PAsupporting 3× the state-of-the-art RFBW without degrading Pout, PAE, or EVM.The three-stage PA uses dual-resonance transformer-matching networks withbandwidths optimized for wideband linearity. A digital gain control (9dB range)is integrated for phased-array operation; a needed functionality absent fromexisting high-performance mm-wave PAs.

Figure 2.7.1 shows the PA schematic. The 1× power transistor layout is similarto [6] (W/L=32×1μm/40nm). Capacitive neutralization is used in stages 2 and 3for higher reverse isolation. Stage 1 is a current steering VGA with 4×2dB gainsteps determined by the width ratios of a switched array of low-Vt cascodetransistors. This topology has robust gain-step accuracy and small input/outputimpedance and insertion phase variations across digital states. An additional 1dBstep is implemented in the biasing of stage 2. The stage scaling, indicated in Fig.2.7.1, helps avoid compression in stages 1 and 2.

The back-off PAE of stage 3 is first optimized using a similar approach to [1].Wideband matching is additionally desired to improve linearity by generallyavoiding memory effects, e.g., due to sharp RF gain or phase variations withfrequency. Broadband transformer-matching networks are realized using loosemagnetic coupling, k, to attain two in-band resonances separated by Δf. Usingideal transformer models and by simulating the amplitude-to-amplitude/amplitude-to-phase modulation conversion (AM-AM /AM-PM) of thePA at 28GHz, the effect of Δfin on linearity/PAE in stage 3 for constant bias andterminations are determined and illustrated in Fig. 2.7.2. Explicit input shuntresistance is used, ranging from 660 to 100Ω, to enable increase in Δfin from 1to 7GHz at the cost of power gain, which drops from 13 to 6dB. A wider-separationΔfin reduces the slope versus frequency of the insertion phase of the transformer-matching network. In turn, this insertion phase is increasingly desensitized to thenonlinear variation in Cin of the amplifier stage with signal strength, therebyreducing AM-PM conversion. Figure 2.7.2 shows that the AM-AM conversion isinsensitive, while the AM-PM conversion decreases with increasing Δfin. Also, Pout

at a constant EVM (for a 64-QAM OFDM signal) increases with Δfin, andapproaches the artificial case of setting the AM-PM conversion to zero. Δfin=3GHzis chosen as a compromise between Pout and PAE/gain. To realize a desired Δfin,transformer windings are offset to control k. The low Ropt,diff=45Ω target fromload-pull simulation enables broadband output matching (Δfout ~7GHz). Shuntinput resistance and transformer self-inductances scale inversely with Cin of eachstage such that the gain is ~7 to 8dB/stage with the overall bandwidth limited byCin of stage 3.

The PA die micrograph is shown in Fig. 2.7.7. It was fabricated in 1P6M 40nmCMOS LP with core dimensions of 0.90×0.25mm2 and using a 1.1V nominalsupply. S-parameter measurements across 20 to 40GHz and gain settings areshown in Fig. 2.7.3. Input return loss is >10dB over 24.3 to 36.6GHz and variesnegligibly across settings. Peak gain is 22.4/13.3dB for a maximum/minimumsetting at 28GHz. Expected skin effect in transformers and transistor maximum-available-gain (MAG) roll-off, and unexpectedly small capacitance (w.r.t.simulation) cause the observed gain slope. Also, Fig. 2.7.3 shows the peaknonlinearity error <0.5dB in the gain step over 26 to 34.3GHz. Phase error is small(peak<9.3°), which mitigates complexity of phased-array calibration.

Measured continuous-wave (CW) Pin sweeps up to Pin,max=–3.5dBm are reportedin Fig. 2.7.4 for the highest gain setting and over 26 to 33GHz with a 1GHz step(Pmax in Fig. 2.7.4 is Pout at Pin,max). The PA is driven to at least 1dB compressionacross 26 to 33GHz, and to 2-to-3dB compression only over 27 to 30GHz. Thepeak performance is at 27GHz, with Psat/PAEmax of 15.1dBm/33.7%, where Psat isPout at 3dB compression. Also, P1dB/PAE1dB remain >13.4dBm/25%, while PAE atP1dB–5dB remains >13.2% across 26 to 33GHz.

Figure 2.7.5 shows measurements using a 64-QAM OFDM signal (2048-point FFT,75kHz tone spacing, 9.7dB PAPR at 0.01% complementary cumulativedistribution function). To test with 5G data-rates, 1-, 4-, and 8-component-carrier(CC) aggregation scenarios are measured, for 90MHz-wide CCs and 10MHz guardbands. CCs are amplified concurrently with the composite Pin divided evenlyamong them. PAE/EVM are plotted vs. Pout at 27GHz for {1,4,8}CC. Pout/PAE for –25dBc or better EVM on each CC are also summarized vs. center frequency. For8CC, the peak performance is at 27GHz: Pout = 6.7dBm at 11% PAE. A snapshotof a corresponding measured output spectrum shows lower/upper-adjacent-channel-leakage ratios (ACLR) are –34.4/–29.4dBc. Pout/PAE remain>6.5dBm/9.6% across 27 to 32GHz for 8CC.

Figure 2.7.6 shows a comparison with the state-of-the-art. This work extendsRFBW by 3× over that in [1] while achieving higher Pout/PAE at equal EVM for thesame signal PAPR. A narrower RFBW and lower signal PAPR tested in [2] makecomparison of linearity difficult. Relative to [4], this PA produces almost the samePout at the same EVM for a wider RFBW relative to the center frequency and at 2×higher PAE from a lower supply voltage. Normalizing the PA performance to thesupply voltage and the number of combined PA cores shows CW Psat of this workis on-par with the state-of-the-art. The back-off CW PAE of this work only seemslower than the single-/two-stage designs of [2]/[1], but this is a natural result ofthe 12dB/6dB higher gain achieved. For example, the CW drain efficiency of stage3 in this work at P1dB-5dB is 25.6%, i.e. very close to the ~26.3% in [2] for a 1.1Vsupply. This work simultaneously achieves higher back-off PAE and 7dB highergain than [3]. In summary, the implemented wideband CMOS PA can handlechallenging 5G data-rates at low cost without sacrificing range or efficiency.

Acknowledgement:The authors thank Hyun-Chul Park and Bon-Hyun Ku for technical discussions,and Andrew Yang, David Palmer and Osvaldo Alcala for measurement support.The authors also especially thank Martin Lim and Rohde & Schwarz, Inc. for testequipment support.

References:[1] S. Shakib, et al., "A 28GHz Efficient Linear Power Amplifier for 5G PhasedArrays in 28nm Bulk CMOS," ISSCC, pp. 352-353, Feb. 2016.[2] B. Park, et al., "Highly Linear CMOS Power Amplifier for mm-WaveApplications," IEEE Int. Microwave Symp. Dig., pp. 1-3, May 2016.[3] A. Sarkar and B. Floyd, "A 28-GHz Class-J Power Amplifier with 18-dBm OutputPower and 35% Peak PAE in 120-nm SiGe BiCMOS," SiRF, pp. 71-73, Jan. 2014.[4] S. Kulkarni and P. Reynaert, "A Push-Pull mm-Wave Power Amplifier with<0.8° AM-PM Distortion in 40nm CMOS," ISSCC, pp. 252-253, Feb. 2014.[5] A. Larie, et al., "A 60GHz 28nm UTBB FD-SOI CMOS reconfigurable poweramplifier with 21% PAE, 18.2dBm P1dB and 74mW PDC," ISSCC, pp.1-3, Feb.2015.[6] D. Zhao and P. Reynaert, "A 60-GHz Dual-Mode Class AB Power Amplifier in40-nm CMOS," IEEE JSSC, vol. 48, no. 10, pp. 2323-2337, Oct. 2013.

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Figure 2.7.1: Three-stage PA; cascode VGA 1st stage; neutralized common-source 2nd and 3rd stages.

Figure 2.7.2: Linearity-PAE optimization in stage 3 using spacing of the tworesonance frequencies Δfin.

Figure 2.7.3: Measured S-parameters across digital gain states; associatedgain/phase errors vs. frequency.

Figure 2.7.5: Measurements for 64-QAM OFDM with {1,4,8}CC; measuredspectrum for peak 8CC performance.

Figure 2.7.6: Comparison with the state-of-the-art linear mm-wave silicon PAsfor data communication.

Figure 2.7.4: CW signal measurements: power sweeps across 27 to 30GHz;Pout/PAE summary vs. frequency.

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2.8 A Class-G Voltage-Mode Doherty Power Amplifier

Voravit Vorapipat, Cooper Levy, Peter Asbeck

University of California, San Diego, CA

In modern communication, wideband and high-spectral-efficiency modulationresults in high peak-to-average power ratio (PAPR), up to 8 to 10dB. Well-knownPA-efficiency-enhancement techniques, such as Doherty and outphasing, offerreduced efficiency improvement beyond 6dB back-off, limiting the efficiencyenhancement obtainable with high PAPR modulation. Recent works have shownthat a combination of different techniques [1-3] can result in improved efficiencywell beyond 6dB back-off. However, these combined techniques have come at acost of glitches due to mode-transitions, when power supply voltage or loadimpedance undergo large variations at critical power levels. In [1,2] switchingbetween power supply voltages causes significant glitches, which degrade theEVM and ACPR of the transmitted signal. In [1], reasonable EVM is achieved, byreducing the average output power so that power supply switching is lessfrequent. A “skipping window” technique is proposed in [3] to skip high-frequencymode-transitions reducing overall glitching. While this improves the ACPR, theefficiency is degraded since there is no enhancement during a skipped transition.

In this work, we demonstrate the combination of the voltage-mode Doherty (VMD)[4] and Class-G switched-capacitor power amplifier (SCPA) [5] techniques.Together, these techniques provide efficiency peaking at both 6 and 12dB back-off over a wide bandwidth without introducing the glitches present in previousworks. The Class-G VMD with integrated matching network achieves a PAE of24% and better than -32dB EVM for 256-QAM OFDM signals.

Figure 2.8.1 shows two Class-G SCPAs, which behave like RF voltage sources,connected across a transformer, forming the Class-G VMD structure. The SCPAis based on segmentation of a voltage mode Class-D RF power amplifier, in whichthe capacitor and a totem-pole driver are partitioned into small unit cells. When asub-set of unit cells is turned on, the output voltage is proportional to the numberof active unit cells [5]. By allowing the unit-cell totem-pole driver to independentlyoperate at either a full or half supply voltage (Fig. 2.8.2), high efficiency can beachieved when all unit cells operate at either of these conditions [5]. At full power,the two SCPAs drive the transformer in anti-phase at full amplitude, and theimpedance seen by each SCPA is 25Ω. As the unit cells of the peaking SCPA areturned off reducing its output amplitude, the impedance seen by the main SCPAstarts to increase until it reaches 50Ω. Here the peaking SCPA is completely off,providing efficiency peaking at 6dB back-off [4]. From 6-to-12dB back-off, theunit cells of the main PA transition one-by-one from full supply to half supply,gradually decreasing the main PA amplitude until all main PA unit cells operate athalf supply. With high impedance (50Ω) presented by the VMD, and a half supplyswing presented by the Class-G SCPA, efficiency peaking at 12dB back-off isachieved. As output power varies from zero to full power, the PA operation onlyinvolves mode-switching at the unit-cell level, thus avoiding large mode-switchingglitches present in previous works [1,2] associated with switching the supply forthe entire PA.

The implementation of the Class-G VMD is shown in Fig. 2.8.2. The SCPAs areimplemented with a polar architecture, and the phase-modulated RF (PMRF)inputs are the same for both main and peaking PAs. The amplitude-control word(ACW) independently controls the state of individual unit cells (“on” at full supply,“on” at half supply, or “off”) in each SCPA. A series-combined primary load-modulation transformer is used. This increases the output power by lowering theimpedance presented to the SCPAs, and fully utilizes the transformer structure atany power level to provide low insertion loss, especially at 6dB back-off and lower[4]. Using ACW control over unit cell operation as shown in Fig. 2.8.1, efficiencypeaking at both 6 and 12dB back-off is achieved. Figure 2.8.2 also shows theClass-G SCPA unit cell, composed of a pull-down network to ground, and twopull-up networks connected to full and half supply, respectively [5]. In a full-

supply mode, VinpF and Vinn are switching, providing a 2.4Vp-p square wave. VenH

prevents current flow from the 2.4V to 1.2V supply [5]. In a half-supply mode,VinpH and Vinn are switching, providing a 1.2Vp-p square wave. The unit-cellcapacitors are resonated with the transformer leakage inductance. This seriesresonance is followed by a parallel resonance of the transformer core inductanceand Cp. Together, the two resonances form an impedance-compensation network,resulting in wide bandwidth. The unit cells are segmented into 5b unary cells and4b binary cells. Since half supply is not used in the peak PA unit cells, the LSBunit cell of the main PA is discarded to maintain the same resolution (Fig. 2.8.1)in both PAs (9b effective resolution for each).

The PA is fabricated in 45nm CMOS SOI (Fig. 2.8.7). All transistors used in thedesign are thin-oxide with regular Vt. The chip is assembled on a PCB and itsoutput measured with a 50Ω GSG probe. Output loss is calibrated to the padswhere the probe is landed. The quoted PAE includes all power consumed on thechip, but excludes PMRF/Serial Data/ClkSer/ClkBB input powers since most ofthis power is consumed in the termination resistors. In an integrated solution,these input powers will be replaced by the power required to drive a fewminimum-size inverters, which is negligible compared to the output power of thisdesign. The CW measurement (Fig. 2.8.3) shows that the PA achieves peakpower/peak PAE/6dB PAE/12dB PAE of 25.3dBm/30.4%/25.3%/17.4% at 3.5GHz.This presents an improvement in PAE of 66%/129% at a 6dB/12dB back-off overa Class-B PA normalized to the same peak efficiency. The 1dB Psat bandwidth isgreater than 38% spanning from 2.9 to 4.3GHz while still maintaining high peakand back-off PAEs.

The PA is linearized by memoryless AM-AM and AM-PM look-up tables (LUTs),calibrated with a 30kHz amplitude modulation with 100% modulation index. Witha 10MHz 32-carrier 256-QAM OFDM signal and 8.2dB PAPR, the PA achieves17.1dBm Pavg, -40.1dB EVM, >45dBc ACPR and 21.4% PAE (Fig. 2.8.4), morethan a 1.8× improvement in efficiency compared to Class-B back-off. Theasymmetry of the close-in spectrum is due to the reconstruction filter in the RFvector signal generator, which leads to a distortion in a polar architecture. Thisfilter also limits the modulation bandwidth of the measurement setup to 10MHz.The chip should be able to support modulation bandwidths in excess of 80MHz,at which point the bandwidth would be limited by the 1:24 deserializer. In separatemeasurements, the average output power was varied to demonstrate the trade-off between PAE and EVM for this PA (Fig. 2.8.5). A summary of measurementresults and comparison with recent works is shown in Fig. 2.8.6.

This work demonstrates a CMOS power amplifier that achieves widebandefficiency peaking at both 6 and 12dB back-off without mode-transition glitches.This is evidenced by the excellent EVM that is achieved without backing off theoutput signal power. The absence of glitches allows the Class-G VMD to transmithigh PAPR modulation with high efficiency and excellent EVM using a simplememoryless LUT.

Acknowledgements:The authors would like to thank GlobalFoundries for circuit fabrication andIntegrand Software for use of an electromagnetics simulation tool (EMX).

References:[1] S. Hu, et al., "A Broadband CMOS Digital Power Amplifier with Hybrid Class-G Doherty Efficiency Enhancement," ISSCC, pp. 44-45, Feb. 2015.[2] P. Godoy, et al., "A 2.4-GHz, 27-dBm Asymmetric Multilevel Outphasing PowerAmplifier in 65-nm CMOS," IEEE JSSC, vol. 47, no. 10, pp. 2372-2384, Oct. 2012.[3] W. Tai, et al., "A Transformer-Combined 31.5 dBm Outphasing Power Amplifierin 45 nm LP CMOS With Dynamic Power Control for Back-Off Power EfficiencyEnhancement," IEEE JSSC, vol. 47, no. 7, pp. 1646-1658, July 2012.[4] V. Vorapipat, et al., "A wideband Voltage Mode Doherty Power Amplifier," IEEERFIC, pp. 266-269, May 2016.[5] S. M. Yoo, et al., "A Class-G Switched-Capacitor RF Power Amplifier," IEEEJSSC, vol. 48, no. 5, pp. 1212-1224, May 2013.

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Figure 2.8.1: Class-G Voltage-Mode Doherty operation at 0/6/12dB back-off;idealized efficiency vs Pout; and unit-cell state table. Figure 2.8.2: Class-G Voltage-Mode Doherty implementation.

Figure 2.8.3: CW measurement results of output power and PAE.

Figure 2.8.5: PAE and EVM vs output power for a 10MHz 32-Carrier 256-QAMOFDM signal with nominal 8.2dB PAPR.

Figure 2.8.6: Summary of measurement results and comparison with previouslypublished CMOS PAs with greater than 6dB efficiency enhancement.

Figure 2.8.4: Measured spectrum and constellation of a 10MHz 32-Carrier 256-QAM OFDM signal with 8.2dB PAPR.

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Figure 2.8.7: Die micrograph (1.2mm×1mm).

session 2 overview: power amplifiers

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