[sic-en-2013-16] gan power transistor modeling for high-speed converter circuit design

646 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 2, FEBRUARY 2013

GaN Power Transistor Modeling for High-SpeedConverter Circuit Design

Akira Nakajima, Kazuto Takao, and Hiromichi Ohashi, Life Member, IEEE

AbstractA circuit simulator has been developed to designpower losses of high-frequency power converters using GaN-basedheterojunction field-effect transistors (GaN-HFETs). The simula-tor is based on a high-accuracy equivalent model of GaN-HFETswith peculiar device physics and high-speed loss calculation meth-ods. The simulated power losses were consistent with measuredresults in dcdc converters constructed by a GaN-HFET and aSiC Schottky diode with more than 93% accuracy. By utilizing thedeveloped simulator, key requirements in heat-dissipation tech-nologies, circuit parasitic inductances, and gate-drive technologiesfor next-generation converters are discussed.

Index TermsGaN, heterojunction field-effect transistor(HFET), power converters, semiconductor device modeling.

I. INTRODUCTION

THE OUTPUT power densities of electric power convertershave linearly increased by two orders of magnitude overthe last 30 years [1]. The power density increment has beenmainly achieved by a switching frequency increment of semi-conductor power devices to reduce sizes of passive componentsand power loss reduction to miniaturize heat sink volumes.From the trend, it is expected that high-density converters ofmore than 50 W/cm3 will be commercialized at around 2020by further frequency increment and loss reduction.

However, a higher switching frequency causes a largerswitching loss in general. As a solution of the contradictingrequirements, novel power devices using wide band-gap semi-conductors, in particular, gallium nitride-based heterojunctionfield-effect transistors (GaN-HFETs), are promising candidatesas semiconductor switches in next-generation power converters.GaN has the high electric field strength over 3 MV/cm, whichis ten times larger than that of the Si and high-electron mobilitymore than 1400 cm2/V s by utilizing the unique polarizationproperties. As a result, a low ON-resistance with maintaining

Manuscript received July 15, 2012; revised September 13, 2012; acceptedOctober 12, 2012. Date of publication December 21, 2012; date of currentversion January 18, 2013. This work was supported by a Grant for AdvancedIndustrial Technology Development in 2011 under Project 11B06003d anda Low power loss nitride device project for communication network underProject P03033 from the New Energy and Industrial Technology DevelopmentOrganization of Japan. The review of this paper was arranged by EditorN. Arora.

A. Nakajima and H. Ohashi are with Advanced Industrial Scienceand Technology, Tsukuba 305-8568, Japan (e-mail: [email protected];[email protected]).

K. Takao was with Advanced Industrial Science and Technology, Tsukuba305-8568, Japan. He is now with Corporate Research and Develop-ment Center, Toshiba Corporation, Kawasaki 212-8582, Japan (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2012.2226180

Fig. 1. (a) Schematic cross section of a typical device structure of GaN-HFETs. There are two issues of GaN-HFETs: 1) electron traps cause the currentcollapse; and 2) punchthrough induces short-channel effects. (b) Equivalentcircuit configuration of GaN-HFETs.

high switching speed over the tradeoff limitation of Si-baseddevices can be obtained in GaN-HFETs.

On the other hand, to bring out intrinsic high performancesof such wide band-gap devices, total design methodologies, in-cluding circuit, magnetic, noise, and thermal designs could playan important role to realize next-generation power converters.For example, as mentioned in this paper, power losses of high-frequency power converters using GaN-HFETs are significantlyinfluenced by stray inductances in converter circuits and gate-drive conditions due to high-speed switching capabilities ofGaN-HFETs.

Recently, we have proposed an equivalent circuit model ofGaN-HFETs for exact circuit simulation in power converters[2]. In this paper, we report more details of the equivalent circuitmodel and parameter extraction methodologies by taking intoaccount peculiar device physics of GaN-HFETs and novel losscalculation methods with short computation time. In addition,we discuss some key issues in power converters using GaNHFETs from calculated results by the developed simulator.

II. EQUIVALENT CIRCUIT MODEL OF GaN HFETS

Fig. 1(a) shows a simplified schematic of conventionalGaN-HFETs. GaN power devices are generally fabricated ina several-micrometer-thick AlGaN/GaN layer structure on aheterogeneous substrate such as silicon, silicon carbide (SiC),and sapphire substrates. High-density 2-D electron gas (2DEG)

0018-9383/$31.00 2012 IEEE

NAKAJIMA et al.: GaN POWER TRANSISTOR MODELING FOR CONVERTER CIRCUIT DESIGN 647

TABLE ICHARACTERISTICS AND GATE-DRIVE CONDITIONS

OF MEASURED DEVICES

Fig. 2. Gatedrain capacitance values of a GaN-HFET measured in dc andpulsed bias conditions. The inserted figure shows a comparison of measuredcapacitance values of a GaN-HFET and a Si-MOSFET in dc bias conditions.

over 1013cm2 is generated at the AlGaN/GaN heterointerfaceautomatically without intentional impurity doping by spon-taneous and piezoelectric polarization effects. A 2DEG mo-bility reaches intrinsic bulk mobility of 1400 cm2/V s dueto low-impurity scatterings. As a result, a low area-specificON-resistance can be obtained in a GaN-HFET.

GaN-HFETs are kinds of n-channel lateral-type unipolartransistors. We have applied a commonly used equivalent cir-cuit configuration shown in Fig. 1(b) as a GaN-HFET model.The equivalent model is constructed with four parameters ofa gatesource capacitance Cgs, gatedrain capacitance Cgd,drainsource capacitance Cds, and current source Ich.

Specific features of GaN-HFETs need to be clarified todevelop accurate equivalent models. We have measured com-mercially available GaN-HFETs and Si-MOSFETs shown inTable I and observed two peculiar futures or issues of GaN-HFETs. One is well known that reversible 2DEG density degra-dation and recovery behaviors caused by a dc stress appliedto the drainsource voltage, which is originated by electrontraps at the AlGaN barrier surface and in the low-quality bufferof the epilayer/substrate interface, as illustrated in Fig. 1(a).These voltage stress effects are commonly observed in GaN-HFETs and referred to as current collapse [3]. This devicephenomenon induces the ON-resistance increment observedin pulsed measurements after applying a dc voltage stressin comparison with a resistance measured in simple dc biasconditions [4]. In addition, we have found that the currentcollapse enhances breakdown voltage [5] and reduces devicecapacitance values, as described in the succeeding discussion.Fig. 2 shows the measured gatedrain capacitance values Cgd indc and pulsed bias conditions after applying dc stress voltages

Fig. 3. (a) Measured IdVds characteristics. (b) OFF-state leakage current ofa GaN-HFET.

Vst of 44 and 85 V. As shown in Fig. 2, the measured Cgdcharacteristics depend on the Vst.

The inserted graph in Fig. 2 is a comparison of the GaN-HFET and Si-MOSFET capacitance values measured in dcbias conditions. The measured Cgd of the GaN-HFETs wasone order of magnitude smaller than the Si device capacitance.A transistor switching speed is mainly restricted by a Millercapacitance Cgd. The low Cgd characteristic of the GaN-HFETindicates high switching-speed capabilities of the devices.

The other feature of GaN-HFETs is the drain-currentcharacteristics with short-channel effects. Fig. 3(a) showsthe measured IdVds characteristics of the GaN-HFET. Thesourcegate distance and the gate length are 1.2 and 0.8 m,respectively. The drain current is strongly depending on theVds unless in the saturation region. Unlike Si devices, gateregions of GaN-HFETs are generally fabricated on a nondopedor high-resistive GaN layer and not p-type, as illustrated inFig. 1(a). Therefore, conventional GaN-HFETs are vulnerableto punchthrough effects between the source and drain regions.These effects are particularly significant in GaN-HFETs witha short gate length [6]. In next-generation GaN power devices,some technologies to prevent short-channel effects could be-come important to minimize channel resistance. For example,Mg, Fe, and C doping techniques in a GaN epilayer under gateregions have been reported [7], [8]. These impurities act asshallow or deep acceptors and enhance carrier confinement atAlGaN/GaN interfaces. However, their effects to the currentcollapse and channel mobility are still not clear [9], [10]. Inaddition, insertion of an AlGaN layer under gate regions hasbeen proposed to the enhanced carrier confinement [11].

Fig. 3(b) shows an OFF-state drain leakage characteristicof the GaN-HFET measured by a curve tracer. Although theGaN-HFETs show the unsaturated IdVds characteristics in theON-state, the OFF-state leakage current was less than 0.1 mAand an OFF-state power loss can be negligible.


Fig. 4. Equivalent circuit of a dcdc converter (chopper) with key strayparameters.

To reflect the current collapse and short-channel effects inthe equivalent circuit model illustrated in Fig. 1(b), we haveextracted the model parameters of Cgs, Cgd, and Ich afterapplying a stress voltage Vst, which is corresponding to anOFF-state drainsource voltage in circuit simulations. In addi-tion, the unsaturated drain-current characteristics due to short-channel effects are taken into account in the current source Ich.

III. CIRCUIT SIMULATION METHOD

Original circuit simulation programs have been developed toevaluate power losses in converters using GaN-HFETs basedon the equivalent GaN device model described in the previoussection. The equivalent parameter values are individually tabu-lated and directly inputted into the circuit simulator as look-uptables.

In the developed simulator, loss calculation methods aresimplified and specialized for each converter circuit topologies.As an example, a loss calculation method in hard-switchingdcdc choppers is given as follows. Fig. 4 shows an equivalentcircuit of a dcdc chopper with key parasitic parameters; anequivalent resistance Rs1 and inductance Ls1 of the inputdecoupling capacitor, stray inductances (Ls2, Ls3 and Ls4) ofthe circuit board and semiconductor device packages, a straycapacitance Cs1 of the free-wheeling diode, stray capacitancevalues (Cs2, Cs3, and Cs4) of the main switch, and an internalresistance Rs2 of the gate driver.

The total circuit loss Ptotal is given by a sum of conductionlosses and switching losses, i.e.,

Ptotal = Pswitch + Pdiode + Pstray

+ f(Eon + Eo + Egate) (1)

where Pswitch, Pdiode, and Pstray are conduction losses of themain switch, the diode and the parasitic resistances, respec-tively; f is the switching frequency; and Eon, Eo , and Egateare the turn-on energy, the turn-off energy, and the gate-driveenergy of the main switch, respectively.

Fig. 5. Schematic switching waveforms of drain current id, drainsourcevoltage vds, and diode voltage vdi during (a) turn-on and (b) turn-off periods.

The conduction losses of Pswitch, Pdiode, and Pstray can bedirectly calculated from the resistances and the output currentIOUT by the Ohms law. An important challenge is accurateevaluation of the switching losses in a short computation time.Fig. 5 shows the schematic switching waveforms during theturn-on and turn-off periods. As illustrated in Fig. 5(a), the Eonis divided into two parts given by

Eon = Eon-t + Eon-r (2)

where Eon-t is a time-dependent turn-on energy during t = t1to t2, and Eon-r is a residual resonance energy after t = t2. Inthe developed simulator, switching waveforms are numericallycalculated only in t1t2 and t3t4 to minimize the calculationtime. From the calculated waveforms, the Eon-t is evaluated by

Eon-t =

t2t1

id(t) vds(t)dt. (3)

The Eon-r is the residual energy excessively absorbed by thediode capacitance Cdi and the stray parameters Cs1 and Ls. Itcan be analytically estimated by

Eon-r =

VINVdi2

(Cdi + Cs1)(VIN Vdi)dVdi

+12Ls(IOUT Id2)2 (4)


Fig. 6. Measured system.

where Vdi2 and Id2 are a diode voltage and a drain current att = t2. In a similar manner, the turn-off energy is calculated by

Eo = Eo-t + Eo-r (5)where Eo-t is the time-dependent turn-off energy, and Eo-ris the residual resonance energy. They are given by

Eo-t =

t4t3

id(t) vds(t)dt (6)

Eo-r =

VINVds4

(Coss + Cs2 + Cs3)VINdVds

+12LsI

2d4 (7)

where Vds4 and Id4 are a drain voltage and a drain current att = t4. Finally, the gate loss is evaluated using

Egate = |Vgh Vgl| Qgate (8)where Qgate is the gate charge, and Vgh and Vgl are the ON-state and the OFF-state output voltages of the gate driver,respectively.

IV. EXPERIMENTAL VERIFICATION

Switching losses of power converters using the GaN-HFETswere experimentally measured and compared with simulatedresults to verify accuracy of the equivalent circuit model andthe loss calculation methods. The device characteristics andthe gate-drive conditions are summarized in Table I. A circuittopology is the hard-switching dcdc chopper, as illustratedin Fig. 4. A SiC Schottky barrier diode was used as a free-wheeling diode. Fig. 6 shows a photograph of our experimentalsetup. The circuit parameters of the input voltage VIN, theoutput current IOUT, the external gate resistance Rg,ex, andthe stray inductance Ls2 are adjustable in the measurementsystem. In this paper, VIN was fixed at 40 V, and switchinglosses were measured by the changing of IOUT, Rg,ex, andLs2. The parasitic parameter values were measured using aLCR meter; Rs1 = 0.4 , Cs2 = 24 pF, Cs3 = 0.03 pF, andCs4 = 21 pF, which include the capacitance values of themeasurement probes. For the circuit simulation, the measuredparasitic parameters were directly inputted into the simulator.The parasitic parameters of Rs2, Cs1, and Ls3 could not bemeasured in our experimental system and are assumed as fittingparameters in the circuit simulations.

Fig. 7(a) shows the measured and simulated switching lossesat Ls2 = 40 nH and 140 nH with the changing output current

Fig. 7. (a) (Plots) Measured and (lines) simulated switching losses of GaN-HFETs with the changing output current values. (b) Switching loss comparisonbetween a GaN-HFET and a Si-MOSFET.

values from 0.5 to 4.0 A. As shown in Fig. 7(a), the measuredswitching losses are affected by the stray inductance values andEon-t and Eo-t became smaller and larger at the higher induc-tance of 140 nH, respectively. Fig. 7(b) shows the measured andsimulated switching losses with changing of the external gateresistance. As shown in Fig. 7(a) and (b), the simulated resultsbased on the equivalent GaN-HFET model and the calculationmethods well reproduce the measured results for the widecurrent and gate resistance ranges. The simulation accuracy wasmore than 93% in all the measured conditions.

The measured and simulated switching losses in a dcdcchopper with the Si-MOSFET are also plotted in Fig. 7(b). De-tail simulation methods of Si-MOSFETs have been previouslyreported [12]. Although the GaN-HFET shows six to eighttimes smaller switching losses than the Si-MOSFETs lossesin the same Rg,ex condition, the losses strongly depend on thedrive condition. These results imply that high-speed gate-drivetechnologies with low-output impedances are also important torealize ultralow loss converters using GaN devices.

V. OPTIMIZATION OF HIGH-FREQUENCY CONVERTER

Power converters using GaN-HFETs can be designed withstray parameters and drive condition effects by using the devel-oped simulator. As an example, in this final section, we haveevaluated the effects in a next-generation dcdc converter witha high-switching frequency of 10-MHz using a 600-V classGaN-HFET.

We have designed high-voltage GaN-HFETs virtually byusing a commercially available TCAD simulator and made


Fig. 8. (a) Schematic of a 600-V class GaN-HFET designed by TCADsimulations. (b) Extracted ON-state and (c) OFF-state IdVds characteristics.(d) Capacitance characteristics of the GaN-HFET by TCAD.

their equivalent circuit models. Fig. 8(a) shows a schematicstructure of a simulated GaN-HFET rated 600 V. The layerstructures consist with an undoped-Al0.2Ga0.8N layer, a

Fig. 9. (a) Simulated conversion efficiencies depending on current density bychanging a gate resistance. (b) Optimized values at the maximum efficiencies.Ls1 + Ls2 and Ls3 are assumed at 2 nH and 0 nH, respectively.

3-m-thick undoped GaN layer, and an AlN buffer layer on aconductive Si substrate. In this simulation, we have assumed noelectron traps in the devices. The physical parameters are as-sumed to be as follows: the impact ionization coefficient of GaNis 2.9 108 exp(3.4 107/E) [13], the polarization chargedensity is 1.1 1013cm2 at the AlGaN/GaN heterointerface[14], and the 2DEG mobility is the intrinsic bulk mobility of1400 cm2/V s [15].

Fig. 8(b) and (c) shows the extracted IdVds, the OFF-state breakdown, and the capacitance characteristics by TCADsimulations. The gatesource threshold voltage is 6 V, thebreakdown voltage is over 600 V, and the ON-resistance is50 m with a 0.8-mm2 chip size. The extracted values areinputted into the developed circuit simulator as an equivalentmodel of the GaN-HFET. Circuit simulations are performedin a hard drive dcdc chopper circuit illustrated in Fig. 4 atVIN = 300 V, Vgh = 0 V, Vgl = 10 V, and a duty ratio of0.5. In these calculations, to understand the effects of gate-driveconditions and stray inductances, we have assumed simplifiedcircuit conditions; a free-wheeling diode is an ideal diode with aconstant junction capacitance of 10 pF and the stray inductanceLs4 is zero, and the stray capacitance values (Cs1, Cs2, Cs3,and Cs4) and resistances (Rs1 and Rs2) are zero.

First, gate resistance effects to total circuit losses are sim-ulated at a low stray inductance condition with Ls1 + Ls2 =2 nH and Ls3 = 0 nH. Fig. 9(a) shows the simulated conver-sion efficiencies with changing current density (= IOUT/chip


Fig. 10. (a) Simulated switching loss. (b) Conversion efficiency. (c) Surgevoltage at Rg,ex = 1 and IOUT = 12 A.

size). There is an optimum current density to achieve themaximum efficiency depending on the external gate resistanceRg,ex. The evaluated maximum efficiencies and the optimumcurrent densities are plotted in Fig. 9(b). As shown in thisfigure, the conversion efficiency and optimized current densitystrongly depend on the gate resistance. When Rg,ex was lessthan 1 , high conversion efficiencies more than 98% wereestimated. At Rg,ex = 1 , the optimum current density was1630 A/cm2(IOUT = 12 A). In this condition, the peak gatecurrent of (Vgh Vgl)/Rg,ex reaches to 10 A, which is com-parable with the output current of 12 A in the main circuit.In addition, an evaluated heat density in the GaN device chipwas 3390 W/cm2, which is one order of magnitude higher thanthat of conventional Si-IGBTs. In real applications, a current

rating and short-circuit capability of semiconductor devices arelimited by an allowable chip temperature. The simulated resultsindicate that novel heat-dissipation technologies with a lowthermal impedance are required to realize such high-efficiencypower converters using GaN devices.

Then, stray inductance effects are evaluated at the optimizedcondition of Rg,ex = 1 and IOUT = 12 A. Fig. 10(a) showsthe simulated total switching energy Esw, which is a sum ofEon, Eo , and Egate. As shown in this figure, Esw is undulateddepending on the stray inductance values due to interactionsbetween the devices and the stray inductances. In particular,the common source inductance Ls3 significantly effects to thetotal switching loss. Only a small Ls3 of 0.5 nH increased theswitching loss in four times than that in the ideal condition atLs3 = 0 nH. As a result, total conversion efficiencies shown inFig. 10(b) are significantly depending on the stray inductanceLs3. Although the switching loop inductance Ls1 + Ls2 haslittle effect to Esw, the surge voltage Vsrg to the GaN-HFETduring turn-off is increased depending on the switching loopinductance, as shown in Fig. 10(c). In the simulated condition,the surge voltage reached the voltage rating of 600 V at Ls1 +Ls2 = 15 nH.

VI. SUMMARY

We have developed the circuit simulator specialized to eval-uate power losses of high-frequency power converters usingGaN-HFETs. The developed simulator is based on the high-accuracy equivalent model of GaN-HFETs and the parameterextraction methods reflecting the current collapse and short-channel effects. In addition, novel loss calculation methodsare proposed for high-speed loss evaluation. The calculatedlosses of the developed simulator well reproduced the measuredresults in the dcdc converters using the commercially availableGaN-HFETs rated 180 V in more than 93% accuracy.

The 10-MHz dcdc converter using the 600-V class GaN-HFET is designed by utilizing the developed simulator. Theseresults indicate that high-power and high-speed gate driv-ing, stray inductances reduction, and advanced heat-dissipationtechnologies beyond conventional technologies are required forrealization of next-generation converters using GaN devices.

ACKNOWLEDGMENT

The authors would like to thank Dr. M. Shimizu andK. Owada of the National Institute of Advanced IndustrialScience and Technology for the fruitful discussions.

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[6] M. J. Uren, K. J. Nash, R. S. Balmer, T. Martin, E. Morvan, N. Caillas,S. L. Delage, D. Ducatteau, B. Grimbert, and J. C. De Jaeger,Punchthrough in short-channel AlGaN/GaN HFETs, IEEE Trans.Electron Devices, vol. 53, no. 2, pp. 395398, Feb. 2006.

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Akira Nakajima received the Ph.D. degree in elec-tronics from Toyohashi University of Technology,Japan, in 2004.

He is with the Energy Technology Research Insti-tute, National Institute of Advanced Industrial Sci-ence and Technology, Japan.

Kazuto Takao received the Ph.D. degree in energyscience from Toyama University, Toyama, Japan,in 2002.

He is currently with the Electron Devices Labora-tory, Corporate Research and Development Center,Toshiba Corporation, Kawasaki, Japan.

Hiromichi Ohashi (LM12) received the Ph.D. de-gree in electronics from Tohoku University, Sendai,Japan.

He is with the Energy Technology Research Insti-tute, National Institute of Advanced Industrial Sci-ence and Technology, Tsukuba, Japan.

/ColorImageDict > /JPEG2000ColorACSImageDict > /JPEG2000ColorImageDict > /AntiAliasGrayImages false /CropGrayImages true /GrayImageMinResolution 300 /GrayImageMinResolutionPolicy /OK /DownsampleGrayImages true /GrayImageDownsampleType /Bicubic /GrayImageResolution 300 /GrayImageDepth -1 /GrayImageMinDownsampleDepth 2 /GrayImageDownsampleThreshold 1.50000 /EncodeGrayImages true /GrayImageFilter /DCTEncode /AutoFilterGrayImages false /GrayImageAutoFilterStrategy /JPEG /GrayACSImageDict > /GrayImageDict > /JPEG2000GrayACSImageDict > /JPEG2000GrayImageDict > /AntiAliasMonoImages false /CropMonoImages true /MonoImageMinResolution 1200 /MonoImageMinResolutionPolicy /OK /DownsampleMonoImages true /MonoImageDownsampleType /Bicubic /MonoImageResolution 600 /MonoImageDepth -1 /MonoImageDownsampleThreshold 1.50000 /EncodeMonoImages true /MonoImageFilter /CCITTFaxEncode /MonoImageDict > /AllowPSXObjects false /CheckCompliance [ /None ] /PDFX1aCheck false /PDFX3Check false /PDFXCompliantPDFOnly false /PDFXNoTrimBoxError true /PDFXTrimBoxToMediaBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXSetBleedBoxToMediaBox true /PDFXBleedBoxToTrimBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXOutputIntentProfile (None) /PDFXOutputConditionIdentifier () /PDFXOutputCondition () /PDFXRegistryName () /PDFXTrapped /False

/Description > /Namespace [ (Adobe) (Common) (1.0) ] /OtherNamespaces [ > /FormElements false /GenerateStructure false /IncludeBookmarks false /IncludeHyperlinks false /IncludeInteractive false /IncludeLayers false /IncludeProfiles false /MultimediaHandling /UseObjectSettings /Namespace [ (Adobe) (CreativeSuite) (2.0) ] /PDFXOutputIntentProfileSelector /DocumentCMYK /PreserveEditing true /UntaggedCMYKHandling /LeaveUntagged /UntaggedRGBHandling /UseDocumentProfile /UseDocumentBleed false >> ]>> setdistillerparams> setpagedevice

[sic-en-2013-16] gan power transistor modeling for high-speed converter circuit design

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