[sic-en-2013-18] self-powered gate driver for normally on silicon carbide junction field-effect...

1488 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 3, MARCH 2013

Self-Powered Gate Driver for Normally ON SiliconCarbide Junction Field-Effect Transistors Without

External Power SupplyDimosthenis Peftitsis, Student Member, IEEE, Jacek Rabkowski, Member, IEEE,

and Hans-Peter Nee, Senior Member, IEEE

AbstractThe very low on-state resistance, the voltage-controlled gate, and the relative simplicity of fabrication of thenormally ON silicon carbide junction field-effect transistor (JFET)make this device the most important player among all state-of-the-art silicon carbide transistors. However, the normally ON naturecounts as the main factor which keeps this device far from beingconsidered as an alternative to the silicon insulated-gate bipolartransistor. A self-powered gate driver without external power sup-ply for normally ON silicon carbide JFETs is presented in this pa-per. The proposed circuit is able to handle the short-circuit currentswhen the devices are subjected to the dc-link voltage by utilizing theenergy associated with this current. On the other hand, it suppliesthe necessary negative gate-source voltage during the steady-stateoperation. A detailed description of the operating states in conjunc-tion with a theoretical analysis of the proposed self-powered gatedriver is presented. The first part of the experimental investigationhas been performed when the proposed circuit is connected to a de-vice which is directly subjected to the dc-link voltage. The secondset of measurements were recorded when the self-powered gate-driver was employed as the driver of normally ON components ina half-bridge converter. From the experimental results, it is shownthat the short-circuit current is cleared within approximately 20 safter the dc-link voltage is applied, while the power consumptionwhen all devices are kept in the OFF state equals 0.37 W. More-over, it is experimentally shown that the proposed gate driver canproperly switch when it is employed in a half-bridge converter.Finally, limitations regarding the range of the applications wherethe self-powered gate drive can efficiently operate are also dis-cussed.

Index TermsGate-driver power supply, normally ON siliconcarbide (SiC) junction field-effect transistors (JFETs), protectioncircuit, silicon carbide.

I. INTRODUCTION

DURING recent years, several types of power transis-tors in silicon carbide (SiC) have been introduced onthe market [1], [2]. The only type that can be driven froma standard driver for silicon insulated-gate bipolar transistorsis the SiC metaloxide silicon field-effect transistor (MOS-FET) [3]. This device, however, is far more complicated to

Manuscript received May 19, 2012; revised July 3, 2012; accepted July 12,2012. Date of current version October 12, 2012. Recommended for publicationby Associate Editor Y. C. Liang.

The authors are with the Electrical Energy Conversion (E2C) Lab, School ofElectrical Engineering, KTH Royal Institute of Technology, SE-10044 Stock-holm, Sweden (e-mail: [email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2012.2209185

fabricate [4] than SiC junction field-effect transistors (JFETs)or SiC bipolar junction transistors (BJTs) [5] because the SiCMOSFET requires a gate-oxide layer as the silicon counterpart.There are mainly two problems associated with this gate-oxidelayer in SiC MOSFETs. First, the oxide itself may not have asufficient long-term reliability [6][8], especially at high tem-peratures. The second problem is found directly beneath thegate oxide. The mobility in the channel is more than one orderof magnitude lower than what could be expected [4], [9][11],which causes a substantial increase in the on-state resistance(at least for 12001700 V devices). Even if the values of thechannel mobility have increased over the years, the SiC MOS-FET still cannot compete with JFETs and BJTs in SiC in termsof on-state resistance [12], but in the future high-voltage SiCMOSFETs may become very competitive [13]. SiC BJTs, onthe other hand, require a considerable base current as long asthe BJT is in the ON state [14]. With current gains of approxi-mately 85 [15], the base driver must provide more power thangate drivers of SiC MOSFETS or JFETs. The other drawbackof SiC BJTs is that the BJT cannot conduct in the reverse direc-tion. It may seem strange that this is put against the SiC BJT.However, if an antiparallel or free-wheeling diode in SiC is em-ployed, the voltage drop of this diode is significantly higher thanthat of a silicon diode, and up ten times higher than the on-statevoltage of a SiC JFET, depending on the choice of current den-sity in the JFET. The SiC JFET, however, can conduct in thereverse direction [16], [17] and has no gate-oxide layer. JFETscan be designed as enhancement-mode normally OFF [18][21]JFETs or depletion-mode normally ON JFETs [18][21]. Somesemiconductor structures such as the vertical trench JFET canbe designed to be either normally ON or normally OFF simplyby changing the doping level of the channel region [22], [23].Especially, in this context it becomes clear that a normally ONJFET will have a lower on-state resistance [24]. Another draw-back of the normally OFF JFET is that the gate-source junctionhas to be forward biased in order to turn the JFET ON. Thisimplies a considerable gate current [25], almost as high as thebase current of the SiC BJT. In the opinion of the authors, thenormally ON JFET is, therefore, preferable if the normally ONproblem can be accepted [26]. This is a problem that has to behandled on the system level in such a way that a sufficient relia-bility can be ensured. This may involve several safety systems,of which some would be used also for normally OFF transistors.A vital unit in such a safety system is an automatic power-upgate driver without the need for external power sources. Such a

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PEFTITSIS et al.: SELF-POWERED GATE DRIVER FOR NORMALLY ON SILICON CARBIDE JUNCTION FIELD-EFFECT TRANSISTORS 1489

gate driver should be able to handle the short circuit caused bythe normally ON JFETs at start-up and bring them to a stableOFF state. Additionally, it should be capable of driving the JFETduring normal operating conditions taking the power from themain circuit.

In the literature, five suggestions for solutions to the nor-mally ON problem have been presented. The first [27], [28]is based on a cascode connection with a low-voltage siliconMOSFET. The solution is promising because the cascode con-nection makes the switch to behave as a normally OFF de-vice. However, this is achieved at the cost of three drawbacks.First, the series-connected silicon MOSFET will add voltagedrop [29]. Second, the two devices of the cascode connec-tion must be matched in order to cooperate successfully. Suchmatches are usually cost driving. Finally, by introducing a sili-con device, operation at high temperatures is prohibited. This is asevere shortcoming of the cascode concept as high-temperatureoperation is one of the most important benefits of SiC technol-ogy [30][36]. To conclude, it is the opinion of the authors thatthis is a temporary solution until better alternatives appear. Thesecond solution which has been presented in the literature dealswith handling both the start-up and gate-driver power failures ofnormally ON SiC JFETs employed in a voltage source converter(VSC) [37], [38]. An auxiliary normally ON JFET is used asa linear regulator and it is connected to the input of the VSC.Under either the start-up process or a gate-driver failure, theprotection scheme is activated, and by employing an ultrafastconverter a negative voltage is supplied to the gates of the lowerSiC JFETs of the VSC. Even though the short-circuit currentsare handled in a very short time (approximately 100 s), thegate drivers of the SiC JFETs still require an external powersupply for the steady-state operation. Moreover, the protectionscheme is only employed on the low-side JFETs. Thus, theupper JFETs operate without any protection scheme. A protec-tion circuit against gate-driver failures has also been presentedin [39]. It is able to handle the short-circuit current within a fewmicroseconds, but the external power supply which is requiredcounts as a basic drawback of this solution. A shoot-throughprotection scheme for VSCs with normally ON SiC JFETs hasalso been shown in [40]. It basically consists of a Si insulatedgate bipolar transistor (IGBT) in series connection with a relaywhile both are connected in parallel with a charging resistor.This protection scheme is employed in the mid-point betweenthe dc-link capacitors and it is able to clear any short circuits ina very short time. Nevertheless, an external power supply for thegate drivers of the SiC JFETs is also needed in this case. Under ashort-circuit case on a phase-leg of the VSC, the fault is detectedand a high impedance path is created due to the charging resistor.Thus, the short-circuit current dissipates power in this resistor.A successful example of a protection circuit for normally ONSiC JFETs employed in a switch-mode power supply (SMPS)fed by the grid has been presented in [41]. The proposed circuitutilizes the inrush current during the start-up process in order toturn OFF the JFET. It must be noted that this circuit ensures asafe operation of the JFET either if the sinusoidal input voltagestarts at zero or at any other value when the SMPS is connectedto the grid. As most of the previous ideas described previously,

this protection scheme also requires an external power supplyfor the gate driver of the SiC JFET under steady-state operation.

In this paper, a self-powered gate driver (SPGD) for normallyON SiC JFETs without the need for an external power supplyis presented. The proposed circuit is able not only to handle thestart-up process of the normally ON SiC JFET, but also to prop-erly supply the gate during steady-state operation. A modifieddc/dc forward converter is used in order to handle the start-upprocess, while the gate power during steady-state operation isprovided by a dc/dc flyback converter. The (start-up) forwardconverter basically utilizes the JFET voltage drop caused by awell-defined shoot-through current and supplies a negative gate-source voltage which turns the JFET OFF. The shoot-throughcurrent is determined by a start-up resistor, in the same way as inmany commercial products. During normal operation, the highblocking voltage across the JFET is converted to a negative lowvoltage which continuously supplies the gate driver by means ofa flyback converter. A detailed analysis of the proposed circuitis provided in Section II. The experimental investigation of theSPGD has been performed using two different test circuits aspresented in Section III. A discussion on the design limitationsof the proposed idea is given in Section IV, while Section Vsummarizes the main conclusions of this paper.

II. SELF-POWERED GATE-DRIVER CONCEPTThere are basically two design requirements that must be

taken into account when a smart gate driver for normallyON SiC JFETs is designed. On the one hand, a solution tothe normally ON problem must be provided in order to stopthe shoot-through current which might thermally destroy thedevice. On the other hand, a power supply to the gate-driveunit must also be provided in order to enable stable steady-stateswitch-mode operation of the device. These two main issueshave been considered during the design steps of the proposedSPGD for normally on SiC JFETs. A brief description of theSPGD concept is presented next, while a more detailed analysisis also shown in Section II-B.

A. SPGD ConceptThe proposed SPGD includes two switch-mode converters as

shown in the block diagram in Fig. 1. The input stage of bothconverters is in parallel connection with the main SiC JFET,Jm . In order to analyze the sequence of the operation of the twoconverters, the output capacitors C1 and C2 are also depictedin Fig. 1. In particular, a capacitor is connected at the output ofeach converter. The start-up converter only operates during thestart-up process of the SiC JFET, and by utilizing a well-definedshort-circuit current flowing through the device, it generates anegative gate-source voltage Vsu which appears across C1 . Thisvoltage must be more negative than the pinch-off voltage of theSiC JFET in order to turn OFF the normally ON SiC JFET. Thus,the short circuit is turned OFF and the drain-source voltage ofthe JFET equals the blocking voltage, which is determined bythe circuit parameters (e.g., in the case of a half-bridge inverterthe blocking voltage equals half of the dc-link voltage, etc). Ascan be seen from Fig. 1 the start-up converter only supplies the


Fig. 1. Block diagram of the proposed self-powered gate driver for normallyON SiC JFETs.

integrated-circuit driver (IC driver) and not the optocoupler dueto the diode D3 . This practically means that the optocoupleris disconnected from the circuit, and thus, the input signal tothe IC driver is in the low state. Consequently, the output ofthe IC driver is equal to the low voltage state, which in thiscase is the negative voltage supplied by the start-up converter.The steady-state converter, on the other hand, converts the highblocking voltage to a low voltage, Vss , which supplies both theIC driver and the optocoupler. This converter is able to startoperating as soon as the drain-source voltage of Jm , Vdsm , ishigh, or practically when Vds exceeds a certain voltage limit.During the steady-state operation of the steady-state converter,the capacitor C2 is continuously charged to a certain voltagelevel determined by the duty-ratio controller of M1 . Hence, theSiC JFET Jm can be properly driven by providing appropriatecontrol signals to the input of the optocoupler. A sufficientlylarge capacitance value for C2 is required in order to ensure thatthe output voltage Vss will be kept approximately constant.

B. Operating States of the SPGDAs described previously, there are basically two operating

states of the proposed SPGD: the start-up and the steady-stateones. It is worth to mention that it is the combination of these twostates which is required in order to eliminate the short-circuitcurrent and properly switch the device. Fig. 2 shows a detailedschematic of the SPGD where all the vital components are de-picted. The RpmCgm Rg network has shown to be successfulin providing fast switchings, noise immunity, and the possibilityto parallel-connect several SiC JFETs [42], [43].

The start-up converter, which is a forward converter with-out a freewheeling diode, is illustrated with the bold lines inFig. 3(a). It consists of a normally ON SiC JFET, Jaux , a high-frequency current transformer with very high turns ratio T/F1 ,a low-voltage diode D1 , and a capacitor C1 . This converter isconnected across the main SiC JFET. On the contrary, the steady-state converter is a high-to-low voltage flyback converter as indi-cated with the bold lines in Fig. 3(b). As the start-up converter, itis also connected across the main SiC JFET, or in other words inparallel with Jm . The vital components of the steady-state con-verter are the high-frequency transformer T/F2 , the diode D2 ,

Fig. 2. Detailed schematic of the SPGD.

Fig. 3. Identification of (a) start-up and (b) steady-state converters of theself-powered gate driver.


Fig. 4. Detailed circuit schematic of the MOSFET with the integrated controller.

and the output capacitor C2 . A silicon MOSFET, M1 , with an in-tegrated controller is employed as the main switch for the steady-state converter. It must be noted that this integrated switch isable to operate when the drain-source voltage of the MOS-FET exceeds a certain value as this is determined by the man-ufacturer. Once the drain-source voltage across the MOSFETexceeds this certain limit, the integrated controller is enabledand no external duty-ratio controller is required. A detailedfunctional block diagram of the MOSFET with the integratedcontroller, as released by the manufacturer, is shown in Fig. 4.It basically consists of an n-type MOSFET, which is integratedwith a dedicated control circuit. The control circuit is mainlydenoted with blocks in conjunction with several logic gates inFig. 4. In this figure, the DRAIN (D) and the SOURCE (S) con-nections are shown, while two additional connection points arealso illustrated. The ENABLE/UNDERVOLTAGE pin enablesand controls the switching process of the MOSFET. It is alsoable to terminate the switching process if a current greater thana threshold current is drawn from this pin. An external capacitoris connected to the BYPASS/MULTIFUNCTION pin in orderto keep the internally generated voltage of 5.85 V constant. De-pending on this capacitor value, the threshold current which hasbeen mentioned previously can also be set to a certain value.The connectivity of this MOSFET in a flyback converter withthe integrated controller is shown in detail in Section III-A.

In Fig. 3 the IC driver and the optocoupler are also depicted.Diode D3 is connected in such a way that even though theIC driver is supplied both from the start-up and the steady-state converters, the optocoupler is only supplied by the steady-state one. The reason for this is that during the start-up processthe optocoupler is not utilized, and hence it does not require apower supplied. On the contrary, under the normal operation ofthe SPGD, the optocoupler, which optically isolates the signals

from the microprocessor from the SPGD, is supplied by thesteady-state converter.

The detailed circuit schematics of the optocoupler and theIC driver are depicted in Figs. 5 and 6, respectively. Both theoptocoupler and the IC driver are basically totem poles employ-ing MOSFETs. The only difference is that the optocoupler isoptically isolated as shown in Fig. 5, where the input stage con-sists of a light-emitting diode and an integrated photodetectorwhich do not require any external power supply. Thus, the mi-croprocessor signals are isolated from the main circuit. On thecontrary, the input of the IC driver is not isolated with respectto the output. However, the IC driver is able to supply highoutput currents (in the range of few tens of amperes) which areneeded if fast switching speeds are required. It is clear that bothcomponents are necessary to obtain a stable system operationwith very fast switching speeds. In order to clarify the way thatthe negative supply voltage Vss and the reference ground areconnected to the optocoupler and the IC driver, these two pointsare also denoted in Figs. 5 and 6. Thus, in conjunction withFig. 1 and with Figs. 25, the ground point (drawn with a smallup-side down triangle) and the point where the supply voltageVss is connected are the same for all these figures.

Figs. 79 show the three main operating states of the SPGD. Inthese figures, the parallel networks of the resistor and the speed-up capacitor (Rpm , Cgm and Rp aux , Cg aux ) which are connectedto the gates of the SiC JFETs are also shown. Assuming thatthe main normally on SiC JFET Jm is connected to a directvoltage source Vdc as shown in Fig. 7, the short-circuit currentis flowing both through Jm and Jaux (bold lines in Fig. 7).Both of these SiC JFETs are normally ON devices and it isobvious that without any negative gate-source voltage supplythey are kept in the ON state. The steady-state converter isinactive during this state, because the MOSFET M1 with the


Fig. 5. Detailed circuit schematic of the optocoupler.

Fig. 6. Detailed circuit schematic of the IC driver.

Fig. 7. Short-circuit current paths during the start-up process of Jm .

integrated control circuit requires a certain voltage across it inorder to start operating.

A detailed schematic showing the components which are in-volved in the operation of the start-up converter is depicted inFig. 8 with bold lines. The transformer T/F1 , the diode D1 , andthe capacitor C1 are involved in this state. The short-circuit cur-rents IJm and IJ aux flowing through the main and the auxiliarySiC JFETs, respectively, are also indicated with small arrows inFig. 8. A very low voltage drop across the primary winding ofT/F1 and Jaux is caused due to IJ aux . Considering that the turns

Fig. 8. Operating state of the start-up converter.

Fig. 9. Start-up sequence of the SPGD.

ratio of T/F1 is very high (e.g., 1:100 or higher), the voltagewhich appears across the secondary winding is also expectedto be high. The diode D1 is forward biased and hence the ca-pacitor C1 is charged up to a certain voltage level which equalsthe voltage across the secondary winding of T/F1 . The IC driveris directly supplied from the output of the start-up converter,Vsu , while the same voltage is directly supplied to the gate ofthe auxiliary SiC JFET Jaux . As has been already mentioned


Fig. 10. Operating state of the steady-state converter.

earlier, the input signal to the IC driver is low, and the output ofthe driver also equals its low-input voltage. As a consequence,Jm is turned OFF, as soon as the absolute value of Vsu exceedsthe absolute value of the pinch-off voltage of Jm . Similarly tothis, Jaux is also turned OFF when Vsu becomes less negativethan its pinch-off voltage. It is, therefore, obvious that the drain-source voltage across Jm and Jaux equals the direct voltage Vdc .Even though the optocoupler is disconnected in this operatingstate, the input signal to it is kept in the low state. Thus, whenthe optocoupler is supplied by the steady-state converter, theSiC JFETs will continue to be in the OFF state. A schematic ofthe theoretical performance of the SPGD is shown in Fig. 9. As-suming that the direct voltage is applied across Jm at t1 , the firstand third traces of Fig. 9 show the short-circuit currents throughJm and Jaux , respectively. From the third trace of Fig. 6(a), alower slope of IJ aux is observed due to the series connectionof the primary winding of T/F1 with Jaux . The fourth and fifthtraces of Fig. 9 depict the output voltages of the start-up andsteady-state converters, respectively. A certain time is requiredin order to magnetize the transformer T/F1 and thus the outputvoltage Vsu across C1 starts to appear at t2 . The short-circuitcurrent IJm is turned OFF at t3 , when Vsu equals the pinch-offvoltage of the main SiC JFET Jm . If it is assumed that the twoSiC JFETs have different pinch-off voltages, especially Jaux hasa less negative one, it is turned OFF at t4 as shown in Fig. 9. Fi-nally, at t5 , the drain-source voltage of Jm equals the dc voltageVdc .

As soon as the drain-source voltage of Jm equals the directvoltage Vdc , the steady-state converter is able to operate andconstantly supply a negative output voltage Vss . Even though thevoltage across the MOSFET M1 with the integrated controlleris higher than the limit voltage which allows it to operate, adelay time might occur. This delay time might be caused bythe soft-starting feature of M1 . The steady-state converter startssupplying the output voltage at t6 , while the final value of Vss isreached at t7 . It is upon the design requirements of the specificapplication to decide about the value of Vss . A circuit schematic

of the steady-state converter operation is shown in Fig. 10 withbold lines. As already mentioned, the steady-state converter isbasically a low-power flyback converter. When the steady-stateconverter operates, the output voltage of the start-up converterVsu starts increasing to zero at t6 while Vsu equals 0 V at t8as shown in the fourth trace of Fig. 9. Moreover, diode D3 isalso forward biased in this case and both the IC driver and theoptocoupler are supplied by Vss . The auxiliary SiC JFET Jaux isstill kept in the OFF state, while the main SiC JFET Jm is nowable to switch. It can be seen from Fig. 9 that the main JFETstarts switching at t9 . The last trace of this figure shows thegate-source voltage of Jm , while the corresponding switchingcurves for the JFET current and the drain-source voltage arepresented in the first and second traces, respectively.

Considering the analysis presented so far, it is clear that theproposed SPGD is able to operate as a protection circuit againstthe shoot-through currents, on the one hand, while on the otherhand it is employed as a normal power supply for the gate-drive unit. Moreover, it is worth to mention that the choiceof the SPGD parameters must be made with care in order toensure a reliable and stable operation. A detailed analysis of theparameter choices is presented in the next section.

III. EXPERIMENTAL RESULTS

In order to experimentally investigate the performance of theSPGD, two sets of measurements were performed. The first setof measurements deals with the stand-alone investigation of theSPGD, while the second one has been done when the SPGDis employed in a half-bridge converter. However, Section III-Ashows the choice of the SPGD parameters, which are crucial forthe reliable operation.

The SiC JFETs which have been used for the experimen-tal verification of the SPGD are the so-called depletion-modevertical-trench JFETs (DMVTJFET). A graphical illustration ofthe cross-section of this device is shown in Fig. 11. Samples ofthis certain design rated at 1200 V and 27 A are commerciallyavailable and they have been considered in the current investi-gation. The pinch-off voltage of this SiC JFET equals approx-imately 6 V, while the reverse breakdown voltage of the gateis in the range from 19 to 28 V. Typical transfer characteris-tics of this device which were measured at various gate-sourcevoltages are illustrated in Fig. 12. Finally, it is worth to men-tion that compared to other JFET designs the DMVTJFET hasno antiparallel body diode, but there is still the possibility forreverse current flow through the channel.

A. Choice of the SPGD ParametersIn order to make the operation of the SPGD reliable and sta-

ble, a special effort on selecting various design parameters mustbe made. Especially, the start-up converter must be designedwith care. Without the start-up converter, the short-circuit cur-rents cannot be turned OFF, and thus, the steady-state converteris also not able to operate. The start-up converter must be able toturn OFF both the main and auxiliary JFETs for a certain timeuntil the steady-state converter starts. This practically meansthat a certain amount of energy must be supplied by the start-up


Fig. 11. Graphical illustration of the cross section of the depletion-modevertical trench JFET.

Fig. 12. Static transfer characteristics at various gate-source voltages for theSiC DMVTJFET.

converter to the gates of Jm and Jaux . The presented analysisis based on the simplified circuit schematic of the start-up con-verter shown in Fig. 13. The on-state resistances of the main andauxiliary JFETs rJm and rJ aux , respectively, are also shown inthis figure with the dashed lines. Moreover, the resistance of theprimary winding of the transformer rL 1 is also shown.

Assume that the on-state resistances of Jm and Jaux are equal.(In the future, Jm would be a large device while Jaux wouldbe a small device.) It is obvious that the total resistance of theprimary winding of the transformer and Jaux is higher thanrJm . It is, therefore, clear that IJm which is flowing throughJm is slightly higher than IJ aux . Hence, the voltage drop acrossthe primary winding of T/F1 equals the difference between thevoltage drop across Jm and the voltage across Jaux . Keeping inmind that typical values of the on-state resistance of the JFETsare in the range of few tens of millohms, and that the short-

Fig. 13. Detailed schematic of the start-up converter.

circuit currents must be kept as low as possible, the voltagedrop across L1 is also low. Consequently, in order to obtainan adequate output voltage, Vsu which turns OFF the JFETsproperly, a very high turns-ratio value for T/F1 is required. Theadequate output voltage Vsu corresponds to a value which isless negative than the pinch-off voltage of the JFETs, and thus, itis adequate to turn OFF both Jm and Jaux . If, on the other hand,the turns-ratio value is low, a significantly higher short-circuitcurrent is needed in order to supply a certain output voltage.

As already mentioned previously, the steady-state converterrequires a certain time in order to start operating. During thistime delay, the start-up converter must be able to supply a certainamount of energy to the gate-source junctions of Jm and Jauxin order to keep them in the OFF state. If L1 is the inductanceof the primary winding of T/F1 and IJ aux is the short-circuitcurrent flowing through Jm , the stored energy in the transformeris given by

EL1 =12 L1 I2J aux . (1)

Similarly, if C1 is the output capacitor and Vsu is the outputvoltage, the total stored energy in this capacitor is given by

EC =12 C1 V 2su . (2)

Assuming that there are no losses in the converter, EL 1must be equal to EC and thus a relationship between the out-put voltage Vsu and the short-circuit current IJ aux is obtained.Accordingly,

Vsu =

L1C1

IJ aux . (3)

A graphical presentation of (3) is shown in Fig. 14. Thisfigure actually shows the variation of the output voltage Vsu ofthe start-up converter with respect to the value of the outputcapacitor C1 for various short-circuit currents IJ aux .

The gate capacitance Cg of the SiC JFETs is also shownwith dashed lines in Fig. 13. In order to turn OFF the JFET acertain amount of energy is required to be stored in the gatecapacitance. There is a minimum required value for this energy


Fig. 14. Output voltage of the start-up converter for various output capacitorsand short-circuit currents.

TABLE IPARAMETERS OF THE START-UP CONVERTER

which is given by

Eg,min =Qg Vpi

2(4)

where Qg is the total charge of the gate capacitance and Vpi isthe pinch-off voltage of the JFET. Even though the pinch-offvoltage is the gate-source voltage at which the turn-off processof the JFET starts, a more negative gate source is required inorder to properly turn OFF the device. Taking into accountthis fact, and in conjunction with Fig. 14, it is clear that thechoice of the output capacitor C1 must be made with care sothat, on the one hand, an adequately negative voltage Vsu issupplied to the gates of Jm and Jaux , and that, on the otherhand, the start-up converter is able to supply a certain amount ofenergy for a certain duration. This amount must be significantlyhigher than Eg,min , while the short-circuit current IJ aux mustbe kept between reasonable limits. If this current is too high, itmight cause thermal destruction of the device without letting theSPGD to start operating. An additional reason to why Ec mustbe significantly higher than Eg,min is that losses caused in thegate-source junction as such, but also in the gate circuit must betaken into consideration. Table I summarizes the parameters ofthe start-up converter.

Taking into account the analysis of the start-up parameters sofar and considering the results shown in Fig. 14, the capacitancevalue of C1 can be chosen assuming a certain shoot-throughcurrent IJ aux and a certain turns-ratio of T/F1 . In order to avoidany thermal destruction of the JFETs, IJ aux has been chosen tobe equal to approximately 15 A. This practically means that the

shoot-through current which flows through Jaux equals approx-imately half the rated current of the component. Thus, Jaux iskept far from its thermal limits. In a similar way, the current flow-ing through Jm also equals half the rated current. Consideringthat the typical value for the pinch-off voltage of this particularJFET design equals 6 V, and taking into account Fig. 14, avalue of 100 nF has been chosen for C1 . Consequently, the out-put voltage Vsu of the start-up converter equals approximately9 V, which is an adequate voltage to turn OFF the JFETs. Ascan be seen from Fig. 14, there are basically several combina-tions of C1 and Ijaux which result in a certain output voltageVsu . However, as already mentioned, the energy which is storedin C1 must be adequate in order to compensate for the lossescaused in the gate-source junction as such, but also in the exter-nal gate circuit. Due to the difficulties in measuring these verylow power losses in the gate, experiments using various valuesof C1were performed in order to choose the best-performingvalue of the output capacitor.

If Ijaux had been chosen to be equal to 5 A and assumingthe same turns ratio of T/F1 , then as it is clear from Fig. 14the output voltage Vsu of the start-up converter would not beadequate in order to turn OFF both SiC JFETs and at the sametime supply an adequate energy to the devices. Finally, it mustbe noted that Ijaux can be set at a certain value by properlyadjusting the start-up resistor, Rstart-up .

As for the start-up converter, an investigation concerning thechoice of the parameters of the steady-state converter has beenperformed. The steady-state converter has been designed as-suming an input voltage of Vdc = 500V and an output voltageequals Vss = 30V. A detailed schematic of the steady-stateconverter, which is a flyback converter from 500 to 30 V isshown in Fig. 15. A silicon MOSFET with an integrated con-troller is employed as the main switch of this flyback converteras already mentioned in Section II. Apart from the drain (D)and the source (S) connections of the MOSFET (see Fig. 15),there are also two more input ports (EN and BP as they arecalled by the manufacturer). The first input EN is used in orderto sense the output voltage, and thus, the duty ratio is properlycontrolled. In particular, the output voltage of the converter issensed by means of an optically controlled transistor Tph and azener diode Dz . When the output voltage Vss exceeds the zenervoltage of Dz , Tph is turned ON and thus an input signal to ENis sent. Hence, the switching cycles of M1 are overlapped untilthe output voltage Vss becomes lower than the zener voltage ofDz . On the other hand, a capacitor C3 is connected to the inputport BP, which is responsible for stabilizing the auxiliary volt-age in the integrated switch. The parameters of the steady-stateconverter are shown in Table II.

B. Stand-Alone InvestigationThe SPGD has been experimentally tested when it is em-

ployed as the gate driver of a single SiC JFET which is directlyconnected to a direct voltage. A picture of the SPGD prototypeis illustrated in Fig. 16. Fig. 17 illustrates a schematic of thetest circuit for the stand-alone operation. A 1200 V/55 A IGBTin conjunction with a start-up resistor Rstart-up was employed


Fig. 15. Detailed schematic of the steady-state converter.

TABLE IIPARAMETERS OF THE STEADY-STATE CONVERTER

in order to emulate the start-up process as shown in Fig. 13.The start-up resistor has been selected in such a way that theshoot-through current will be limited, while the IGBT emulatesthe operation of a circuit breaker (or a relay). The IGBT is con-trolled using a special control circuit, which turns the IGBT ONfor a certain time period and thus, the short-circuit current startsflowing through the main SiC JFET Jm . The SPGD also startsoperating as described previously. The reason for that a specialstart-up circuit (IGBT and start-up resistor) is employed is toemulate a standard start-up circuit containing an inrush-currentlimiting start-up resistor (which is short-circuited during nor-mal operation). Table III summarizes the parameters of the testcircuit for stand-alone operation.

Figs. 1821 show various measured quantities during thestart-up process. In particular, Fig. 18 illustrates the shoot-through current (light-pink color) which is turned OFF in ap-proximately 20 s after the start-up process starts. This current

Fig. 16. Experimental circuit prototype of the SPGD.

Fig. 17. Schematic of the test circuit for stand-alone operation.

TABLE IIIPARAMETERS OF THE STAND-ALONE TEST CIRCUIT


Fig. 18. Measured gate-source voltage of the main SiC JFET Jm (purpleline, 10 V/div), drain-source voltage of Jm (dark-pink color, 200 V/div), shoot-through current IJ m (green line, 10 A/div), short-circuit current flows throughJaux , IJ aux (yellow line, 10 A/div) and the sum of the shoot-through currents(light-pink color, 10 A/div), (time base 10 s/div).

Fig. 19. Measured gate-source voltage of the main SiC JFET Jm (purpleline, 10 V/div), gate-source voltage of the auxiliary SiC JFET Jaux (dark-pinkcolor, 10 V/div), shoot-through current IJ m (green line, 10 A/div), short-circuitcurrent flows through Jaux (yellow line, 10 A/div) and the sum of the shoot-through currents (light-pink color, 10 A/div), (time base 10 s/div).

equals the sum of the short-circuit currents flowing throughboth Jm and Jaux . The short-circuit current IJ aux which flowsthrough the auxiliary SiC JFET is shown with the yellow linein the same figure, while IJm is illustrated with the green line.It is obvious that the speed of IJ aux is less than IJm due to theinductance of the primary winding of T/F1 which is connectedin series with Jaux . Regardless of this phenomenon, both cur-rents are turned OFF very rapidly after the start-up process starts(15 s for Jm and 20 s for Jaux ). The gate-source voltage of Jmis shown with the purple line in Fig. 18, while the drain-sourcevoltage of the same device is presented with the dark-pink line.The gate-source voltage is basically equal to the output volt-age Vsu of the start-up converter. It is clear from Fig. 18 thatthe SPGD provides negative gate voltages very rapidly afterthe start-up, and thus, the short-circuit currents through the SiCJFETs are no longer flowing. Additional experimental resultsdealing with the start-up process are shown in Figs. 1921. Thegate-source voltage of Jaux is illustrated with the dark-pinkcolor in Fig. 17. It is obvious from the experimental results thatduring the start-up process Vgs,aux equals Vsu .

Fig. 20. Measured supply voltage of the SPGD (pink line, 10 V/div), drain-source voltage of the main SiC JFET Jm (purple color, 500 V/div), shoot-through current IJ m (green line, 10 A/div) and shoot-through current IJ aux(yellow line, 10 A/div), (time base 5 ms/div).

Fig. 21. Measured gate-source voltage of the main SiC JFET Jm (yellow line,10 V/div), gate-source voltage of the auxiliary SiC JFET Jaux (purple color,10 V/div), shoot-through current IJ m (green line, 10 A/div) and drain-sourcevoltage of Jm (pink line, 200 V/div), (time base 5 ms/div).

Fig. 20 presents the whole start-up process including the start-ing process of the steady-state converter. The dark-pink line inFig. 20 shows the supply voltage to the IC driver and the op-tocoupler. As already mentioned, the steady-state converter re-quires a certain input voltage in order to start its operation. Eventhough the input voltage to the steady-state converter is high,a delay on the starting of this converter is observed in Fig. 20,which approximately equals 25 ms. This is caused due to thesoft-start feature of the MOSFET with the integrated controller.Thus, when the SPGD is enabled, the output voltage equals Vsufor a certain time (approximately 25 ms), while after this theoutput equals Vss which has been adjusted to Vss = 30V. Itmust be noted that the drain-source voltage of Jm is shown withthe purple line in the same figure.

Finally, Fig. 21 shows the gate-source voltages of Jm andJaux (yellow and purple lines, respectively). Even though theoutput voltage of the steady-state converter has been adjustedat Vss = 30V, the measured gate-source voltages are slightlyless negative. The reason for this is that the reverse breakdownvoltages of the gates of the SiC JFETs are less negative than30 V. Thus, the voltage drop across the gate-source junctionequals the reverse breakdown voltage of the gate, while the


Fig. 22. Schematic of the half-bridge converter with the SPGDs.

Fig. 23. Experimental setup of the diodeless half-bridge converter where theSPGDs are employed.

voltage across the parallel network of Rpm and Cgm (see Fig. 10)is equal to the difference between the reverse breakdown voltageof the gate and the supply voltage of30 V. The choice of30 Vsupply voltage is based on experience regarding switching speedand noise immunity. As Rpm has a high value, the negativegate avalanche current is limited to values that are not harmful.Last but not the least, it is worth to mention that the measuredsteady-state power consumption of the SPGD when Jm andJaux are both kept in the OFF state equals 0.37 W. This powerconsumption of the SPGD has been measured using a powermeter connected on the dc-link side. The dc-link input voltageVdc and the input current are both acquired, and thus, the powerconsumption is measured.

C. Experimental Investigation in a Half-Bridge ConverterThe second set of measurements was performed on a half-

bridge converter as shown in Fig. 22. In this case, the half-bridge converter is operating as a step-down dc/dc converterwith open-loop output voltage control. The main idea of thesemeasurements is to show that the proposed SPGD is properlyswitching when it is employed in a realistic power converter. Apicture of the experimental setup is shown in Fig. 23.

TABLE IVPARAMETERS OF THE HALF-BRIDGE TEST CIRCUIT

Two normally ON SiC JFETs Jm1 and Jm2 are employedin the half-bridge converter as the upper and lower switches,respectively, while two individual SPGDs drive the two SiCJFETs. It is obvious from the schematic shown in Fig. 22 thatthere are no antiparallel diodes connected across the SiC JFETs.In the diodeless operation of the half-bridge converter, the re-verse current flows through the channel of the SiC JFET [17],[42], [44]. As illustrated in Fig. 22, the start-up converters aredirectly connected across the main SiC JFETs as illustrated withthe bold lines. On the other hand, both steady-state convertersare supplied by the dc-link voltage Vdc . As in the stand-alone in-vestigation, a start-up IGBT and a start-up resistor are also usedin this case in order to emulate the inrush-current limiting start-up circuit of any standard converter. Additionally, a mechanicalrelay is connected in parallel to the start-up resistor in order tobypass it during the steady-state operation of the converter. Theparameters of this circuit are summarized in Table IV.

As already shown in Figs. 20 and 21 in the previous section,the steady-state converter requires a certain time in order tostart operating. This time is approximately equal to 25 ms. Afterthis time period, the SPGD supplies the nominal output voltage,which has been adjusted to Vss = 30 V. However, the gate-source voltages that are illustrated in Fig. 24 are somewhat lessnegative than30 V due to the reverse breakdown voltage of thegates. This is caused due to the fact that the reverse breakdownvoltages of the gates are less negative than 30 V. A detaileddescription of this phenomenon has been already analyzed in theprevious section. Since the output voltage of the SPGD equals30 V, the mechanical relay can be closed and thus Rstart-up isbypassed. Finally, PWM signals can be sent to the drivers andthe two SPGDs are able to switch. The whole control process forthe half-bridge converter has been implemented using a digitalsignal processor (Texas Instruments TMS320F28335).


Fig. 24. Measured gate-source voltage of the upper SiC JFET Jm 1 (pinkline, 10 V/div), gate-source voltage of the lower SiC JFET Jm 2 (yellow color,10 V/div), shoot-through current IJ m measured on the drain of Jm 1 (green line,10 A/div) and on the drain of Jm 2 (purple line, 10 A/div), (time base 10 ms/div).

Fig. 25. Measured gate-source voltage of the upper SiC JFET Jm 1 (pinkline, 10 V/div), gate-source voltage of the lower SiC JFET Jm 2 (yellow color,10 V/div), drain current of the upper SiC JFET IJ m 1 (green line, 5 A/div), (timebase 10 ms/div).

Fig. 24 shows the gate-source voltages of both JFETs duringthe whole start-up and steady-state processes of the SPGDs.It can be seen that the shoot-through currents are turned OFFvery rapidly. The time delay for the steady-state converter isalso clear from this figure. Finally, after a certain time period,which can be adjusted by the user, the SPGDs are switching.The operating time intervals of each converter are indicated witharrows in Fig. 24. It must be noted that in order to avoid anyhigh transient current when the switching process starts, theduty ratio of the upper SiC JFET is slowly increased from 1%to its final value which has been set to 50%.

An oscilloscope screenshot where the duty ratio equals ap-proximately 25% is illustrated in Fig. 25. The two upper wave-forms in Fig. 25 depict the gate-source voltages of the upperand lower JFETs. It is clear that the operation of these two de-vices is complementary, while a short blanking time has beenalso set (250 ns) so that any shoot-through phenomena will beeliminated. Finally, the lower waveform (green color) in Fig. 25shows the drain current of the upper JFET Jm1 .

Fig. 26. Typical dc/dc boost converter with a high input impedance due to theinductor Lb .

IV. LIMITATIONS OF THE SELF-POWERED GATE DRIVERThe concept and the design of the proposed SPGD in con-

junction with a detailed experimental investigation have beenpresented so far. It is shown that the normally ON problem ofthe SiC JFETs can be solved by employing the SPGD design.Regardless of the outstanding performance of the SPGD as de-scribed in the previous section, there are three limitations of theSPGD operation which must be taken into account.

The first limitation deals with the value of the shoot-throughcurrent which flows though the main and auxiliary SiC JFETs.Even though this current might be adjusted by properly selectingthe value of Rstart-up , the selection must be done consideringtwo issues. On the one hand, the shoot-through current must notbe excessively high because it might thermally destroy the SiCJFETs, and may have an adverse effect on the supply from whichthe current is taken, especially if it is a battery. On the other hand,if the shoot-through current is low, the stored energy Ec on theoutput capacitor of the start-up converter will also be low. Thus,it might be possible that Jm and Jaux will be both accidentallyturned ON before the steady-state converter starts operating.Moreover, as has been shown in Fig. 14, the output voltage ofthe start-up converter also depends on the shoot-through currentof Jaux . For instance, if the shoot-through current IJ aux equals5 A, then in order to reach the desirable output voltage Vsu , avery low capacitor value is required. However, the stored energyin this case might not be sufficient to keep Jm and Jaux in theOFF state for a certain time interval.

The second limitation is related to the range of the power elec-tronics converters where the SPGD can be efficiently employed.A basic requirement in order to activate the start-up converterof the SPGD is a rapidly increased shoot-through current. Thispractically means that the SPGD is only able to operate whenthe input impedance is sufficiently low. Assuming, for instance,a typical dc/dc boost converter as shown in Fig. 26, the inputimpedance of the circuit is high due to the inductor Lb which isconnected on the input of the converter. Thus, the slope of IJ auxis slow and the time needed for activating the start-up converteris longer compared to the low-impedance case. A long activa-tion time for the start-up converter might result in thermallydestruction of the devices due to the shoot-though current. Onthe contrary, in the case of an inverter (or half-bridge converteras previously shown) the input impedance is low and thus arapidly increased shoot-through current directly flows when thecircuit breaker is closed.


The last limitation deals with the shut-down process of theSPGD. Considering, for instance, a phase leg of an inverter,when the system is shut down, the stored energy in the dc-linkcapacitor must be dissipated before the power to the gate driverdisappears. The energy can either be dissipated to the load or toa separate discharging resistor. In the case where the power tothe gate driver disappears before the dc-link capacitor is fullydischarged, there might be a short circuit through the JFETswhich may thermally destroy them.

V. CONCLUSIONIn this paper, a concept along with a circuit solution to the nor-

mally ON problem of the SiC JFETs is presented. The proposedSPGD is able not only to clear the short-circuit current throughthe SiC JFETs, but also to supply the gate-drive circuit withan appropriate negative voltage during steady-state operationwithout the requirement of an external power supply. It basi-cally consists of two separated converters: the start-up converterwhich handles the short-circuit currents and the steady-state con-verter which supplies an appropriate steady-state negative gatevoltage. A certain value of short-circuit current is necessary inorder to activate the start-up converter. It has been shown thatthis current does not need to be excessively high if the passivecomponents of the start-up converter are properly chosen. Thus,the devices are kept far from any thermal destruction due to thehigh short-circuit current. From the experiments, it is clear thatthe activation short-circuit current equals approximately half ofthe rated device current. Moreover, the output voltage of thesteady-state converter might be adjusted to the desired levelaccording to the design requirements. The performance ofSPGD has been investigated on a stand-alone circuit and whenit is employed in a half-bridge converter. From the measure-ments, it is shown that using the SPGD, the short-circuit currentis cleared within approximately 20 s. Additionally, it is exper-imentally shown that the SPGD is able to properly switch thenormally ON SiC JFETs employed in a half-bridge converterwithout any external power supply.

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Dimosthenis Peftitsis (S03) was born in Kavala,Greece, in 1985. He received the Diploma in electri-cal and computer engineering from the DemocritusUniversity of Thrace, Xanthi, Greece, in 2008. Since2008, he has been working toward the Ph.D. degreein the Electrical Energy Conversion Lab (E2C), KTHRoyal Institute of Technology, Stockholm, Sweden.

In 2008, he worked on his diploma thesis atABB Corporate Research, Vasteras, Sweden, for sixmonths. His research interests include gate and basedriver design for SiC JFETs and BJTs, as well as pro-

tection circuits for normally ON SiC JFETs.

Jacek Rabkowski (M10) received the M.Sc. andPh.D. degrees in electrical engineering from theWarsaw University of Technology, Warsaw, Poland,in 2000 and 2005, respectively.

He joined the Institute of Control and IndustrialElectronics, Warsaw University of Technology, as anAssistant Professor in 2005. In 20102011, he hasbeen with Electrical Energy Conversion Lab (E2C),KTH Royal Institute of Technology, in Sweden, asa Guest Researcher. His research interests includenovel topologies of power converters, PWM tech-

niques, drive units, and converters with SiC devices.

Hans-Peter Nee (S91M96SM04) was born inVasteras, Sweden, in 1963. He received the M.Sc.,Licentiate, and Ph.D. degrees in electrical engi-neering from the Royal Institute of Technology(KTH), Stockholm, Sweden, in 1987, 1992, and 1996,respectively.

In 1999, he became a Professor of power electron-ics at KTH, where he currently serves as the Headof the Electrical Energy Conversion Laboratory. Hiscurrent research interests include power electronicconverters, semiconductor components, and control

aspects of utility applications, such as flexible ac transmission systems andhigh-voltage dc transmission, and variable-speed drives.

Dr. Nee has been the recipient of several awards for his research. He is anAssociate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS, and wason the board of the IEEE Sweden Section for several years, serving as its Chair-man during 20022003. He is a member of the European Power Electronics andDrives Association, involved with the Executive Council and the InternationalScientific Committee.

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[sic-en-2013-18] self-powered gate driver for normally on silicon carbide junction field-effect...

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