SiC MOSFET Gate Oxide Breakdown– From Extrinsic to Intrinsic

J. Chbili1,3, Z. Chbili1,2, A. Matsuda1, J. P. Campbell1, K. Matocha4, K. P. Cheung1*

1) NIST, MD2) George Mason University, VA3) Laboratoire SSC, Faculté des Sciences et Techniques, Morocco4) Monolith Semiconductor Inc, TX

1

Two years ago in this workshop ….

2

Our normalized data shown last year

1 10 102 103 104 105-7

-6

-5

-4

-3

-2

-1

0

1

2

3Ln

(-Ln(

1-F)

)

TBD

10%

50%

1%

Assume power system with 1% failure probability in 10 yearsEach system has multiple chips making each chip’s failure probability even lower

0.1%

The extrinsic part of the failure distribution is what really counts. 3

Ogier, J. L. et al., Solid State Dev. Res. Conf., ESSDERC '95. pp 299 - 302

1> Effective thinning model does not work.2> Analysis should be done with joint distributions.

Thick oxide data in the silicon world had similar problem.

4

-5

-4

-3

-2

-1

0

1

2

-5

-4

-3

-2

-1

0

1

2

1 10 100 1000 10000 100000

LN(-L

N(1

-F))

LN(-L

N(1

-F))

Stress Time [s]

T63: 500s, β: 0.5

T63: 50000s, β: 15

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

16000 26000 36000 46000 56000

LN(-L

N(1

-F))

LN(-L

N(1

-F))

Stress Time [s]

~9000s

~26000s

63%

50%

40% extrinsic case

Typical “extrinsic” β value is < 1 Failure rate decreases with time. Screening possible but not guaranteed.

If “extrinsic” β value > 1 Failure rate increases with time. Screening impossible.

Effective thinning tends to have successful screening.

Direct analysis leads to large intrinsic characteristic time underestimation.

Failure fraction scaling:

Active area scaling:

50%

10%

The extrinsic distribution with low beta determines failure.

5

-12

-10

-8

-6

-4

-2

0

2

4

1E+0 1E+1 1E+2 1E+3 1E+4 1E+5 1E+6

Ln(-L

n(1-

F))

Tbd (s)

Failure distributions of different sample sizes

10k devices

50devices

-12

-10

-8

-6

-4

-2

0

2

4

1E+0 1E+1 1E+2 1E+3 1E+4 1E+5 1E+6

Ln(-L

n(1-

F))

Tbd (s)

Failure distributions of different sample sizes

10k devices

50devices

Small sample size can be very misleading when studying extrinsics

Vermeire, B. et al., IEEE Advanced Semiconductor Manufacturing Conf. 2002 pp 299 - 303

Uchida, H. et al. IEDM '90. pp 405 - 408

Gui, D et al. Physical and Failure Analysis of Integrated Circuits, IPFA 2008. pp 1 - 4

Yamabe, K. & Taniguchi, K., IEEE J. Solid-State Circuits 20(1), 343 – 348(2003).

Verhaverbeke, S. et al., IEDM '91. pp 71 – 74.

Yamabe, K. & Taniguchi, K., IEEE Trans. Electron Dev., 32(2), 423 – 428(1985).

The literature is full of reports on the effect of contamination on oxide breakdown

lead to the idea of effective (localized) thinning modelContamination tends to weaken the oxide substantially – not a subtle effect …

Lee, J., I. C. Chen, et al. Symposium on VLSI Technology 1986

Since it does not work, we need a new model that can point the direction to improvement.

- One that can explain why further improvement of cleaning does not work.

7

The “lucky” defect model for early breakdown failure

Differentiate from contamination related “extrinsic” failures

8

Lucky Defect Model

High-Field Stress High-Field Stress with “lucky” defect

Current increases locally!!!

Most oxide breakdown models are current driven.

9

How to quantify this?

What kind of defect distribution can lead to the observed TDDB “extrinsic” tail?

10

...

Trap Assisted Tunneling is defined by the joint probability of :

• Tunneling into the defect (T1)• Tunneling out from the defect (T2)

Maximum when probabilities T1 and T2 are equal.

when defect is at 𝐱𝐱 𝑬𝑬𝒐𝒐𝒐𝒐 = 𝐖𝐖 𝑬𝑬𝒐𝒐𝒐𝒐 ∗ 𝟏𝟏 − �𝟐𝟐 𝟐𝟐

• Independently of the barrier height !!

Important condition: Defect energy matches the electrons in the inversion layer.

11

+ The weakest link model

TAT leads to higher current locally …

Evaluating the impact on lifetime must account for this.

TBD1 = TBD2 •A1A2

1/β

Area scaling:

𝑻𝑻𝑩𝑩𝑩𝑩∗ = 𝑻𝑻𝑩𝑩𝑩𝑩 •𝑱𝑱𝑭𝑭𝑭𝑭

𝑱𝑱𝑭𝑭𝑭𝑭 + 𝑱𝑱𝑻𝑻𝑻𝑻𝑻𝑻𝑻𝑻𝑻𝑻𝑩𝑩𝑭𝑭

𝟏𝟏/𝜷𝜷

= 𝑻𝑻𝑩𝑩𝑩𝑩 •𝟏𝟏𝜼𝜼

𝑻𝑻𝑻𝑻𝑩𝑩𝑭𝑭

𝟏𝟏/𝜷𝜷Net result:

Area (size) of the defect

12

𝐴𝐴𝐷𝐷𝐷𝐷 ?

Cannot be a point with no dimension because of quantum confinementeffect.

If it was a point, there can be no energy level in it !

For our model : 1 nm².

Physically reasonable

Impacts very little the model results.

13

Uniform distribution with a density of defects 108 cm-3

(EOX = 8.3 MV/cm , x(EOX) = 1 nm )

1% of the simulated devices experience early failures similar to the experimental results

100 101 102 103 104 105 106-12

-10

-8

-6

-4

-2

0

2

4

Ln(-

Ln(1

-F))

TBD [s]

10k devices - Uniform distribution of defects

7.10-3 %

1.2 %

63.33 %

99.99 %

0 0.5 1 1.5 2

00.5

11.5

20

10

20

30

40

50

X (cm)

Uniform Defect Distribution 4K

Y (cm)

Z (n

m)

14

Exponential distribution peak at the interface and zero at the gate with a density of defects 108 cm-3

(EOX = 8.3 MV/cm , x(EOX) = 1 nm )

11% of the simulated devices experience early failures Higher amount of “lucky” defects in this

distribution.

100 101 102 103 104 105 106-12

-10

-8

-6

-4

-2

0

2

4

Ln(-L

n(1-

F))

TBD [s]

10k devices - Exponential distribution of defects

7.10-3 %

10.95

63.33

99.99

7.10-3 %

10.95 %

63.33 %

99.99 %

0 0.5 1 1.5 2

01

20

10

20

30

40

50

X(cm)

Exponential Distribution 4K

Y(cm)

Z(n

m)

15

100 101 102 103 104 105 106-12

-10

-8

-6

-4

-2

0

2

4

Ln(-L

n(1-

F))

TBD [s]

10k devices - Normal distribution of defects

63.33 63.33 %63.33 63.33 %

Normal distribution centered at 5nm with 0.58 nm standard width and a defect density of 108 cm-3

(EOX = 8.3 MV/cm , x(EOX) = 1 nm )

00.511.52

01

2

10

20

30

40

50

X(cm)

Normal Defect Distribution 4K

Y(cm)

Z(n

m)

0 0.5 1 1.5 2

01

23

4

5

6

7

X(cm)

Normal Defect Distribution 4K

Y(cm)

Z(n

m)

16

Normal distribution centered at 5 nm with 2.9 nm standard width and a defect density of 108 cm-3

(EOX = 8.3 MV/cm , x(EOX) = 1 nm )

100 101 102 103 104 105 106-12-10

-8-6-4-2024

Ln(-L

n(1-

F))

TBD [s]

10k devices - Normal distribution of defects

63.33

7.10-3

%

99.99 %

0.7%

0 0.5 1 1.5 2

01

20

10

20

30

40

50

X(cm)

Normal Defect Distribution 4K

Y(cm)

Z(nm

)

0 0.5 1 1.5 2

01

20

2

4

6

8

10

X(cm)

Normal Defect Distribution 4K

Y(cm)

Z(n

m)

17

Normal distribution centered at 0.5 nm with 0.29 nm standard width and a defect density of 108 cm-3

(EOX = 8.3 MV/cm , x(EOX) = 1 nm )

0 0.5 1 1.5 20

120

10

20

30

40

50

X(cm)

Normal Defect Distribution 4K

Y(cm)

Z(nm

)

0 0.5 1 1.5 2

01

20

0.5

1

1.5

X(cm)

Normal Defect Distribution 4K

Y(cm)

Z(n

m) 100 101 102 103 104 105 106

-12

-10

-8

-6

-4

-2

0

2

4

Ln(-L

n(1-

F))

TBD [s]

10k devices - Normal distribution of defects

63.33 %

7.10-3 %

99.99 %

31%

18

𝐶𝐶𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜

• Defects in the oxide contribute to the early failures

• Improvement of the oxide process growth

19

SiC MOSCAP fabricated in a silicon foundry

Leverage the low extrinsic failure oxide technology.

20

Cumulative failure distribution for more than 750 SiCMOS caps showing no extrinsic failures (raw data)

SiC nMOS capacitors (40 x 250 um2) with 50 nm thermally grown SiO2

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-1

0

1

2

3

4

5

6

7

8

9

5 6 7 8 9 10 11

Log

(T63

%)

EOX (MV/cm)

2006 - 350C

2008 - 350C

2010 - 375C

McPhersonIEDM98 175C9nmMcPhersonIEDM98 1509nmSuehle TED97400C 22nm

Suehle TED97400C (15nm)

Previously, we reported that SiO2 on SiC is quite similar to on Si.

Our data

22

-1

0

1

2

3

4

5

6

7

8

9

5 6 7 8 9 10

Log

(T63

%)

EOX (MV/cm)

2006 - 350C

2008 - 350C

2010 - 375C

150C

200C

250C

300C

Our new data is a lot better than our old data

New

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-1

0

1

2

3

4

5

6

7

8

9

5 6 7 8 9 10 11

Log

(T63

%)

EOX (MV/cm)

150C

200C

250C

300C

McPhersonIEDM98 175C9nmMcPhersonIEDM98 1509nmSuehle TED97400C 22nm

Suehle TED97400C (15nm)

Our SiO2 on SiC is better than Si data!

How is it possible? 24

Silicon data for thicker oxide are influenced by extrinsic failures.

-0.5

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0

0.1

0.2

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

16000 26000 36000 46000 56000

LN(-L

N(1

-F))

LN(-L

N(1

-F))

Stress Time [s]

~9000s

~26000s

63%

50%

In mid to late 90s, most companies figure out how to grow gate oxide with negligible extrinsic failures. However, by then there are very few studies of thick oxide grown using the new technology.

25

Measured lifetime exhibits a steep field dependent activation energy(Not previously observed in SiC)

26

Thick oxideThin oxide

27

Proc. 29th European Solid-State Device Research Conf., 1999, pp356.

Temperature effect is oxide thickness dependent28

Measured lifetime exhibits a steep temperature dependent field acceleration(Not previously observed in SiC)

3.9 nm

Yassine et al. EDL-20, 390(1999)

Suehle et al. IRPS-94, pp120.

29

-1

0

1

2

3

4

5

6

7

8

9

5 6 7 8 9 10 11

Log

(T63

%)

EOX (MV/cm)

150C

200C

250C

300C

McPhersonIEDM98 175C9nmMcPhersonIEDM98 1509nmSuehle TED97400C 22nm

Suehle TED97400C (15nm)

Can we explain why the slope is steeper for SiC?

30

One potential source is extrinsic failure distribution that depends on stress condition.

Oussalah et al. TED-54, 1713(2007)

31

𝐸𝐸𝑗𝑗 =ℏ2

2𝑚𝑚∗

13 3

2𝜋𝜋𝜋𝜋F𝑠𝑠,eff 𝑗𝑗 +

34

23

F𝑠𝑠,eff = 𝜋𝜋(𝜂𝜂𝑁𝑁𝑠𝑠 + 𝑁𝑁𝑑𝑑)/𝜖𝜖Sior F𝑠𝑠,eff = 𝜂𝜂𝐹𝐹𝑠𝑠𝜂𝜂: weighting coefficient.0.75 for electrons in inversion,0.80 for holes in accumulation

Part of it is due to sub-band energy different.

For silicon, the longitudinal effective mass: ml = 0.98For SiC, the transverse effective mass: mt = 0.42

For high oxide field, only the lowest sub-band matters

Besides difference in extrinsic failures…

32

1.8

1.9

2

2.1

2.2

2.3

2.4

2.5

2.6

2.7

5 6 7 8 9 10

Barr

ier h

eigh

t [eV

]

Oxide field [MV/cm]

Barrier height from 1st subband

Si

SiC

33

FN tunneling …

5.E-05

5.E-04

5 6 7 8 9 10

Cuur

ent r

atio

, SiC

/Si

Oxide field [MV/cm]

As field drops, the tunneling current for SiC drops faster exponentially.

Steeper slope

1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

7 7.5 8 8.5 9 9.5 10

Tunn

elin

g cu

rren

t [A]

Oxide field [MV/cm]

Si vs SiC

SiC

Si

34

10 Yr @6.5MV/cm & 300C --- with high β

For minimum processed capacitors.

Conclusion

1.E-25

1.E-23

1.E-21

1.E-19

1.E-17

1.E-15

1.E-13

1.E-11

1.E-09

1.E-07

1.E-05

1.E-03

1.E-01

0 1 2 3 4 5 6 7 8 9 10

Life

time

fact

or fo

r 100

,000

tim

es

larg

er d

evic

e

Shape factor β

-1

0

1

2

3

4

5

6

7

8

9

5 6 7 8 9 10 11

Log

(T63

%)

EOX (MV/cm)

150C

200C

250C

300C

McPhersonIEDM98 175C9nmMcPhersonIEDM98 1509nmSuehle TED97400C 22nm

Suehle TED97400C (15nm)

000,10010

000,102

2

=cm

µ

Failure fraction scaling:

Active area scaling:

35