signal integrity: problems and solutions - keysight bogatin 2000 slide -1 myths signal integrity:...

Eric Bogatin 2000

Slide -1

www.bogatinenterprises.com

MYTHS

Signal Integrity:Problems and Solutions

Dr. Eric BogatinPresident

Bogatin Enterprises

www.BogatinEnterprises.com(copies of the presentation are available for download on the web site)

Presented at Lockheed, Sunnyvale, CA, March 1, 2000

Eric Bogatin 2000

Slide -2


MYTHS Overview

• What is Signal Integrity?

• Why is it growing in importance?

• What can you do about it?

Eric Bogatin 2000

Slide -3


MYTHS

Signal Integrity and Interconnect Design

How the electrical properties of the interconnects screw up the beautiful,

pristine signals from the chips

Eric Bogatin 2000

Slide -4


MYTHS

The Confusing Mix of Signal Integrity Problems

LOSSY LINES

CROSSTALK

PARASITICS

EMI/EMC

GROUND BOUNCE

INDUCTANCE

EMISSIONS

TRANSMISSION LINES DELTA I NOISE

IR DROP

ATTENUATION

RC DELAY

POWER AND

GROUND DISTRIBUTION

CRITICAL NET

SIGNAL INTEGRITY

SKIN DEPTH

RETURN CURRENT PATHSTUB LENGTHS

TERMINATIONSCAPACITANCE

GAPS IN PLANES

REFLECTIONS

RINGING

LINE DELAY

UNDERSHOOT, OVERSHOOT DISPERSION

LOADED LINES

SUSCEPTABILITY

IMPEDANCE DISCONTINUITIES

NON-MONOTONIC EDGES

Eric Bogatin 2000

Slide -5


MYTHS The Four High Speed Problems

1. Signal quality of one net: reflections and distortions from impedance discontinuities in the signal or return path

2. Cross talk between multiple nets: with ideal return paths, and without (SSO)

3. Rail collapse in the power and ground distribution network

4. EMI from a component or the system

Eric Bogatin 2000

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MYTHS

Signal Quality on One Net:Distorted by the Interconnect

Initial output signal

Signal distorted by interconnect

Simulated with Hyperlynx

Eric Bogatin 2000

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MYTHS

Cross Talk Between Two Adjacent Conductors- Ideal Return Path

Near end

Far end

50ΩΩ

(HP 83480 High speed scope and TDR)

Active line

far end

Near end

The far end noise is ~ 10x larger than the near end noise

rise time ~ 100 psec, TD ~ 1 nsec

Eric Bogatin 2000

Slide -8


MYTHS

On Chip

V SS

VCC

GND

15836© 1991 Integrated Circuit Engineering Corporation

L Bonding

L BondingPower

common lead

inductance

Conceptual Origin of SSO Noise

Icharge

Idischarge

Switching lines

Quiet data line

Eric Bogatin 2000

Slide -9


MYTHS

Simple Example of Rail Collapse

100 nF

Rail collapse: ∆∆V ~ - dI/dt

Source: National Semiconductor

CdecouplingTo

regulator

Current On Current Off

Vdd nominalVdd rail collapse

Eric Bogatin 2000

Slide -10


MYTHS

Radiated Emissions and Power and Ground Routing

Eric Bogatin 2000

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MYTHS

Two Classes of High Speed Problems

• Timing: setup, hold, propagation delay, skewü Scales with decreasing clock period

• Electrical Noise: signal integrity and EMIü Scales with decreasing rise time

dIdt

dVdt

f, f2

Eric Bogatin 2000

Slide -12


MYTHS

On Chip

V SS

VCC

GND

15836© 1991 Integrated Circuit Engineering Corporation

L Bonding

L BondingPower

common lead

inductance

“…it’s the rise time, …”

Icharge

Idischarge Switching data lines

Quiet data line

N = number of switching leads per ground leadsL = lead inductance or lead lengthττ = rise time

SSO noise ~N x L

ττ

Eric Bogatin 2000

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MYTHS

Shorter Delays Mean Shorter Clock Periods, Higher Clock Frequencies

Digital Clock Frequencies are Increasing: doubling every 2 years!

1

10

100

1000

10000

1970 1975 1980 1985 1990 1995 2000

Introduction Year

Clo

ck F

req

uen

cy (

MH

z)

Clock frequency of Intel Processors

High speed usually refers to increasing clock frequency

Eric Bogatin 2000

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MYTHS Increase in Clock Frequencies

0

500

1000

1500

2000

2500

3000

3500

1996 1998 2000 2002 2004 2006 2008 2010 2012 2014

Year

Clo

ck F

req

uen

cy (

MH

z)

on-chip

on-board

Source: SIA Roadmap

Eric Bogatin 2000

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MYTHS

Rise Times Are Loosely Related to Clock Frequency

0.01

0.1

1

10

100

1 10 100 1,000 10,000

Clock Frequency (MHz)

Ap

pro

xim

ate

Ris

e T

ime

(nse

c)

clockF1

101

~τWhat is the consequence of higher speed?

10 nsec period

1 nsec rise time

Eric Bogatin 2000

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MYTHS

The Driving Force Fueling the Electronics Revolution:

Gate Length Feature Size Reduction

50% reduction every 4 years

Eric Bogatin 2000

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MYTHS

Transistors Switch Faster As Channel Length Shrinks

Shorter channel length means:->> shorter delay->> shorter rise time

in out

What can happen to the clock period and clock frequency?

Eric Bogatin 2000

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MYTHS Situation Analysis

• Clock frequency will get faster• Rise times for everyevery chip will get shorter• SI problems will be more significant• Design cycle times will be decreasing

Conclusion:Getting new products to market on time will be harder.

Solution: A new design methodology is needed.

Eric Bogatin 2000

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MYTHS The Old Design Strategy

Guess a design

Hope it works

Build it

Test it

Try to Fix it

Ship it

Eric Bogatin 2000

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MYTHS

Details of the Three Design Approaches

Source: G. Doyle, Mentor Graphics

Design by correcting

Design by virtual iteration

Correct by designThe earlier in the design cycle problems can be identified and solved, the lower the development cost and the faster time to market.

Eric Bogatin 2000

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MYTHS

Two Critical Processes for Virtual Design and Test

Modeling: Translating the physical world into an equivalent electrical circuit model (Schematic)

Simulation: Predicting voltage/current waveforms based on the circuit behavior

Zo,

τ

D Zo,

τ

D

Lpower

Lgnd

Clk1

Lpin

Cpin

LpinLconnLconn

Cconn Cconn

Cpin

Lpower

Lgnd

Clk1

Gate1

Gate2

PCB #1 Backplane PCB #2

Zo,

τ

D

V1

PULSE

R1 50 L1 1U

C1

30P

Q 2

QN3904

Q10

QN3906

R4

680

R2

5K

V3 10

V2 10

X1 WIRER3 10

C2

7P

V(10)

VLOADV(7) VEMITTER

V(3)

VOUT

2 1 3

4

7

8

9

6 10

Eric Bogatin 2000

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MYTHS

1

6

11

16

21

26

M01:i011

M09:i091

M16:i161

M24a:i24a1

0.0

0.5

1.0

1.5

2.0

Ind

uct

ance

(n

H)

• Calculations: (03, 06)ü Rules of thumbü Analytic approximationü Parasitic extraction numerical tools: field solvers

• Measurements: (06)ü Impedance analyzer (LCZ)ü Network Analyzer (NA)ü Time Domain Reflectometer (TDR)

Where do Models Come From?

Courtesy of TDA Systems

Eric Bogatin 2000

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MYTHS

Two Tools for Simulating Circuits

• SPICE: Simulation Program with Integrated Circuit Emphasisü PSPICE from OrCAD/Cadenceü IsSPICE from Intusoftü Advanced Design System (ADS) from HP Eesofü Maxwell SPICE from Ansoftü Micro-CAP from Spectrumü HSPICE from Avant!

• IBIS based simulators: Input/output Buffer Interface Specification ü Hyperlynx (Pads)ü Veribest/Mentor Graphicsü Zukan Redacü Viewlogicü Interconnectix (Mentor Graphics)

Eric Bogatin 2000

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MYTHS Design Principles for Good SI

Noise Categories Design Principles

Signal Quality Signals should see the same impedance through all interconnects

Cross talk Keep spacing of traces greater than a minimum value, minimize mutual inductance of non ideal returns

Rail Collapse Minimize the impedance of the power and ground path

EMI Minimize bandwidth, minimize ground impedance and shield

When are you done? How much reduction is enough?

Eric Bogatin 2000

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MYTHS

time

money

risk

Cost factors:

…just follow these RULES

PerformancePerformance(meet specs)(meet specs)

Eric Bogatin 2000

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MYTHS

Design Tradeoffs Are Negotiated With a Budget

• Total voltage swing is 3.3v• Within 500 mV, all the noise sources must be accounted for:

*

*dynamic effects important

An example:

•• In hi speed systems, keeping within the noise budget is HARD!In hi speed systems, keeping within the noise budget is HARD!•• The more accurately you can predict performance, the less marginThe more accurately you can predict performance, the less margin needed and the higher the needed and the higher the

performance performance

Noise Source Allocated BudgetRinging/reflections 100mVDiscontinuities 40mVCross talk 90mVSSO noise 120mVRail collapse 100mVTotal* 450mVMargin ~50mV

Discontinuities9%

Rail collapse22%

SSO noise27% Cross talk

20%

Ringing22%

Eric Bogatin 2000

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MYTHS

The Most Important General Design Principles

1. Slow down edges

2. Minimize the length of all interconnects

3. Use low dielectric constant materials for signal layers

4. Use controlled impedance lines and terminate

5. Minimize loop mutual inductances between signal lines

6. Use continuous, closely spaced, adjacent power and ground planes

Eric Bogatin 2000

Slide -28


MYTHS

#1 solution: slow down the edges

50 psec

150 mils spacing

50 Ohm line

2 short stubs (capacitive discontinuity)Top view

Longer the rise time, smaller the impact, or,

the shorter the discontinuity, the smaller the impact

Eric Bogatin 2000

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MYTHS Minimize Bandwidth

AVX Z chip: integrated RC, with low stray C

Spread Spectrum Clock Generator (SSCG)

At 2 GHz At 2.3 GHz

Figure 28. Data from Ansoft HFSS showing the field distribution on andoff resonance for a 208 lead QFP, excited at one lead.

Avoid resonance and clock harmonics

Eric Bogatin 2000

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MYTHS

#2 solution:shorter is better

• Reflections:

• Cross talk

• Rail collapse

• EMINear end

Mutual C, mutual L, scale with lengthSeries L scales with lengthRadiated emission scales with length of current path

Eric Bogatin 2000

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MYTHS

Terminations will Minimize Reflected Noise from the Ends

Series R terminate

RC terminate at far end, changing C

Source: Analog Devices

Eric Bogatin 2000

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MYTHS Avoid Stubs and Branches

(for 0.5 nsec edges, stub length < 0.5 inches)

branches

daisy chain

Eric Bogatin 2000

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MYTHS

Thin Power and Ground Layers Reduce Switching Noise

Conventional, 10 mil thick spacing, 2 plane pairs

Thin layer, 2 mil thick, 4 plane pairs“A Low-Cost Technique for Reducing the

Simultaneous Switching Noise in Sub-Board Packaging Configurations”, Koike and Kaizu, IEEE Trans CPMT part B vol 21(4) Nov 1998 p. 428

Small daughtercard

Eric Bogatin 2000

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MYTHS Reduced Switching Noise

Improves effectiveness of the decoupling caps

Reduces SSO noise

Eric Bogatin 2000

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MYTHS

Reducing Emissions: Low Impedance Power and Ground Layers by

Thinner Dielectric

Eric Bogatin 2000

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MYTHS Avoid Splits in Return Path

Archambeault, Bruce; “Proper design of intentional splits in the ground reference plane of PC Boards to minimize emissions from I/O wires and cables”, Proc. 1998 IEEE conf on EMC, p. 768

with split

no split

Avoid all splits in the return path!Avoid all splits in the return path!

Eric Bogatin 2000

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MYTHS Unintentional Splits

Figure 9. How a via field for a connector can create a gap. By decreasingthe clearance hole diameter in the ground plane, a continuous returnpath can be provided.

Figure 10. Data from [10]. Left is the emission from a board with gapsunder via fields- failing the Class A test. Right: the exact same board, butwith smaller clearance holes and no gaps under traces- passing Class Atest.

Decreasing size of clearance holes reduced radiated emissions

Eric Bogatin 2000

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MYTHS The Design Strategy

1. Use design guidelines as design guidelines to shoot for

2. Estimate the magnitude of each effect and the benefit from a design or technology solution

3. Verify the models and simulations based on measurements of test vehicles and previous designs

4. Evaluate cost/performance trade offs

5. Keep optimizing until the noise budget is met

6. The earlier in the design cycle correct design decisions can be made, the shorter time to market and lower the development cost

Eric Bogatin 2000

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MYTHS

SI Problems Apply Across ALL Interconnects

Courtesy of ICE

BOLData Corp

Eric Bogatin 2000

Slide -40


MYTHS

“There are two kinds of design engineers, those that have signal

integrity problems, and those that will”

Good Luck!

signal integrity: problems and solutions - keysight bogatin 2000 slide -1 myths signal integrity:...

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