Silanna Manufacturing Radiation

Hardened Integrated Circuits for Space:

The Journey

Andy Brawley – VP of Manufacturing

Presented at NSW Trade & Investment

18th June 2015

www.silanna.com

andrewb@silanna.com

What are we?

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Silanna

Silanna is a semiconductor component supplier to the Upstream Space Market

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Who are we? Silanna is a semiconductor manufacturing company using a silicon-on-sapphire (SoS) process technology for high-performance RF-CMOS applications. A vertically integrated company that can design a product, manufacture the chips on its own process line, test and qualify the product, as well as provide route to market.

Modern Building situated in the Australia Centre – Sydney Olympic Park NSW

150mm SoS CMOS wafer fab with 1100m2 Class 1-10 Cleanrooms

150mm Compound Semiconductor Fab with 550m2 Class 1 Cleanroom,

Production Shift - 24 hrs/day, 7 days/week

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New Compound Semiconductor Research Facility

A $30M Investment in New Processes and Tool Types

Deposition – Molecular Beam Epitaxy - Veeco Gen200 Dual Chamber

Etch - PlasmaTherm LLC Versaline LL ICP

Rapid Thermal Processor - Mattson 2800CS

E-Beam Evaporator - Temescal

X-ray Diffractometer - PANalytical X'Pert-PRO MRD

Photoluminescence Mapping System - Nanometrics Vertex

Hall Measurement System - Coherent Scientific

System capable of depositing nitrides such as AlN, GaN, AlGaN etc

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Applications that use our chips

What do we do?

Deep Space Probes

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The farthest man-made

object from the Earth is the

Voyager 1 spacecraft, that

has an RCA-built SoS

microprocessor on-board.

It was launched in 1977

and left our solar system in

2003. As of today it is

more than 19 billion

kilometres from earth and

still functioning

Space Environment – just a little bit nasty

In 2003 a large magnetic storm caused more than 47 satellites to malfunction, including the total loss of

a scientific satellite valued at $640m.

The largest magnetic storm ever recorded – Carrington of 1859 – If such a super-storm occurred today,

the cost could be as high as $30bn

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REF: http://www.sail-world.com/index.cfm?nid=94565

Space Radiation Effects

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SoS vs. Competing RF Processes

Bulk CMOS Process SoS Process

oxide gate gate contact contact

silicon layer contact

insulating sapphire substrate

p-channel FET n-channel FET

SiGe BiCMOS Process

p+ base

semi-insulating GaAs substrate

n+ GaAs subcollector

n- GaAs collector

AlGaAs

emitter

collector

contact

base

contact

emitter

contact base

contact

GaAs HBT Process

isolation

implant

npn-bipolar HBT

contact gate isolation

n+ n+ n+ p+ p+ p+

p+substrate

p-epitaxial layer

n-well

oxide gate contact contact

body

tie

n-channel FET p-channel FET

p-well

p-substrate

n+subcollector n+ n-well

p+ n-collector p+

p+

n+

n+

p-channel FET

p+

npn-bipolar

gate contact

contacts emitter SiGe

base

collector

contacts

trench

isolation oxide

p-well n+ n+ n+

contact contact

gate

n-channel FET

p-

p+

body

tie

Oxide-isolated devices

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Zero volt

Vt devices

NO field

inversion

or latchup

N-channel P-channel

SiO2 Dielectrically

isolated

transistors Sapphire

Sapphire

Gate Oxide

Fully-depleted Channel

NO back-channel effect

Source Drain

NO body effect

or major kink

Gate

NO junction

spiking

Reduced

E-fields

Ldd Ldd

SoS Radiation Basics

+++++++++++++++++++++

Zero substrate

capacitance

NO Back-bias or

thermal effects

Fully-depleted

structure solves

TID effects

Short lifetime

improves

SEE/SEU

Ultra-thin

layer ideal

for

SEE/SEU

Radiation induced

+ charge only

shifts Vt (Gauss’ Law)

How we support Space applications

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ELECTRONICS that has:

Easy integration of RF, passives, mixed signal, and

EEPROM on a single die

Radiation-hard and Cryogenic temperature operation

Optically transparent substrate for use in optical applications

Lower parasitic capacitance = Higher Speed + Lower Power

Consumption

Fully depleted transistors, improving linearity, speed, and

low voltage performance

Excellent RF performance:

o fmax typically 3X ft (60 GHz at 0.5 µm and 100 GHz at

0.25 µm)

o very high linearity transistors (+38 dBm IP3 mixers)

o high Q integrated inductors (QL > 40 at 2 GHz for 5 nH

inductor)

High isolation (>50 dB between adjacent devices)

Processed in standard CMOS facilities on large wafers with

low cost advantages

How we offer Space applications (2)

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SYSTEMS that include:

ISO 9001:2008 LRQA certification

AS9100 Rev.C LRQA accreditation

US Defence MicroElectronic Activity (DMEA) Trusted Foundry clearance to “secret” level

International Traffic in Arms Regulation (ITAR) free

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Performance Advantages

Transistor Size

Transistor

Speed

100nm 1000nm 1nm

100GHz

1000GHz

Lower Cost,

Higher Returns Silanna

IBM and Semiconductor

Industry Association

Roadmap

Cost of

building a

Wafer Fab

free $200M $4B $50B

Our customers

Peregrine Semiconductor based in San Diego CA USA.

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Aerospace Corp

Air Research Lab

Alcatel Alenia

Army Research Lab

Astrium

Boeing

Defence Microelectronic Activity

DSTO

General Dynamics

Honeywell

Jet Propulsion Lab

Lockheed Martin

MRC

NASA Goddard

Northrop Grumman

Oak Ridge National Lab

Rockwell Collins

Space Micro

Thales

Ultra Communications

Target Features

4 high speed (400 Mbps)

channels

2 transmit, 2 receive (Data+Strobe)

Cable-side: LVDS

Module-side: LVTTL or LVDS

LVTTL: LV049 Mode

LVDS: Repeater Mode

LVDS failsafe

Isolation voltage: 1 kVrms

SpaceWire Link Isolator

Integrated DC-to-DC isolator to power cable-side from module-side

Cable-side data lines align well with SpaceWire cable connection

LV049 Mode is functionally & signal-pin compatible w/ standard dual

LVDS transceiver devices (ie. TI/NSC DS90LV049 series)

LV049 Mode

RIN1-

RIN1+

RIN2+

RIN2-

DOUT2-

DOUT2+

DOUT1+

DOUT1-

EN

ROUT1

ROUT2

GND

VDD

DIN2

DIN1

EN-

VDD

GNDGNDI

VR

EGDC-DC DC-DC

I/O C

ON

TRO

L

VR

EG

VDDI

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CSIRO SKA Radio Telescope

Silanna Antenna

Receiver Chip

LNA chip designed by

LaTrobe University

Low Noise Applications

Integrated Wide Band Receiver

“SKA is not possible without miniaturization”

FROM THIS

TO THIS

200 Receivers

0.5 to 1.8 GHz

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ASKAP Project Leader, Dr Dave

DeBoer, with a receiver for CSIRO's

prototype phased array feed.

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90 x 900nm

SCANNING TUNNELING MICROSCOPE

SCANNING ELECTRON

MICROSCOPE OPTICAL MICROSCOPE

30μm 100μm

HUMAN EYE

Atomic-scale lithography

1 nm 2 mm

Single Atom Nanoelectronics

Fabrication of external metal

contacts aligned to buried

phosphorus doped

nanostructure

Centre for Quantum Computer Technology

Quantum Computer

Silanna voltage pulse

generator for Qubit transistor

operating at 30mK

Very Low Temperature Applications

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Single-chip Military GPS Receiver

Low Power - High Density Applications

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Optics on Sapphire (micro-displays)

Full color micro-display on UltraCMOS sapphire

• XGA, VGA, SVGA demonstrated

• RGB LED’s • No bulky optics • Standard UTSi

CMOS process

Space and Naval Warfare Systems Center (SSC) in San Diego and

Optron Systems collaborated on the fabrication of a first-generation,

monochrome microdisplay. In 1999, Radiant Images, Inc., a spinoff

from Optron Systems, was formed to commercialize the invention.

Photonics on Sapphire

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Optical Transceiver

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Similar process to standard MEMS

Standard SoS process

Minor design rule changes

Designed for optical, magnetic, &

capacitive sensing

Simple, standard post-CMOS

processing

Low-loss substrate helps MMW RF

MEMS on Sapphire

Low cost prototypes

A large cost of chip development

is mask tooling and prototype

wafers

Compressed Reticle program

significantly reduces tooling

cost

Small runs of protos or

production possible

Multiple mask layers on one Reticle

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Production Flow for Space Products

Silanna Semiconductor Europe Overall Program Management

Product development & Design

Full documentation set up

Quality assurance

Mask Shop (Singapore) Mask

Foundry (Silanna Australia) Wafer processing

WAT/WLR

Backgrinding

Assembly (Europe) Wafer sawing

Assembly (Packaging and bonding)

Mechanical screening

Thermal cycles

PIND test

Leakages

Test & Screening (Europe) Wafer probe

Electrical test

DC, AC, RF and PN

Electrical screening (Burn in, Life test,…)

Qualification and Periodic Tests

Product Development

Design-Simulations-Layout

Tape Out

MaskShop

Wafer Fab

Design Validation

Characterization

Wafer Sawing

Assembly

Electrical test

Screening

Pro

gra

m M

an

ag

em

en

t

Lo

gis

tic -

Qu

alit

y M

an

ag

em

en

t

Radiation

Test

Data Package validation

& Product control - Customer CSI

Precap

Program SOW

PR

OD

. DE

V. S

pe

c

PID

& S

CC

90

00

PDR

CDR

MR

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Chip Manufacturing Services

Ideal for RF/Mixed Signal and Digital designers

Silicon-on-Sapphire

0.5 µm Single Poly Triple Metal SoS

0.25 µm Single Poly Triple Metal SoS

3 variants of each

High volume - High mix – High Flexibility

6 weeks fab cycle time – Compressed reticle

Cadence & AWR Process Design Kit (PDKs)

Wafer dicing + Prototype assembly services

“Use SoS for your advanced RFIC designs”

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No schedules – start when ready

Wafer dedicated to customer design

Potentially thousands of devices per

wafer

Can use for low volume production

Quicker re-spin times

Much lower chip cost

Easy transition to production

Compressed Reticle Compared to Multi-Project Wafers

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Laser scribe and break – sapphire and quartz

Die bonding

Wirebonding – wide range of open cavity plastic & ceramic

packages

Expertise in Assembly with 20+ years experience in IC

assembly

ESD safe Class 10K clean room

Fast turn including same day delivery of small quantities

Prototype IC Packaging

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Questions please

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2004 AEEMA Excellence Award for Commercialising R&D

Presented by Minister Hon. Ian Macfarlane Received by Jim Cable, Ron Reedy & Andrew Brawley

2004 Western Sydney Industry Awards

Presented by NSW Premier Bob Carr

for Innovation and Advanced Manufacturing

2005 WSIA for

Innovation and

Global Excellence

Presented by

Minister for

Western Sydney –

Diane Beamer

Excellence Awards

2006 WSIA for

Innovation Presented

by NSW Premier

Morris Iemma

2006 EDN Innovation

Award for Best

Application of RF

Design

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AEEMA 2006 Excellence Awards for Best New Product and

Commercialising R&D presented by Bob Baldwin representing

Minister Macfarlane and Angus Robinson, AEEMA CEO, accepted

by Ron Reedy Jim Cable and Andy Brawley

Manufacturing

Presented

by Senator

Helen

Coonan

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Winner of Global Excellence and Most Outstanding Large Business

presented by Minister of Western Sydney, Barbara Perry

Western Sydney Industry 10th Awards 2008