silicon wafer preparation

8/20/2019 silicon wafer preparation

1/43

Silicon V2.1 En

ROM SILICA

TO SILICON WA ER

The Silicon Single Crystal

and

Wafers Manufacturing

Version 2.1 En


2/43

Silicon V2.1 En

VS

VPS s.r.o., P.O. Box B-11, Partizanska 31, 921 01 Piestany 1, Slovak Repuli!

tel., "ax.# $%21 33 &&301'1, e(ail# vps)vps.sk

This presentation was prepared for the needs of the company ON Semiconductor with the aim to

approximate the production principles of single crystal silicon ingots and silicon wafers.

The manufacturing process details, pictures and ideo clips come from the company TE!OS"#, a.s.

$ased in !o%no pod !adhostem, &%ech !epu$lic, we appreciate their friendly help in compiling the

presentation.

"n our effort to continuously improe our products we than' you in adance for your comments,

which will help us in the preparing of further ersions.

(iestany, )ugust 2**1


3/43

Silicon V2.1 En

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end of presentation

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ouse *ontrol

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eyoar *ontrol

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y locating the cursor on a $utton, the shape

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"f you do not notice an animation action

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4/43

Silicon V2.1 En /

ppenix

&lean !ooms

Some Special 0nits

Contents

ntrou!tion

+at is nsie an le!troni! 4evi!e5

Sili!on

Silicon the Structure

Silicon "nside the Single &rystal

&rystalline efects

oping

Silicon 3afer

Silicon O$taining

(olycrystalline Silicon

*li!kin6 on t+is ox 7ill navi6ate you

to t+e *ontrollin6 t+e Presentationslie

a"er anu"a!turin6

3afer Edge 4rindingou$leSided #apping

Stress !elief Etching

Etching 5achine

ac'side Treatment

&V E6uipment

(olishing

(olishing 5achine&hemical &leaning

"nspection

Scru$$ing

7inal "nspection

pitaxy

Epitaxial !eactor

Epitaxial #ayer &haracteristics

*zo!+ralski *rystal 8ro7t+

&%ochrals'i (uller

&rystal5elt "nterface

Oxygen and &ar$on in Silicon &rystal

Segregation &oefficientSingle &rystal "ngot

n6ot S+apin6 an estin6

*roppe n6ot

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5/43

Silicon V2.1 En

Introduction

+e !o(pany ROS:, a.s., lo!ate in

Roznov po Ra+oste(, *ze!+ Repuli!, isprou!er o" sili!on sin6le !rystals, 7a"ers an

epitaxial layers "or (i!roele!troni! evi!e

"ari!ation.

ROS:, a.s. is a non 7+olly o7ne

susiiary o" O/ Se(i!onu!tor, 6loalsupplier o" +i6+-per"or(an!e roaan an

po7er (ana6e(ent inte6rate !ir!uits an

stanar se(i!onu!tors.


6/43

Silicon V2.1 En

What is Inside an Electronic !e"ice#

"f we remoe the $lac' material from the pac'age,

we can see the leads leading up to a small piece of

matter inside which the whole function of anelectronic deice proceeds.

This small piece of matter is called chip. )fter an

enlargement we can see its structure.

The $asic material of a chip is a semiconductor

silicon.


7/43


8/43Silicon V2.1 En

Silicon % the Structure

a B *,8 / + n m

Silicon is a chemical element from the group "V

in the (eriodic ta$le.

Silicon crystallographic structure is diamond

type lattice. "t is $ased on a face centered cu$ic

structure a cu$e with atoms in its ertices and

in the wall centers.

"f we moe a copy of this structure $y 1@/ of the

main diagonal, $oth the original and the shifted

atoms form a diamond type lattice.

Each silicon atom has four neigh$ors, which it

forms a $ond with.

"t is necessary to add that silicon has

appropriate properties for semiconductor chips

only when the atoms in the whole olume of the

chip are arranged exactly according to this

structure. Such and arrangement is called

single crystal. ) iew of a fictitious o$serer

inside the silicon single crystal loo's li'e the

following picture.

2


9/43Silicon V2.1 En

Silicon % Inside the Single Crystal


10/43Silicon V2.1 En

Crystalline !efects

)ny imperfection in the crystalline structure is considered a defect. )

defect can influence the electrical and mechanical properties of a

crystal. To demonstrate arious 'inds of crystalline defects a

simplified crystalline structure is used not silicon-.

)n atom missing from the regular crystal site gies rise to a acancy.

Vacancy

"nterstitial

Edge dislocation

Screw dislocation

)n additional atom occupying a site in$etween regular sites is called

an intersticial.

)n edge dislocation appears as if an extra plane has $een inserted

into the crystal.

) screw dislocation can $e descri$ed as atomic layers partly cut with

scissors and shifted each other.

"n fact, ariety of defects does exist. efect isuali%ation can $e

achieed $y selectie etching of silicon surface. The crystalline

defects could then appear li'e demonstrated on the

microphotograph.



""".) V.)"V.)

!o&ing (resence of some chemical elements dopants in silicon, can

su$stantially influence the silicon electric conductiity. oron,

phosphorus, arsenic and antimony are especially used for this

purpose.

(hysically, $oron presence causes a different mechanism of electric

current transfer in silicon than phosphorus or arsenic. Silicon doped

with $oron is called the (type silicon while silicon doped with

phosphorus, arsenic or antimony is called the Ntype one.

Only a ery small amount of a dopant is sufficient for doping silicon.

The unit of a dopant concentration is the num$er of dopant atoms

per unit olume of silicon, usually gien in Datoms@cm+.

The range of dopant concentration used in the semiconductor

industry is 1*1/ to 1*2* of dopant atoms@cm+. Silicon lattice itself

contains 8.1*22 atoms@cm+.

121.:8

81S$

)ntimony

:/,C219

++ )s

)rsenic

+*.C:+:9

18( (hosphorus

1*,



Silicon Wafer

) chip is ery small, ust a few s6uare millimeters. "t

would $e difficult, if not een impossi$le, to

produce each chip indiidually.

(rimary 7lat

Secondary 7lat

F1**GF111G

7or that reason, many chips are processed

together in one slice of semiconductor silicon

wafer. )t the end of the process the wafer is cut up

into indiidual chips.

The silicon wafer is roundshaped. The diameters

of 1**, 128, 18* mm or more are commonly used.

) 1** mm wafer is a$out half of millimeter thic'.

)lready the wafer material is doped and it is ( or N

type then.

The crystallographic orientation, in respect to the

silicon wafer surface, is important for the wafer

properties. "n practice, the orientations according to

the pictures are used and they are classified as

F111G or F1**G.

The conductiity ( or N- type and a silicon wafer

crystallographic orientation are encoded in a

relatie position of primary and secondary flat on

each wafer. The top side of silicon wafer is highly

polished.

The wafers are fa$ricated $y cutting from a

monocrystalline silicon cylinder pulled from molten

silicon in special e6uipment.

( F1**G

The next slides will proide deeper details of a

silicon wafer manufacturing process.


13/43


14/43Silicon V2.1 En 1/

olycristalline Silicon


15/43Silicon V2.1 En 18

ppenix

&lean !ooms

Some Special 0nits

Cha&ter ( O"er"ie)

ntrou!tion


Sili!on



&rystalline efects

oping

Silicon 3afer

Silicon O$taining


a"er anu"a!turin6



Etching 5achine

ac'side Treatment

&V E6uipment

(olishing


"nspection

Scru$$ing

7inal "nspection

pitaxy

Epitaxial !eactor



&%ochrals'i (uller





&ropped "ngot



C*ochrals+i Crystal ,ro)th

Seedchuc'

Seed

&ruci$le rotation

Seed chuc' rotation

>uart% cruci$le

4raphite cruci$lesusceptor-

4raphite heater

&ruci$le shaft

5elt

Nec'

&rown

odyTail

Shoulder

"n 1C1



C*ochrals+i uller

>uart% cruci$le

4raphite cruci$le

4raphite heater

Thermal shield

Electric current leadin

&ruci$le shaft

&ruci$le rotation

Seed chuc'

rotation

&a$le

Seed chuc'

The 6uart% cruci$le is the component containing the

silicon melt. The cruci$le material must $e chosen such

that it reacts ery slowly with the melt. The only

material that can $e used is 6uart%.

)rgon inlet

Optical

pyrometer

&amera

diameter control-"solation ale

Visor

To acuum

pump

3ater

cooled ac'et

The 6uart% cruci$le is supported $y a graphite cruci$le

which seres simultaneously as the heat susceptor.

oth cruci$les are placed on a graphite shaft ena$ling

the rotation and lifting.

) graphite heating element is placed around the

graphite cruci$le susceptor.

7inally, the last part of the heat %one is a thermal shield

eliminating the heat losses.

The lift seed chuc' and ca$le- holds the seed and

growing crystal during the process ena$ling the

controlled pull rate and rotation.

The whole system is placed in acuum cham$er with

watercooled ac'et. 5onitoring system pyrometer and

camera- and computer control the growth process.

)n isolation ale allows access to upper cham$er

while 'eeping the controled am$ient in lower acuum

cham$er.

The &%ochrals'i puller schematical drawing can $e

compared with real e6uipment picture next.



Crystal%Melt Interface

The fundamental process $ehind the growth of a

crystal inoles the transformation of a li6uid into a

solid. To grow a crystal, the atoms of the li6uid

must organi%e themseles as they $ecome part ofthe solid. This underlines the importance of good

control of the process at the interface $etween the

melt and the crystal.

A e a t f l o w

Aeat input Aeat output

5elt flow 5elt flow

&onex crystalmelt interface &oncae crystalmelt interface

) good control of the temperature at the interface

$etween the crystal and the melt is crucial. ) good

control of the heat flow throughout the interface is

the critical condition for that.

The area $etween the melt and crystal has to $e

maintained at the silicon free%ing point. This is the

coldest region in the melt, otherwise solidification

will occur in other parts as well. Aeat inputs andoutputs must $e monitored and $e regulated to

insure proper crystal growth.

The crystalli%ation ta'es place at the crystalmelt

interface. The shape of the interface directly

influences the crystalline perfection and the

impurity distri$ution throughout the section. Theconcae shape helps to remoe dislocations and is

maintained during the crystal $ody growth.

uring crystal growth, the melt flow pattern in the

cruci$le plays an important role of crystalmelt

interface shape and dopant ariation. The

spontaneous melt flow originates from temperaturedifferences in the melt left $ottom picture.

5elt flows are also generated $y the rotation of the

crystal and the cruci$le and $y pulling of the

crystal. uring crystal growth, a com$ination of

crystal and cruci$le rotation is used to generate thedesired melt flow right $ottom picture.

&rystal rotation

&ruci$le rotationno rotation

&rystal melt interface 5elt

&rystal

cross

section

$lac'-



O-ygen and Car'on in Silicon Crystal

Oxygen is the most common impurity in silicon crystal. "ts

main source is the cruci$le material 6uart% SiO2-. This

surface is in contact with the silicon melt. The reaction

$etween the silicon melt and the cruci$le produces siliconmonoxide SiO-. 5ost of the silicon monoxide eaporates

from the melt surface $ut a small 6uantity stays in the melt.

>uart% cruci$le

4raphite heater 4raphite cruci$le

&ar$on impurities originate from the polysilicon charge and

from the reaction $etween the graphite heating element

and silicon monoxide eaporated from the melt. &ar$on

has much lower concentration than oxygen in the crystal.

Traces of other impurities are also present in the crystal.

Their concentration is lower than that of car$on and they

accumulate in the melt residue left in the cruci$le.

*O, *O2 *O, *O2

SiO SiO

SiO SiOSiO

SiO $ 2* Si* $ *O



4opant *on!entration;Resistivityvs. 2n6ot :en6t+ >exa(ple?

9

<

1*

* 2** /** 9** p? @ *0>1-p?k-1

p normali%ed length p B 1 for #max-' segregation coefficient

! e s i s t i i t y J m Ω c m K

resistiity

*:=A4 @ 1,0 x 1019 !(-3

*SO:4 @ 3,' x 101 !(-3

Se6re6ation *oe""i!ient# k @ *SO:4

*:=A4

One of the 'ey operations in crystal pulling is

the introduction of a specific amount of dopant

into the crystal. The dopant is added to the

polysilicon charge or melt in the cruci$le.

Segregation Coefficient

"n the crystal growth process, there are two

phases at the interface the solid crystal and

the li6uid melt. etween the two phases,

redistri$ution of the dopant ta'es place. This is

measured in term of a segregation coefficient

as a ratio of concentrations of the dopant in the

two phases.

7or example, phosphorus has a segregation

coefficient of *,+8. That is, near the interface,

dopant concentration in the crystal will $e *,+8

times the concentration of phosphorus in the

melt. Therefore, in order to achiee a gien

dopant leel in the crystal, the dopant

concentration in the melt has to $e

appropriately higher.

5ost of elements hae segregation coefficient

less than unity. ue to this, only a part of

dopant is integrated into the crystal. The rest is

reected $ac' into the melt. "t results in dopant

accumulation in the melt as crystal growth

proceeds. "n turn, $ecause the concentration

increases in the melt, the dopant concentration

increases in the crystal as well.

The dopant concentration in the crystal will $e

the lowest at the top end and the highest at the

$ottom end of the ingot. )n example of a

dopant concentration profile along crystal is

illustrated on the graph $elow. Aeay metals

hae ery low segregation coefficients which

results in further material purification.

le(ent Se6re6ation

*oe""i!ient

7e *,*****<

)u *,****28

Ni *,****+

&u *,***/

N *,***:S$ *,*2+

& *,*:

)s *,+

( *,+8

*,<

O 1,28

le(ent Se6re6ation

*oe""i!ient

7e *,*****<

)u *,****28

Ni *,****+

&u *,***/

N *,***:S$ *,*2+

& *,*:

)s *,+

( *,+8

*,<

O 1,28

m e t a l s

d o p a n t s



Single Crystal Ingot



ppenix

&lean !ooms

Some Special 0nits

Cha&ter $ O"er"ie)

ntrou!tion


Sili!on



&rystalline efects

oping

Silicon 3afer

Silicon O$taining


a"er anu"a!turin6



Etching 5achine

ac'side Treatment

&V E6uipment

(olishing


"nspection

Scru$$ing

7inal "nspection

pitaxy

Epitaxial !eactor



&%ochrals'i (uller





&ropped "ngot



Ingot Sha&ing and Testing

The pulled ingot is cut into indiidual sections. This operation is

called cropping. Each section is examided for defects. )lso, the

ends of the ingot are remoed.

Lray source

etector

uring the cropping of the crystal, a few thin slices are remoed for

testing. 0sually resistiity profiles, oxygen and car$on

concentration and crystallographic defects are tested. The set of

slices allows to erify the ariation of measured parameters.

The crystal section is placed in the grinding machine and the

machine grinds down the crystal until the target diameter of the

cylinder is reached.

&rystallographic orientation of the cylinder axis is gien $y the seed

orientation. To identify a radial crystallographic orientation of the

crystal a flat is ground into it. Mnowing the orientation, the position

of the flat is accurately determined $y Lray diffraction.

The photograph of finished silicon single crystal cylinder with flat is

on the next slide.


24/43

Silicon V2.1 En 2/

Cro&&ed Ingot


25/43

Silicon V2.1 En 28

ppenix

&lean !ooms

Some Special 0nits

Cha&ter . O"er"ie)

ntrou!tion


Sili!on



&rystalline efects

oping

Silicon 3afer

Silicon O$taining


a"er anu"a!turin6



Etching 5achine

ac'side Treatment

&V E6uipment

(olishing


"nspection

Scru$$ing

7inal "nspection

pitaxy

Epitaxial !eactor



&%ochrals'i (uller





*roppe n6ot


26/43

Silicon V2.1 En

Wafer Manufacturing

The first step in the production of silicon wafers from

a crystal ingot is sawing. ) graphite $eam is attached

to the crystal with an adhesie to hold the wafer after

the saw $lade has cut through the ingot.

V"EO +82 x 2


27/43

Silicon V2.1 En

Wafer Edge ,rinding

)fter sawing, the wafers hae an edge with

sharp corners. The edge is ground to form a

$ullet shaped edge. This increases edge

strength and ma'e the edges less prone tochipping in later processing.

#ow speed

Aigh speed

The wafer is placed on acuum chuc' and

slowly turned as the grinding wheel, which is

rotating at high speed, is forced against the

wafer edge.

The grinding wheel is a disc with grooe of

desired I$ullet noseI shape of wafer edge. There

are em$edded diamond particles in the grooe.


28/43

Silicon V2.1 En

!ou'le%Sided La&&ing

The next step in wafer production is called

lapping. (urpose of this step is to ma'e wafer

surface smooth, flat and parallel.

uring lapping, wafers are placed in a carrier and

are drien $etween two cast iron made lapping

plates. The carrier is thinner than the wafers

allowing $oth sides of the wafer to $e lappedsimultaneously.

)n a$rasie slurry aluminium oxide )l2O+

suspended in water with surfactant- is fed to the

wafers surface as they are moed $etween the

lapping plates. This remoes the silicon andleaes $ehind a more uniform surface. 3afers

are ery flat $ecause the lapping plates are

extremely flat.

The silicon wafers in carriers and the $ottom

lapping plate are isi$le on the dou$le sided

planetary lapper ideo. To see the wafers

moement the upper lapping plate is lifted fordemonstration. )t the end of the ideo there is

the complete machine during the lapping

process.

V"EO +82 x 2


29/43

Silicon V2.1 En

Relative et!+in6 rates vs. ti(e

Time ,Stoc' !emoal-

E t c h r a

t e

)cid

)l'aline

Stress Relief Etching

Since lapping allows only to remoe the $ul'

of the saw damage and always leaes a thin

uniform layer of damage, some other

method must $e used to remoe the

damage from lapping. This damage needs

to $e remoed while causing as little

additional damage as possi$le. Typically, the

chemical etching is used.

One method of etching the wafers is the use

of an al'aline hydroxide, such as potassium

hydroxide MOA-. "n this method, the wafers

are dipped in MOA and water mixture for

a$out 2 minutes. The mixture is usually at

eleated temperature of a$out 1**?&. Then

the wafers are dipped into a " water $ath to

stop any remaining reaction.

)nother form of etching used on silicon

wafers is acid etching. ) common mixture

used for acid etching is ANO+ and A7.

Sometimes, additional chemicals are added

to the mixture to ma'e the reaction more

controlla$le. "n any case, the acid etching

process is a igorous process which needs

tight control as it has no self limiting

properties.

The figure $elow shows a relatie

comparison of the etch rates of a typical

acid and a typical al'aline etch. "t can $e

seen that the acid etch continues to etch

silicon wafer at a high rate for as long as the

two are 'ept in contact. Therefore the acid

etch must $e controlled ery closely to end

up with an accepta$le wafer.

"n $oth forms of etching, al'aline and acid,

there are adantages and disadantages to

choosing a specific form. The ta$le on the

$ottom left side shows a comparison.

The picture of a chemical etching e6uipment

and chemical $ath is on the next slide.

Si H A2O H 2MOA M2SiO+ H 2A2

)l'aline Etching

)cid Etching

+Si H /ANO+ H 1


30/43

Silicon V2.1 En

Etching Machine


31/43

Silicon V2.1 En

/ac+side Treat0ent

7or wafers that are highly doped and are

going to go through a high temperature

process, a layer is deposited on the $ac'

side of the wafer to preent the dopant fromout diffusing.

Silicon dioxide can $e used as a $ac'seal.

The layer is deposited on the wafer $y

chemical apor deposition. The oxide acts

strictly as a sealant.

(olysilicon on the $ac'side preents out

diffusing as well as getters heay metals

from the $ul' of the wafer. Normally a silane

SiA/- source is used for polysilicondeposition.

) $atch of silicon wafers in carrier prepared

for deposition is on the $ottom picture. ou

can see a chemical apor deposition

e6uipment on the next slide.

Oxide eposition

SiA/ H O2 SiO2 H 2A2/2*?&

(olysilicon eposition

SiA/ Si H 2A292*?&


32/43

Silicon V2.1 En

CV! E1ui&0ent


33/43

Silicon V2.1 En

Slurry

olishing

The purpose of wafer polishing is to produce a ery

smooth, flat, damage free silicon surface. The

polishing step is, unli'e lapping, a

chemical@mechanical process. This difference is thereason polishing produces a much smoother final

surface than lapping.

One of the polishing techni6ues is the template

mounting method. The wafers are situated in a round

template attached on a carrier and set on a soft

polyurethane insert in the template. The insert has aporous structure. 3hen the wafer is pressed against

the water soa'ed insert, it is held against it.

) polishing pad is mounted on the $ottom plate. The

soft insert is necessary to hold the wafers in place

when the wafers are mounted to the polishing

e6uipment with the surface facing down. The $ottomplate and carriers are rotating around their own axis.

The ideo shows the wafers unloading right after

polishing. ) polishing e6uipment is shown on the

next slide.

Slurry "or Sili!on Polis+in6The polishing slurry consists of

silica silicon dioxide, SiO2-particles in a6ueous suspension

with an organic al'ali

and a surfactant.

ottom plate

(olishing pad

3afer "nsert&arrier

Template


34/43

Silicon V2.1 En

olishing Machine


35/43

Silicon V2.1 En

Che0ical Cleaning

)fter the wafers hae $een polished, they hae a

large num$er of contaminants on the surface. "n

general, these contaminants are particles, organic

residuals and metallic ions. The chemical cleaning

is designed to remoe them.


36/43

Silicon V2.1 En

Ins&ection

)fter the wafers hae $een polished and cleaned,

they are ready to $e inspected. uring the

inspection process, the resistiity and geometrical

parameters are measured $y noncontactmethods. V"EO +82 x 24(ax - 4(in? ; 2

Tmax

3afer

Tmin

V @ (ax - (inR @ +(ax - +(in

hmax

3afer

hmin

Vacuum

chuc'


37/43

Silicon V2.1 En

V"EO +82 x 2


38/43

Silicon V2.1 En +<

3afer iameter 1**, 128, 18* mm

TTV F 8 Pm

T"! F / Pm

3)!( F +* Pmtypical for 1** mm wafers-

(articles G*,8 Pm F 8

5etal &ontamination ≤ +x1*1* atoms@cm2

inal Ins&ection

"or (ore spe!i"i!ation# 777.terosil.!o(


39/43

Silicon V2.1 En +C

ppenix

&lean !ooms

Some Special 0nits

Cha&ter 2 O"er"ie)

ntrou!tion


Sili!on



&rystalline efects

oping

Silicon 3afer

Silicon O$taining


a"er anu"a!turin6



Etching 5achine

ac'side Treatment

&V E6uipment

(olishing

(olishing 5achine

&hemical &leaning

"nspection

Scru$$ing

7inal "nspection

pitaxy

Epitaxial !eactor



&%ochrals'i (uller





&ropped "ngot


40/43


41/43

Silicon V2.1 En

E&ita-ial Reactor

/2


42/43

Silicon V2.1 En /2

E&ita-ial Layer

Characteristics

3afer iameter 1**, 18* mm

Epi #ayer Thic'ness + 8* Pm

Epi #ayer !esistiity + 8* Ωcm

"or (ore spe!i"i!ation# 777.terosil.!o(


43/43

ppenix

&lean !ooms

Some Special 0nits

Cha&ter 3 O"er"ie)

ntrou!tion


Sili!on



&rystalline efects

oping

Silicon 3afer

Silicon O$taining


a"er anu"a!turin6



Etching 5achine

ac'side Treatment

&V E6uipment

(olishing

(olishing 5achine

&hemical &leaning

"nspection

Scru$$ing

7inal "nspection

pitaxy

Epitaxial !eactor



&%ochrals'i (uller



Segregation &oefficient

Single &rystal "ngot


&ropped "ngot
http://var/www/apps/conversion/tmp/scratch_7/

silicon wafer preparation

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