silicon wafer thinning to reveal cu tsv - semi mauer - silicon wafer... · • wet etch process to...
TRANSCRIPT
![Page 1: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/1.jpg)
1
Silicon Wafer Thinning to Reveal Cu TSV (Innovation in Middle End Process Cu Via Reveal)
Laura Mauer, John Taddei, Ramey Youssef, Elena Lawrence
European 3D TSV Summit
Grenoble January 22-23,2013
Solid State Equipment LLC
![Page 2: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/2.jpg)
Outline
• Wafer thinning to reveal Cu TSV
• Silicon etch with KOH
• Integrated Wafer Thickness Measurement
• Process Results
• Summary
2
![Page 3: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/3.jpg)
Background
• High cost of TSV processes
• Opportunity to lower costs and improve manufacturing productivity
– Wet etch to reveal TSV
– Integrated Metrology
– Endpoint Detection
Develop Low Cost Wet Etch Process with Integrated Metrology
![Page 4: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/4.jpg)
Wafer Thinning to Reveal TSV
4
![Page 5: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/5.jpg)
TSV Reveal, Protect and Planarize
5
carrier
adhesive
Silicon thickness Via depth
carrier
adhesive
carrier
adhesive
Post Grind After Si Etch – TSV Revealed
Oxide/Nitride deposition to
protect Si surface from Cu
carrier
adhesive
Surface planarized and Cu vias exposed
![Page 6: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/6.jpg)
TSV Reveal: Process Options post Grind
6
![Page 7: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/7.jpg)
Why KOH as etchant?
• Requirements for Etchant: – Good etch rate for Silicon
– Does not etch SiO2 or Copper
• Possible Candidates:
– Higher etch rate for KOH
Faster single wafer process
Higher throughput and lower CoO
Silicon Etch Rate (µm/minute)
TMAH 0.3-0.5
KOH 1.5-2.0
![Page 8: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/8.jpg)
• Device wafer on carrier
• Grinding process used to get within 10-20µm of Cu TSV
• Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner
Wafer Thinning to Reveal Cu TSV
carrier
adhesive
carrier
adhesive
Silicon thickness Via depth Etch target
8
![Page 9: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/9.jpg)
Integrated Thickness Measurement
• Need to know – Silicon thickness post grind
– Uniformity of Silicon
– Via depth
• Use of integrated measurement provides – Silicon thickness and radial thickness variation
– Etch rate feedback from previous wafer
• Determine amount of Silicon to etch – Average silicon thickness to be removed
– Radial profile of etch
– Assume 2µm reveal height
Table shows large variation in amount of
Silicon to be etched depending upon post
grind thickness and via depth
carrier
adhesive
Silicon thickness Via depth
Example
![Page 10: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/10.jpg)
Single wafer spin etching
• Post Grind non-uniformities can have radial dependence – Center to edge variations
• Single wafer etch process can compensate for radial non-uniformities – More/Less etch in center of wafer
• Resulting Silicon wafer thickness is more uniform
Post Grind
Post Silicon Etch
10
![Page 11: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/11.jpg)
Wafer Thinning to Cu TSV
11
![Page 12: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/12.jpg)
KOH etching of Silicon requires Post Clean
12
Post Etch Post Clean
![Page 13: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/13.jpg)
Wet Etch TSV Reveal – post clean
VPD-ICPMS measurements indicate the cleaning process is
effective at removing the residual Potassium from the etch process.
![Page 14: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/14.jpg)
TSV revealed post etch and clean
14
![Page 15: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/15.jpg)
15
TSV revealed post etch and clean
![Page 16: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/16.jpg)
FIB section – after TSV reveal
16
![Page 17: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/17.jpg)
Wafer Thinning to Cu TSV
17
![Page 18: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/18.jpg)
Wafer Thinning to Cu TSV
18
![Page 19: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/19.jpg)
19
Surface Roughness after Grind
![Page 20: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/20.jpg)
Surface Roughness post KOH etch
20
![Page 21: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/21.jpg)
Wafer Thinning to Cu TSV
EDX analysis shows the oxide liner and Cu via remain intact
21
![Page 22: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/22.jpg)
Integrated Wafer Thickness Measurement:
Process Control
• Create map before etch
• Create map after etch
• Compute etch rate
• Compute etch uniformity
• Spike chemistry
• Determine etch time
22
![Page 23: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/23.jpg)
Integrated Wafer Thickness Measurement
![Page 24: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/24.jpg)
Integrated Wafer Thickness Measurement
24
![Page 25: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/25.jpg)
Wafer Thickness Measurements
25
SSEC Integrated Sensor Graphics ISIS SemDex Graphics
![Page 26: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/26.jpg)
Integrated Wafer Thickness Measurement
- mapping options
26
Ring map Surface map
![Page 27: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/27.jpg)
Cost comparison
27
![Page 28: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/28.jpg)
TSV wafer post wet etch reveal
Optical
SEM
Illustration of wafer with revealed TSVs after
wet etch and clean processes
![Page 29: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/29.jpg)
Summary
• Process demonstrated to etch silicon and safely reveal Cu TSV
• Clean silicon surface and isolated Cu TSVs
• Integrated Wafer Thickness Measurement for process control
• Low cost of ownership
29
![Page 30: Silicon Wafer Thinning to Reveal Cu TSV - SEMI Mauer - Silicon Wafer... · • Wet etch process to reveal Cu TSV – Use of KOH to etch Silicon without attack of Cu via or Oxide liner](https://reader030.vdocument.in/reader030/viewer/2022040103/5e555691609b6740487cdc5e/html5/thumbnails/30.jpg)
“Success is when Customers are Delighted.”
30