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Simulation for 3GPP LTE From Concept-to-Test

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Agenda

Mixed-Signal Design Challenges

Algorithm Design

RF Design

Mixed-Signal System Verification

R&D Hardware Testing

Summary

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Mixed-Signal Challenges: System Design Tradeoffs

Tx RxCodingAlgorithms

D/A

Bits In DecodingAlgorithms

Bits Out

ChannelA/D

GainLinearityPower

GainNFLinearity

Mixed-Signal Application Examples:• PAs ( polar loop, DPD)• Direct conversion receivers and A/D converters

Considerations:• Sampling Rates• Bitwidth• Key Algorithms• RF Gain, Linearity, NF• Channel Impairments and Interferers

Fixed-Point Digital Filter

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System Design Tradeoffs- Performance BudgetingSystem Design Tradeoffs for EVM & BER/PER

PANonlinearities

RF Upconverter/ Downconverter

Baseband HWBitwidth

LOs(Phase Noise)

Tx RxCodingAlgorithms

D/A

Bits In DecodingAlgorithms

Bits Out

RF ChannelA/D

ChannelCompensation

With LTE having such high performance targets every part of the transmit and receive chain becomes critical to the link budget

So how to decide the optimum balance?

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System Design Flow Challenges...several teams, disconnected tools

RF

Ana

log

Dig

ital

ConceptCritical algorithms, top-level behavior

ArchitectureHW/SW, digital/RFpartitioning

FunctionBlock behavioral design

ComponentCircuit design, layout

M1 C1 M2

H1(s)

ENC

OD

E

System Architect

Algorithm Design

Algorithm and Circuit

Implementers

Implementation Handoff

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Agilent ESL Tools for Mixed Signal Design

Production

Partition

Refine

Integ

rate

Verify

SystemVue

AlgorithmDesign

Functional Design

ComponentFirmwareDesign

ComponentVerification

ADS

SystemArchitecture System

Verification

PrototypeVerification

Wireless Libraries

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Agenda

Mixed-Signal Design Challenges

Algorithm Design

RF Design

Mixed-Signal System Verification

R&D Hardware Testing

Summary

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SystemVue Algorithm and Fixed-Point AnalysisEvaluate fixed-point resolution on system performance in one summary table

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SystemVue HDL Code Generation

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SystemVue Example- LTE IQ Modulator

LTE IQ Data from ADS LTE

Wireless Library

HDL CodeExport HDL

with HDSTo ADS for

HDL Co-Simulation

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Agenda

Mixed-Signal Design Challenges

Algorithm Design

RF Design

Mixed-Signal System Verification

R&D Hardware Testing

Summary

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Agilent Advanced Design System for RF Design & Verification

Design

Verif

icat

ion

Simulated and real world analysis

Simulated and real world signal inputs

RF/Analog Subsystem

Transistor-levelRF sub-System Designer

RF Circuit Designer

ADS Ptolemy Top Level

ESG / MXG MXA PSA Infiniium Logic Analyzer

DC Power Analyzer

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ADS Example: RF Transmitter Design

ADS LTE Downlink Source

ADS LTE DownlinkEVM Measurement

Set UE Constellation Types forQPSK, 16QAM, or 64QAM

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Perform System-Level Design Tradeoffs for EVMTrade-Off for EVM Budgeting:- Bitwidth of RRC filter- Phase noise of LO- 1dB compression point of PA

Phase noise (dBc/Hz) vs. frequency offset

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Initial RF System Performance with Fixed-Pt RRCLTE Downlink

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Initial RF System Performance with Fixed-Pt RRCLTE Uplink

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LTE DL Receiver Design with Swept Phase Noise

Swept SNRSwept Phase

Noise

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LTE DL Receiver Uncoded BER ResultsUE 1 Set for QPSK, 16 QAM, and 64 QAM

UE1: QPSK UE1: 16 QAM UE1: 64 QAM

Phase Noise Swept from -60 dBc/Hz to -80 dBc/Hz @ 10kHz offset

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Comparing Coded LTE BER vs. Uncoded LTE BERPhase Noise Swept from -60 dBc/Hz to -80 dBc/Hz @ 10kHz offset

-60 dBc/Hz

-70 dBc/Hz

-80 dBc/Hz

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Comparing LTE and WiMAX™ BER(Using same RF Receiver Design)

Swept SNR

Swept PhaseNoise

“WiMAX,” “Mobile WiMAX” and “WiMAX Forum” are trademarks of the WiMAX Forum®

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Comparing Coded WiMAX BER to Coded LTE BERPhase Noise Swept from -60 dBc/Hz to -80 dBc/Hz @ 10kHz offset

-60 dBc/Hz

-70 dBc/Hz-80 dBc/Hz

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Agenda

Mixed-Signal Design Challenges

Algorithm Design

RF Design

Mixed-Signal System Verification

R&D Hardware Testing

Summary

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Agilent Advanced Design System for Baseband Verification

Design

Verif

icat

ion

Simulated and real world analysis

Simulated and real world signal inputs

DSP Floating or Fixed Point

RTL HDLwire [6:0] M1_B_1_Result; // hpeesof_id : M1.B_1wire [9:0] M1_B_2_Result; // hpeesof_id : M1.B_2

hp_CONST_S C5 (.Result(C5_Result));defparam C5.Width = 3;defparam C5.ConstValue = 24576;

hp_ADD_SATTRUNC_S A5 (.A(R4_R1_Q),.B(M3_Result),.Result(A5_Result));

ADS Ptolemy Top Level

ESG / MXG MXA PSA Infiniium Logic Analyzer

DC Power Analyzer

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• Support of leading hardware description languages• Support for System-C• Fixed point digital filter synthesis & verification

• Support of leading hardware description languages• Support for System-C• Fixed point digital filter synthesis & verification

DSP/System Verification Through Co-Simulation

DSP Floating or Fixed Point

RTL HDLwire [6:0] M1_B_1_Result; // hpeesof_id : M1.B_1wire [9:0] M1_B_2_Result; // hpeesof_id : M1.B_2

hp_CONST_S C5 (.Result(C5_Result));defparam C5.Width = 3;defparam C5.ConstValue = 24576;

hp_ADD_SATTRUNC_S A5 (.A(R4_R1_Q),.B(M3_Result),.Result(A5_Result));

VerilogVHDL

Fixed Point Digital Filter Verification

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Conceptual: Using ADS Wireless Libraries for Algorithm Verification

ADS Wireless Library 10010110 01110110m-code 10010110 01110110HDL code 10010110 01111110

Bit Reversal Detected !

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Algorithm Reference Schematic:Compare ADS CRC to FPGA HDL Code to m-code

HDL Co-Simulation

MATLAB® Co-Simulation

ADS LTE Reference Algorithm

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ADS_Reference

0.0001.0001.0001.0000.0001.0001.0000.0001.0000.0000.000

MATLAB_CoSim

0.0001.0001.0001.0000.0001.0001.0000.0001.0000.0000.000

HDL_CoSim

0.0001.0001.0001.0000.0001.0001.0000.0001.0000.0000.000

10 20 30 400 50

0.2

0.4

0.6

0.8

0.0

1.0

ADS_

Ref

eren

ceM

ATL

AB_

CoS

imH

DL_

CoS

im

Algorithm Reference Results:Compare ADS CRC to FPGA HDL Code to m-code

No Errors Detected

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Mixed-Signal System Verification Example:LTE HDL Co-Simulation with RF Ckt Co-Simulation

HDL Generated withSystemVue HDS3

FPGA Target RF Amplifier

SystemVue IQ Modulator with ADS

LTE IQ Data

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LTE IQ Mod HDL with RF Ckt Co-Sim Results

ADS-VSA Simulation ResultIncludes Baseband & RF

Impairments

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Demo

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Agenda

Mixed-Signal Design Challenges

Algorithm Design

RF Design

Mixed-Signal System Verification

R&D Hardware Testing

Summary

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Typical Double Conversion Transceiver

Q

I

Q

I

0

ReceiverTransmitter

Modulator

Modem Modem

Demodulator

RF IFPAIFBaseband

CodingBasebandDe-Coding

Bits In Bits Out

Sent BitsErrorsBER =

BER: Example System Diagram

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Demodulator

RF IF

BasebandDe-Coding

RF/RF BER

A/DConverter

I

Q

Where can R&D BER Measurements be Performed?

Simulated Portion of System Design

MXG, ESGMXA*, PSA

ADS, VSA SW

*Note: Different Analyzer(s) may be used, dependent on required capture depth

Simulated

Step 1Download

Signal

Step 2Capture Signal

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Demodulator

RF IF

BasebandDe-Coding

RF/IF BER

A/DConverter

I

Q

MXG, ESGMXA*, PSA

ADS, VSA SW

Where can R&D BER Measurements be Performed?

Simulated Portion of System Design

*Note: Different Analyzer(s) may be used, dependent on required capture depth

Simulated

Step 1Download

Signal

Step 2Capture Signal

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Demodulator

RF IF

BasebandDe-Coding

A/DConverter

I

Q

Where can R&D BER Measurements be Performed?

Simulated Portion of System Design

MXG, ESG

ADS, VSA SW

RF/Digital IF BER

Logic Analyzer

SimulatedI

Q

I Q

Step 1Download

Signal

Step 2Capture Signal

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RF IFBaseband

Demodulation and De-Coding

A/DConverter

IF

Where can R&D BER Measurements be Performed?

Simulated Portion of System Design

MXG, ESG

ADS, VSA SW

RF/Digital IF BER

Logic Analyzer

Simulated

Step 1Download

Signal

Step 2Capture Signal

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BasebandDe-Coding

BasebandEncoding

Where can R&D BER Measurements be Performed?

SimulatedSimulated

Digital/Digital BER

ESG + N5102, or Logic Analyzer withPattern Generator Board

Logic Analyzers

ADS, VSA SWStep 1

Download Signal

Step 2Capture Signal

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Mixed-Signal R&D Testing Example: ADS, ESG, LA, N6705A (Application Example- ADS not shipped with LA)

16822ALogicAnalyzer

N6705PowerSupply

E4438CESG

ESG

A/D Converter DUT

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Test Setup Diagram

Trigger In

16822 Logic Analysis

System withADS SW installed

14-Bit A/DConverter

Board (DUT)

LAN Cable

Event 1 Marker Out

Analog In

Clk In

30.72 MHzDig.Out

ESG

ADS-Arb LTE Signal at 10 MHz IF

Download ADS LTESignal via LAN

ADS LTE LibraryESG E4438C

USB-GPIB

Converter

+ 3.3V + 5V

N6705A DC Power Analyzer

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ADS Schematic in Logic Analyzer(Application Example- ADS not shipped with LA)

Mixed-SignalDUT

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LTE Measurement Results- Uplink

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LTE Measurement Results- Downlink

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LTE Measurement Results-Swept Downlink Uncoded BER

1 % BER at approx. -56 dBmat + 5V bias andat approx. -54 dBmAt +4.3V bias

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FPGA R&D Testing Example: ADS, MXA, LA (Application Example- ADS not shipped with LA or MXA)

16822A Logic16822A LogicAnalyzer + Analyzer + VSA SWVSA SW

FPGA DUT*FPGA DUT*

MXA MXA SignalSignal

AnalyzerAnalyzer

*Note: FPGA Implemented with HDL shown in mixed-signal simulation;See appendix for FPGA implementation flow used

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• Performed system-level design trade-offs vs. phase noise, bit width, PA non-linearities

• Compared and contrasted LTE uncoded BER vs. coded BER

• Compared and contrasted LTE DL OFDMA coded BER with WiMAX™ DL OFDMA coded BER

• Showed how to verify existing RF designs for compatibility with both LTE and WiMAX™ by using the ADS Wireless Libraries

• Combined simulation with test equipment to perform measurementson mixed-signal and FPGA hardware for R&D testing

Summary

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Additional InformationAgilent LTE main sitewww.agilent.com/find/lte

Webinar- Concepts of 3GPP LTE http://www.techonline.com/learning/webinar/201801263

Webinar- Addressing the Design & Verification Challenges of LTE http://www.techonline.com/learning/webinar/201802528

Webinar- Understanding SC-FDMA –The New LTE Uplinkhttp://seminar2.techonline.com/s/agilent_mar2008

Advanced Design System:http://eesof.tm.agilent.com/products/e8895a-new.html

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Appendix

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FPGA Implementation and Test Flow

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RF R&D Testing Example: ADS, MXG, MXA (Application Example- ADS not shipped with MXA)

MXA SignalAnalyzer

MXG SignalSource

AmplifierDUT *

* Note: Different DUT than simulated amplifier used in case study

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ADS Connected Solutions Schematic in MXA(Application Example- ADS not shipped with MXA)

RFDUT

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DUT Test Results: Swept-Power EVM

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DUT Test Results: Swept-Power Uncoded BER

Downlink

Uplink

*Note: Different Analyzer(s) may be used, dependent on required capture depth

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RF- RF/IF Test Equipment ConfigurationSimulation ADS 2008A Update Release 1 with Agilent Ptolemy Simulator (E8823) ADS 3GPP LTE Wireless Library (E8895) ORADS Mobile WiMAX Wireless Library (E8869)

Signal SourceN5182A MXG with options:

- 506 (Freq. range 100kHz to 6 GHz)- 652 (Internal BB generator 60 MSa/s, 8 MSa) , or- 654 (Internal BB generator 125 MSa/s, 8 MSa)

ORE4438C ESG with options:

- 506 (6 GHz Freq. range)- 602 (Internal BB generator 64MSa)

Signal Analyzer89600 VSA Software (version 8.0 or later) with options:

- 105 (Dynamic link to ADS)- BHD (LTE modulation analysis) OR- B7Y (802.16 OFDMA modulation analysis)

N9020A MXA with options - B25 (25 MHz bandwidth)- 508 (Freq. range 20 Hz to 3.6 GHz)

ORE4443A PSA with options

- 140 (40MHz bandwidth digitizer ) OR- 122 ( 80MHz bandwidth digitizer, 128MSa capture depth)

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RF- Baseband Test Equipment ConfigurationSimulation ADS 2008A Update Release 1 with Agilent Ptolemy Simulator (E8823) ADS 3GPP LTE Wireless Library (E8895) ORADS Mobile WiMAX Wireless Library (E8869)

Signal SourceN5182A MXG with options:

- 506 (Freq. range 100kHz to 6 GHz)- 652 (Internal BB generator 60 MSa/s, 8 MSa) , or- 654 (Internal BB generator 125 MSa/s, 8 MSa)

ORE4438C ESG with options:

- 506 (6 GHz Freq. range)- 602 (Internal BB generator 64MSa)

Signal Analyzer89600 VSA Software (version 8.0 or later) with options:

- 105 (Dynamic link to ADS)- BHD (LTE modulation analysis) OR- B7Y (802.16 OFDMA modulation analysis)

16800 Series Logic Analyzer with option 032 (32 MSa capture depth)OR16900 Series Logic Analyzer with option 032 (32 MSa capture depth) or option 064 (64 MSa capture depth)