simulation study goals
DESCRIPTION
Simulation Study Goals. Use existing 160x18 FPIX Verilog model to create a 128x22 and a 128x24 model. Determine max RCLK frequency for each of the three array sizes. Compare performance of the three array sizes in terms of efficiency at 0.5, 1, 2, 4, and 6 interactions per crossing. - PowerPoint PPT PresentationTRANSCRIPT
B. Hall April 6, 2001 Pixel Readout Page 1
Simulation Study Goals
• Use existing 160x18 FPIX Verilog model to create a 128x22 and a 128x24 model.
• Determine max RCLK frequency for each of the three array sizes.
• Compare performance of the three array sizes in terms of efficiency at 0.5, 1, 2, 4, and 6 interactions per crossing.
• Analyze performance of 6 chip module of 128x22 FPIX chips.
• Get new estimate of number of serial lines required based on proposed periphery serialization technique.
B. Hall April 6, 2001 Pixel Readout Page 2
Max RCLK
• Created a worst case pattern for vertical token passing: hit in top pixel and hit in bottom pixel in same BCO and same column.
• A setup violation occurs if the period of RCLK is less than the time it take the token to be released from the top pixel to the time it gets to the bottom pixel.
Array Size Max RCLK160x18 29.07Mhz128x22 34.72Mhz128x24 34.72Mhz
B. Hall April 6, 2001 Pixel Readout Page 3
Input Files
• Dave provided input files (pixel hits) for 0.5, 1.0, 2.0, 4.0, and 6.0 interactions per crossing.
Ave Interactions Ave Num Ave Hit Ave Num Ave Hit Ave Num Ave Hit
Per Crossing BCOs Hits per BCO Size (pixels) Hits per BCO Size (pixels) Hits per BCO Size (pixels)0.5 20298 0.3 3.1 0.3 3.1 0.3 3.11 10071 0.6 3.3 0.7 3.3 0.7 3.42 4986 1.3 3.6 1.3 3.6 1.4 3.74 2546 2.5 4.4 2.6 4.4 2.7 4.66 1677 3.8 5.2 3.9 5.3 4.2 5.5
160x18 128x22 128x24
B. Hall April 6, 2001 Pixel Readout Page 4
Results
Adjusted Efficiency Summary
160x18 128x22 128x22 128x24 128x24Hits.dat File @ 29.07Mhz @ 29.07Mhz @ 34.72Mhz @ 29.07Mhz @ 34.72Mhz
0.5 99.92% 99.94% 99.94% 99.94% 99.94%1 99.81% 99.85% 99.85% 99.87% 99.87%2 99.68% 99.68% 99.71% 99.71% 99.76%4 98.97% 99.15% 99.48% 99.05% 99.40%6 91.36% 90.93% 97.58% 87.62% 96.65%
B. Hall April 6, 2001 Pixel Readout Page 5
Results
Adjusted Efficiency
60.00%
65.00%
70.00%
75.00%
80.00%
85.00%
90.00%
95.00%
100.00%
0.5 1 2 4 6
Average Interactions per Crossing
Ad
jus
ted
Eff
icie
nc
y
160x18 @ 29.07Mhz
128x22 @ 29.07Mhz
128x22 @ 34.72Mhz
128x24 @ 29.07Mhz
128z24 @ 34.72Mhz
B. Hall April 6, 2001 Pixel Readout Page 6
6 Chip Module Simulation
-0.16c m 0.76c m 1.68c m 2.60c m 3.52c m 4.44c m
C hip1
C hip2
C hip3
C hip4
C hip5
C hip6
Be a m
• Dave provided input files (pixel hits) for Chips 1, 2, 3, 4, 5, and 6 at 6 interactions per crossing.
B. Hall April 6, 2001 Pixel Readout Page 7
6 Chip Module Input Hits Summary
Chip Center Entries Ave HitChip in x (cm) (Hits) Per BCO Ave Hit*
1 -0.16 6391 3.811 5.2602 0.76 4263 2.542 4.1673 1.68 1797 1.072 3.1924 2.6 811 0.484 2.4885 3.52 436 0.260 2.4366 4.44 342 0.206 2.295
* Ave number of hits in BCOs with 1 or more hits
B. Hall April 6, 2001 Pixel Readout Page 8
Pixel Readout
• Send two CLKs to each FPIX module
• CLKA & CLKB are of same frequency but 90deg out of phase.
B. Hall April 6, 2001 Pixel Readout Page 9
Serialization Technique
DCBalanceEncoder
23 29 AddWord Mark
Bit
30 SSR
SCLK
23 bit Word @ RCLK
Return CLK
SerData1
RCLK = SCLK/30
• Periphery serialization BW equals the peak data rate out of the core….no need for buffering (never any data loss in periphery) or data compression.
• Set the core clock frequency (RCLK) so that the core peak data rate equals the serializer(s) BW. RCLK will be fast (34.72Mhz max) for hot chips, and slow for cold chips.
Possible FPIX Periphery w/ single serial line
B. Hall April 6, 2001 Pixel Readout Page 10
Serialization
DCBalanceEncoder
23 29 SSR
SCLK
23 bit Word @ RCLK
AddWord Mark
Bit
SSR
Return CLK
SerData1
SerData2
15
14 15
RCLK = SCLK/15
DCBalanceEncoder
23 29 SSR
SCLK
23 bit Word @ RCLK
AddWord Mark
Bit
SSR
Return CLK
SerData2
SerData3
10
9 10
SSR SerData110
RCLK = SCLK/10
FPIX Periphery w/ 2 serial lines and 3 serial lines
B. Hall April 6, 2001 Pixel Readout Page 11
Serialization
DCBalanceEncoder
23 29 SSR
SCLK
23 bit Word @ RCLK
AddWord Mark
Bit
SSR
Return CLK
SerData5
SerData6
5
4
SSR SerData45
SSR SerData35
5
SSRSerData2
5
SSRSerData1
5
RCLK = SCLK/5
FPIX Periphery w/ 6 serial lines
B. Hall April 6, 2001 Pixel Readout Page 12
Serialization
With SCLK = 173.6MhzSerial Lines RCLK Div RCLK (Mhz)
6 5 34.725 6 28.934 8 21.73 10 17.362 15 11.571 30 5.79
• Assuming max RCLK frequency allowed is 34.72Mhz and max number of serial lines allowed is 6….serialization clock must be 34.72Mhz * 5 = 173.6Mhz.
B. Hall April 6, 2001 Pixel Readout Page 13
Module Efficiency at 6 Interactions/Crossing (3x Nominal)
FPIX (128x22) Efficiency vs Serialization
34.72Mhz 28.93Mhz 21.70Mhz 17.36Mhz 11.57Mhz 5.79Mhz(6 serial) (5 serial) (4 serial) (3 serial) (2 serial) (1 serial)
Chip1 97.97% 92.74% 71.93% 58.07% 39.49% 20.79%Chip2 99.55% 99.01% 95.12% 83.56% 57.35% 31.03%Chip3 99.83% 99.83% 99.55% 99.39% 98.61% 71.34%Chip4 99.88% 99.88% 99.75% 99.75% 99.75% 99.01%Chip5 100.00% 100.00% 100.00% 100.00% 100.00% 100.00%Chip6 99.71% 99.71% 99.71% 99.71% 99.71% 99.71%
Dave's Proposed
Requirement (2/1/01) (6,6,5,2,1,1) (6,5,5,2,1,1) (6,5,3,2,1,1) (6,6,3,1,1,1)Inner Chip Efficiency >98.0% 97.97% 97.97% 97.97% 97.97%Efficiency of Balance >99.5% 99.67%* 99.37%* 99.57%* 99.49%*
* Weighted average
Simulation Results (serial lines)