Single-Event Characterization of XilinxUltraScale+r MPSOC under Standard andUltra-High Energy Heavy-Ion Irradiation

Maximilien Glorieux, Adrian Evans, Thomas Lange, A-Duong In, Dan Alexandrescu, Cesar Boatella-Polo,Ruben Garcıa Alıa, Maris Tali, Carlos Urbina Ortega, Maria Kastriotou, Pablo Fernandez-Martınez,

and Veronique Ferlet-Cavrois

Abstract—Heavy-Ion irradiation of a Xilinx Ultrascale+ MP-SOC was performed to measure Single-Event-Latch-up andSingle-Event-Upset Cross-Sections. Additionally, irradiation witha ultra high energy xenon beam shows similar upset sensitivity.

Index Terms—Single-Event-Effect, Radiation Testing, FPGA,Single-Event-Upset, Single-Event-Latchup

I. INTRODUCTION

As technology scales, configurable devices such as XilinxFPGAs and MPSOCs can be configured to implement increas-ingly complex applications. Additionally, new technologies,such as FDSOI and FinFETs, shows much lower singleevent effect sensitivity, than older bulk processes. Given theirresiliency and their affordable cost, new generation FPGAscompare very favorably to Application Specific IntegratedCircuits (ASICs).

II. TEST DESCRIPTION

A. Device Under Test CharacteristicsThe Xilinx Ultrascale+ devices are available in different de-

vice families. The Zynqrfamiliy embeds a high performanceprocessing system (PS), based on ARMrprocessors, and alastest generation FPGA, based on the Xilinx Ultrascale ar-chitecture. Many configurations of Zynq devices are available,with differences in the PS (number of CPU cores, maximumoperating frequency, presence of a video codec IP, ...) and theFPGA (number of logic slices, size and type of user memory,I/O pin count). The part selected for this test is the XCZU3EG-SFVA625-1-E. This component is a small device of the EGcategory of the Zynq family, meaning that its PS embeds 4ARM A53 APU cores and 2 ARM R5 RPU cores. However,the size of the FPGA is relatively small and advanced featuressuck as high-speed transceivers, DRAM memory controllerand UltraRAM are not available. It is a flip-chip device, whosemain core voltage is 0.85 V and its auxiliary voltage is 1.8V.Table I lists the main characteristics of the tested device.

The device under test was prepared for the heavy-ion irradi-ation by removing the lid and thinning the die to approximately70 µm by mechanical milling.

M. Glorieux, T. Lange, A-D. In and D. Alexandrescu are with IROCTechnologies, 38000 Grenoble, France.

C. Boatella-Polo, C. Urbina Ortega and V. Ferlet-Cavrois are with theEuropean Space Agency, ESTEC, 2200 AG Noordwijk, The Netherlands.

R. Garcia Alia, M. Tali, M. Kastriotou and P. Fernandez are with CERN,CH-1211 Geneve 23, Switzerland.

TABLE IMAIN CHARACTERISTICS OF THE XCZU3EG-SFVA625-1-E DEVICE

Feature ZU3EGProcessing SystemAPU 4x ARM CORTEXTM A53 - 1.5 GHzRPU 2x ARM CORTEXTM R5 - 0.6 GHzGPU ARM MALITM -400 MP2On-Chip Memory 256 KB, ECC ProtectedProgrammable Logic (FPGA)System Logic Cells 154,000CLB Flip-Flops 141,000CLB LUTs 71,000Maximum Distributed RAM 1.8 MbitTotal Block RAM 7.6 Mbit

B. Radiation Test Board

A custom test board, shown in figure 1, has been designed tofulfill the requirements of the radiation testing. On this board,the current consumption on each of the 19 power domains ofthe ZU3EG device was monitored independently, using shuntresistors. This independent current measurement allows thedetection of any sudden current increase, which is the typicalsignature of Single-Event-Latchup Events.

Fig. 1. Radiation Test Board designed for the XCZU3EG Device, with onede-lided device.

Additionally, the test board implements a reset managementcircuit which is used to reboot the device under test in thecase of a fatal error (uncorrectable FPGA CRAM error, CPUcrashes). It also embeds two QSPI flash memories, used tostore the software running on the PS and the configurationbitstream of the FPGA. Finally, a UART-to-USB chip is usedon the board to monitor and log the standard output of the PSduring the radiation tests.

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C. Implemented Design for Radiation Testing

The main objective of the radiation test campaign was tomeasure the SEL and SEU cross-section of the FPGA features(configuration and block memory, programmable logic).

In order to measure SEL cross-sections in worst caseconditions, all the I/Os were operating at the highest voltageI/O standard for each type of bank (1.8 V for HPIO and3.3 V for HDIO). Additionally, the voltage was increasedto the part’s maximum limit for each supply rails for SELtest conditions. SEL detection was based on the currentmeasurements performed on each of the power domains of theZU3EG device. Current and Voltage sampling was performed10 times per seconds during the heavy-ion irradiations.

The goal of the SEU testing was to measure the SEUcross-section of the configuration RAM (CRAM), the BlockRAM (BRAM), the Distributed RAM (DistRAM) and theuser flip-flops during irradiation of the ZU3EG device. Devicescrubbing, using the Xilinx SEM-IP solution, was enabledduring the radiation testing to report and correct SEUs oc-curring in the CRAM of the device under test. This approachhas several advantages compared to static irradiation duringwhich the configuration is readback regularly [1]: First, itavoids the accumulation of interval voltage contentions, dueto configuration errors, leading to a constant increase of thepower consumption of the core power domain. Second, it ismore representative of the real usage of an SRAM based FPGAin space applications. Third, it maintains a correct behavior ofthe device during the irradiation, allowing to measure SEUcross-section of user logical cells and memories. Finally, thecorrect operation of the Xilinx scrubbing solution and itscapability to maintain the expected logical behavior of thedevice can be validated during radiation testing.

The BRAM, DistRAM and flip-flops were tested concur-rently with to the CRAM, because the logic portion of theFPGA was sufficiently stable due to the scrubbing performedby the SEM-IP. Most of BRAM and DistRAM cells of thedevice were aggregated in two large memory arrays. Thesetwo arrays were tested by an external tester, using a dy-namic test algorithm and standard patterns (ALL1, ALL0 andCheckerboard). The FPGA flip-flops were tested using twoshift registers. The first one connects the output of one flip-flop directly to the input of the following one, by bypassingthe slice look-up table. The second register can be configuredeither as a standard shift register or a TMR shift register,with its depth divided by three. The selection between bothmodes and the voting logic are implemented using one look-up table of the device. The TMR is implemented using threeindependent voting circuits at each stage of the shift register,feeding into the three redundant flip-flops, to maximize itsrobustness, as reported in [2]. Note that the three redundantlogic cells of each stage were manually placed in threedifferent logic slices of the device to avoid MCU effects. SEUcross-sections of both shift registers were measured using adynamic test algorithm and standard logical patterns duringthe heavy-ion irradiations. The memory and flip-flop shiftertest algorithms were designed to detect and filter burst eventsinduced by upset occurring in the configuration RAM.

TABLE IIHEAVY-ION USED AT UCL FOR THE TEST OF ZU3EG DEVICE

Ion Energy Range LETSURF LETEFF

(MeV) (µm) (MeV.cm2/mg) (MeV.cm2/mg)C 131 269.3 1.3 1.5Ne 238 202 3.3 4Al 250 131.2 5.7 7.9Ar 379 120.5 10.0 12.8Ni 582 100.5 20.4 30.4Xe 995 73.1 62.5 17.2

During the radiation test, an FPGA based tester was used toreport and log the errors. Currents and voltages of the 19 powerdomains were measured and logged 10 times per seconds.SEL events was detected by the successive observation ofthree current samples with a value higher than a predefinedthreshold. In this case, the tester triggered a power cyclewhich lasted approximately one second. An effective heavy-ion fluence, considering the dead-times (power cycles, reset,time between successive memory read and write operations...),was calculated for each type of events and used to computethe associated cross-sections.

D. Heavy-Ion Test Facilities

1) Standard Heavy-Ions - UCL: Main heavy-ion tests wereperformed at UCL Heavy-Ion Irradiation Facility, at Louvain-La-Neuve, Belgium. UCL uses a cyclotron capable of acceler-ating heavy-ions up to an energy of 110 Q2/M . Table II liststhe heavy-ions used at UCL for radiation testing of the ZU3EGdevice, and their characteristics. For each ion, an effective LETwas computed using SRIM to consider the ion energy changeacross the 70 um silicon substrates. Note that the range ofthe Xe ion is closed to the thickness of the device undertest, leading to an effective LET lower than the one of theNi ion. Additionally, some non-negligible strangling effectsinduce some variability of the effective LET. Due to thesemeasurement uncertainties, the cross-sections measured withthe Xe ion were not taken into account while computing theWeibull fits.

2) Ultra-High-Energy Heavy-Ions - CERN: Additionally tothe standard heavy-ion tests, the ZU3EG device have beenirradiated with 30 GeV/n xenon beam, at CERN, in the H8 SPSNorth Area beam line. The xenon beam was directly extractedfrom the Super Proton Synchrotron (SPS). Ions acceleratedin the SPS can be extracted to the North Experimental Area(NA) with an energy range of 13-150 GeV/n. The beam isdelivered as a series of spills with a duration of 4.5 to 10seconds, depending on the configuration of the accelerator.The periodicity of the spills varied between 30 to 50 secondsduring the test. The delivery of the beam in spills willgenerate additional complexity (when compared to constantbeam experiments) during the result analysis phase, as we needto compute an effective fluence and dead time by carefullymonitoring the beam flux. Particularly, the test setup shouldbe able to handle and correctly discriminate from a temporalperspective the high number of errors that are induced duringa fast spill event.

The beam intensity was measured using a scintillator, lo-cated approximately 50 meters behind the device under test.

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Fig. 2. VCCAUX Power Domain Single-Event-Latchup Cross-Section ofXCZU3EG Device (Weibull fit: XSSAT =2.1e-4cm2; LETTH=6.11MeV ·cm2/mg; W=9.0; S=1.9)

Pulse height analysis techniques were used to determine thefraction of the scintillator counts corresponding to the primaryxenon beam. The remaining counts correspond to minimumionizing particle propagated with the beam and neglectedfor the SEE analysis due to their very low LET value. Theeffective LET of this 30 GeV/n Xe ions was evaluated at3.7 MeV · cm2/mg using FLUKA simulations[3] and at4.3 MeV · cm2/mg by measuring the main peak energydeposition on a diode.

An important difference between UCL and CERN test isthat the device under test used at CERN was not thinned (thelid was removed). This is not an issue for high-energy heavy-ions testing as the inelastic interaction length of the beamin silicon is roughly 6 cm. However, heavy-ion can generatenuclear reactions while going through the silicon substrate,which may lead to the generation of secondaries particles,which trough calculations were shown to have similar LETdistribution than that generated by high energy protons.

III. TEST RESULTS

This section presents SEL and SEU test results measuredon the ZU3EG device during both test campaigns. On all theplots, error bars include to 95% statistical confidence intervalsplus the dosimetry uncertainties (10% for UCL and 25% forCERN).

A. SEL Test Results

During the standard heavy-ion test campaign, SEL eventswere observed on VCCAUX , VCC PSAUX and VAUXIO powerdomains, for all ions with an LET above than 5.7 MeV ·cm2/mg. VCCAUX , VCC PSAUX and VAUXIO correspondto the auxiliary supply voltage of the programmable logic(FPGA), the processing system and the HPIO respectively.Figures 2, 3 and 4 show the measured SEL cross-sections onthese three power domains.

During the high-energy heavy-ion test performed at CERN,no SEL were observed at normal incidence, as shown inFigures 2, 3 and 4. However, the total fluence used duringthis test was only 2.8 × 106 hi/cm2 due to the beam distri-bution as spills, which limits the average flux. This result is

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Fig. 3. VCC PSAUX Power Domain Single-Event-Latchup Cross-Section ofXCZU3EG Device (Weibull fit: XSSAT =1.3e-4cm2; LETTH=5.5MeV ·cm2/mg; W=9.8; S=2.1)

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Fig. 4. VAUXIO Power Domain Single-Event-Latchup Cross-Section ofXCZU3EG Device (Weibull fit: XSSAT =1.2e-3cm2; LETTH=7.4MeV ·cm2/mg; W=10.0; S=2.3)

consistent with the measurement performed at UCL, at whichthe SEL threshold was found between LET = 3.3 and 5.7MeV · cm2/mg. Tests were also performed at 30°, 60° and90° incidence angles to emulate higher LET ions and see ifthe device was SEL sensitive with high-energy heavy-ions.SELs were observed only at an incidence of 90°. However,accurate measurement of their cross-section was difficult atCERN, due to multiple simultaneous events occurring at suchgrazing angles.

B. SEU Test ResultsFigures 5, 6 and 7 show the heavy-ion SEU cross-section

measured during the UCL and CERN test campaign for theCRAM, the BRAM and the DistRAM of the ZU3EG device.The CRAM upset cross-section was computed on the basisof 29,192,364 configuration bits. This number was extractedfrom the bitstream mask file, which is usually an effectivemethod to evaluates the number of true configuration bitsof a programmable devices. CRAM and BRAM SEU cross-sections of this Ultrascale+ device are 2-4 times lower thanthe one of the previous generation, denoted as Ultrascale, andreported in [1]. Measured cross-sections at CERN show thatthe ZU3EG device has similar SEU sensitivity with high-energy heavy-ions and standard heavy-ions. This is discussedin section IV.

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Fig. 5. Per bit CRAM Single-Event-Upset Cross-Section of XCZU3EGDevice (Weibull fit: XSSAT =5.4e-10cm2; LETTH=0.3MeV · cm2/mg;W=15.7; S=2.3)

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Fig. 6. Per bit BRAM Single-Event-Upset Cross-Section of XCZU3EGDevice (Weibull fit: XSSAT =1.8e-9cm2; LETTH=0.3MeV · cm2/mg;W=10.3; S=2.2)

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Fig. 7. Per bit Distributed RAM Single-Event-Upset Cross-Section ofXCZU3EG Device (Weibull fit: XSSAT =1.9e-9cm2; LETTH=1.4MeV ·cm2/mg; W=10.5; S=1.6)

Figure 8 shows the heavy-ion SEU flip-flop cross-section ofthe ZU3EG device, measured at CERN and UCL. Note thatno upset was observed during the CERN test campaign. TheTMR shifter was also tested during both test campaigns butno SEU was observed. However, as the depth of the TMRshifter was 3 times lower than the one of the standard shifter,the measured upper limit SEU cross-section of this TMRimplementation is about 5.5E−10 cm2/bit with Xe ion (LET =

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Fig. 8. Per bit FF Single-Event-Upset Cross-Section of XCZU3EG Device(Weibull fit: XSSAT =2.3e-9cm2; LETTH=1.5MeV · cm2/mg; W=17.2;S=2.3)

62.5 MeV.cm2/mg). Burst events were also observed on bothshift-registers during radiation testings. Several mechanismssuch as upset in the configuration RAM or incorrect operationof the IO during SEL events may explain these bursts. Testresults show that the shift registers can be ranked in term ofsensitivity to burst events as follows: The TMR shift register isobviously the least sensitive. The shift register bypassing thelook-up tables is approximately two time less sensitive thanthe standard shift register, routed through the look-up tables.

IV. DISCUSSION

Measured SEL and SEU cross-sections provided by thehigh-energy heavy-ion test campaign at CERN are consistentwith the results obtained with standard heavy-ion tests. NoSELs was observed during the ultra high energy heavy-ion testat normal incidence, confirming that the SEL LET thresholdis between 3.7 MeV ·cm2/mg and 5.7 MeV ·cm2/mg. SEUcross-sections measured on the three different memories arevery close to the value obtained during the UCL test campaign.

This result is consistent with previous works [4]–[8] whichcompare SRAM SEU cross-sections against the ion energy, upto several hundred of MeV/n, at constant LET. Conclusionsof these works are that the ion energy has a very low impacton the measured SEU cross-sections of SRAM memories, forLET higher than the upset threshold, as most of the events aredue to direct ionization mechanisms. For LET values that arelower than the upset threshold, previous works report that theSEU cross-section can either decrease [4]–[7] or increase [8]by several orders of magnitude. These large variations are dueto indirect ionization mechanisms, which are the main sourceof upset as the incident ions don’t deposit enough energy toinduce an SEU.

Xe ions used during the CERN test campaign had a higherLET than the upset threshold of the memories of the ZU3EGdevice. The good correlation between the measurements ob-tained at CERN and UCL shows that results reported in [4]–[8]are still valid for energies in the range of several tens of GeV/nand for advanced FinFETs technologies.

Ultra high energy heavy-ion testing had several advantagescompared to standard energy heavy-ion test: first, it is notneeded to de-lid or thin the device. It is also possible to

perform test at 90° tilt angle. Finally, the possibility to performtest in air simplifies the setup.

V. CONCLUSION

Standard and high energy heavy-ion test results on a lastestgeneration SRAM based FPGA were reported, for a largevariety of the device features.

ACKNOWLEDGMENTS

This work was supported by the European Space Agencyunder contract No. 4000116569.

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