sizing_pass_transistor.pdf

7/30/2019 Sizing_Pass_Transistor.pdf

1/6

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 12, DECEMBER 2010 1757

of which can provide data encryption and decryption using only an en-

cryption primitive.

It is hoped that this design will open up new opportunities for the

AES in resource-sensitive applications, where it was not considered

previously.

ACKNOWLEDGMENT

The authors would like to thank J. Spreutels and E. Deumens of the

Interuniversity Microelectronics Centre (IMEC), and L. Wong and M.

Wilmott at the Microelectronic Support Unit, Rutherford-Appleton

Laboratory, Chilton, U.K., for assistance with the design flow and

foundry service.

REFERENCES

[1] Nat. Inst. Standards Technol. (NIST), Federal Information ProcessingStandards (FIPS) Publication 197, Advanced Encryption Standard,Nov. 2001.

[2] A. Satoh, S. Morioka, K. Takano, and S. Munetoh, A compact Ri-jndael hardware architecture with S-box optimization, in Proc. ASI-

ACRYPT, Gold Coast, Qld., Australia, Dec. 2001, vol. 2248, LecturerNotes in Computer Science, pp. 239254.

[3] T. Good and M. Benaissa, Very small FPGA application-specific in-structionprocessor for AES,IEEE Trans. Circuits Syst. I, Reg. Papers,vol. 53, no. 7, pp. 14771486, Jul. 2006.

[4] M. Feldhofer, J. Wolkerstorfer, and V. Rijmen, AES implementationon a grain of sand, Proc. Inst. Electr. Eng. Inf. Security, vol. 1, pp.1320, 2005.

[5] NIST, Recommendation for block cipher modes of operation,Special Publication SP-800-38A, 2001. [Online]. Available:http://csrc.nist.gov/publications/PubsSPs.html

[6] D. Whiting, R. Housley, and N. Ferguson, Counter With CBC-MAC(CCM), Jun. 2002. [Online]. Available: http://csrc.nist.gov/groups/ST/toolkit/BCM/documents/proposedmodes/ccm/ccm.pdf

[7] V. Rijmen, Efficient Implementation of the Rijndael S-Box, 2000.[Online]. Available: http://www.iaik.tu-graz.ac.at/research/krypto/AES/old/~rijmen/rijndael/sbox.pdf

[8] D. Canright, A very compact S-box for AES, in Proc. CHES, Edin-burgh, U.K., 2005, vol. 3659, LNCS, pp. 441456.

[9] C. Paar, Efficient VLSI architectures for bit-parallel computation inGalois fields,, Ph.D.dissertation,Inst. Exp.Math., Univ. Essen, Essen,Germany, Jun. 1994.

[10] T. Good andM. Benaissa, ASIC Hardware Performance. Berlin, Ger-many: Springer-Verlag, 2008, vol. 4986, Lecture Notes in ComputerScience State-of-the-Art-Survey, pp. 267293.

[11] J.-P. Kaps and B. Sunar, Energy comparison of AES and SHA-1for ubiquitous computing, in Proc. Embedded Ubiquitous Comput.(EUC), Seoul, Korea, Aug. 2006, pp. 372381.

[12] H. Kuo, I. Verbauwhede, and P. Schaumont, A 2.29 Gbits/sec, 56 mWnon-pipelined Rijndael AES encryption IC in a 1.8 V 0.18 um CMOStechnology, in Proc. CICC, Orlando, FL, 2002, pp. 147150.

[13] S.-F. Hsaio, M.-C. Chen, and C.-S. Tu, Memory-free low-costdesignsof advanced encryption standard using common subexpression elimi-

nation for subfunctions in transformations, IEEE Trans. Circuits Syst.I, Reg. Papers, vol. 53, no. 3, pp. 615626, Mar. 2006.

[14] S.-Y. Lin and C.-T. Huang, A high-throughput low-power AES cipherfor network applications, in Proc. ASP-DAC, Yokohama, Japan, Jan.2007, pp. 595600.

A Chip-Area Efficient Voltage Regulator for VLSI Systems

Ka Nang Leung, Yuan Yen Mai, and Philip K. T. Mok

AbstractThis paper presents an error amplifier structure to improveload regulation of low-voltage low-dropout regulators. The proposed error

amplifier has ultrawide swing to extend the high-gain region so that thesize of power transistor can be reduced. Experimental results show thatthe required power transistor size is reduced by 25% to achieve similarperformance in load regulation. Moreover, extra power consumption andincrease of silicon area are not significant.

Index TermsLoad regulation, low-dropout regulator.

I. INTRODUCTION

Integrated power management is a pivotal issue in VLSI systems.

In particular, low-dropout voltage regulator (LDO) can achieve local

on-chip regulation for VLSI systems [1]. This motivates recent LDO

researches focusing on lower minimum supply voltage [2], faster dy-

namic response [3], higher stability [4], [5], higher steady-state accu-

racy [6], and less silicon consumption. In general, all LDO specifica-tions constrain each other [2][6]. It is difficult to improve all of them

simultaneously.

Load regulation ( 1 VO U T

= 1 I

O U T

) of an LDO shown in Fig. 1 is

determined by the low-frequency loop gain (L

O

) [2][5].L

O

depends

on both the gain of the error amplifier (A

E A

) and the gain of the power

transistor ( AP T

). From Fig. 1, VO U T

is given by

V

O U T

=

L

O

+ L

O

+

R

F 1

R

F 2

V

R E F

+

R

F 1

R

F 2

V

R E F

(1)

where LO

= A

E A

A

P T

R

F 2

= ( R

F 1

+ R

F 2

) . From (1), VO U T

is in-

dependent of input voltage ( VI N

), and is set by RF 1

= R

F 2

and VR E F

whenL

O

. A higher loop gain enables a better load regulation,

but it cannot be increased by just increasing the gain of the error am-plifier due to stability problem [7]. Therefore, a low-frequency zero

is generated in [7] by inserting a large value RC network in the error

amplifier structure. Although the LDO stability and the load regula-

tion are both enhanced, the large-signal response is limited due to the

added large on-chip capacitance inside the low-power error amplifier.

For example, when an error amplifier has a bias current of 2 A , a

5-pF on-chip capacitance to create a zero for compensation seriously

degrades the response time in the submicrosecond range.

Therefore, a single-sided gain-retained method to extend the high-

gain region of the error amplifier and retain the voltage gain at large

load current is proposed in this paper. The major contribution of the

Manuscript received April 06, 2008; revised June 25, 2008. First publishedJanuary 12, 2010; current version publishedNovember 24, 2010. This work wassupported by the Research Grant Council of Hong Kong Special AdministrativeRegion (SAR) Government under Project HKUST 617707.

K. N. Leung was with the Department of Electronic and Computer Engi-neering, The HongKong University of Science andTechnology, Kowloon, HongKong. He is currently with the Department of Electronic Engineering, The Chi-nese University of Hong Kong, Shatin, Hong Kong (e-mail: [email protected]).

Y. Y. Mai was with the Department of Electronic and Computer Engineering,The Hong Kong University of Science and Technology, Kowloon, Hong Kong.He is currently with Supertex, Inc., Kowloon, Hong Kong (e-mail: [email protected]).

P. K. T. Mok is with theDepartmentof Electronic andComputer Engineering,The Hong Kong University of Science and Technology, Kowloon, Hong Kong(e-mail: [email protected]).

Digital Object Identifier 10.1109/TVLSI.2009.2026176

1063-8210/$26.00 2010 IEEE


2/6

1758 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 12, DECEMBER 2010

Fig. 1. Structure of an LDO.

Fig. 2. Simulated load regulations of LDO using the same amplifier with dif-ferent W = L aspect ratios of power transistor.

proposed idea is to improve the load regulation without adding any RCcomponents to the LDO.

II. RELATIONSHIP BETWEEN LOAD REGULATION AND OUTPUT SWING

OF AN ERROR AMPLIFIER

Fig. 2 shows simulations of the load regulation of an LDO with dif-

ferent power-transistor sizes providing a preset VO U T

= 1 : 3 V. Fig. 2

shows that the load regulation is poor at high IO U T

(denoted as critical

region in Fig. 2). As depicted in Fig. 2, larger aspect ratio can enhance

load regulation. There is clearly a tradeoff between the load regulation

and the chip area.

This phenomenon can be explained by the VS G

of the power tran-

sistor at different IO U T

. The error amplifier operates in the low-gain

region due to the high VS G

of the power transistor to deliver more

I

O U T

. Thus, a larger aspect ratio of the power transistor helps to im-

prove the load regulation, since relatively lower VS G

is needed for pro-

viding equal amount of IO U T

. However, the gain reduction cannot be

solved by a high-gain cascade or cascade error amplifier since LDO is

unstable when the loop gain is too high [5]. Therefore, the gain of the

error amplifier is needed to be retained throughout the whole range of

I

O U T

.

From this analysis, the design of the output stage of the error ampli-

fier has a substantial impact on the required size of the power transistor

for the improvement of load regulation, especially when the supply

voltage of the VLSI systems is low.

III. POWER TRANSISTOR SIZE REQUIREMENT

The power transistor of an LDO generally operates in the linear re-gion when the sourcegate voltage is large for the maximum output

Fig. 3. Plot of size ratio versus V at different V .

current. Referring to Fig. 1, the output current is therefore approxi-

mated by (the approximation is based on the fact that VS G

0 j V

T H P

j

V

I N

0 V

O U T

in low-voltage LDO design)

I

O U T

p

C

O X

W

L

( V

S G

0 j V

T H P

j ) ( V

I N

0 V

O U T

) : (2)

The power transistor size is determined at the maximum IO U T

(the

worst case). The ideal maximum VS G

for providing the maximum

I

O U T

is VI N

. As a result, the ideal aspect ratio ( W = L )I D E A L

of the

power transistor has a relation given by

I

O U T ( M A X )

p

C

O X

W

L

I D E A L

( V

I N

0 j V

T H P

j ) ( V

I N

0 V

O U T

) :

(3)

However, the effective V S G is reduced by the nonzero lower outputswing (defined as V

O L

) of the error amplifier. The actual required as-

pect ratio ( W = L )A C T

of the power transistor is

I

O U T ( M A X )

p

C

O X

W

L

A C T

( V

I N

0 V

O L

0 j V

T H P

j ) ( V

I N

0 V

O U T

) :

(4)

Based on (3) and (4), when providing equal maximum IO U T

, the size

relationship due to the nonzero VO L

is given by

( W = L )

A C T

( W = L )

I D E A L

1 +

V

O L

V

I N

0 j V

T H P

j 0 V

O L

:

(5)

A simple analysis can be done by considering an LDO design. Sup-

posej

V

T H P

j

= 0

:

8

V, then the required size ratio given in (5) as afunction of V

O L

at different VI N

(1.5, 2, and 3 V) is shown in Fig. 3.

The reference size ratio is 1, which indicates the ideal transistor size

whenV

O L

= 0

V.

Fig. 3 shows that the required size ratio increases asV

O L

increases.

The increasing size ratio becomes more serious when the LDO oper-

ates at low input voltage. For example, when VI N

= 1 : 5 V, the size

ratios are about 1.2 and 1.4 for VO L

= 0 : 1 and 0.2 V, respectively. By

considering an LDO implemented in a 0.35-

m CMOS technology,

suppose that the power transistor size is 14 000 m/0.35 m when

V

O L

= 0 : 2 V, then the required size will be significantly reduced to 12

000 m/0.35 m when VO L

= 0 : 1 V. It can be concluded that there is

substantial size reduction of the power transistor when theV

O L

of the

error amplifier can be reduced. Smaller transistor size enables faster

transient response since slew-rate limit at the gate of the power tran-sistor is relatively not serious [2].


3/6


Fig. 4. Proposed error-amplifier structure.

IV. PROPOSED SINGLE-SIDED GAIN-RETAINED METHOD

The key requirements of the error amplifier are wide output swing

to maximize the VS G

of the power transistor and simple frequency re-

sponse to ease frequency compensation of the LDO. A current-mirror

amplifier is a good choice. It is applied to the LDO in Fig. 1. The pro-

posed error amplifier structure in Fig. 4 is a modified current-mirror

amplifier. MN 1

, MN 2

, MN 3

, MN 4

, and the auxiliary amplifier with

a voltage gain of A form the proposed single-sided ultrawide-swing

gain-retained output stage.

Both MN 1

and MN 2

are designed to operate in the linear region.

This can be done by the transistor sizing of MN 2

and MN 4

to define

V

X

. In general, when the body effect ofM

N 4

is taken into account,( W = L )

N 4

> 5 ( W = L )

N 2

! 6 ( W = L )

N 2

is needed to make MN 2

op-

erate in the saturation region. Therefore, the condition that makesM

N 2

operate in the linear region is suggested to be

2

W

L

N 2

W

L

N 4

R

O N C

in all the three cases.

Case I) ( M0

: Saturation) versus ( M1

: Linear, M2

: Saturation):

When M2

operates in the saturation region, RO G R

is always larger

Fig. 5. Noncascode structure and gain-retained structure at high I condi-tion. (a) Gain retained. (b) Noncascode. (c) Three possible cases.

thanR

O N C

[8]. Therefore, the gain is retained and mainly defined by

M

P 1

.

Case II) ( M0

: Saturation) versus ( M1

: Linear, M2

: Linear): When

a MOSFET operates in the linear region, gm

= V

D S

and rd s

=

[ ( V

G S

0 V

T H

0 V

D S

) ]

0 1 , where = CO X

( W = L ) . For the single-

sided gain-retained structure, both M1

and M2

operate in the linear

region. Thus

R

O G R

r

d s 1

A g

m 2

r

d s 2

=

A V

D S 2

1

( V

G S 1

0 V

T H

0 V

D S 1

) ( V

G S 2

0 V

T H

0 V

D S 2

)

:

(7)

Since both M1

and M2

operate in the linear region, we have

V

G S 1

0 V

T H

V

D S 1 (

s a t

)

> V

D S 1

(8)

and

V

G S 2

0 V

T H

V

D S 2 ( s a t )

> V

D S 2

: (9)

Therefore, (7) can be approximated to

R

O G R

A V

D S 2

1

( V

G S 1

0 V

T H

) ( V

G S 2

0 V

T H

)

: (10)

The output resistance of the noncascode structure is

R

O N C

=

1

I

D S 0

=

2

0

( V

G S 0

0 V

T H

)

2

: (11)

The condition for R O G R > R O N C can be obtained by (10) and (11),which resulted in

A >

1

( V

G S 1

0 V

T H

) ( V

G S 2

0 V

T H

)

0

( V

G S 0

0 V

T H

)

2

2

V

D S 2

: (12)

For the same drain current of M0

, M1

, and M2

with the same power

consumption of the error amplifier, VG S 1

> V

G S 0

and VG S 2

> V

G S 0

,

since M1

and M2

operate in the linear region while M0

, M1

operates in

the saturation region. Moreover, when 1

0

, (12) is approximated

to

A >

2

V

D S 2

: (13)

From (13), it is obvious that when VD S 2

increases, the required A is

decrease. The gain-retained structure is more effective when M2

pro-vides higher gain. This is, in fact, the case when M

2

trends to operate


4/6


in the saturation region (i.e., a higher VD S 2

). Therefore, the worst case

occurs when M0

is at the boundary of the linear region and the satu-

ration region (i.e., VD S 0

= V

D S ( s a t )

). The minimum A is determined

based on the channel length as well.

The improvement can be shown by a case study. Assuming that

I

D S 0

= I

D S 1

= I

D S 2

= 1 0 A , VD S 0 ( sat) = V G S 0 0 V T H = 0 : 1 V,

V

D S 0

= 0 : 2 V, VD S 1 ( sat) = V G S 1 0 V T H = 0 : 2 V ; and V D S 1 =

0 : 1 V < V D S 1 ( sat) . M 0 operates in the saturation region, but both M 1and

M

2

operate in the linear region. The values of

0

and

1

are found

to be 1 mA/V and 667 A = V, respectively. When the gain of the aux-

iliary amplifier is 1 k V/V and = 0 : 0 5 V0 1 , based on (10) and (11),

R

O G R

= 3 : 7 M is larger than RO N C

= 2 M .

Case III) (M

0

: Linear) versus (M

1

: Linear,M

2

: Linear): For the

noncascode structure, when M0

operates in the linear region

R

O N C

=

1

0

( V

G S 0

0 V

T H

0 V

D S 0

)

: (14)

The condition for RO G R

> R

O N C

can be obtained by (7) and (14),

which resulted in

A V

D S 2

1

(

V

G S 1

0 V

T H

0 V

D S 1

) ( V

G S 2

0 V

T H

0 V

D S 2

)

>

1

0

( V

G S 0

0 V

T H

0 V

D S 0

)

: (15)

This expression can be rewritten as

V

D S 2

>

V

G S 1

0 V

T H

0 V

D S 1

V

G S 0

0 V

T H

0 V

D S 0

1

( V

G S 2

0 V

T H

0 V

D S 2

)

A

0

:

(16)

Similarly, for the same drain current of Mo

, M1

, and M2

with the

same power consumption of the error amplifier, VG S 1

> V

G S 0

since

V

D S 0

> V

D S 1

(see to Fig. 5). Therefore, when

1

0

(17)

it is approximated to

V

D S 2

>

V

G S 2

0 V

T H

0 V

D S 2

A

: (18)

This expression gives

V

D S 2

>

V

G S 2

0 V

T H

A + 1

=

V

D S 2 ( sat)

A + 1

: (19)

From (19),R

O G R

is larger thanR

O N C

untilV

D S 2

is less than its sat-

uration voltage divided by the gain of the auxiliary amplifier.

The earlier analysis and conclusion are verified by simulations

shown in Fig. 6. The simulations were performed by BSIM3v3 models

from austriamicrosystems (AMS) 0.35- m CMOS technology. The

loop gain LO

, which relies on the gain of the error amplifier, is the

best when using the single-sided gain-retained method on both the

magnitude and also the gain drop at higher I O U T (corresponding tolower V

O E A

). At the designed maximum IO U T

of 110 mA, LO

is

about 14 dB higher when the single-sided gain-retained error amplifier

is used.

The frequency response of the proposed structure can be studied by

the output impedance of the error amplifier ZO E A

shown in Fig. 7. The

capacitance CG P T

models the gate capacitance of the power transistor.

It is always much larger than the parasitic capacitances in the proposed

structure. The auxiliary amplifier is a single-stage amplifier and has a

transconductance of gm a

.

From Fig. 7, the output impedance is given by

Z

O E A

r

d s 1

A g

m 2

r

d s 2

( 1 + s C

G P T

r

d s 1

A g

m 2

r

d s 2

) ( 1 + s C

g 2

C

g d 1

= C

G P T

r

d s 1

A g

m 2

g

m a

)

(20)

Fig. 6. Simulated loop gainversus I for differentoutput stagesof theerroramplifier.

Fig. 7. Frequency response for the output impedance.

whereC

g 2

is the gate capacitance ofM

2

. It is noted that there is a pole-

zero doublet (at the same frequency) equal to the unity-gain frequency

(UGF) of the auxiliary amplifier. A first-order single-pole error ampli-

fier is generally preferred in LDOdesign for simple and easy frequency

compensation. Therefore, the nondominant pole should be located at a

much higher frequency than the UGF of the open-loop response of the

error amplifier. Thus, the following relationship is set:

U G F =

g

m A 1

C

G P T

C

G P T

r

d s 1

A g

m 2

g

m a

C

g 2

C

g d 2

(21)

where gm A 1

is the transconductance of the input stage of the error am-

plifier ( MA 1

and MA 2

in Fig. 4). Equation (21) is rewritten as

C

2

G P T

C

g 2

C

g d 2

r

d s 1

A g

m 2

g

m a

g

m A 1

1 : (22)

This condition in (22) always holds when the local loop gain by M2

and A is higher than 0 dB, since the capacitance ratio is always much

greater than 1 due to the large gate capacitance of the power transistor.

In addition,g

m a

, which corresponds to the required power needed by

the auxiliary amplifier, does not need to be high to make the condition

stated in (22) valid. Thus, the power consumption of the auxiliary am-plifier can be neglected.


5/6


Fig. 8. Micrograph of the proposed LDO using single-sided gain-retainedmethod.

TABLE ISUMMARY OF LDO PERFORMANCE

V. EXPERIMENTAL RESULTS

Two LDOs have been implemented in an AMS CMOS 0.35- m

technology. Both of them have equal size of powertransistor (i.e., 9000

m/0.35 m). One uses the error amplifier with a noncascode output

stage (denoted as the classical LDO) and another uses the one pro-

posed in Fig. 4 (denoted as the proposed LDO). The micrograph of the

proposed LDO is shown in Fig. 8. The increase of the chip area due

the proposed structure is very small when compare to the integrated

power transistor. The overall performances of the two LDOs are listed

in Table I for comparison. The ground currents are similar, since the

current consumption of the auxiliary amplifier is not significant and

the gain-retained structure is always stable in the LDO design.

The measured load regulations of the two LDOs atV

I N

= 1

:

5

Vand V

O U T

= 1 : 3 V are plotted in Fig. 9. The testing range of the

output current is from 1 to 130 mA. The load regulations in Fig. 9 can

be separated into three regions for studies. When IO U T

9 0 m A , the

proposed LDO shows a better regulation due to the slightly higher loop

gain. When 9 0 m A < IO U T

1 1 0 m A , VO U T

of the proposed LDO

slightly drops, while VO U T

of the classical LDO relatively drops much

larger. This shows that the proposed high-swing gain-retained struc-

ture can retain the voltage gain of the error amplifier even when the

I

O U T

is high (i.e., VS G

of the power transistor is large). Lastly, when

I

O U T

> 1 1 0 m A , VO U T

of both LDOs drop similarly, since both

output stages cease to provide high output resistances. From this result,

the load regulation of the proposed LDO is better, which corresponds

to the reduction of the steady-state error ofVO U T

by 0.55%. Thediffer-

ence with the simulated result shown in Fig. 6 is due to the accuracy ofthedevice models. This improvement is very significant to typical LDO

Fig. 9. Measured load regulations.

Fig. 10. Measured load transient responses.

products of 0.6%2% accuracy budget. As a remark, according to the

simulations for further analysis, the size of the power transistor needed

to achieve similar load regulation by the classical LDO is about 12000

m/0.35

m. This corresponds to 25%size reduction of thepower tran-

sistor when the proposed method to improve the load regulation is use.

Finally, the transient response is not affected by the proposed struc-

ture since there is no difference in the loop bandwidth and the slew

rate at the gate of the power transistor [2]. Fig. 10 shows the load tran-

sient responses of the conventional and the proposed LDOs under the

same change of the output current (1110 mA). The load capacitance

is 100 pF to model the capacitance of the power-supply routings. The

proposed LDOprovidesa similar load transientresponseas theconven-

tional LDO. In addition, there is an improvement of the load regulationshown in the steady state.


6/6


VI. CONCLUSION

Single-sided ultrawide-swing gain-retained method for the error am-

plifier design has been proposed to improve the load regulation of an

LDO. Theoretical study and experimental results have been introduced

to prove the idea. The idea can be extended to the analog-driver design

for maximizing the output capability.

REFERENCES[1] D. D. Buss, Technology in the internet age, in Dig. IEEE Int. Solid-

State Circuits Conf., 2002, pp. 1821.[2] G. A. Rincon-Mora and P. E. Allen, A low-voltage, low quiescent

current, low drop-out regulator, IEEE J. Solid-State Circuits, vol. 33,no. 1, pp. 3644, Jan. 1998.

[3] H. Lee, P. K. T. Mok, and K. N. Leung, Design of low-poweranalog drivers based on slew-rate enhancement circuits for CMOSlow-dropout regulators, IEEE Trans. Circuits Syst. II, Exp. Briefs,vol. 52, no. 9, pp. 563567, Sep. 2005.

[4] K. N. Leung and P. K. T. Mok, A capacitor-free CMOS low-dropoutregulator with damping-factor-control frequency compensation,IEEE

J. Solid-State Circuits, vol. 38, no. 10, pp. 16911702, Oct. 2003.[5] C. K. Chava and J. Silva-Martinez, A frequencycompensationscheme

for LDO voltage regulators, IEEE Trans. Circuits Syst. I, Reg. Papers,

vol. 51, no. 6, pp. 10411050, Jun. 2004.[6] Y. H. Lam, W. H. Ki, and C. Y. Tsui, Adaptively biased capacitor lessCMOS low dropout regulator with direct current feedback, in Proc.

IEEE/ACM 11th Asia South Pacific Design Autom. Conf., Jan. 2006,pp. 104105.

[7] G. A. Rincon-Mora and P. E. Allen, Optimized frequency-shapingcircuit topologies for LDOs, IEEE Trans Circuit Syst. II, Exp. Briefs,vol. 45, no. 6, pp. 703708, Jun. 1998.

[8] B. Razavi, Design of Analog CMOS Integrated Circuits. Boston, MA:McGraw-Hill, 2001.

Diagnosis of MRAM Write Disturbance Fault

Chin-Lung Su, Chih-Wea Tsai, Ching-Yi Chen,

Wan-Yu Lo, Cheng-Wen Wu, Ji-Jan Chen, Wen-Ching Wu,

Chien-Chung Hung, and Ming-Jer Kao

AbstractIn this paper, we propose a new test method to detect write dis-turbance fault (WDF) for magnetic RAM(MRAM). Furthermore, an adap-tive diagnosis algorithm (ADA) is also introduced to identify and diagnosethe WDF for MRAM. The proposed test method can evaluate process sta-bilityand uniformity. We also develop a built-in self-test (BIST) circuit thatsupports the proposed WDF diagnosis test method. A 1-Mb toggle MRAMprototype chip with the proposed BIST circuit has been designed and fab-ricated using a special

0 1 5

- m CMOS technology. TheBIST circuit over-head is only about 0.05% with respect to the 1-Mb MRAM. The test timeis reduced by about 30% as compared with the test method without usingthe decision write mechanism. The chip measurement results show the ef-ficiency of our proposed method.

Index TermsFault diagnosis, magnetic RAM (MRAM), memorytesting, nonvolatile memory, write disturbance fault (WDF).

I. INTRODUCTION

Many applications require a system-on-chip (SOC) to integrate

nonvolatile memories. Although flash memory is widely used today,

high voltage for program and erase operations, and some reliability

issues are hard to handle[1]. In recent years, the industry has tried

to find an appropriate nonvolatile memory that can replace flash

memory. MRAM is considered a good choice due to its high speed,

low operating voltage, and virtually unlimited read/write endurance

[2], [3]. We, therefore, see a growing need for MRAM testing and

diagnosis methodologies [4][8].

In recent years, there are two different types of MRAM that have

been proposed, i.e., the asteroid MRAM and the toggle MRAM. How-

ever, the asteroid MRAM devices have some problems such as the dis-turbance by half-selected cells and loss of data due to thermal agita-

tion [9]. The toggle MRAM has been proposed to solve that issue [10].

In general, compared with conventional asteroid MRAM, the toggle

MRAM hasbetter write and read margins, higherreliability, betterscal-

ability, etc. However, this does not mean the reliability andtest issuesof

toggle MRAM aresolved [11]. There are only a few technical paperson

MRAM testing so far. The authors in [4] propose some defect models

based on SPICE simulation forasteroid MRAM. Later, the write distur-

bance fault(WDF) model fortoggleMRAM is proposed [5], [8], which

is a fault thataffects the data stored in the MRAM cells due to excessive

magnetic field generated during the write operation. In general, March

test algorithms, which are widely used for memory testing, have linear

complexity and high coverage for conventional RAM faults; however,

Manuscript received October 25, 2008; revised April 05, 2009. First pub-lished September 01, 2009; current version published November 24, 2010. Thiswork was supported in part by the National Science Council, Taiwan, underGrant NSC 95-2221-E-007-258-MY3.

C.-L. Su and C.-W. Tsai are with the R&D Department, Skymedi Corpora-tion, Hsinchu 300, Taiwan (e-mail: [email protected]).

C.-Y. Chen, W.-Y. Lo, and C.-W. Wu are with the Department of ElectricalEngineering, National Tsing Hua University, Hsinchu 30013, Taiwan.

J.-J. Chen, W.-C. Wu, and C.-W. Wu are with the SOC Technology Center,Industrial Technology Research Institute, Hsinchu 31040, Taiwan.

C.-C. Hung and M.-J. Kao are with the Electronics and Opto-Electronics Re-search Laboratory, Industrial Technology Research Institute, Hsinchu 31040,Taiwan.

Digital Object Identifier 10.1109/TVLSI.2009.2026905

1063-8210/$26.00 2009 IEEE

sizing_pass_transistor.pdf

Documents