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S K Y L I N E T E S T E Q U I P M E N T , I N C .

2 4 2 3 O l d M i d d l e f i e l d W a y , S t e E , M o u n t a i n V i e w C A 9 4 0 4 3

Version 3.01

January 31, 1996

Copyright 1996-2002 by Skyline Test Equipment, Inc.

DEC and PDP are trademarks of Digital Equipment CorporationPentium is a trademark of Intel Corporation

Reproduction or publication of the content in any manner, withoutexpress permission of the publisher, is prohibited. No liabilityis assumed with respect to the use of the information herein.

Printed in the United States of America

TABLE OF CONTENTS 3

INTRODUCTION TO THE PC-HOST.........................................................7Features...........................................................................................7

PC-POB Software.................................................................8Hardware Requirements..................................................................9

Computer..............................................................................9PC-Host Interface Boards.....................................................9

Installation......................................................................................11Basic PC-Host Installation...................................................11Expanded Memory Installation............................................12GPIB Board Installation.......................................................14GT200 Counter Board Installation.......................................16

QTL PROGRAMMING..............................................................................17QTL Compiler.................................................................................17

Basics..................................................................................17The PC-Host QTL Compilers..............................................18When to Use QTL62...........................................................20Compiling and Linking.........................................................20Converting QTL Programs for the PC-Host........................21SKY284, Q2 and Q8000 Reserved Words..........................23Q2/52 Reserved Words.......................................................24

Basic Program Components..........................................................26Program Header..................................................................26Product Header...................................................................27Sequence and Binning Tables............................................28Test Blocks: Pin Setup........................................................31Test Blocks: Voltage and Current Setup.............................31Test Blocks: Timing Setup..................................................36Test Blocks: Additional Setup.............................................38Test Blocks: Setup for Parametric Tests.............................39Test Blocks: Parametric Tests............................................40Test Blocks: Setup for Functional Tests..............................43Test Blocks: Functional Tests.............................................44

Additional Test Programming Commands.....................................46Flow Control........................................................................46Registers.............................................................................48Access to I/O Ports.............................................................50Searches.............................................................................53I/O and Host Functions.......................................................55Data Logging.......................................................................57Schmoos.............................................................................58Other Data Analysis Tools..................................................60Identity Tests.......................................................................60

Q2/52 Specific Topics....................................................................61The Q Buffer........................................................................61

TABLE OF CONTENTS 4

Q2/52 PGM Control.............................................................61PGM Buffers........................................................................63Q2/52 PGM Parametric Test Setup...................................66Q2/52 PGM Pattern Loading and Execution.......................67Q2/52 PGM Program Flow Control.....................................70Q2/52 PGM Error Catch Control.........................................74Q2/52 Redundancy Analysis...............................................76Q2/52 PGM High Voltage Module.......................................96Pattern Generator Programming.........................................97Q2/52 Bit Map Commands................................................117Q2/52 Reference: PGM Registers....................................118Q2/52 Reference: PGM Tables.........................................119Q2/52 Reference: The TYPE Table..................................120Q2/52 Reference: The STATUS Buffer.............................132Q2/52 Reference: Pin Electronics Modes.........................136

Q2/62 Specific Topics..................................................................140The Q2/62 Pattern Execution Module (PEM)....................140The Q Buffer......................................................................141Q2/62 PEM Control...........................................................142Q2/62 POB Control...........................................................144Q2/62 Reference: The TYPE Table..................................145

SKY284 Specific Topics...............................................................147The SKY284 Vector Generator.........................................147The Q Buffer......................................................................148VG Control........................................................................148SKY284 ROM Code Loading............................................150SKY284 Reference: The TYPE Table...............................151

SKY284 and Q2/62 Functional Programming..............................152TESTER OPERATION: The Q-MONITOR.............................................157

Q-Monitor Basics.........................................................................157Q-Monitor Command Formats..........................................157Expressions in Q Commands............................................158Variables in Q Commands................................................159

The Q Setup Command...............................................................160Q-Monitor Commands.................................................................162

Q Commands for Program Loading and Execution..........162Q Commands for Front Panel Functions...........................164Breakpoints.......................................................................165Registers...........................................................................166Ports..................................................................................167SKY284 Pin Electronics (PE84) Specific Commands.......168Interface Board Configuration...........................................168Wafer Mapping..................................................................168DC Level and Supply Commands.....................................169Programmable Timing Generator Commands..................171

TABLE OF CONTENTS 5

Q2/52 PGM Specific Commands......................................173Q2/62 PEM Specific Commands.......................................177SKY284 Vector Generator (VG84) Specific Commands...180Datalogging Commands....................................................183Characterization Commands.............................................184

Q Program Commands................................................................186DOS, UNIX, and RT-11 Like Commands.....................................189Macros.........................................................................................191

SELFCHECK AND TIMING CALIBRATION...........................................195Introduction to Q2 Selfcheck........................................................195Selfcheck Requirements..............................................................196

Selfcheck: Calibration Status............................................196Selfcheck: Hardware Requirements..................................196Selfcheck: Software Requirements...................................196

Running Selfcheck.......................................................................197Selfcheck Q Commands...................................................197CSC40 Load Board Commands........................................198Troubleshooting................................................................198

Selfcheck Test Listings................................................................200Test Listing for Q2/62 Selfcheck Module #1.....................200Test Listing for Q2/62 Selfcheck Module #2.....................204Test Listing for Q2/52 Selfcheck Module #1.....................205Test Listing for Q2/52 Selfcheck Module #2.....................207Test Listing for Q2/52 Selfcheck Module #3.....................211Test Listing for Q2/52 Selfcheck Module #4.....................214Test Listing for Q2/52 Selfcheck Module #5.....................214Test Listing for Q8000 Selfcheck......................................215Test Listing for CSC40 Load Board Diagnostic.................216

DC Calibration..............................................................................217Equipment Required.........................................................217

Introduction to Q2 Timing Calibration..........................................218Calibration: Hardware Requirements................................218Calibration: Software Requirements.................................219

Calibration: Counter and GPIB Interface Setup...........................220GT200 Counter.................................................................220HP 5370 Counter..............................................................220Selecting the Counter Type...............................................220Resetting the Counter.......................................................221Counter Diagnostic Check................................................221

PTG Calibration...........................................................................223PTG Verify.........................................................................223PTG Verify on a Single Range..........................................225PTG Calibration.................................................................225Storing Calibration Data in the PTG..................................227Verifying the New Calibration............................................228

TABLE OF CONTENTS 6

Q2 Driver Deskew Verify and Calibration....................................229Driver Deskew: Requirements..........................................230Load Board, Library, and Probe Placement Summary......230Driver Deskew Verify.........................................................230Driver Deskew Calibration.................................................232

Q2 Strobe Deskew Verify and Calibration...................................235Strobe Deskew: Requirements.........................................235Load Board, Library, and Probe Placement Summary......236Strobe Deskew Verify........................................................236Strobe Deskew Calibration................................................238

Q2/52 Offset Calibration..............................................................241Definition...........................................................................241Falling and Rising Edge of PEL Offsets............................241Falling and Rising Edge of PES Offsets............................242Falling and Rising Edge of PEE Offsets............................242Requirements....................................................................242Offset Calibration Procedure.............................................243Storing Offsets..................................................................244

CSC40 Load Board Commands..................................................246Q2 Calibration: Command Summary...........................................247PC-Host/CCL Equivalencies........................................................250Converting CCL Programs...........................................................252

UTILITIES...............................................................................................255Host Access.................................................................................255Megahost Terminal Emulation.....................................................257PC-Ked........................................................................................259Hexadecimal to Binary Conversion..............................................261

APPENDIX..............................................................................................263PC-Host Software and Documentation........................................263Warranty......................................................................................266

INDEX.....................................................................................................267

INTRODUCTION TO THE PC-HOST- Features 7

INTRODUCTION TO THE PC-HOST

FEATURES

Skyline Test Equipment’s PC-Host software and interfaces enable an IBM PC-compatible computer to control a SKY284, Q2/62, Q2/52, or Q8000 test system. When a PC-Host is used, a PDP-11 computer is unnecessary. In addition to improved reliability and uptime, PC-Host provides the following features:

· A PC-Host can control one SKY284, or one Q2/62, up to 5 Q2/52s or up to 5 Q8000s.

· The high-performance QTL compiler compiles up to 100 times faster than the PDP-11-based QTL compiler. On a 33-MHz 80386-based computer, Q2/62 QTL programs compile at 2000 bytes per second and Q2/52 programs compile at 1000 bytes per second.

· The high-speed Q2/62 pattern compiler compiles 60,000 vectors per minute.

· The interactive Q Monitor supports all SUPERQ commands, as well as new commands such as HELP, MORE, DATE, TIME and OTIMES (offset times).

· Tester calibration is implemented via the powerful Q Macro capability, so QCAL and Q2CCL are no longer necessary. The calibration and verify procedures execute two to ten times faster than their PDP-11-based predecessors.

· The high-speed pattern overlay buffer provides up to 255 4K vector patterns (12 megabytes) per tester.

· Terminal emulation for host functions, control of the tester on-the-fly, and file transfers to and from other computers are all supported.

The PC-Host comes with a one-year warranty.

INTRODUCTION TO PC-HOST - Features 8

PC-POB Software

For Q2/62s, the PC-Host’s POB software emulates the Pattern Overlay Buffer hardware found in the Patternhost. It supports up to 12M of patterns in RAM per tester (up to 255 48K byte patterns). The PC-POB software loads patterns from disk to RAM much faster than on the Patternhost, and provides improved reliability and maintainability.

The first 640K of the computer’s RAM is used for applications programs; if extended or expanded memory is not present, any available free space in that 640K will be used for storing patterns. If extended or expanded memory is present, patterns will be stored there. Each megabyte of expanded memory can store 21 to 64 patterns, depending on the size of the patterns.

Patternhost POB functions emulated by the PC-POB software include:

· Pattern loading: Patterns in PC-RAM are loaded directly into the tester. Patterns not in PC-RAM are loaded from disk to PC-RAM, and from there into the tester.

· Pattern saving: Patterns can be saved to the PC disk drive.

· Messages: Tester messages are displayed on the monitor.

· Selfcheck support: The PC-POB software displays POB status and executes tests of free expanded memory.

· Directory listings: The PC-POB software displays directory listings on the monitor.

· Pattern deleting: Patterns can be deleted from PC-RAM.

· POB reset: The PC-POB software can be reset just like the Patternhost’s POB.

For complete information on using the PC-POB software, see the Tester Operation section of this manual.

INTRODUCTION TO PC-HOST - Hardware Requirements 9

HARDWARE REQUIREMENTS

Computer

The PC-Host requires the following:

· IBM-compatible “PC” computer. PC/AT-compatible computers with 386, 486 or Pentium processors are recommended as Q2/62 hosts. Any PC/AT or PC/XT compatible computer may be used as a Q2/52 host.

· A minimum of 4MB of RAM. For Q2/62 hosts, 8 MB is recommended.

· 40 MB hard disk minimum; 500 MB or larger is recommended.

· 1.44 MB 3.5" floppy disk drive.

· Any monitor and keyboard.

· One parallel port for connection the PC-Host hardware key.

For faster and easier data transfers to other computers, the PC-Host can be used with:

· Ethernet interface.

PC-Host Interface Boards

The interface board for the SKY284, ESCape Q2 and ESCape Q8000 is the PCX board. The PCX occupies a PC/AT-type 16 bit slot and uses I/O addresses 31C-31F. For SKY284 and Q2/62 use, the optional 16K byte memory addressing should be enabled. Installation of the PCX board is covered in the ESCape Hardware Manual. The interface board for the standard Q2/52 is the PCQ Serial Interface Board, which is connected to the tester via one RS232 interface cable. The PCQ occupies one PC/XT-type 8-bit slot or PC/AT-type 16-bit slot, and uses I/O addresses 3F8-3FF (COM1), 2F8-2FF (COM2), 3E8-3EF (COM3), 2E8-2EF (COM4), 378-37F (LPT1), or 278-27F (LPT2). Two DB25 connector cut-outs may be required. For installation instructions, refer to the PCQ Reference Manual.

The interface board for the standard Q2/62 is the PC62 Interface Board, which is connected to the tester via a 37 pin ribbon cable. The PC62 interface board contains a RS232 port and two high-speed parallel ports (used for Pattern Overlay Buffer (POB)

INTRODUCTION TO PC-HOST - Hardware Requirements 10

emulation) that are connected to the Q2/62’s PEM-Out and PEM-In connectors. The PC62 occupies a PC/AT-type 16-bit slot, and uses I/O addresses 31C-31F and 3F8-3FF (COM1), 2F8-2FF (COM2), 3E8-3EF (COM3), 2E8-2EF (COM4), 378-37F (LPT1), or 278-27F (LPT2), as well as memory addresses E4000-EFFFF. Two DB25 connector cut-outs may be required. Installation of the PC62 board is covered in the PC62 Reference Manual.

INTRODUCTION TO PC-HOST - Installation 11

INSTALLATION

Basic PC-Host Installation

1. With the power off, install the hardware key on the PC’s parallel port.

Caution: The hardware key contains sensitive electronic components and should be handled accordingly: always exercise proper static-protection procedures. To prevent damage to the hardware key, never “hot-switch” it—always make sure the power is off before inserting or removing the hardware key.

2. Power up the PC. If DOS is not already installed, install it now. For best results, Skyline recommends that DOS 5.0 or later be used, although DOS 4.01 will also work. If older versions of DOS are used, you may have problems with the VT-100 terminal emulation.

3. Install the ANSI.SYS device driver. A typical CONFIG.SYS file might look like this:

BREAK=ONBUFFERS=20FILES=20LASTDRIVE=ESHELL=C:\DOS\COMMAND.COM /P /E:256DEVICE=C:\DOS\ANSI.SYSINSTALL=C:\DOS\FASTOPEN.EXE C:=(50,25)

An additional line is required for computers that have expanded memory and are to be used to control Q2/62s. See “Expanded Memory Installation,” following.


4. Update the PATH statement in the AUTOEXEC.BAT file to add the path C:\PCHOST.

PATH C:\DOS;C:\PCHOST

5. Install the PC-Host software by inserting the distribution disk in drive A: and typing:

C:> A:INSTALL

The directory C:\PCHOST will be created and the files will be copied into it.

6. If your tester is not capable of loading binary files, delete the files C:\PCHOST\*.BIN as follows:

C:> DEL C:\PCHOST\*.BIN

To add custom features, such as macro definitions or customer screen initialization, to the Q program, create a \PCHOST\Q.BAT file. This file is executed whenever the Q program is started. Its format is the same as that of any Q program batch file.

When it starts up, the Q program requires about 400K bytes in first 640K of main memory. Loading symbol tables and macros and other temporary buffer requirements increase memory use. If expanded memory is not installed, the PC-POB software will use free memory for storing Q2/62 patterns.

Expanded Memory Installation

Expanded memory is no longer required for Q2/62 PC-Hosts. However, the following expanded memory products are recommended:

processor DOS version

expanded memory product

386, 486, Pentium 5.0 EMM386 device driver386, 486, Pentium 5.0 or 4.01 Quarterdeck Expanded Memory Manager 386

(QEMM)286 5.0 or 4.01 Boca Research BOCARAM/AT PLUS board

To install the EMM386 device driver, add a line of the following form to the CONFIG.SYS file immediately after the line that installs the HIMEM.SYS driver:

DEVICE=C:\DOS\EMM386.EXE memory FRAME=address H=handles

· The first value you must supply, memory, is the number of kilobytes of main memory to reserve for expanded memory management. In most cases, you should reserve at least 2M (2048K) as shown in the example below. (If the


computer has only 2M of expanded memory, you should reserve at least 512K of main memory).

· The next value, address, is the address at which to locate the memory page frame. Correct placement of the page frame is essential for proper memory management. Color monitors, Ethernet interfaces and other options may affect the location of the page frame.

Place the page frame at one of the following addresses: C400, C800, CC00, D000, or D400. (If a monochrome monitor is used, place the page frame at C000.) If an Ethernet board is present, its memory location will affect your selection of page frame address as follows: determine the starting address of the Ethernet board, and then place the page frame at the next higher of the addresses given above. For example, if the Ethernet board is at address CC00, place the page frame at address D000. Note that these are general rules, and some situations may have additional considerations. Consult the DOS product manual for complete information.

· The third value, handles, represents the maximum number of pattern files that can be stored in the expanded memory. The default is 64 handles (for 63 pattern files). Skyline recommends that the number be set to the maximum: 255 handles (for 254 pattern files).

Following is a sample line from a CONFIG.SYS file:

DEVICE=C:\DOS\EMM386.EXE 2048 FRAME=D000 H=255

This line reserves 2M (2048K) of main memory, places the page frame at address D000, and sets the number of handles to 255 (for 254 patterns).

To install the Quarterdeck Expanded Memory Manager 386, follow the instructions supplied with the software. Then, find the line in the CONFIG.SYS file that looks like this:

DEVICE=C:\QEMM\QEMM386.SYS

and change it to the following form:

DEVICE=C:\QEMM\QEMM386.SYS FRAME:address HANDLES:handles EXCLUDE=E400-EFFF

· The first value you must supply, address, is the address at which to locate the memory page frame. Note: You must edit this line in the CONFIG.SYS file to move the page frame to an appropriate place, or it may be placed at segment E000, conflicting with the PC62 board. Refer to the general instructions for


placing the page frame, above, and consult the QEMM product manual for complete information.

· The second value, handles, represents the maximum number of pattern files that can be stored in the expanded memory. The default is 64 handles (for 63 pattern files). Skyline recommends that the number be set to the maximum: 255 handles (for 254 pattern files).

Note: The addresses specified with the keyword EXCLUDE= must always be E400–EFFF. These are the addresses used by the PC62 board, and must be excluded from use by the memory manager.

To install the Boca Research BOCARAM/AT PLUS memory add-in board (on 286-based computers only), consult the manufacturer’s instructions.

GPIB Board Installation

If an HP 5370 Time Interval Counter is used for calibration, one of the following National Instruments GPIB Interface Boards must be installed in the computer: AT-GPIB, GPIB-PCII or GPIB-PCIIA. The AT-GPIB/TNT is not recommended. It has been impossible to use this board successfully with the HP5370. (If a GT200 Counter is used, no GPIB board is necessary.)

The board should be installed according to the manufacturer’s instructions. Set the switches on the board to the following default values:

switchr AT-GPIB GPIB-PCII GPIB-PCIIA

ADDRESS 2CO 2B8 2E1INTERRUPT LINE 11 7 7DMA CHANNEL 5 1 1

Note that the GPIB-PCII and GPIB-PCIIA are physically identical, but the software and switch settings are different. Make sure that the switches match the supplied software disk.

1. Insert the National Instruments software disk into floppy disk drive A: and install the software by typing:

C:> A:INSTALL

Press Enter several times to accept all of the default installation parameters.

2. Now connect the counter to the GPIB board and power up the counter.

3. Configure the software with the IBCONF program. For an AT-GPIB board, type:


C:> \AT-GPIB\IBCONF

For a GPIB-PCII or GPIB-PCIIA board, type:

C:> \GPIB-PC\IBCONF

4. After entering the IBCONF program, press the F3 key to configure the software automatically.

5. Next move the cursor to “DEV1” and press F4 to rename “DEV1” to “HP5370.”

6. Press F8 to check the device characteristics. They should be as shown in the following table—correct them if necessary.

Device: HP5370 Access: GPIB0Primary GPIB Address 11Secondary GPIB Address NONETimeout setting T10sEOS byte 00HTerminate Read on EOS noSet EOI with EOS on Write noType of compare on EOS 7-bitSet EOI w/ last byte of Write yesRepeat addressing no

7. Move the cursor back to “GPIB0” and press F8 to check the board characteristics. They should be as shown in the following table—correct them if necessary.

AT-GPIB GPIB-PCII GPIB-PCIIA

Primary GPIB Address 0 0 0Secondary GPIB Address NONE NONE NONETimeout setting T10s T10s T10sEOS byte 00H 00H 00HTerminate Read on EOS no no noSet EOI with EOS on Write no no noType of compare on EOS 7-bit 7-bit 7-bitSet EOI w/last byte of Write yes yes yesGPIB-PC Model — PC2 PC2ABoard is System Controller yes yes yesAssert REN when SC no — —Local Lockout on all devices yes yesEnable Auto Serial Polling yes — —Disable Auto Serial Polling — yes yesDisable Device Unaddressing — no no


Timing 500nsec — —High-speed timing — no noEnable 488.2 Protocols yes — —CIC Protocol no — —Parallel Poll 2 Mode no — —Parallel Poll Enable NONE — —Individual Status Bit false — —Interrupt jumper setting 11 7 7Base I/O Address 02C0H 02B8H 02E1HDMA channel (arbitration) 5 1 1Internal Clock Freq. (in MHz) — 6 6

8. After completing the installation, move to the \PCHOST directory (C:\PCHOST >) and type Q to run the interactive monitor.

C:\PCHOST> Q

9. At the interactive monitor prompt (Q2>), type /R or /RESET to test everything. If the installation was successful, the counter lights will flash and the trigger levels “.15 .15” will be displayed on the front panel.

GT200 Counter Board Installation

A Guide Technology GT200 Counter board can be used for calibration instead of an HP 5370. To install the GT200, set the address switch to hexadecimal 290 (1010 0100) and insert the board in any available slot in the PC.

0 0 0 0 0

1 1 1

1 2 3 4 5 6 7 8

Address 290 (hexadecimal)

QTL PROGRAMMING

QTL COMPILER

Basics

Arithmetic: There are two protocols for arithmetic: sign magnitude (“old math”) and two’s complement (“new math”). By default, “new math” is used—it is appropriate for almost all applications. In some situations where precise backward-compatibility is required, “old math” may be specified by including a HEADER OLD command as the first statement in the QTL program.

Case Sensitivity: Upper and lower case are unique. For example, register “r” is not the same register as “R”. All command names and other keywords must be upper case.

User-defined Identifiers: User-defined labels and register names may contain the following characters:

ABCDEFGHIJKLMNOPQRSTUVWZYZ abcdefghijklmnopqrstuvwxyz 0123456789_#

Do not use command names and other keywords as labels or register names. For example, VOL and VOH may not be used as labels for test blocks, because they are QTL commands.

Labels: Multiple labels on one statement are not allowed.

Strings: Strings may be entered in either the QTL format (<string>) or the C format ("string"). To enter a special character in the QTL format, use a hexadecimal code in the format <code>. To enter a special character in the C format, use an escape sequence beginning with backslash (\). The hex codes and escape sequences are as follows:

Character QTL hex code C escape sequenceLine Feed <0A> \nTab <09> \tBackspace <08> \bCarriage Return <0D> \rForm Feed <0C> \f

Backslash <5C> \\Octal value of character — \number

Some examples of valid strings are:

<This is a QTL string<0D><0A>>"This is a C string\r\n"

Number Base: The default number base is decimal. Hexadecimal numbers may be specified in the QTL format .n, the C format 0xn, or the Intel format 0nH. Some examples of valid numbers are:

1234 .A .0D .ABCDEF 0x0A 0xFFFF 0FFH 01234H

Units: The ambiguous units M, U and N are not accepted.

Logical Operators: The following C logical operators are accepted in expressions:

& | ^ ~ << >> != ==

The PC-Host QTL Compilers

The PC-Host software package contains three QTL compilers:

· QTL52.EXE, for Q2/52 programs only, compiles at about 400 bytes per second on a 20 MHz 386-based computer, or at about 900 bytes per second on a 486-based computer.

· QTL.EXE, for simple SKY284, Q2/62 and Q8000 programs, compiles at about 1K bytes per second on a 20 MHz 386-based computer.

· QTL62.EXE, for SKY284, Q2/62 and Q8000 programs that contain INCLUDE statements, compiles at the same speed as QTL.EXE. See “When to Use QTL62,” below.

The command syntax is the same for all three compilers:

C:\QTL> compiler [/switches] program

where compiler is the appropriate compiler, without its .EXE filename extension (QTL52, QTL, or QTL62) and program is the name of the QTL program, without its .QTL filename extension. The optional compiler switches are described below.

For example, the following command compiles a QTL program named SAMPLE.QTL for the Q2/52:

C:\QTL> QTL52 SAMPLE

The compiler reads the program file (SAMPLE.QTL in this example) and produces two output files: a binary executable (SAMPLE.BIN) and a symbol table (SAMPLE.SYM). Two temporary files (SAMPLE.TMP and SAMPLE.SRC) are also created; they can be deleted after the compile is complete.

Compiler switches: Compiler switches may be entered between the compiler command (QTL52, QTL, or QTL62) and the program name. They may be entered in either lower or upper case: /Q is identical to /q. They may be preceded by either a slash (/) or a hyphen (-): /Q is identical to -Q.

To produce an object (.OBJ) file in Intel hexadecimal format instead of a binary executable, use the /O switch. For example, the following command compiles the file SAMPLE.QTL and produces the output files SAMPLE.OBJ (Intel hex format object file) and SAMPLE.SYM (symbol table):

C:\QTL> QTL /O SAMPLE

To produce an executable (.SAV) file in Intel hexadecimal format instead of a binary executable, use the /S switch. For example, the following command compiles the file SAMPLE.QTL and produces the output files SAMPLE.SAV (Intel hex format executable) and SAMPLE.SYM (symbol table):

C:\QTL> QTL62 /S SAMPLE

NOTE: Q8000 testers do not recognize binary files. Therefore, either the /O or /S switch must be used to compile them into hexadecimal format.

To produce output files in QLINK format, use the /Q switch. For example, the following command compiles the file Q2/52 QTL SAMPLE.QTL and produces the output files SAMPLE.OBJ (QLINK format executable ) and SAMPLE.SYM (symbol table):

C:\QTL> QTL52 /Q SAMPLE

Error messages: Both compilers return error messages that indicate the line numbers where each error occurred. By default, error messages are displayed on the monitor screen—no error list file is produced. To generate a list file with the extension .LST, use the /L switch. For example to generate the list file SAMPLE.LST, type

C:\QTL> QTL52 /L SAMPLE

Error messages may also be redirected to a file using the normal DOS “>” syntax. For example, to redirect all error messages to the file SAMPLE.ERR, type:

C:\QTL> QTL52 SAMPLE >SAMPLE.ERR

You can also type the error message list into DOS’s SORT utility, as follows:

C:\QTL> QTL52 SAMPLE | SORT >SAMPLE.ERR

When to Use QTL62

SKY284, Q2/62 and Q8000 programs that contain INCLUDE statements must be compiled with the QTL62 command instead of QTL, as follows:

C:\QTL> QTL62 [/switches] program

QTL62 takes the same switches (options) as QTL.

Compiling and Linking

Because the QTL program compiles and links in one pass, it needs access to the pattern symbol tables. The PLOAD and PATTERN commands read the pattern symbol table files. For example:

PLOAD PROGPAT

reads the file PROGPAT.SYM to obtain the symbol definitions for the pattern PROGPAT. To ensure that the pattern symbol tables are correct at the time of compilation, compile the pattern(s) before the QTL program.

If a PLOAD statement contains an RT-11 device name, the device name will be ignored for purposes of locating the symbol table file on the PC. For example, the command

PLOAD DL1:PROGPAT.OBJ

will look for the file PROGPAT.SYM on the PC.

The commands “PLOAD PROGPAT” and “QPLOAD PROGPAT” always load at PEM address 0. To load at other addresses, use the commands “PLOAD n,PROGPAT” and “QPLOAD n,PROGPAT”.

Converting QTL Programs for the PC-Host

When converting QTL programs from the PDP-11-based compiler to the PC-Host-based compiler, the most common compatibility problem involves the use of reserved words. The PDP-11-based QTL compiler, unlike most modern compilers, allows a word to be used in many different capacities: as a command, a label, a variable, and a test name, all

in the same program. The PC-Host is much stricter: it allows a word to be used for only one purpose. Therefore, to convert a program to run on the PC-Host, it is essential that all user-defined identifiers do not conflict with the PC-Host compiler’s reserved words. The list of reserved words is found below.

The other common complication occurs because the PC-Host’s QTL compiler performs very rigorous error checking—often finding errors overlooked by the PDP-11 compiler.

Following are some examples taken from actual programs that were converted to run on the PC-Host. Each of the statements in this list is accepted by the PDP-11-based QTL compiler. Following each is an explanation and possible modification to convert the statement for the PC-Host’s QTL compiler.

DOTEST 200,VOLVOL is a reserved word, and hence cannot be used as a user-defined label. To convert this statement for the PC-Host, change VOL to VOLTEST.

FUNTEST EXQ :commentThe PDP-11 compiler accepted a colon (:) instead of a semicolon (;) as the start of a comment. The PC-Host requires that a comment begin with a semicolon.

ASSIGN W=W*2.5Although the Q2 tester can only recognize integers, the PDP-11 compiler accepted real numbers—but then truncated them. (This example would assign W to W*2, not W*2.5.) A better way to achieve the desired result is ASSIGN W=W*5/2.

YALU YMAIN,XCARE,COFF,HOLD,YMAINThe PDP-11 compiler accepted YMAIN instead of DYMAIN; the PC-Host compiler does not.

XALU XUDATA,XCARE,COFF,HOLD,DYMAINThe PDP-11 compiler accepted DYMAIN instead of DXMAIN in microcode for the X address generator; the PC-Host compiler requires the correct keyword DXMAIN.

GETBYTE C,IPORT,FAIL;

QTL PROGRAMMING - QTL Compiler 17

Although the GETBYTE command takes only two arguments, the PDP-11 compiler accepted additional arguments—but ignored them. The PC-Host compiler will report an error if too many arguments are supplied.

IPAR REGISTER,1UALikewise, although this form of the IPAR command takes only two arguments, the PDP-11 compiler accepted additional arguments—but ignored them. The PC-Host compiler will report an error if too many arguments are supplied.

PARTIME 255The maximum PARTIME value accepted by the Q2 tester is 159. If a greater value was supplied, the PDP-11 compiler did not report an error, but set PARTIME to the specified value minus 159. The PC-Host compiler will report an error if a value over 159 is specified.

POBDELETE &LPP.TMPThe PC-Host compiler will not accept an ampersand (&) at the beginning of a filename given as an argument to a command unless the filename is surrounded by quotes or angle brackets: for example, POBDELETE <&LPP.TMP>.

STORE D,<CRCX6Y1X6<0D>>A bug in the PDP-11 compiler caused it to misinterpret double closing brackets (>>) as a single closing bracket (>). Thus, this example would store in register D the string CRCX6Y1X6<0D, not CRCX6Y1X6 followed by a carriage return (hex code 0D). To store the first string (as for the PDP-11), use quotes as follows: STORE D,"CRCX6Y1X6<0D".

STORE STRING.1,<string>,4The PC-Host compiler will report an error if a third argument is supplied to a STORE statement in which the second argument is a string, not the name of a string. The Q2 accepts only three forms of the STORE statement: 1) two arguments: the destination string register and the immediate string, in angle brackets, to store there; 2) two arguments: the destination string register and the source string register; 3) three arguments: the destination string register, the source string register, and the number of characters from the source to store in the destination register. The PDP-11 compiler accepts the form shown above, that is, three arguments: the destination string register, an immediate string, and a limit value.

SETTIMES TLISTAlthough the correct command name is SETTIME, the PDP-11 compiler accepted SETTIMES. The PC-Host compiler will not.


LFLAG = FALSEThe PDP-11 compiler accepted an equal sign (=) in the LFLAG FALSE command; the PC-Host compiler will not.

LFLAG FLASEThe PDP-11 compiler accepted many misspellings such as this; the PC-Host compiler will not.

SKY284, Q2 and Q8000 Reserved Words

For all SKY284, Q2 and Q8000 QTL programs the words listed below are reserved. They should not be used as labels, register names, or any other user-defined constructs.

AND FALSE LPORTA POBDIRECTORY STOREAPPEND FLOAD LPORTB PPARAM STOREBINASSIGN FORCEI LPP PRINT STRINGAUTOSTART FORCEV LSEARCH PRINTDB SUMSTATEAUXPORT FPORTA MACRO PRINTLN SYMBOLBASE FPORTB MAP PSCONNECT SYSTEMBEGIN FRONTA MATCH PSV1 TESTNUMBE

RBEXLPP FRONTB MEASURE PSV2 TESTPINBSEARCH FUNJIF MESSAGE PSV3 TIMEBYTE FUNTEST MOD PTU TIMINGGRO

UPCALIBLOCK GETBYTE NOP PTUCONNECT TNOPCALL GETREG NOT QINSERT TP1CASE GETSTRING OFFSET QPLOAD TPARAMCLEARBINS HAND OPENPSTEST QSCHMOO TRUECLOSE HEADER OPORTA RESETSTOP TRULESCOMPARE I1 OPORTAB RETESTCLEAR TUNDCONMESS I2 OPORTB RETURN UNDEFCONTINUE I3 OR RUN USEDCHANN

ELCREATE IACC10 OSTART SAVE V1CREG IACC75 OSTOP SCHMOO V2CURRENT INCLUDE PARALLEL SCRAMBLE V3CYCLE INITOFF PARAM SENDBYTE VBIASDATA INPUT PARCAL SENDFDM VIHDELAY INSEND PARTEST SENDPGMSEND

REGVIH1

DELAYM INSERT PARTIME SENDSTRING VIH2DISCONNECT

INTERFACE PASS SENDWORD VIHC


DISPLAY IPAR PASSNCL SEQUENCE VILDOSUMMARY

IPORT PASNICL SETCHANNEL VIL1

DOTEST IV1 PASSPCL SETLEVEL VIL2DOUBLEWORD

IV2 PASSVG SETPIN VILC

DPLOT IV3 PASSVL SETTIME VOHEARLY JNSET PATTERN SETUP VOLEND JSET PAUSE SFLAG VOLTAGEENDLIST JUMP PGMBYTE SHL VOUTENDMAC LATE PGMLIST SHR VPARENDTEST LEARN PGMWORD SKIPTO WORDERROR LFLAG PINCONNEC

TSRCDATA WPORT

EX8080 LOADBOARD PINLIST SRCREAD XOREXQ LOADMAP PLOAD SSET XPARAMnFAIL LOG POBDELETE STARTTEST YPARAMn

Q2/52 Reserved Words

The following additional words are reserved by the QTL compiler for the Q2/52.

ABASE CJMPNZ CSUBZ IBINEQ PDELAY SPREVADRACOUNT CJMPZ CURMAR IBINGT PERROR STARTPATTERNACTUALDATA CMEQMAX CURRENT IBINLT PESTEP STARTPGOFFSETADD CMEQMIN DATBUF INC PGMBYTE STATUSADHIZ CMNEMAX DATDAT INCLUDE PGMNOP STEPAFIELD CMNEMIN DATGEN INCR PGMWORD STKPTRALL1S CMPLDR DATJAM INCREMENT PGOFFSET STOPPATTERNALLERR CNTDNDR DATREG INSEND PIPECLEAR STRINGAMAIN CNTDNYN DCOUNT INSERT PLOAD STRTPGOFFSETAMAX CNTUPDR DEC INSFB PLUS SUBTRACTAND CNTUPYN DECR INTADR PNSTEP SUMMARYAOFF COFF DECR2 INTEN POP TIMEAON COLCLEAR DECREMENT INTENADR POSITIVE TIME0ARELOAD COLCOUNT DISABLE INVSNS PREVADR TIME1BBEQMAX COLDUMP DISFB IRAIL PREVDATA TIMENBBEQMIN COLUMN DISPLAY ISOLATE PREVIOUS TRANSFERBBNEMAX COMP DONE ITEST PREVMAR TYPEBBNEMIN COMPARE DOUBLE JAMBUF PROGRAM UDATABCKBITS COMPLETE DOUBLEWORD JAMDAT PSTEP UDATADRBCKDTOP CON DRELOAD JAMJAM PTOLE UDATAJAMBCKDTOPO COUNT DTOPO JAMREG PUSH UDATAYNBCKFDIS COUNTA DUT JOYSTICK PV UNDERBCKFEN COUNTB DUTADR JUMP Q UNREPAIRABLEBCKFUN COUNTC DUTDATA LBDATA QTOLEX URAMSTARTBCOUNT COUNTD DUTLOAD LEX2FB RAS USERGEGIN COUNTE DUTMAR LLOAD RBINn VALUEBFEQMAX COUNTUDATA DXBASE LOAD RCCLEAR VOLTAGE


BFEQMIN CRELOAD DXFIELD LSTART RCDMPBAD VPULSEBFNEMAX CRETE DXMAIN LT RCDMPFIXED VRAILBFNEMIN CRETNE DYBASE LUTDUMP RCINIT WORDBIN CRETNZ DYFIELD LUTLOAD RCREPAIR WRITEBINEQ CRETZ DYMAIN MAPCOMMOFF RCREPDONE XALUBINGT CS1 ECCLEAR MAPDUMP READ XBASEBINLT CS1F ECOUNT MAPSELECT RED XBMSCRAMBLEBITMAP CS1HIZ ECR MAR RELOADA XCAREBLUE CS1PF ECRSEG MARSEGMENT RELOADB XEQBBMEQMAX CS1PT ECRSEGMENT MINUS RELOADC XEQBORFBMEQMIN CS1RDF ENABLE MMINIT RELOADD XEQYBPNBMNEMAX CS1RDT ENDLEX MMVALUE RELOADE XEQYPNBMNEMIN CS1T ENDLIST MVINIT REPAIR XFIELDBOFF CS2 ENDREPEAT NEGATIVE REPAIRABLE XLEBBON CS2F EPM NOCLKS REPEAT XLTBBOOST CS2HIZ EQFDIS NOCLOCK RESET XMAINBRANCH CS2PF ERELOAD NOCLOCKS RESETERR XMAXBRELOAD CS2RDF ERRADR NOCOUNT RETADR XORBSRINIT CS2RDT ERRCOUNT NODEST RETQ XORINVBSRLOAD CS2T ERRMAR NOERROR RETURN XOUTBUFBUF CS3 ERROR NOERRORS ROTLDR XTOPOBUFDAT CS3F ERRORS NOINT ROTRDR XUDATABUFFER CS3H1Z EXPECTDATA NOREAD ROW XYEQBBUFJAM CS3PF EXQ NOT ROWCLEAR XYLEBXFBYTE CS3RDF EXU NOTCOMPLETE ROWCOL XYLEBYFCAS CS3RDT FBINn NOTINV ROWCOUNT XYLTBXFCBAR CS3T FULL NOTZERO ROWDUMP XYLTBYFCBEQMAX CS4 FULLEC NUMXBITS RSTTMR YALUCBEQMIN CS4F GENERATE NUMYBITS SDUTADR YBASECBINn CS4HIZ GENERR ONLY SELECTBUF YBMSCRAMBLECBNEMAX CS4PF GETREG OR SENDPGM YEQBCBNEMIN CS4RDF GOSUB OUTHIGH SENDREG YEQBORFCBXPND CS4RDT GREEN OUTLOW SERRADR YFIELDCCAL CS4T GT OVER SET YINDEXCCOUNT CS5 HALT OXBASE SETADDRESS YLEBCFEQMAX CS5F HOLD OXFIELD SETCHIPSON YLTBCFEQMIN CS5PF HOLDDR OXMAIN SETDATA YMAINCFNEMAX CS5T HOLDYN OYBASE SETJAM YMAXCFNEMIN CSLOAD HOME OYFIELD SHLDR YOUTCHECKSUM CSUBE HTOLEX OYMAIN SHLEFT YTOPOCHIPS CSUBNE HVM P2HOST SHRDR YUDATACJMPE CSUBNZ IBIN PATTERN SHRIGHT ZEROCJMPNE

QTL PROGRAMMING - Basic Program Components 21

BASIC PROGRAM COMPONENTS

Program Header

The first section of every QTL program is known as the Program Header. It contains one HEADER statement and one or more LOADBOARD statements.

The first command in the Program Header must be a HEADER command. Its argument specifies the type of arithmetic that will be used throughout the program.

HEADER Use two’s complement arithmetic (“new math”). For all Q2 programs.

HEADER 2SCOMP Use two’s complement arithmetic. For all Q2 programs.HEADER NEW Enable operation of more than 40 pins and more than 256

registers. For ESCape only.HEADER OLD Use sign magnitude (“old math”). For all Q2 programs.HEADER Q8000 For Q8000 programs only.

Immediately following the HEADER command are one or more LOADBOARD commands.

LOADBOARD number, label For load board ID number, use product header at label.

A single program may be used with different load boards to test different device types; the LOADBOARD commands specify which product header (described below) to use for each valid load board ID. Note that for the purposes of selecting a product header, only the six most significant bits of the load board ID are checked: load board ID numbers .B8, .B9, .BA, and .BB are considered the same.

A typical Program Header might look like this:

HEADERLOADBOARD .80,PH1LOADBOARD .40,PH2LOADBOARD .20,PH3LOADBOARD .10,PH4

This example specifies that two’s complement math will be used. Four load board IDs are given, each with a label to a product header. (The load board IDs in this example are given in hexadecimal, as indicated by the “.” preceding each.)


Product Header

The Product Header section follows the Program Header. The Product Header defines timing groups, tester channels used, sequence and binning instructions, and pin scrambling. The Product Header contains the following command types:

TIMINGGROUP group, pins Orders system timing channels into hardwired groups. TIMINGGROUP statements are required in Q2/52 programs and optional in Q2/62 programs.

USEDCHANNEL channels Specifies which PE channels are used.SEQUENCE label1, label2, label3, label4 Specifies which sequence and binning table to

use, based on the load board ID.SCRAMBLE channels Specifies scrambling information between

DUT pins and PE channels.

TIMINGGROUP statements define hardwired groups of timing channels by name. TIMINGGROUP statements are optional in Q2/62 programs. In Q2/52 programs, TIMINGGROUP statements are not only required, but they must appear exactly as follows:

TIMINGGROUP FORMAT,18,1,2,3,4,5,11,12,14TIMINGGROUP CLOCKS,17,6,7,8,9,10TIMINGGROUP STROBE,19,13

(On Q2/52s, timing channels 1 though 14 and 17 though 19 are permanently hardwired.)

USEDCHANNEL statements take one or more arguments; the arguments are the numbers of PE channels used by the DUT. (This is another difference from the PDP-11 compiler, which had a limit of eight arguments.) At least one USEDCHANNEL statement is required in every program. See the example following.

The SEQUENCE statement specifies four sequence and binning tables, each identified by a unique label. The load board ID, also known as the “SET” variable, determines which of the four Sequence and Binning Tables is used. If the SET variable is 00, the first of the four Sequence and Binning Tables is used; if the SET variable is 01, the second is used, and so on.

The optional SCRAMBLE statements make up the “scramble table,” which defines the correspondence between DUT pins and the PE channels. Each of the PE channels must be assigned to a unique DUT pin; each SCRAMBLE statement can list one or more channels. DUT pins used for power supplies or ground should be assigned to unused PE channels. See the example following.

A typical Product Header might look like this:


PH1: TIMINGGROUP FORMAT,18,1,2,3,4,5,11,12,14TIMINGGROUP CLOCKS,17,6,7,8,9,10TIMINGGROUP STROBE,19,13USEDCHANNEL 1,2,3,5,6,10,11,12USEDCHANNEL 13,14,21,22,23,24SEQUENCE SB1,SB2,SB3,SB4SCRAMBLE 1,2,3,11,5,6,12,4SCRAMBLE 13,10,21,14,22,23,24,7SCRAMBLE 8,9,15,16,17,18,19,20SCRAMBLE 25,26,27,28,29,30,31,32SCRAMBLE 33,34,35,36,37,38,39,40

In this example, fourteen PE channels are used—they are specified in the two USEDCHANNEL statements. The four possible sequence and binning tables appear at labels SB1, SB2, SB3, and SB4. The first eight PE channels correspond to DUT pins 1, 2, 3, 11, 5, 6, 12, and 4, the next eight to DUT pins 13, 10, 21, etc. Forty PE channels must be accounted for in the SCRAMBLE statements, even though only 14 are used, unless HEADER NEW is specified.

Sequence and Binning Tables

The Sequence and Binning Tables follow the Product Header. The Sequence and Binning (“S&B”) Tables specify messages, actions to be taken upon BEGIN, SUMMARY or READY instructions, and (optionally) Calibration Blocks.

Each S&B Table must be indicated by a unique label. (See the example following.)

Messages and Calibration Block Section. The first part of each Sequence and Binning Table contains messages and specification of the Calibration Block, if used.

MESSAGE <message> Prints a message to the monitor at runtime.

MESSAGE < message>,begin, summary Prints a message; specifies labels for BEGIN and SUMMARY instructions.

MESSAGE <message>, begin, summary, ready Prints a message; specifies labels for BEGIN, SUMMARY, and READY instructions.

CONMESS <message> Prints continuation of a message.CALIBLOCK calblock Specifies a label for Calibration

instructions.

A program can contain up to four MESSAGE statements. If multiple MESSAGE statements are used, the least significant two bits of the load board ID (the “SET” variable) determine which message is printed (SET=00 prints the first message, SET=01 prints the second, etc.)


MESSAGE statements can have two or three labels after the message string. If two labels are given, they point to blocks of instructions to be executed at BEGIN and SUMMARY operations, respectively. If a third label is given, it points to a block of instructions known as the READY Block, which is optionally executed after each device is tested.

The CONMESS (continuation of message) statement should be used for messages that are longer than one line.

A CALIBLOCK (calibration block) statement may be used at the end of the message section. It specifies a label that points to the Calibration Block, a set of tests that can be executed when the Q2’s single-step switch is used. If no Calibration Block is specified, one will be automatically generated by the compiler, consisting only of an ENDTEST statement.

Sequence Blocks. Following the messages section of the S&B Table are one or more sequence blocks. Each sequence block specifies a test and the actions to take upon pass or fail, and is made up of three statements:

DOTEST number, label Execute test number located at label.PASS action [, action, action...] If the test passes, then take actions.FAIL action[, action, action...] If the test fails, then take actions.

The possible actions are summarized below:

PASSBIN Increment the units-passed and units-tested counters on the front panel and light the green pass light on the test deck.

PARFAIL Light the parametric error indicator on the front panel and activate the PARFAIL signal on the handler interface.

FUNFAIL Light the functional error indicator on the front panel and activate the FUNFAIL signal on the handler interface.

FAILBIN Increment just the units-tested counter on the front panel and light the red fail light on the test deck.

OPENFAIL Light the open pin indicator on the front panel and activate the OPEN signal on the handler interface.

INTBIN+n Activate the BINn signal on the handler interface. (BIN1 through BIN6 are available.)

INTBINn Same as INTBIN+n.IBINn Same as INTBIN+n.DATABIN+n Increment data bin n. There are 32 data bins (1 to 32).DATABINn Same as DATABIN+n.DBINn Same as DATABIN+n.BINn Same as DATABIN+n.


NODETAIL Disable detailed print out, overriding the front panel DETAIL switch.

RETEST Decrement all bins set by the previous test and activate the RETEST signal on the handler interface.

STOP Stop testing.label Branch to label.NEXT Proceed to the next test.[no action] Same as NEXT.

Binning takes place only when a STOP is reached, and only the most recent information is used for binning.

Example. A typical Sequence and Binning Table might look like this:

SB1: MESSAGE <8226 PROGRAM >,BEGINBLOCK,SUMMARYBLOCKCONMESS <JULY 27, 1990>

CALIBLOCK CALIBBLOCK

DOTEST 100,SHORTSPASSFAIL STOP,PARFAIL,DBIN6,INTBIN+6

DOTEST 150,OPENSPASSFAIL STOP,OPENFAIL,DBIN6,INTBIN+6

DOTEST 200,INLEAKPASSFAIL STOP,PARFAIL,DBIN5,INTBIN+5

DOTEST 300,OUTLEAKPASSFAIL STOP,PARFAIL,DBIN5,INTBIN+5

DOTEST 400,ICCPASSFAIL STOP,PARFAIL,DBIN4,INTBIN+4

DOTEST 500,FUNCTPASSFAIL STOP,FUNFAIL,DBIN2,INTBIN+2

DOTEST 600,CHARPASS STOP,PASSBIN,DBIN1,INTBIN+1FAIL STOP,FUNFAIL,DBIN2,INTBIN+2

In this example, the Sequence and Binning Table is located at the label SB1. The message (“8226 PROGRAM”) is printed and labels are given pointing to a BEGIN Block (“BEGINBLOCK”) and a SUMMARY Block (“SUMMARYBLOCK”). The message continues with “JULY 27, 1990”. The Calibration Block is named “CALIBBLOCK”.

There are seven sequence blocks. The first six each executes a test (specified by number and name), proceeds to the next test on pass, and stops testing and bins on fail. The last stops testing and bins on both pass and fail.


Test Blocks: Pin Setup

Each test block consists of setup commands and test commands. There are three kinds of setup commands: pin setups, voltage and current setup, and timing setups.

The first set of setup commands specifies the pins for testing.

SETPIN Specifies the DUT pins to be tested: a list of PINLIST statements follows immediately, and is terminated with an ENDLIST statement.

SETPIN label Like SETPIN, but the list of PINLIST statements begins at label.

SETPIN pin#, pin#, pin# ... Specifies the DUT pins to be tested.PINLIST pin#, pin#, pin# ... Lists DUT pins by number in the order in which they will

be tested. Each PINLIST statement can list one or more pins.

ENDLIST Terminates a series of one or more PINLIST statements.

In each test block, the SETPIN statement specifies the pinlist to be tested in that test block and the order in which to test the pins in it. A pinlist is a series of one or more PINLIST statements terminated with an ENDLIST statement, and can be either immediate or remote: it can appear immediately following the SETPIN statement or it can appear at a label elsewhere in the program. To exclude all pins from a test block, use a PINLIST statement with no arguments.

Test Blocks: Voltage and Current Setup

SETCHANNEL Specifies voltages and currents to be set, sensed, or forced: a “channel list” follows immediately, and is terminated with an ENDLIST statement.

SETCHANNEL label Like SETCHANNEL, but the channel list begins at label.SETLEVEL Specifies voltages and currents to be set, sensed, or forced:

a “channel list” follows immediately, and is terminated with an ENDLIST statement.

SETLEVEL label Like SETLEVEL, but the channel list begins at label.voltage value Sets voltage to value.voltage register Sets voltage to value stored in register.current value Sets current to value.current register Sets current to value stored in register.


current number, multiplier

Sets current to number * multiplier.

ENDLIST Terminates a series of one or more voltage or current assignments.

The Channel List. In each test block, the SETCHANNEL statement specifies the voltages and currents to be set, sensed, or forced in that test block. The complete set of voltages and currents is called the “channel list.” Like the pinlist, the channel list can be immediate or remote: it can appear immediately following the SETCHANNEL statement or it can appear at a label elsewhere in the program.

Voltage Parameters. Channel lists can contain the following voltage parameters:

V1, V2, V3 DUT power supplies available at the load board. V1 and V2 are positive; V3 is negative.

VBIAS Voltage available on the load board; can be used to supply power to device loads.

VIH, VIH1, VIH2, VIL, VIL1, VIL2

High and low rails for pin electronics channels: VIH1/VIL1 for channels 1–10 and 31–40, VIH2/VIL2 for channels 11–30. VIH sets VIH1 and VIH2; VIL sets VIL1 and VIL2. Do not program VIH1 and VIH2 below 1.8V. Note that all drivers have source impedance of 50W.

VIHC, VILC Additional reference voltages available on the load board.VOH, VOL, VOUT

Output reference voltages for functional tests. For high, anything above VOH passes, for low, anything below VOL passes. VOUT sets both VOH and VOL to the same value.

VPAR Voltage for parametric tests: either a compare level or a forced voltage. See the description of PARTEST.

VRAIL Voltage available on the load board. Often used for device programming (SKY284 only).

Units that can be included with voltage values are V (volts), MV (millivolts), and UV (microvolts). Units must follow the values immediately, with no space in between. If units are not specified, values for voltages are assumed to be millivolts.

Current Parameters. Channel lists can contain the following current parameters:

I1, I2, I3 Comparison or force levels for power supply currents. See the description of PARTEST TESTSUPPLY and FUNTEST TESTSUPPLY.

IV1, IV2, IV3 Same as I1, I2, and I3.IPAR Current used for parametric tests: either a compare level or a forced

current. See the description of PARTEST.

Units that can be included with current values are MA (milliamps), UA (microamps), and NA (nanoamps). Units must follow the values immediately, with no space in between. If units are not specified, values for currents are assumed to be milliamps.


Currents in channel lists can also be specified as a number and a multiplier; the different currents accept different multipliers, as follows:

Current Multipliers Allowed

I1 100UAI2 100UAI3 1UA, 10UA, 100UAIPAR 1NA, 10NA, 100NA, 1UA, 10UA, 100UAIV1 100UAIV2 100UAIV3 1UA, 10UA, 100UA

For example, both of the following statements set IPAR to 200 microamps:

IPAR 200UAIPAR 2000,100NA

Q2 and Q8000 Resolutions. The value ranges and resolutions for all the Q2 and Q8000 voltage and current parameters are as follows:

Voltage Parameters Current Parameters

parameter minimum maximum resolution parameter minimum maximum resolution

VHI1 1800MV 7000MV 5MV IV1 0 400MA 200UAVIH2 1800MV 7000MV 5MV IV2 0 200MA 100UA

VIH 1800MV 7000MV 5MV IV3 -2MA 0 1UAVIL1 -1500MV 2000MV 5MV IV3 -20MA 0 10UAVIL2 -1500MV 2000MV 5MV IV3 -200MA 0 100UA

VIL -1500MV 2000MV 5MV IPAR -2UA 2UA 1NAVIHC 0 20000MV 5MV IPAR -20UA 20UA 10NAVILC -1500MV 5000MV 5MV IPAR -200UA 200UA 100NA

VBIAS 0 5000MV 5MV IPAR -2MA 2MA 1UAVBIAS -6000MV -6000MV 6000MV IPAR -20MA 20MA 10UA

V1 0 20000MV 5MV IPAR -100MA +100MA 100UAV2 0 20000MV 5MVV3 -15000MV 0 5MV

VOH -1500MV 5000MV 5MVVOL -1500MV 5000MV 5MV

VOUT -1500MV 5000MV 5MVVPAR -5000MV 20000MV 5MV


When setting current parameters, consider the direction of current flow, not just the magnitude. The current flowing from the tester into the DUT pin is positive; the current flowing from the DUT towards the tester is negative.

Take care to respect the minimum limit of 1800 millivolts (1.8 volts) for VIH1 and VIH2. Programming below 1.8 volts could cause inaccurate voltage levels at the DUT or damage the tester hardware.

SKY284 Resolutions. The value ranges and resolutions for all the SKY284 voltage and current parameters are as follows:

Voltage Parameters Current Parameters

parameter minimum maximum resolution parameter minimum maximum resolution

VHI1 -1500MV 7000MV 1.25MV IV1 0 1MA 62.5NAVIH2 -1500MV 7000MV 1.25MV IV1 0 10MA 625NAVIH -1500MV 7000MV 1.25MV IV1 0 100MA 6.25UA

VIL1 -2000MV 6000MV 1.25MV IV1 0 1000MA 62.5UAVIL2 -2000MV 6000MV 1.25MV IV2 0 4MA 250NA

VIL -2000MV 6000MV 1.25MV IV2 0 40MA 2.5UAVIHC 0 20000MV 1.25MV IV2 0 400MA 25UAVILC -2000MV 8000MV 1.25MV IV3 -4MA 0 250NA

VBIAS -6000 8000MV 1.25MV IV3 -40MA 0 2.5UAV1 0 20000MV 1.25MV IV3 -400MA 0 25UAV2 0 20000MV 1.25MV IPAR -2UA 2UA 1NAV3 -15000MV 0 1.25MV IPAR -20UA 20UA 10NA

VOH -2000MV 7000MV 1.25MV IPAR -200UA 200UA 100NAVOL -2000MV 7000MV 1.25MV IPAR -2MA 2MA 1UA

VOUT -2000MV 7000MV 1.25MV IPAR -20MA 20MA 10UAVPAR -5000MV 20000MV 1.25MV IPAR -100MA +100MA 100UA

VRAIL 0 28000MV 2MV

Multiple Settings for Individual Parameters. If a channel list contains more than one setting for the same voltage or current parameter, the SET variable (least two significant bits of the load board ID) is used to determine which setting is used: the first setting if SET=00, the second setting if SET=01, etc.) Note, however, that multiple settings cannot be specified for VIH and VIL, since they each set two parameters (VIH sets VIH1 and VIH2; VIL sets VIL1 and VIL2). In addition, all values for a single parameter must have the same sign and the same resolution; therefore, when multiple values are given for a current parameter, they should be specified in terms of a unit and a multiplier.

When Parameters are Reset. Voltage and current parameters settings remain in effect until a subsequent SETCHANNEL statement. All voltage and current parameters are set to 0 at the end of each BEGIN Block and each SUMMARY Block, and at the end of program execution (STOP in the sequence and binning table).


VPAR vs. IPAR. The allowable values for VPAR and IPAR are interrelated. The following diagram shows the operating region of the Parametric Test Unit and the trade-offs between IPAR and VPAR.

Examples. Following are some examples of channel lists.

The immediate channel list sets V1 and VPAR each to 5.25 volts and IPAR to 80 microamps.

SETCHANNELV1 5.25VVPAR 5.25VIPAR 80UA

ENDLIST

This immediate channel list sets VIH (that is, both VIH1 and VIH2) to 4 volts, VIL (that is, both VIL1 and VIL2) to 0 volts, and both VOL and VOH to 1.5 volts.

SETCHANNELVIH 4VVIL 0VVOL 1.5VVOH 1.5V

ENDLIST

This SETCHANNEL statement references a remote channel list that appears later in the program at the label SHORTS.


SETCHANNEL SHORTS

These are several remote channel lists that could be referenced in SETCHANNEL statements earlier in the program.

SHORTS: V1 0VVIL1 0VVIL2 0VVIH1 0VVIH2 0VVPAR 300MVIPAR 100UAENDLIST

INLEAK: VPAR 5.25VIPAR 20UAENDLIST

OUTLEAK: VPAR 0.45VIPAR 20UAVIH1 4VVIH2 4VENDLIST

ICC: V1 5.25VI1 120MAENDLIST

Test Blocks: Timing Setup

SETTIME Specifies timing parameters: a “timing list” follows immediately, and is terminated with an ENDLIST statement.

SETTIME label Like SETTIME, but the timing list begins at label.CYCLE time Sets the cycle time (period) to time.START channel, time Sets the start edge of channel to time.START channela, channelb, time Sets the start edges of channela through channelb to time.STOP channel, time Sets the stop edge of channel to time.STOP channela, channelb, time Sets the stop edges of channela through channelb to time.SENDPTG <command> Send command to PTG (ESC only). Example:

SENDPTG <DSTART 1=0>ENDLIST Terminates a series of one or more timing assignments.


The Timing List. The SETTIME statement sets the timing parameters for the test block. The complete set of timings is called the “timing list.” Like the pinlist and channel list, the timing list can be immediate or remote: it can appear immediately following the SETTIME statement or it can appear at a label elsewhere in the program.

Timing lists can contain three statement types: CYCLE, START, and STOP. CYCLE sets the cycle time: the period, in nanoseconds, for the device address and for always-enabled timing channels. START and STOP set the start and stop edges of one or more channels to a time, in nanoseconds, relative to the beginning of the cycle (i.e., the DUT address transition).

Resolution and Pulse Width Limits. The Q2 cycle time resolution, start and stop edge resolution, and minimum pulse width achievable for any timing channel depends on the cycle time specified in the CYCLE statement, as follows:

Cycle TimeCycle Time Resolution

Q2 Start and StopEdge Resolution

Q2 Minimum Pulse Width

SKY284 Minimum Pulse Width

25–49.875 ns .125 ns – – 6 ns50–99.75 ns .25 ns – – 6 ns

100–199.5 ns 0.5 ns 0.1 ns 25 ns 6 ns200–399 ns 1 ns 0.1 ns 25 ns 6 ns400–798 ns 2 ns 0.2 ns 27 ns 6 ns

800–1596 ns 4 ns 0.25 ns 30 ns 6 ns1600–3192 ns 8 ns 0.5 ns 36 ns 6 ns3200–6384 ns 16 ns 1.0 ns 44 ns 6 ns

6400–12768 ns 32 ns 2.0 ns 64 ns 6 ns

On the Q2/52, timing generators can be combined to achieve narrower pulse widths than possible with individual timing generators. The practical limits of the PGM are as follows: for clocks, 20 ns; for address channels, 22 ns; for data channels, 22 ns; and for strobes, 19 ns.

Setting Both START and STOP Edges. If a timing is specified for the start edge of a channel, a timing must also be specified for the stop edge of that channel, and vice versa. Note that on Q2/52s, timings can be set automatically for the start and stop edges of certain edges; see the description of TRULES, below.

Multiple Settings for Individual Edges. If a timing list contains more than one setting for the same edge, the SET variable (least significant two bits of the load board ID) is used to determine which timing is used: the first timing if SET=00, the second timing if SET=01, etc.


When Channels are Reset. Timing channels are not reset automatically at the end of a QTL program or in the BEGIN and SUMMARY Blocks. The only way to reset a timing channel is with a SETTIME statement.

Test Blocks: Additional Setup

SYMBOL <file> Loads symbol table from file.SYMBOL register Loads symbol table from register.LPP <file> Loads pattern program from file.LPP register Loads pattern program from register.TRULES setting Specifies whether or not timing rules are set automatically.OFFSET tablenumber Loads resident timing offset tablenumber.FLOAD <file> Loads timing offset table from file.FLOAD register Loads timing offset table from register.INITOFF Begins initial timing offset table.OSTART edge, time Sets offset for start edge to time.OSTOP edge, time Sets offset for stop edge to time.BASE group, time Sets base time for group to time.EARLY group, time Sets early time for group to time.LATE group, time Sets late time for group to time.TP1 Disconnects test point 1 on the load board. Used for some

calibration operations.TP1 connection Connects test point 1 on the load board to connection,

which must be one of the following: SYNC (that is, scope sync), T0, TG0, or TMAX/2.

DELAY time Sets delay to time. For Q2/62 programs only.DELAY mode Sets delay to mode, which must be one of the following:

INHIBIT, SYNC, or TG0. For Q2/62 programs only.

Loading the Symbol Table. The “symbol table,” generated by the compiler, lists all user-defined register names and memory locations. Without the symbol table, user-defined registers cannot be resolved. The symbol table is not loaded automatically—it must be loaded via a SYMBOL statement within the QTL program, preferably in the Begin Block.

Loading the Pattern File(s). Likewise, the pattern files are not loaded automatically—they must be loaded via LPP (Load Pattern Program) statements within the QTL program, preferably in the Begin Block.

The TRULES statement affects the automatic setting of timing rules for Q2/52s only. When TRULES is set to ON, certain edges of timing channels used as internal clocks in the Q2/52 are programmed automatically. These are the stop edges of channels 6, 8, and


13, and the start edges of channels 20, 21, and 22. When TRULES is set to OFF, these edges can be user-programmed; this is necessary for double-pulsed chip selects or when two strobes per cycle are required. When TRULES is set to OVERRIDE, these edges are programmed automatically but can also be programmed by the user. The default setting for TRULES on the Q2/52 is ON. For Q2/62s, TRULES is unnecessary, because the Q2/62 does not use timing channels as internal clocks.

The OFFSET statement specifies which resident offset table to use. Offset tables, which contain an offset value for each of the timing edges, are generated during offset calibration. Offset tables can be stored in memory on the PGM or SRC.

The FLOAD statement specifies an offset table stored on disk or in a system register (which must be a 14-byte-long string register).

Test Blocks: Setup for Parametric Tests

PARCAL Perform leakage calibration on all 40 pins at six voltages from -5 volts to +20 volts.

PARCAL pinlist Perform leakage calibration on pinlist at six voltages from -5 volts to +20 volts.

PARCAL minimum, maximum Perform leakage calibration on all pins at six voltages from minimum voltage to maximum voltage.

PARCAL minimum, maximum, pinlist

Perform leakage calibration on pinlist at six voltages from minimum voltage to maximum voltage.

PARTIME delay Set the delay between when a voltage or current is forced and when the test condition is checked.

Parametric Calibration Offsets. In order to achieve accuracy of ±10 nanoamps (as specified by the IACC10 operand to FORCEV), the PTU must compensate for the leakage current contributed by the load board in use and the tester itself. This is done by measuring the leakage current at each pin at several voltages; a complete set of leakage measurements is called a leakage current offset table. Since the leakage current varies with each individual load board or test fixture and is affected by external factors as well, a new leakage current offset table should be generated each time a BEGIN Block is executed. The PARCAL statement generates a leakage current offset table. With no operands, it generates an offset table for all pins at six voltages: from -5, 0, +5, +10, +15, and +20 volts. Calibration of all 40 pins at all six voltages takes about one minute. PARCAL accepts operands to limit the pins calibrated and to narrow the range of voltages at which pins are calibrated. If minimum and maximum voltages are specified, they should be outside the PARTEST voltages.


For information on displaying the leakage current offset table or writing it to a file, see the description of the Q-Monitor command PARDUMP.

All leakage offset values are set to zero when the tester is powered up or reset, or when a BEGIN block is entered.

If PARCAL detects a leakage current in excess of ±250 nanoamps, it sets the logic (pass/fail) flag to false, displays a message identifying the failing pin, and sets the leakage offset value for that pin to 0. PARCAL will complete calibration of all pins before reporting failures.

Parametric Test Delay. Ordinarily, the PTU waits from 350 to 700 microseconds between forcing a voltage or current and checking for the test condition. This time delay depends on tester firmware revision and PTU range. The PARTIME statement can be used to provide additional delay if necessary. Specify a single delay value in milliseconds, from 1 to 159. (Do not use units.) The delay specified by PARTIME will be added to the default 700 microsecond delay. There is no way to achieve a delay of less than 700 microseconds.

The parametric test delay set by PARTIME remains in effect and is used for all parametric tests until explicitly reset by another PARTIME command.

Test Blocks: Parametric Tests

OPENPSTEST powersupply Perform an opens test on an individual powersupply pin: V1, V2, or V3.

PARTEST TESTSUPPLY Perform a parametric test of the power supply pins.

PARTEST FORCEV, passcondition Force voltage and measure current on the selected pins sequentially in the order in which they appear in the SETPIN statement; pass if the passcondition is met.

PARTEST FORCEV, passcondition, PARALLEL Force voltage and measure current on all the selected pins in parallel; pass if passcondition is met.

PARTEST FORCEV, passcondition, PARALLEL, PTU Force voltage and measure current on all the selected pins in parallel; sense current at the PTU; pass if passcondition is met.

PARTEST FORCEV, passcondition, accuracy Force voltage and measure


current on the selected pins sequentially in the order in which they appear in the SETPIN statement; measure current in the specified accuracy range; pass if the passcondition is met.

PARTEST FORCEI, passcondition Force current and measure voltage on the selected pins sequentially in the order in which they appear in the SETPIN statement; pass if the passcondition is met.

PARTEST FORCEI, passcondition, PARALLEL Force current and measure voltage on all the selected pins in parallel; pass if passcondition is met.

PARTEST FORCEI, passcondition, PARALLEL, PTU Force current and measure voltage on all the selected pins in parallel; sense voltage at the PTU; pass if passcondition is met.

Power Supply Pin Tests. Since power supply pins are hardwired on the load board and not included in any pin list, the usual parametric test commands cannot be used on them.

OPENPSTEST performs an opens test on one power supply pin: it determines whether or not the pin is physically connected in the socket. Specify either V1, V2, or V3. The current specified by IPAR is forced on the pin; the test passes if the sensed voltage is within the limit set by VPAR (for V1 and V2) or VOL (for V3). VPAR must be -2.5 volts or greater; VOL should be 4 volts or less, and for V3, IPAR must be positive.

PARTEST TESTSUPPLY forces a voltage onto the last power supply pin to which a current was assigned in a channel list. The test passes if the sensed current is less than the supply level in the channel list for whichever supply was last set: IV1, IV2, or IV3.

Parallel vs. Sequential Parametric Tests. Ordinarily, the PARTEST commands perform parametric tests on DUT pins in the order in which they appear in the SETPIN statement in the test block. If PARALLEL is specified, the pins are tested in parallel. The IPAR value is compared against the sum of the currents drawn by all the pins in the pin list.

Sensing at the PTU During Parallel Tests. If PARALLEL, PTU is specified, current sensing takes place at the Parametric Test Unit (PTU) instead of at the first pin in the pin list. This is only possible for parallel tests.

Force Voltage/Measure Current Tests. The PARTEST FORCEV commands all force voltage and measure current on the pins specified in the SETPIN statement in the test


block. The test passes if the specified pass condition is met. There are three pass conditions:

PASSNCL “Pass if within Negative Current Limit”: Pass if the negative current measured (that is, current flowing from the DUT to the PTU) is greater than the magnitude of IPAR.

PASSPCL “Pass if within Positive Current Limit”: Pass if the positive current measured (that is, current flowing from the PTU to the DUT) is greater than the magnitude of IPAR.

PASSNICL “Pass if Not In Current Limit”: Pass if the magnitude of the current (either direction) is less than the magnitude of IPAR.

The following drawing illustrates these pass condition ranges:

Different Accuracy Levels for Current Tests. Ordinarily, force voltage/measure current tests operate at an accuracy range of ±250 nanoamps. Greater accuracy can be achieved, at the expense of throughput, by specifying either IACC75 or IACC10 (for ±75 nanoamps or ±10 nanoamps, respectively) with the FORCEV statement. Note that if IACC10 is specified, a PTU calibration offset table must be generated via a PARCAL statement—see “Test Blocks: Setup for Parametric Tests,” below.

Parallel vs. Sequential Parametric Tests. Ordinarily, the PARTEST commands perform parametric tests on DUT pins in the order in which they appear in the SETPIN statement in the test block. If PARALLEL is specified, the pins are tested in parallel. The IPAR value is compared against the sum of the currents drawn by all the pins in the pin list.

Force Current/Measure Voltage Tests. The PARTEST FORCEI commands all force current and measure voltage on the pins specified in the SETPIN statement in the test block. The test passes if the specified pass condition is met. There are two pass conditions:

PASSVG “Pass if Voltage is Greater than VPAR”: Pass if the voltage measured is greater than the VPAR parameter.

PASSVL “Pass if Voltage is Less than VPAR”: Pass if the voltage measured is less than the VPAR parameter.


Test Blocks: Setup for Functional Tests

PSCONNECT Disconnects all three power supplies: V1, V2 and V3.

PSCONNECT supply Connects one power supply.PSCONNECT supply, supply Connects two power supplies.PSCONNECT supply, supply, supply Connects three power supplies.DISCONNECT Disconnects specified PE channels: a list of

PINLIST statements follows immediately, and is terminated with an ENDLIST statement.

DISCONNECT label Like DISCONNECT, but the list of PINLIST statements begins at label.

DISCONNECT pin#, pin#, pin# Disconnects specified PE channels.DISCONNECT OLD Disconnect works the old way (default).DISCONNECT NEW Disconnect works the new way.DISCONNECT SELFTEST Drivers are not disconnected during parametric

tests (ESC only).DISCONNECT V3_VPAR Connect V3 to VPAR (ESC only).DISCONNECT V3 Disconnect V3 from VPAR (ESC only).PINCONNECT Connects all pins in USEDCHANNEL list.PTUCONNECT Connects PTU to pins in last-specified pin list;

sense first pin.PTUCONNECT PTU Connects PTU to pins in last-specified pin list;

sense at PTU.

Power Supply Connections. By default, all power supplies are connected to the DUT. The PSCONNECT statement connects exactly zero, one, two, or all three supplies. Any power supply not specified in the last-executed PSCONNECT statement is disconnected.

PE Channel Connections. By default, all pin electronics channels are connected. The DISCONNECT statement disconnects one or more channels that correspond to the DUT pin numbers in the PINLIST statements that follow. The PINCONNECT statement can be used to reconnect all the pin channels specified in the USEDCHANNEL statements (in the Product Header).

Parametric Test Unit Connections. The PTUCONNECT statement connects the Parametric Test Unit in parallel to all the pins in the current pin list; sensing occurs at the first pin in the list. If PTUCONNECT PTU is used, sensing occurs at the PTU.

Test Blocks: Functional Tests


FUNTEST EXQ Executes the contents of the Q buffer. (The argument EXQ can be replaced by an op-code for special-purpose applications.)

FUNTEST EXQ, TESTSUPPLY Like FUNTEST EXQ, but executes a power supply test and functional test concurrently; fails if either test reports an error.

FUNTEST EXQ, ONLYTESTSUPPLY Like FUNTEST EXQ, but executes a power supply test and functional test concurrently; fails only if the power supply test reports an error.

FUNTEST EXQ, NOERROR Like FUNTEST EXQ, but all errors are ignored.

FUNJIF EXQ, label Like FUNTEST EXQ, but jumps to label if the test fails.

TESTPIN Sets the logic flag for the last functional test based on specified pins: a list of PINLIST statements follows immediately, and is terminated with an ENDLIST statement.

TESTPIN label Like TESTPIN, but the list of PINLIST statements begins at label.

TNOP Increments the test number counter by one, but performs no operation.

TESTNUMBER Disables the test number counter.TESTNUMBER CONTINUE Reenables the test number counter.TESTNUMBER number Sets the test number counter to number.TESTNUMBER register Load test number from a word register

(ESCape only).PAUSE time Pauses for time: 0.1 to 25.5 milliseconds.

Executing the Contents of the Q Buffer. Both the FUNTEST EXQ and FUNJIF EXQ statements increment the test number counter on the front panel by one and then execute the test in the Q Buffer. (See "Q2/52 PGM Commands," below, for information on loading the Q Buffer.) The logic flag is set to false if any pin fails the functional test. If FUNTEST is used, test flow returns to the Sequence and Binning Table on failure; if FUNJIF is used, flow jumps to the specified label on failure.

Executing Power Supply Tests with Functional Tests. Both the arguments TESTSUPPLY and ONLYTESTSUPPLY execute a power supply test concurrently with the specified functional test. If TESTSUPPLY is used, the logic flag is set to false if either the power supply test or the functional test fails; if ONLYTESTSUPPLY is used, any functional errors are ignored.

Ignoring Errors. If the argument NOERROR is used, the test passes (i.e., the logic flag remains set to true) regardless of errors detected.


Testing Only Specified Pins. The TESTPIN statement sets the logic flag based on the pass-fail status of specified pins. In practical use, the sequence flag should be set to continue (see the description of SFLAG, below) before executing the test, or program flow will return to the Sequence and Binning Table immediately.

Controlling the Test Number Counter. The TESTNUMBER statement provides control over the counter and TEST NUMBER display on the front panel. Without an argument, it disables the counter; with the argument CONTINUE it reenables the counter; with a number as an argument it sets the counter accordingly.

Pausing During Testing. The PAUSE statement causes the tester to idle for a specified period. (This can be used to allow for settling time for external circuitry.) Units accepted are N or NS for nanoseconds, U or US for microseconds, and M or MS for milliseconds. There must be no space between the integer and the units. If no units are supplied, nanoseconds are assumed.

QTL PROGRAMMING - Additional Test Programming Commands 41

ADDITIONAL TEST PROGRAMMING COMMANDS

Flow Control

These commands can be used anywhere in a test block.

JUMP label Jumps to label.JUMP TRUE, label If logic flag is true, jumps to label.JUMP FALSE, label If logic flag is false, jumps to label.SKIPTO label Skips to label.CASE register, label [, label, label...] Branches to the label whose position in the

list equals the value in register.CASE CONTINUE, label [, label, label...] Specifies additional labels (cases).CALL label Calls subroutine at label.CALL TRUE, label If logic flag is true, calls subroutine at label.CALL FALSE, label If logic flag is false, calls subroutine at label.RETURN Returns from subroutine.MACRO macro Begins definition of macro. The macro

consists of all QTL statements that follow until an ENDMAC statement is reached.

ENDMAC Ends macro definition.@macro Executes macro macro.NOP No operation.SFLAG CONTINUE Sets sequence flag to CONTINUE.SFLAG RETURN Sets sequence flag to RETURN.LFLAG TRUE Sets the logic flag to true.LFLAG FALSE Sets the logic flag to false.JSET value, label If the SET variable equals value, jumps to

label.JNSET value, label If the SET variable does not equal value,

jumps to label.SSET value Sets the SET variable to value.ERROR Forces error.ENDTEST Ends test block.

Jumping, Skipping, and Branching. The JUMP statement can be used with or without a Boolean (true or false) condition. SKIPTO is almost functionally the same as JUMP without a condition, but is limited to 256 bytes forward. SKIPTO also takes slightly less object code than JUMP does, however; this may be a factor in very large QTL programs.


The CASE statement allows more complex branching: program flow branches depending on the value in the specified byte register. If the register = 0, no branching occurs; if the register = 1, flow branches to the first label in the list; if the register = 2, flow branches to the second label in the list, and so on. To specify more labels on additional lines, use the argument CONTINUE instead of the register name. The JSET and JNSET statements jump depending on the value of the SET variable; see "The SET Variable," below.

Subroutines. The CALL statement can be used with or without a Boolean (true or false) condition. If no condition is given, or if the condition is met, flow proceeds to the code beginning at the specified label. The last statement in the subroutine must be RETURN, to cause flow to return to the original CALL statement.

Macros. The MACRO statement begins the definition of a macro. The macro consists of all following QTL statements until an ENDMAC statement is reached.

Sequence Flag. By default, program flow returns to the Sequence and Binning Table whenever the logic flag is false—that is, whenever a test fails. If the sequence flag is set to return ("SFLAG RETURN"), flow returns to the S&B Table immediately; if the sequence flag is set to continue ("SFLAG CONTINUE"), flow does not return until an ENDTEST is reached. The FUNJIF and ERROR statements override the sequence flag.

The Logic Flag. By default the logic flag is set to true; it is set false whenever a test fails. The LFLAG statement sets the logic flag to either true or false, regardless of the actual result of the last executed test. The ERROR statement forces a "fail," sets the logic flag to false, and returns flow to the Sequence and Binning Table, where the FAIL branch is taken.

The SET Variable. Many QTL commands have varying actions depending on the value of the SET variable. Initially, the SET variable is assigned the value of the two least-significant bits of the load board ID. The SSET statement reassigns the value of the SET variable. The JSET statement jumps to the specified label if the SET variable equals a specified value; the JNSET statement jumps to the specified label if the SET variable does not equal a specified value.

Ending a Test. Whenever an ENDTEST statement is reached, the test block ends and flow returns to the Sequence and Binning Table where the PASS branch is taken.

Registers


BYTE register [,register, register...] Declares one or more byte (8-bit) registers.

WORD register [,register, register...] Declares one or more word (two-byte; 16 bit) registers.

DOUBLEWORD register [,register, register...] Declares one or more double word (four-byte; 32 bit) registers.

FLOAT register [,register, register...] Declares one or more floating point registers.

LONG register [,register, register...] Declares one or more double word (four-byte; 32 bit) registers.

VOLTAGE register [,register, register...] Declares one or more voltage (word) registers.

CURRENT register [,register, register...] Declares one or more current (double word) registers.

TIME register [,register, register...] Declares one or more time (double word) registers.

STRING register, length Declares a string register, of length (in bytes).

ASSIGN register = value Assigns value to register.COMPARE register operator expression Compares register with expression,

according to operator; sets logic flag based on comparison. The operator can be =, ==, <, >, <>, !=, <=, or >=.

MATCH register, <string> Matches register with <string>; sets logic flag true if they match exactly.

MATCH register1, register2 Matches register1 with register2; sets logic flag true if they match exactly.

STORE register,<string> Stores string <string> in register.STORE register1, register2 Stores contents of register2 in register1.STORE register1, register2, limit Stores first limit characters from

register2 in register1. SENDREG PGMregister, Q2register Copies contents of Q2register to

PGMregister.GETREG Q2register, PGMregister Copies contents of PGMregister to

Q2register.CREG Clears all registers.

Register Arrays. An array of registers may be declared by specifying the size in square brackets after the register name. Arrays begin with element 0. For example, "BYTE A[8]" declares an array with 8 elements, A[0] through A[7]. Arrays are only available with the ESCape controller.

Register Sizes. Byte registers are eight bits long, word registers are 16 bits long, and double word, long registers and float are 32 bits long. Voltage registers are word


registers; current and time registers are double word registers. String registers can be of any size.

Declaring Registers. Registers must be declared before they are used. If HEADER NEW is used, there are 4,096 registers of each type. Otherwise, there are 255 byte registers available (byte register 0 is the SET variable), 256 word registers, and 234 double word, long registers or float. String registers share space with byte registers; all byte and string registers together must not exceed the maximum available.

Assigning Values to Registers. After a register is declared, it can be assigned a value with the ASSIGN statement. The value can be a decimal number, the name of another register, or an expression. For convenience, all of the following units are accepted for assigning values: V, MV, UV, A, MA, UA, S, MS, US, and NS. Units are not stored with the values, however. Values assigned to voltage registers are stored as millivolts (for example, 1V is stored as 1000), values assigned to current registers are stored as nanoamps (for example, 0.1UA is stored as 100), and values assigned to time registers are stored as tens of picoseconds (for example, 1NS is stored as 100).

Register Operations. The COMPARE statement sets the logic flag based on the result of a comparison of two registers. The operator can be = or == (equal to), < (less than), > (greater than), <> or != (not equal to), <= (less than or equal to), or >= (greater than or equal to). The MATCH statement sets the logic flag based on the results of a simple comparison of two string registers or of a string register and a string.

Copying Registers. The STORE statement loads a string register from a supplied string or from another string register. If the source is another string register, a limit to the number of characters copied can be given. The SENDREG statement copies the contents of a Q2 mainframe register to a PGM register; the GETREG statement copies the contents of a PGM register to a Q2 mainframe register.

Clearing All Registers. The CREG statement assigns the value 0 to all registers (except for byte register 0, the SET variable). It is not selective.

Expressions. Expressions can be used to assign values to registers. The available operators, and their order of precedence, are as follows. Operations of equal precedence are performed left to right. Other evaluation orders may be forced by using parentheses.


Highest precedenceNext-HighestPrecedence

Next-Lowest Precedence

Lowest Precedence

NOTUnary 1's complement

(reverses state of each bit)

AND or &Bitwise AND

*Multiply

+Add

~Unary 1's complement

(reverses state of each bit)

OR or |Bitwise OR

/Divide

-Subtract

-Unary arithmetic

complement (1 becomes -1)

XOR or ^Bitwise exclusive

ORSHL or <<

Bitwise shift leftSHR or >>

Bitwise shift right

Access to I/O Ports

AUTOSTART option If option is ON, enables READY Block execution; if option is OFF, disables READY Block execution.

STARTTEST Executes a TEST command. Valid only within the READY Block.

DOSUMMARY Executes the SUMMARY Block. Valid only within the READY Block.

SUMSTATE option If option is ON, enables the output of standard summary data; if option is OFF, disables the output of standard summary data.

CLEARBINS bin [, bin...] Clears one or more bin counters: SYSTEM, DATA, and/or INTERFACE. At least one must be specified.

STOREBIN bintype, register Stores the number of the last-incremented bin of bintype (DATA or INTERFACE) in register.

GETBYTE register, port Retrieves a byte of data from port and stores it in register. Available ports are FRONTA, FRONTB, HAND, IPORT, LPORTA, and LPORTB. With ESCape Only: A tester port number from 0 to 255 may be specified in place of using the port name.

GETBYTE register, port, label Retrieves a byte of data from one port and stores it in register; jumps to label if operation fails. Available ports are AUXPORT and WPORT.

GETBYTE register, port, label With ESCape Only. Retrieves a byte of data from one port and stores it in register; jumps to label if operation fails. Available ports are AUXPORT and WPORT. A tester port number from 0 to 255 may be specified in place of using the port name.

GETSTRING register, AUXPORT, Retrieves a string of data from the Auxiliary Serial Port and stores it in register; jumps to label if


label, [termchar] operation fails. An optional termination character code, termchar, may be given.

SENDBYTE byte, port Sends a byte to port. Available ports are FPORTA, FPORTB, LPORTA, LPORTB, OPORTA, and OPORTB. With ESCape Only: A tester port number from 0 to 255 may be specified in place of using the port name.

SENDBYTE register, port Sends a byte register to port. Available ports are FPORTA, FPORTB, LPORTA, LPORTB, OPORTA, and OPORTB. With ESCape Only: A tester port number from 0 to 255 may be specified in place of using the port name.

SENDBYTE byte, AUXPORT, labelSends a byte to AUXPORT; jumps to label if operation fails. SENDBYTE register, AUXPORT, label Sends a byte register to AUXPORT; jumps to label if

operation fails. SENDSTRING <string>, port, label Sends a string of data to port; jumps to label if

operation fails. Available ports are AUXPORT and WPORT.

SENDSTRING register, port, label

Sends the contents of register to port; jumps to label if operation fails. Available ports are AUXPORT and WPORT.

RETESTCLEARClears retest input latch on interface board. SENDWORD word, OPORTABSends word to ports OPORTA and OPORTB.MAP option If option is ON, enables wafer mapping; if option is

OFF, disables wafer mapping; if option is QTL, enables wafer mapping from QTL (via the LOADMAP statement) only.

LOADMAP x, y [, bin] Stores specific X and Y die coordinates and bin number into the Q2/52's wafer map. If no bin is specified, stores the most recently incremented bin number.

Enabling the READY Block. The name of a READY Block (instructions that can be executed optionally after each device is tested) can be included in the MESSAGE statement in the Sequence and Binning Table. If a READY Block is used, an AUTOSTART ON statement must appear to enable READY Block execution.

Starting to Test. To transfer control to the Sequence and Binning Table and begin testing from within the READY Block, use the STARTTEST statement. STARTTEST is only valid in the READY Block.


Summaries. The SUMSTATE statement enables and disables the output of the standard system summary data; if the standard output is disabled, only the user-defined summary data is printed.

The Bin Counters. The CLEARBINS statement clears one or more of the three bin counters: SYSTEM, DATA, and INTERFACE. Any one, any two, or all three bin counters may be specified. The STOREBIN statement stores the number of the last-incremented bin of a specified type into a register.

Retrieving Data from Tester Ports. The GETBYTE statement retrieves a byte of data from one of the tester ports and stores it in a byte register. Available ports are:

FRONTA and FRONTB Front Panel PortsHAND Handler/Prober PortIPORT Auxiliary Parallel Port (input only)LPORTA and LPORTB Load Board PortsAUXPORT Auxiliary Serial PortWPORT Wafer Map Port

If the specified port is AUXPORT or WPORT, a label must be specified for program flow to jump to if the GETBYTE operation fails. The GETSTRING statement retrieves a string of data from the Auxiliary Serial Port (AUXPORT) and stores it in a string register, jumping to the specified label if the operation fails. If less than the entire string is desired, a termination character code can be specified. For example, to stop storing the string after the first carriage return, specify a termination character code of 13. The default termination character code is 10 (line feed).

Sending Data to Tester Ports. The SENDBYTE statement sends a byte of data to one of the tester ports. Available ports are:

AUXPORT Auxiliary Serial PortHAND Handler/Prober PortLPORTA and LPORTB Load Board PortsFPORTA and FPORTB Functional Ports (for special purpose

applications)OPORTA and OPORTB Auxiliary Parallel Port (output only)

The source can be either an actual byte of data or the name of a byte register. If data is sent to the Auxiliary Serial Port, a label must be given for program flow to jump to if the SENDBYTE operation fails. The SENDSTRING statement sends a string of data to either the Auxiliary Serial or Wafer Map Port; again, a label must be supplied for program flow to jump to if the SENDSTRING operation fails. The SENDWORD


statement sends a word (two bytes) of data to the OPORTA and OPORTB simultaneously.

Bit Definitions for Ports.

bit FRONTA FRONTB HAND0 SSR (Single Step, ready) OHR (Opens Halt, run) Start Test1 SSS (Single Step, step) OHC (Opens Halt, continue) undefined2 STE (Error Mode, step to

error)B (Results, begin) Retest (EOW)

3 ACC (Error Mode, accumulate)

S (Results, summary) undefined

4 DO (Display Mode, off) R (the Retest button) undefined5 DD (Display Mode, detail) T (the Test button) undefined6 NA (not applicable) NA (not applicable) undefined7 NA (not applicable) NA (not applicable) undefined

Wafer Map Data. Wafer mapping is enabled by the MAP ON statement. After each device is tested, the tester logs the X and Y coordinates (single-byte values) of the device and the data bin incremented. (The coordinates range from -127 to +127. Wafer mapping works correctly only when two's complement arithmetic is used. Do not use the HEADER OLD command with wafer mapping. The first device tested on the wafer is assigned the coordinates 0,0.) The MAP OFF statement disables wafer mapping. The MAP QTL and LOADMAP statement provide additional flexibility: the MAP QTL statement enables the LOADMAP statement, which allows arbitrary X and Y coordinates and bin number to be logged in the wafer map (all arguments to LOADMAP are byte registers). If no bin is specified with LOADMAP, the most recently incremented bin is logged. When a SUMMARY is performed, wafer map data is transferred from the tester's QTL RAM space to the currently opened disk file of type DAT, regardless of whether the wafer map data was logged automatically by the system (MAP ON) or manually by the QTL program (MAP QTL and LOADMAP).

Searches

Two types of searches can be performed via QTL: linear searches and binary searches.

LSEARCH parameter, label Performs a linear search on parameter; jumps to label if no edge found .

BSEARCH parameter, label Performs a binary search on parameter; jumps to label if no edge found.


Binary Searches. In a binary search, the search region is divided in half repeatedly until the pass/fail boundary of the test is found. Before a binary search can be executed, the following double-word registers must be set via ASSIGN statements:

LOWLIMIT For TG search parameters (see below): the lower boundary of the start edge (the stop edge follows the start edge by the value in the WIDTH register). For other search parameters: the lower boundary of the search region.

HIGHLIMIT For TG search parameters (see below): the upper boundary of the start edge (the stop edge follows the start edge by the value in the WIDTH register). For other search parameters: the upper boundary of the search region.

EPSILON The resolution of the search. The final result has an error no greater than EPSILON unless EPSILON is smaller than the possible resolution for the parameter.

WIDTH For TG search parameters (see below) only: the width of the pulse.

The BSEARCH statement must be immediately followed by a FUNTEST or PARTEST statement. The result of the search is written to the SEARCH register, where it is accessible after the search.

Linear Searches. A linear search starts at one end of the search region and proceeds linearly towards the other end until pass/fail boundary of the test is found. Although linear searches are slower than binary searches, they are useful for dynamic RAM applications where the measurement must be accurate the first time the pass/fail boundary is passed.

Before a linear search can be executed, the following double-word registers must be set via ASSIGN statements:

START For TG search parameters (see below): the lower boundary of the start edge (the stop edge follows the start edge by the value in the WIDTH register). For other search parameters: the starting value for the linear search.

STOP For TG search parameters (see below): the upper boundary of the start edge (the stop edge follows the start edge by the value in the WIDTH register). For other search parameters: the end point for the search.

INCREMENT The size of steps to be taken in the search. If negative, then the value of START must be greater than the value of STOP.

WIDTH For TG search parameters (see below): the width of the pulse.

The LSEARCH statement must be immediately followed by a FUNTEST or PARTEST statement. The result of the search is written to the SEARCH register, where it is accessible after the search.


Search Parameters. The following parameters can be searched: CYCLE, START1 to START24, STOP1 to STOP24, TG1 to TG24, V1, V2, V3, PSV1, PSV2, PSV3, VBIAS, VIH1, VIH2, VIHC, VIL1, VIL2, VILC, VOH, VOL, VOUT, VPAR, IPAR, I1, I2, I3, IV1, IV2, IV3.

Examples. Following are some examples of binary and linear searches:

ASSIGN LOWLIMIT = 50NSASSIGN HIGHLIMIT = 90NSASSIGN EPSILON = 1NSBSEARCH START6 , NOFINDFUNTEST EXQPRINTLN SEARCHASSIGN START = 50NSASSIGN STOP = 90NSASSIGN WIDTH = 25NSASSIGN INCREMENT = 1NSLSEARCH TG6 , NOFINDFUNTEST EXQPRINTLN SEARCHENDTEST

NOFIND: PRINTLN <No edge found>ENDTEST

I/O and Host Functions

CREATE <type>, <name> Creates and opens a file named name; type must be either DAT (data) or LST (list).

CREATE <type>, register Creates and opens a file whose name is the contents of register; type must be DAT or LST.

APPEND <type>, <name> Appends to file of type (DAT or LST), named name.

APPEND <type>, register Appends to file of type (DAT or LST), whose name is the contents of register.

CLOSE <type> Closes currently open file of type (DAT or LST).

CLOSE Closes any currently open file.PRINT <string> Prints string to the monitor screen.PRINT register Prints the contents of register to the monitor

screen.PRINTLN <string> Prints string to the monitor screen, followed

by CR and LF.PRINTLN register Prints the contents of register to the monitor

screen, followed by CR and LF. PRINTDB register Prints the contents of register to the monitor


screen in “register=value” format.GETDATE s Get date to string register s.GETDATE s, compile Store date at which QTL program was

compiled in string register s.GETTIME d Get time to doubleword register d.GETTIME s Get time to string register s.GETTIME s, compile Store time at which QTL program was

compiled in string register s.INPUT register Accepts input from keyboard and stores it in

register.DOS <program> [<param> <param>...] Executes DOS program, passing any

arguments in the order given.

Creating and Opening a DAT or LST File for Data Logging. At any time during program execution, a maximum of one data-type and one list-type file can be open simultaneously for data logging. The CREATE statement opens a file of the specified type (either DAT or LST). If a file of the same type is already open, it is closed. If a file of the same name already exists, it is overwritten. If the name of the file is specified immediately, it must be enclosed within angle brackets; if it is specified via a register, omit the angle brackets. The file type (DAT or LST) must always be enclosed in angle brackets.

Generally, LST-type files are intended for people to read, and DAT-type files are intended for computer processing. For new applications, LST-type files are recommended, since they provided more complete control of the file format and are less subject to compatibility issues than are DAT-type files.

Appending to an Existing File. The APPEND statement opens an existing file for writing. Since only one file of each type can be open at a time, if a file of the same type is already open, it is closed. If the name of the file is specified immediately, it must be enclosed within angle brackets; if it is specified via a register, omit the angle brackets. The file type (DAT or LST) must always be enclosed in angle brackets.

Printing to the Monitor Screen. The PRINT statement prints either an immediate string or the contents of a register to the monitor screen. PRINTLN does the same, but follows the string or register with a carriage return and line feed. In both cases, if the string is specified immediately, it must be enclosed within angle brackets; if it is specified via a register, omit the angle brackets. The PRINTDB statement prints both the name and contents (value) of a register to the monitor screen.

Accepting Input from the Keyboard. The INPUT statement accepts input from the keyboard and stores it in a specified register. Note that INPUT does not generate a prompt; use PRINT or PRINTLN to prompt the user for input. Input is terminated by the Enter key. If the input string is shorter (that is, contains fewer characters) than the


register, the remaining register space is filled with blank bytes. If the input string is longer than the register, an error results and the user is asked to try again.

Getting the Time. The GETTIME command may be used to determine how long a section of a test program takes to execute. This command places a value in hundreths of a second in a doubleword register. By executing GETTIME twice and subtracting the first value from the second value, execution time may be determined. For example:

GETTIME STARTFUNTEST EXQGETTIME STOPASSIGN STOP = STOP-STARTPRINT < TEST TIME = >PRINTLN STOP

An example for GETDATE s and GETTIME s follows:

STRING S,8GETDATE SPRINTLN SGETTIME SPRINTLN S

Executing a DOS Program from QTL. The DOS statement accepts up to 8 arguments. The first is the name of a DOS program to be executed; any additional arguments are parameters passed to the program.

Data Logging

PARAM <parameter> [, parameter...] Specifies parameters for subsequent data logging.

LOG Logs certain PARAM parameters to currently open DAT or LST file, then returns control to tester.

Parameters for Data Logging. The PARAM statement lists up to eight parameters, each enclosed in angle brackets, to be logged during testing. The following table shows the available parameters:

Parameter: Logs: Format in LST File: Format in DAT File:

PRINT All PRINT, PRINTLN, or PRINTDB messages

Exactly as printed on screen

Exactly as printed on screen

DATE Current date (in PC-DOS, not RT-11 format)

MO-DA-YR DATE=MO-DA-YR *

TIME Current time (in PC- HR:MN:SC TIME=HR:MN:SC *


DOS, not RT-11 format)PINS Output of interactive

PE (Pin Errors) command and result of test

Exact output of PE command

Exact output of PE command

RESULTS Result of test: PASS or FAIL

PASS or FAIL RES=PASS or RES=FAIL *

SUMMARY Summary data Output of S command

Output of S command

DETAIL If front panel DETAIL switch is on, detail printout from tester

Exactly as printed on monitor screen

Exactly as printed on monitor screen

ERROR Error messages Error message number and explanatory text

Error message number and explanatory text

* Followed by a carriage return and line feed.

When Data is Logged. Different parameters are logged at different times during execution: PRINT parameters are logged at the execution of any PRINT, PRINTLN, or PRINTDB statements, DETAIL parameters are logged when an STOP instruction is reached in the Sequence and Binning Table, ERROR parameters are logged when the error occurs, and all other parameters are logged at the execution of a LOG statement.

In order for any parameters to be logged, a DAT or LST type file must be opened for writing (via CREATE or APPEND, above). The file must be closed (via CLOSE), or data will be lost.

Note: Due to a bug in the Q2 system control board software, the LOG statement cannot be used in the READY Block.

Schmoos

TPARAM <title> Specifies a title for a subsequent schmoo.

PPARAM <pin, pin...> Specifies pins to be schmooed in subsequent QSCHMOO.

XPARAMn <parname> <min> <max> [<#steps>] Sets up nth X schmoo parameter.YPARAMn <parname> <min> <max> [<#steps>] Sets up nth Y schmoo parameter.QSCHMOO Performs schmoo with parameters set

in preceding TPARAM, PPARAM, XPARAM, and YPARAM statements.


Defining a Title for the Schmoo. The TPARAM statement defines a title that appears at the top of a subsequent schmoo plot. Up to 80 characters are permitted; the title string must be enclosed in angle brackets.

Specifying Pins to be Schmooed. The PPARAM statement specifies which pins are to be considered in formulating a result for the schmoo plot: if any of the specified pins fail, the schmoo plot shows a FAIL. If no pins are specified, or if no PPARAM statement is used, the schmoo will include all pins in the pin list (for parametric tests) or all strobed pins (for functional tests). Each PPARAM statement can specify up to 8 pin names; if more pins are needed, use additional PPARAM statements.

Defining X and Y Parameters. Each XPARAMn statement defines one X parameter; each YPARAMn statement defines one Y parameter. For example, a statement that begins with XPARAM1 defines the first X parameter, XPARAM2 defines the second X parameter, and so on. Up to 5 of each kind of parameter can be schmooed simultaneously.

XPARAM1 and YPARAM1 each take three or four arguments; the other XPARAMn and YPARAMn statements each take three. The first is the name of the parameter: any current, voltage, or timing parameter. The second and third are the minimum and maximum values, respectively, that define the range for the parameter. If units are not specified for the minimum and maximum arguments, default units of millivolts, nanoamps, and ten picoseconds are used. Register names cannot be used to set the minimum and maximum values.

The optional argument to XPARAM1 and YPARAM1 is the number of incremental steps in the relevant dimension—the resolution of the schmoo. The other parameters (XPARAM2 through XPARAM5) have the same number of steps as XPARAM1, and likewise for the Y dimension. For the X-axis, the maximum number of steps is 65, and the default (if none is specified) is 31. For the Y-axis, the maximum number of steps is 32767, and the default is 11.

Generating the Schmoo. To create a schmoo, set the necessary parameters, execute a QSCHMOO statement, and then execute a test statement (either PARTEST or FUNTEST). The test statement must follow the QSCHMOO statement immediately.

Schmoos are always output to the monitor screen. If a LST type file is open, the schmoo is also logged there. If a DAT type file is open (with APPEND), the raw data for the schmoo is logged there, where it can be used for subsequent composite schmoos.

Note: Due to a bug in the Q2 system control board software, the QSCHMOO statement cannot be used in the READY Block.


Other Data Analysis Tools

MEASURE [mode] With no mode argument, or if mode is ON, measures all parametric tests. If mode is FAIL, measures only failing parametric tests. If mode is OFF, parametric tests are not measured.

DPLOT file [, file...] Compiler generates instructions for PDP-11 DPLOT utility using up to four user-written option files.

SCHMOO file [, file...] Compiler generates instructions for PDP-11 SCHMOO utility using up to four user-written option files.

Measuring During Tests. Ordinarily, only pass/fail data is reported and logged. The MEASURE statement causes actual measurements to be returned as well. There are three possible values for the measurement modes: MEASURE ON causes all tests to be measured, MEASURE FAIL causes only failing tests to be measured, and MEASURE OFF disables measurement. MEASURE without an argument is equivalent to MEASURE ON.

Notes: The MEASURE statement is an exclusive feature of the PC-Host. MEASURE can only be used if the Q2 is controlled by a PC-Host. It will not run on a PDP-11-based host. In addition, MEASURE statements cannot be used in the READY Block, due to a bug in the Q2 system control board software.

Additional Utilities. The PC-Host compiler can generate the necessary instructions to invoke DPLOT and SCHMOO from QTL, but the PC-Host does not support execution of these utilities.

Identity Tests

TESTNUMBER ESC Sets LFLAG true if the new External System Controller (ESCape) is installed.

TESTNUMBER Q8000 Sets LFLAG true if ESCape is installed and the tester is a Q8000. See example below:

BYTE ESCASSIGN ESC = 1TESTNUMBER ESCJUMP TRUE, YESASSIGN ESC = 0

YES: ENTEST

QTL PROGRAMMING - Q2/52 Specific Topics 56

Q2/52 SPECIFIC TOPICS

The Q Buffer

SENDPGM Begins a PGM list of instructions for the Q Buffer.SENDPGM label Like SENDPGM, but PGM list begins at label.ENDLIST Ends PGM list.

All commands for the Q2/52’s Pattern Generator Module, or PGM, are loaded into a special buffer on the PGM called the Q Buffer and only executed when a FUNTEST EXQ statement is executed. (See “Test Blocks: Functional Tests,” under Basic Program Components earlier in this section, for information on FUNTEST and other functional test statements.) The Q Buffer is 1500 bytes long.

PGM Lists. A list of instructions for the PGM is called a PGM list. Every PGM list begins with a SENDPGM statement and ends with an ENDLIST statement, although labels can be used to specify remote PGM lists. (If a label is used, the ENDLIST statement appears at the end of the remote list.) Each PGM list overwrites the entire Q Buffer, so each must be executed before another is loaded. That is, only one SENDPGM statement can appear between FUNTEST or FUNJIF statements.

The SENDPGM statement does not execute the PGM list that follows it—SENDPGM just sends the instructions to the Q Buffer. They are executed only when a FUNTEST EXQ or FUNJIF EXQ statement is reached.

The commands in this section are not QTL statements. They are PGM-specific commands that must be loaded into the Q Buffer within PGM lists.

Q2/52 PGM Control

BIN DEC n Decrements FBINn.BIN INC n Increments FBINn.BIN SET n, value Sets FBINn to value.BIN COUNT n, counter Sets FBINn to value in counter.IBIN DEC base, offset Decrements FBINn, where n = base+offset.IBIN INC base, offset Increments FBINn, where n = base+offset.IBIN SET base, offset, value Sets FBINn, where n = base+offset, to value.

SUMMARY Displays contents of all PGM Row, Column, and Functional Bins (RBINs, CBINs, and FBINs).


BEGIN Initializes PGM. Sets all PGM FBINs to 0.

TRANSFER destination, source Transfers contents of destination PGM or Q2 mainframe register to source PGM or Q2 mainframe register.

PGM Bins. There are three types of PGM bins: Functional Bins (FBINs), Row Bins (RBINs), and Column Bins (CBINs). The BIN and IBIN commands perform the same operation on FBINs—the difference is the way the FBIN is specified. In a BIN command, the number of the FBIN is specified directly, whereas in an IBIN command the number of the FBIN is specified in terms of a base bin number and an offset. Both BIN and IBIN commands allow the FBIN to be incremented by one (INC), decremented by one (DEC), or set to an arbitrary value (SET). The BIN command also allows an FBIN to be set to the contents of one of the five PGM loop counters: ACOUNT, BCOUNT, CCOUNT, DCOUNT, or ECOUNT.

Displaying Bins. The SUMMARY command displays the contents of all FBINs, RBINs, and CBINs.

Initializing the PGM. The first command sent to the PGM is usually a BEGIN. BEGIN initializes the PGM by clearing (i.e., setting to 0) all the FBINs. It does not clear the RBINs or CBINs; see “PGM Error Catch Control,” below, for information on clearing those bins. When a BEGIN command is executed, a sign-on message is displayed indicating the PGM Operating System version number, the option modules present (if any), and the contents of all FBINs (before they were cleared) and non-zero RBINs and CBINs.

PGM Registers. All FBINs, RBINs, and CBINs are technically PGM registers, as are most of the pattern generator registers represented by STATUS Buffer entries (see below). PGM registers are not the same thing as the user-defined Q2 mainframe registers (declared with BYTE, WORD, LONG, DOUBLEWORD, and STRING statements.) The TRANSFER command transfers the contents of a PGM register to a Q2 mainframe register, vice versa, or the contents of one PGM register into another PGM register.

The TRANSFER command is similar to the SENDREG and GETREG QTL statements, but TRANSFER can only appear in a SENDPGM list.

The PGM registers that may be used as arguments to TRANSFER are as follows:

FBIN0 to FBIN127 ARELOAD DATREG PREVADRRBIN0 to RBIN31 * BRELOAD JAMREG SPREVADRCBIN0 to CBIN31 * CRELOAD DATBUF PREVDATACURMAR DRELOAD YINDEX PREVMARMARSEGMENT ERELOAD DATGEN DUTADRINTADR YOUT LBDATA SDUTADRSTKPTR XOUT ACTUALDATA DUTDATA


RETADR YMAIN ERRADR DUTMARACOUNT XMAIN SERRADR ROWCOUNTBCOUNT YBASE EXPECTDATA COLCOUNTCCOUNT XBASE ERRMARDCOUNT YFIELDECOUNT XFIELD

* RBIN32 through RBIN63 and CBIN32 through CBIN63 cannot be used for TRANSFER operations.

If the 8086 system controller is in use and a breakpoint appears in the same test block as a TRANSFER command, the test breaks before the TRANSFER, rather than at the end of the test block. If the test block contains more than one TRANSFER, the test breaks before the first one. This problem does not occur when the External System Controller is used.

PGM Buffers

PGM Buffers are special memory locations on the PGM in which pattern programs and PGM configuration and status information is stored. Buffers can be loaded from disk or from the QTL program.

INSERT buffer [address] Inserts to buffer starting at address. If no address is supplied, inserts starting at 0.

INSEND Ends INSERT data.

PGMBYTE byte1 [, byte2 ... , byteN] Send bytes to PGM buffer.

PGMWORD word Send word (16 bits) to PGM buffer.

INSFB buffer, address, n Inserts FBINn to buffer starting at address.DISFB buffer, address, n Copies buffer, starting at address, to FBINn.

DISPLAY buffer, address1, address2 Displays buffer from address1 to address2 on the monitor screen in readable ASCII format.

WRITE buffer, address1, address2 Displays buffer from address1 to address2 on the monitor screen in Intel hex format.

SELECTBUF n Selects Data Buffer segment n.DUTLOAD Learns ROM code to DATA Buffer.CSLOAD Learns chip select polarity to TYPE Table.

CHECKSUM GENERATE Generates checksum of the contents of the DATA Buffer.

CHECKSUM COMPARE Compares last-generated checksum with that of the DATA Buffer’s current contents.

CHECKSUM LOAD, value Loads DATA Buffer Checksum with value.

Loading a PGM Buffer. The INSERT command starts loading data into a PGM buffers at a specified address. (If no starting address is supplied, data is inserted starting at address 0.) The INSEND command terminates the data insertion.


The PGM Buffers that can be loaded with INSERT are as follows:

Buffer Size Description

USER 1024 bytes User Area. Stores a sequence of PGM commands that can be used repeatedly in different parts of the QTL program. See “Q2/52 Specific Topics; Q2/52 PGM Program Flow Control” later in this section.

TYPE 37 bytes Type Table. Configuration information for PGM: PGM mode, DUT array dimensions, chip select and strobe function, and signal formatting. See “Q2/52 Reference: The TYPE Table,” later in this section.

BUFFER Up to 16M (x 8 or x 16)

Data Buffer Memory or DBM. Storage of reference data for functional tests. Configured via Byte 15 of the TYPE Table.

PROGRAM 1536 bytes Pattern Program Buffer. Intermediate storage (between QTL program and PGM) of user-written pattern programs.

STATUS 95 bytes Status Buffer. Stores contents of PGM registers. See “Q2/52 PGM Buffers: The STATUS Buffer,” later in this section.

DTOPO 4096 bytes X and Y Data Topological Scramble Tables or X and Y Data Topo RAMs. Performs data topological inversion for pattern generator data field. Allows true polarity testing of devices that use both positive-true and negative-true storage within a memory array. Inversion takes place as a function of unscrambled pattern generator address.

XTOPO and YTOPO

4096 addresses

X and Y Address Topological Scramble Tables or X and Y Address Topo RAMs. Relate every X and Y Address Generator output to a DUT X and Y address. Can also be loaded via LPP command.

XBMSCRAMBLE and YBMSCRAMBLE

4096 X and Y Bit Map Scramble Tables.

ROWCOL 4096 two-bit locations

Row and Column Error Buffers/RAMs. See “Q2/52 Redundancy Analysis,” later in this section.

ECR 1M 1 bit or4M x 1 bit

Error Catch RAM/Memory. Used for redundancy analysis and for bitmapping. See “Q2/52 Specific Topics; Q2/52 Redundancy Analysis,” later in this section.

REPAIR 176 Repair Table. Describes topology of device, for redundancy analysis. See “Q2/52 Specific Topics; Q2/52 Redundancy Analysis,” later in this section.

BITMAPTABLE 131 Bit Map Table. For bitmap applications.RED, GREEN, and BLUE

256 Red, Green, and Blue Color Lookup Tables. For bitmap applications.


The Q Buffer cannot be loaded with INSERT. Use SENDPGM as described in “Q2/52 Specific Topics; The Q Buffer,” above.

The format of the data inserted varies depending on the buffer. The USER Buffer requires Q2/52 PGM commands, the PROGRAM Buffer requires Q2/52 microcode instructions (see “Q2/52 Pattern Programming” below), and the TYPE Table and all the other buffers require data in PGMBYTE and PGMWORD commands.

PGM Buffers and Functional Bins. The INSFB command loads a PGM buffer by inserting the contents of a functional bin into it, starting at a specified address. The remainder of the buffer (that is, addresses previous to the starting address and following the newly inserted data) is unchanged. The DISFB command copies all or a portion of a PGM buffer into a functional bin, starting at a specified buffer address.

Displaying a PGM Buffer. The DISPLAY and WRITE commands display a specified portion of a PGM buffer on the monitor screen. The only difference is that WRITE displays the data in Intel hexadecimal format.

DATA Buffer Partitioning. If the DATA Buffer is larger than the size of the device’s memory array, as specified in the Q2/52 Reference: TYPE Table section outlined later in this chapter, it is automatically partitioned into segments equal to the size of the memory array. Only one segment of the DATA Buffer can be active, or usable, at a time. The SELECTBUF command specifies which segment active. The active segment remains active until another SELECTBUF command. Upon power-up, or when the TYPE Table has been edited (except formatter or interrupt timer bytes), DATA Buffer segment 0 is the active segment. DATA Buffer segmentation allows multiple ROM codes to be resident in the DATA Buffer simultaneously (see below).

Loading ROM Code into the DATA Buffer. The DUTLOAD command loads the data from a sample ROM into the currently active segment of the PGM’s DATA Buffer. The device is single-stepped from 0 to its maximum address; at each address, chip selects are pulsed true and a device read is performed. Before executing a DUTLOAD, make sure that the following have been done:

· The device configuration has been properly described in the TYPE Table.

· All voltages required by the DUT in read mode have been properly programmed.

· All timing channels have been programmed.

Loading Chip Select Polarity into the TYPE Table. The CSLOAD command loads the chip select polarity from a sample ROM into Byte 4 of the TYPE Table. This is useful for determining the chip select polarity of a ROM that has mask-programmable chip selects. There are five chip selects. During CSLOAD, each combination of active high


and active low chip selects is tried until a valid logic one is found in the DUT array. If no logic one is found anywhere, with any combination of chip selects, an error message is generated. Before executing a CSLOAD, make sure that the following have been done:




· Loading networks for DUT outputs have been disabled or set to pull outputs to logic zero.

DATA Buffer Checksums. Checksums are a valuable tool for determining the integrity of the DATA Buffer. The CHECKSUM GENERATE command computes a checksum based on the current contents of the DATA Buffer and stores it as the DATA Buffer Checksum. The CHECKSUM COMPARE command computes a checksum based on the current contents of the DATA Buffer and compares it against the value stored as the DATA Buffer Checksum. If the values differ (that is, the checksum has changed since last computed), an error message is generated. If the values are the same, no action is taken. The CHECKSUM LOAD command loads a specified value (0 to 65535) as the DATA Buffer Checksum.

Q2/52 PGM Parametric Test Setup

LBDATA n Sets load board control bits to n.

OUTHIGH n Searches for DUT address with high (logic one) bit number n.

OUTLOW n Searches for DUT address with low (logic zero) bit number n.

SETADDRESS address Sets address outputs to address.SETDATA value Sets data outputs to value.SETCHIPSON cs1 [,cs2] [,cs3] [,cs4] [,cs5] Sets chip select outputs to active (true).SETJAM value Sets PGM jam register to value (for use in

microcode pattern section).

Load Board Control Bits. The PGM contains three load board control data bits. These bits are available on the load board edge connector (labelled “SP3”, “SP4”, and “SP5”) where they can be used to control special circuitry or relays on the load board. The LBDATA command sets all three bits: the argument is a number from 0 to 7. Bit 0 corresponds to SP3, bit 1 to SP4, and bit 2 to SP5.

Searching for High and Low DUT Addresses. To perform a DC parametric test for DUT output source current (IOH), the pin to be tested must be in a high. The OUTHIGH command single-steps from 0 to the maximum DUT address, pulsing chip selects true


and performing a device read at each location. When an address is found at which the specified DUT bit number (n) is high (logic one), the DC parametric test can be performed. Similarly, the OUTLOW command prepares for an output sink current (IOL) test by locating an address at which the specified DUT bit number is low (logic zero).

Before executing either OUTHIGH or OUTLOW, make sure that the following have been done:




Setting Pattern Generator Outputs. The SETADDRESS command sets the PGM’s address outputs to the scrambled version of a specified address, which can be any value from 0 to the maximum address of the DUT. The SETDATA command sets the PGM’s data outputs to a specified value, which can be any value from 0 to .FFFF. If the PGM data width is only 8 bits, the range is 0 to .FF. (SETDATA does not set the Pin Electronics channels to Drive mode.) The SETCHIPSON command sets specified PGM chip select outputs to active (true); any chip selects not specified in the command are set to inactive (false). The SETJAM command sets the PGM jam register to the specified value; this value remains in the jam register during pattern program execution and can be used as a data source. See “Q2/52 Specific Topics: Q2/52 Pattern Programming,” in this section.

Q2/52 PGM Pattern Loading and Execution

User-written pattern programs, or “microcode,” contain the input drive and expect data that perform functional testing of the DUT. Pattern programs are written within the QTL test program and loaded into the PGM’s MicroRAM, from which they are executed.

MARSEGMENT segment Selects MAR segment (0, 1, or 2).

PLOAD PROGRAM Loads pattern program into MicroRAM, but does not execute it.

PATTERN PROGRAM Loads and executes pattern.PATTERN PROGRAM, ERROR [, DISPLAY] Loads and executes pattern, halts on error;

optionally displays state of PGM.

PGOFFSET n Executes pattern at address n.PGOFFSET n, ERROR [, DISPLAY] Executes pattern at address n; halt on error;

optionally displays STATUS Buffer.PGOFFSET n, COLUMN [, COUNT][, NOERROR] Executes pattern at address n; enables

Column ECR; optionally decrements Column Error Counter on error; optionally


doesn't scan for errors after pattern execution.

PGOFFSET n, ROW [, COUNT] [, NOERROR] Executes pattern at address n; enables Row ECR; optionally decrements Row Error Counter on error; optionally doesn't scan for errors after pattern execution.

PGOFFSET n, ROW, COLUMN [, NOERROR] Executes pattern at address n; enables both Row and Column ECRs; optionally doesn't scan for errors after pattern execution.

PGOFFSET n, FULL[EC] [, NOERROR] Executes pattern at address n; enables Full ECR; optionally doesn’t scan for errors after pattern execution.

PGOFFSET n, NOCLOCK[S] Sets MAR to address n, but doesn’t execute.

STARTPATTERN [PROGRAM] Loads pattern and begins executing.ST[A]RTPGOFFSET n Begins executing pattern program at

location n in the MicroRAM.STOPPATTERN Halts pattern program execution.

STEP n Steps pattern n times; no display.PSTEP n Steps pattern n times; stops if pattern

completes; displays at each step.PNSTEP n Steps pattern n times; stops if pattern

completes; displays once after stepping.PESTEP n Steps pattern to nth error; stops if pattern

completes; displays all errors.PIPECLEAR Clears PGM pipeline.

Specifying the MicroRAM Segment. The MicroRAM consists of 768 words of 140 bits each, and is divided into three 256-word segments. Pattern programs cannot cross segment boundaries; each must be entirely resident within a segment. Addresses are numbered from 0 to 255 within each segment. In order to load a pattern into the MicroRAM or execute a pattern resident in the MicroRAM, it is necessary to specify both a segment number (0, 1, or 2) and an address (0 to 255). The MARSEGMENT command selects one of the three segments. (The “MAR” is the PGM’s Microprogram Address Register, which is used to point to locations within the MicroRAM.)

Loading a Pattern Program into the MicroRAM. The PLOAD PROGRAM command loads the pattern program contained in the PATTERN Buffer into the MicroRAM, but does not execute it. The pattern program specifies the starting location at which it is inserted in the MicroRAM, as well as initial conditions for the PGM hardware and the STATUS Buffer. After the pattern program is loaded into the MicroRAM, the MAR is set to the beginning of the pattern program and the pipelines are initialized so that the pattern is ready to execute. The STATUS Buffer is not updated after the pipelines are initialized, so that the initial conditions loaded by PLOAD can be displayed using Q-Monitor commands (see the TESTER OPERATION section). To update the STATUS Buffer after the pipelines are initialized, use a PSTEP 0 command (below).


Loading and Executing a Pattern Program. The PATTERN PROGRAM command loads the pattern program contained in the PATTERN Buffer into the MicroRAM and begins executing it. If the ERROR argument is included, execution halts at the first DUT error; if ERROR is not included, pattern execution continues until the end of the pattern, regardless of DUT errors. If ERROR, DISPLAY is included, execution halts at the first DUT error and the state of the PGM at the time of the error is displayed.

Executing a Pattern Program from a Specified Location. The PGOFFSET command executes the pattern program resident in the MicroRAM. The argument, n, is the address, from 0 to 255, in the active segment of the MicroRAM, at which execution begins. If the ERROR argument is used, execution halts at the first DUT error; if ERROR is not included, pattern execution continues until the end of the pattern, regardless of DUT errors. If ERROR, DISPLAY is used, execution halts at the first DUT error and the state of the PGM at the time of the error is displayed.

If COLUMN used is included, the Column Error Catch RAM and the Column Error Counter (in the STATUS Buffer) are enabled. Each time a DUT error occurs, the bit in the Column ECR corresponding to the column in which the error occurred is set. If COLUMN, COUNT is used, the Column Error Counter is also decremented once per failing column (regardless of the number of errors in the column). If the Column Error Counter reaches 0, execution halts and a fail result is returned. Note: if COLUMN, COUNT is used, both the Column and Row Error Counters must contain non-zero values.

Likewise, if ROW is used, the Row Error Catch RAM and the Row Error Counter (in the STATUS Buffer) are enabled. Each time a DUT error occurs, the bit in the Row ECR corresponding to the row in which the error occurred is set. If ROW, COUNT is used, the Row Error Counter is also decremented once per failing row (regardless of the number of errors in the row). If the Row Error Counter reaches 0, execution halts and a fail result is returned. Note: if ROW, COUNT is used, both the Row and Column Error Counters must contain non-zero values.

If ROW, COLUMN is used, both the Row and Column ECRs are enabled. Each time an error occurs, bits are set in both ECRs corresponding to the row and column that failed. The pattern runs to completion, regardless of the Row and Column Error Counters.

If FULLEC (or FULL) is used, the Full Error Catch RAM is enabled as well as both the Row and Column Error Catch RAMs. Each time a DUT error occurs, its location is logged in the Full ECR, and bits are set in both the Row and Column ECRs corresponding to the row and column that failed. The pattern runs to completion.

If FULLEC, NOERROR (or FULL, NOERROR) is used, the PGM does not scan for errors after the pattern has been run. This is useful for redundancy applications, where it is important to log all errors without halting execution.


If NOCLOCKS (or NOCLOCK) is used, the MAR is set to a specified address, but the pattern program is not executed, and the pipelines are not initialized.

Looping on Patterns. The STARTPATTERN command loads the pattern program from the PROGRAM Buffer into the MicroRAM, begins executing it, and returns control to the QTL program. The pattern program continues to execute infinitely (assuming it does not contain a DONE instruction). The PROGRAM argument is optional. Similarly, STARTPGOFFSET (identical to STRTPGOFFSET) starts executing the pattern program resident in the MicroRAM at a specified location, and returns control to the QTL program. All three commands allow the QTL program to continue while the PGM is exercising the DUT. The STOPPATTERN command halts execution of a looping pattern that was started with STARTPATTERN, STARTPGOFFSET, or STRTPGOFFSET.

The PGM Pipeline. The PGM pipeline is three stages deep: it takes three steps to initialize it. The PIPECLEAR command clears the PGM pipeline by filling it with no-op instructions. Use PIPECLEAR to re-initialize the pipeline after a pattern has been halted in mid-execution. The STEP, PSTEP, and PNSTEP commands all step the pattern a specified number of times from 0 to 65535; PESTEP steps the pattern a specified number of errors. See the command table at the beginning of the section for particulars on the display each command generates.

Q2/52 PGM Program Flow Control

BRANCH label Unconditionally branches to label.BRANCH relationship, bin, value, label Branches to label based on relationship

between FBINn and value.BRANCH relationship, base, offset, value, label Branches to label based on relationship

between FBINn and value, where n = base+offset.

BRANCH condition, label Branches to label if condition is met. Condition can be ERROR, NOERROR, ZERO, NOTZERO, POSITIVE, NEGATIVE, COMPLETE, NOTCOMPLETE, REPAIRABLE, or UNREPAIRABLE.

COMP DUT, n Compares current DUT address with n; sets ZERO and SIGN flags based on result.

COMP ERROR, n Compares the address of the first DUT error with n; sets ZERO and SIGN flags based on result.

COMP PREVIOUS, n Compares the address previous to the first DUT error with n; sets ZERO and SIGN flags based on result.


COMP BIN, m, n Compares FBINm to FBINn; sets ZERO and SIGN flags based on result.

COMP m, n Compares FBINm to FBINn; sets ZERO and SIGN flags based on result.

GENERR Sets ERROR flag; generates a functional error.

RESETERR Clears ERROR flag; clears functional errors.

EXQ Executes contents of Q Buffer.EXU n Executes contents of USER Buffer starting

at location n.RETQ Return from USER Buffer to Q Buffer.

PERROR ENABLE Enables error detection.PERROR DISABLE Disables error detection.

REPEAT n Begins repeat loop: repeats loop n times.ENDREPEAT Ends repeat loop.

HALT Halts PGM command execution.

PDELAY n Pauses for n microseconds.

PGMNOP PGM no operation.

Unconditional Branching. The BRANCH command with just one argument, a label, causes pattern program flow to branch (or jump) forward to the location specified by the label. The following restrictions apply to BRANCH commands:

· Branches are only permitted to labels (locations) within the same PGM list.

· Direct branching to an ENDLIST command is not permitted. (However, program flow can branch to a PGMNOP command inserted directly before the ENDLIST.)

· Branches can only go forward in the PGM code, never backwards.

Branching on Bin. Conditional branches can be made based on the comparison of the contents of an FBIN with a specified value. The number of the FBIN can be specified directly or in terms of a base bin number and an offset. The following table shows the BRANCH operands for conditional branching based on a bin.

BINGT Branches if contents of FBINn > value.BINLT Branches if contents of FBINn < value.BINEQ Branches if contents of FBINn = value.IBINGT Branches if contents of FBINn > value; n base + offset.IBINLT Branches if contents of FBINn < value; n base + offset.IBINEQ Branches if contents of FBINn = value; n base + offset.


Branching on PGM Flags. Conditional branches can be made based on the state of the four PGM flags: ZERO, SIGN, Error, and PATTERN COMPLETE. The following table shows the BRANCH operands for conditional branching based on these flags. (The ZERO and SIGN flags are set based on the results of a COMP command, below.)

ZERO Branch if the ZERO flag = 1.NOTZERO Branch if the ZERO flag = 0.POSITIVE Branch if the SIGN flag = 0.NEGATIVE Branch if the SIGN flag = 1.ERRORS Branch if the ERROR flag = set.NOERRORS Branch if the ERROR flag = unset.COMPLETE Branch if the PATTERN COMPLETE flag set—last pattern executed

ran to completion.NOTCOMPLETE Branch if the PATTERN COMPLETE flag unset—last pattern executed

halted before completion (stopped on error, or because either the Row or Column Error Counter reached 0).

REPAIRABLE Branch if the Repairable flag is set (DUT is repairable or no errors were detected).

UNREPAIRABLE Branch if the Repairable flag is unset (the DUT is not repairable).

Setting the ZERO and SIGN Flags. The COMP command compares either a particular DUT address with a specified value or the contents of two FBINs and sets both the ZERO and SIGN flags based on the result of the comparison. Some conditional branches are based on the state of these flags.

COMP DUT compares the current PGM DUT address, COMP ERROR compares the PGM address of the first DUT error, and COMP PREVIOUS compares the PGM address previous to the first DUT error with the specified value, which can be any 24-bit value from 0 to 16,777,215. The ZERO and SIGN flags are set as follows:

ZERO Flag SIGN Flag

PGM address < number 0 0PGM address = number 1 0PGM address > number 0 1

COMP BIN compares the contents of the two specified FBINs. The BIN argument is optional: for example, COMP 2, 3 is identical to COMP BIN 2, 3. The ZERO and SIGN flags are set as follows:

ZERO flag SIGN flag

FBINm < FBINn 0 0FBINm = FBINn 1 0


FBINm > FBINn 0 1

Setting and Clearing the Error Flag. The GENERR command generates a PGM error and sets the ERROR flag. The RESETERR command sends a hardware reset to all Pin Electronics error latches, resets the hardware error latch on the PGM, and clears the ERROR flag. RESETERR also clears the IERROR flag on the High Voltage Module (see “Q2/52 Specific Topics: Q2/52 PGM High Voltage Module,” below). Note that errors are automatically cleared at the start of every functional test.

Executing from the Q and USER Buffers. The EXQ command executes the Q Buffer, starting at the beginning of the buffer. The EXU command executes the USER Buffer, starting at a specified location. The USER Buffer is 1000 bytes long. The Q Buffer is loaded by the SENDPGM command and the USER Buffer is loaded by the INSERT command in the QTL program. EXU is a command executed out of the Q Buffer. The RETQ command returns control from the USER Buffer to the Q Buffer at the end of every USER Buffer sequence.

Setting and Clearing the ERROR Flag. Ordinarily, the ERROR flag is set whenever a DUT error is detected by the PGM. The GENERR command forces a PGM error and thereby sets the ERROR flag. The RESETERR command clears the ERROR flag, sends a hardware reset to all Pin Electronics error latches, and resets the hardware error latch on the PGM. RESETERR also clears the IERROR flag on the High Voltage Module (see “Q2/52 Specific Topics: Q2/52 PGM High Voltage Module” below). Note that errors are automatically cleared at the start of every functional test.

More Control Over PGM Errors. The PERROR command enables or disables the detection of DUT functional test errors by the Pin Electronics. PERROR has no effect on the current state of the error latches.

PGM Repeat Loops. The REPEAT command signals the beginning of a PGM loop; the ENDREPEAT command ends the loop. The PGM command sequence between REPEAT the subsequent ENDREPEAT is executed the specified number of times. The maximum number of iterations is 65,535.

Ending PGM Command Execution. The HALT command terminates execution of PGM commands and returns control to the QTL program. It is not necessary to use HALT at the end of every PGM command list; a HALT is automatically executed at the conclusion of any PGM list loaded into the Q Buffer. If a HALT command is included in the USER Buffer, control returns to the QTL program without returning to the Q Buffer.

Pausing the PGM. The PDELAY command pauses the PGM for a specified number of microseconds. The resolution is 50 µs; the maximum delay that can be programmed is 3,276,000 µs.


PGM “No Operation.” The PGMNOP performs no operation. It may be used to reserve space in a PGM List, or as a branching location immediately before an ENDLIST.

Q2/52 PGM Error Catch Control

The following PGM commands manipulate the Row, Column and Full Error Catch RAMs.

ROWCLEARClears Row ECR.COLCLEAR Clears Column ECR.RCCLEARClears Row and Column ECRs.ROWDUMP Transfers Row ECR to RBINs.COLDUMP Transfers Column ECR to CBINs.ECRSEG number Selects Error Catch RAM segment based on number.ECRSEGMENT number Selects Error Catch RAM segment based on number.

Row and Column Error Catch RAMs (ECRs). The Row ECR contains 4096 bits, for up to 12 DUT X address bits. The Column ECR contains 2048 bits for up to 11 DUT Y address bits. A “row” consists of all bits in the DUT array with the same X address; a column is all the bits in the DUT array with the same Y address.

The Row and Column ECRs have two discreet modes of use: dynamic error catch and strobe masking. The mode for each ECR is selected in Byte 10 of the TYPE Table. In dynamic error catch mode, the ECRs store row and/or column errors during pattern execution; failures are indicated by logic zeroes. In strobe masking mode, the ECRs disable strobes on specified rows and/or columns—a strobe is disabled when its corresponding bit in the ECRs is set to zero.


Together, the Row and Column ECRs are referred to as the ROWCOL Buffer. Like the other buffers, the Row and Column ECRs and the ROWCOL Buffer can be loaded from the program via INSERT commands (see “The Q Buffer: PGM Buffers,” in this section).

Clearing the Row and Column ECRs. The ROWCLEAR command clears the Row ECR by resetting all bits to logic ones (no-error); it also clears the RBINs by setting their contents to zero. Likewise, the COLCLEAR command clears the Column ECR and the CBINs. The RCCLEAR command clears the Row ECR, the Column ECR, the RBINs, and the CBINs.

Transferring Failure Information to the RBINs and CBINs. The PGM contains 64 Row Bins (RBINs) and 64 Column Bins (CBINs). The Row ECR contains one bit per DUT row; the Column ECR contains one bit per DUT column. An ECR bit is set to 0 (fail) if any address in the element (row or column) failed during pattern program execution, and if row and/or column error catching is enabled (via a PGOFFSET command). When ROWDUMP is executed, the address of each failing rows is transferred from the Row ECR to an RBIN: the address of the first bad row to RBIN0, the address of the second in RBIN1, etc., up to 64 (RBIN63). Likewise, COLDUMP transfers the addresses of failing columns to the CBINs, one address per CBIN.

Full Error Catch RAM (ECR) Option. The PGM can support one of three different Full Error Catch RAM (ECR) option boards:

· 9Y, 11X, 1 Megabit ECR.

· 10Y, 10X, 1 Megabit ECR.

· 4 Megabit ECR/BEM, software configurable for X and Y dimensions.

If the DUT doesn’t span the entire address space of the ECR, the unused addresses can be used to store failure data in different regions of the ECR during redundancy and bitmapping applications. The ECRSEG command selects different regions of the ECR: its argument ECRSEG is a 16-bit number that enables or disables ECR address lines individually. The bit descriptions for the 16-bit number vary depending on the ECR in use, as follows:

MSB LSB

9Y, 11X, 1M ECR 0 0 0 0 Y8 Y7 Y6 Y5 Y4 X10 X9 X8 X7 X6 X5 X4

10X, 10Y, 1M ECR 0 0 0 0 Y8 Y7 Y6 Y5 Y4 Y9 X9 X8 X7 X6 X5 X4

4M ECR (BEM) X11 Y10 Y9 0 Y8 Y7 Y6 Y5 Y4 X10 X9 X8 X7 X6 X5 X4


For example, consider a device with 9 X and 9 Y addresses. If the 9Y, 11X ECR is used, the unused addresses (X9 and X10) can be used to address different regions of the ECR; complete failure data from up to four pattern executions can be stored in the ECR.

11 X

9 Yaddressed when

X9 = 0 andX10 = 0

addressed whenX9 = 1 and

X10 = 0


X10 = 1


X10 = 1

Q2/52 Redundancy Analysis

RCINITInitializes repair algorithm for new device.ECCLEAR Clears Full ECR. RCREPAIRPerforms repair analysis.RCREPDONEFlags all elements in RBINs and CBINs as “repaired”; saves them to temporary storage; clears RBINs and CBINs.RCDMPBADLogs to-be-repaired elements in RBINs and CBINs.RCDMPFIXEDRetrieves list of “repaired” elements and stores in RBINs and CBINs.PGOFFSET number, FULLEC Start pattern execution with ECR enabled.

The following section Copyright 1993 by Sytest Systems Corporation.

Repairing Devices Using RCREPAIR (Redundancy Algorithm). The commands in this section are used in conjunction with the optional Full Error Catch RAM module and the Row and Column Error Catch RAMs on the PGM, which records and analyzes failing locations during a test.

At the conclusion of test pattern execution, the RCREPAIR command can be used to analyze the contents of the Full Error Catch RAM and return to the user a list of rows and columns to replace in order to repair the device. (Note that RCREPAIR does not actually make the repairs.)


RCREPAIR is useful for devices having both redundant rows and columns, because it determines in each case whether it is more efficient to replace a row or a column—a strategy that conserves redundant elements. The programmer can indicate a preference for either row or column repair, and can even specify the exclusive use of one type of element, regardless of efficiency. Analysis can be restricted to any part of the device for partial testing and repair. Segmented devices, devices with multiple-row or multiple-column redundant elements, and devices whose redundant elements are shared between segments can all be accommodated.

Special note for segmented devices: RCREPAIR can only be used for devices where each segment’s address space can be completely described by a first and last row, and a first and last column. See “The User Preference Byte (USERP),” below, for more information.

Basic Principles of RCREPAIR. RCREPAIR consists of two distinct operations: first it builds a list of must-replace rows and columns, assigning the necessary redundant elements to replace them, and then it attempts to cover any remaining bad locations with the remaining spares. Both operations are performed for every segment, one segment at a time, until all segments in the defined analysis region have been analyzed and repairs have been assigned or until some segment is found to be unrepairable, in which case RCREPAIR returns immediately.

In building the bad-location list, RCREPAIR scans the Column ECR to find a column with errors. When a bad column is found, RCREPAIR reads bits from the Full Error Catch RAM for that column and records the row/column coordinates of the bad locations it finds. If the number of failed rows in the column exceeds the number of spare rows in the segment, the replacement of the column is recommended, and the locations so far recorded for the column are removed from the bad-location list. For the purpose of continuing the analysis, RCREPAIR considers the repair to be complete once it has recorded a recommended repair.

When all columns have been scanned, and all must-replace columns have been accounted for, the list of bad locations is scanned for must-replace rows. When all of these have had redundant rows assigned for their repair, one of three conditions will result: either no bad locations remain—the segment can be successfully repaired; or there are still bad locations but no spares remain, in which case the segment is not repairable; or bad locations as well as spares remain, and an attempt must be made to finish the repair pattern plan.

In the third case, RCREPAIR finds the worst remaining row or column in the segment, and assigns to it a redundant element, according to user preference and availability of spares. This process is repeated until all bad locations have been covered, or all spares in the segment have been exhausted; in the latter case, if bad locations remain, the segment is not repairable.


If RCREPAIR finds an unrepairable segment, it returns immediately, even if some segments remain unexamined.

If all segments are repairable, RCREPAIR returns RBIN and CBIN tables containing the rows and columns to be replaced.

If the number of repairs to be returned exceeds the available space in the RBIN and CBIN tables, a bit is set in a PGM operating system. variable, indicating that the algorithm could not complete successfully. This bit is the same one set if the part is unrepairable, so the algorithm failure would appear to the user program as an unrepairable device.

The Repair Table. To analyze error data, RCREPAIR must have information on the topology of the device. The parameters describing the device are contained in a single buffer, called the Repair Table. The Repair Table must be loaded before the redundancy algorithm can be used. The fields of this table are described below:

First byte offset(dec) (hex) Name Type Contents

0 .0 NSEG byte Number of segments in this device (1 to 16, decimal).1 .1 INSC byte Initial number of spare columns per segment (0 to 8).2 .2 INSR byte Initial number of spare rows per segment (0 to 8).3 .3 CUT word Columns used together—how many physical columns are

replaced by one spare (1, 2, 4, or 8).5 .5 RUT word Rows used together—how many physical rows are replaced

by one spare (1, 2, 4, or 8).7 .7 RLTBL byte array Row linkage table—for each segment, if linked to another

segment by row, the number of the segment to which it is linked; if not linked by row, .FF. See the examples following.

23 .17 CLTBL byte array Column linkage table—for each segment, if linked to another segment by column, the number of the segment to which it is linked; if not linked by column, .FF. See the example following.

39 .27 SBFR word array Segment boundary: first row. For each segment, this is the first row in the segment.

71 .47 SBLR word array Segment boundary: last row. For each segment, this is the last row in the segment.

103 .67 SBFC word array Segment boundary: first column. For each segment, this is the first column in the segment.

135 .87 SBLC word array Segment boundary: last column. For each segment, this is the last column in the segment.

167 .A7 FROW word First row to be considered in this call.169 .A9 LROW word Last row to be considered in this call.


171 .AB FCOL word First column to be considered in this call.173 .AD LCOL word Last column to be considered in this call.175 .AF USERP byte User Preference Byte (see below).

Four words in the Repair Table—FROW, LROW, FCOL and LCOL—may need to be modified repeatedly: they define the limits of the error analysis, and may need to be changed between RCREPAIR commands to examine different regions of the device.

The User Preference Byte (USERP). In the User Preference byte, the user program specifies whether rows or columns should be used preferentially, whether logical or physical row and column addresses should be returned, whether logical or physical (scrambled) addresses should be used during analysis, and whether the Row and/or Column Error Catch RAM alone should determine replacement recommendations, or whether the full Error Catch RAM should be used. (This last decision is determined by the redundancy optimization bit.)

The format of the User Preference byte is shown below. Full bit descriptions follow.

User Preference Byte—Bit Descriptions.Bit 0: This bit specifies the type of redundant element to use first in assigning repairs: a 0 indicates


that columns are to be used first (if available), and a 1 indicates that rows are to be used first (if available).

Bit 1: This bit specifies whether the choice in bit 0 is absolute or merely a preference. Here, a 0 indicates that the chosen element type (row or column) is to be used until no more are available, before any elements of the other type are used. A 1 indicates that after the worst row and worst column are found, whichever is worse will be replaced (assuming both types of spares remain available), regardless of bit 0’s value. If the worst row and worst column have the same number of bad locations, the row/column preference bit (0) determines which type is replaced.

Bit 2: This is the redundancy scrambling bit; it is usually set to 0. It need only be set to 1 if any of the redundancy segments contain non-contiguous addresses. For example, if a part has two redundancy segments, one consisting of all the even rows and one consisting of all the odd rows, it could not be analyzed correctly if the repair algorithm assumes that the addresses in a segment are contiguous. Setting this bit to a 1 instructs the algorithm to look up the “real” addresses in the Bit Map Scramble RAMs, which can be used to provide a contiguous address space interface to the repair algorithm. These RAMs must be loaded with the correct data—see Repair Table Example 1, following. Note that the same Bit Map Scramble RAMs are also used whenever physical rows or columns are to be returned (see bits 3 and 4, below).

Bit 3: This bit specifies whether logical or physical rows are to be returned in the RBIN array. The default is 0 (logical addresses). The algorithm uses logical rows internally. If four rows are used together, then there are only one quarter as many logical rows as physical rows. If physical rows are selected, then after the algorithm has performed the analysis it looks in the Bit Map Scramble RAMs to determine the physical row to put in the RBIN array—see Repair Table Example 2, following. Note that the same Bit Map Scramble RAMs are used for redundancy scrambling (bit 2, above). Set this bit to a 1 (return physical row addresses instead of logical) for devices that use several rows together in a single spare element.

Bit 4: This bit indicates whether logical (0) or physical (1) columns are to be returned in the CBIN array—it is analogous to bit 3, but for columns instead of rows.

Bit 5: This bit controls redundancy optimization. It is usually set to 0—redundancy optimization enabled. By default, when a device with linked segments is tested, and all the linked elements have been used and a new segment is about to be analyzed, the redundancy algorithm will use row-only or column-only replacement (based on the type of element remaining). This means that the Row and Column Error Catch RAMs are used solely to determine replacement recommendations, which can cause problems if there is more than one segment in the direction (row or column) that still has spares. In such cases, this bit should be set to 1 (no optimization). See “When Not to Use Redundancy Optimization,” below.

When Not to Use Redundancy Optimization. In general, redundancy optimization should be turned off (bit 5 of the User Preference Byte set to 1) when the device to be tested has both row and column spares.

Consider the following device:


This device has four segments, with one redundant row and one redundant column per segment. The columns are linked: segments 0 and 1 share a column and segments 2 and 3 share a column.

There are four errors:

in segment 1: (column 15, row 80) and (column 40, row 110)in segment 2: (column 70, row 10) and (column 80, row 20)

If redundancy optimization is ON (the default condition), the system would consider this part unrepairable. The reasoning is as follows: segments 1 and 2 would each use one row and one column spare. Since no more column spares remain, only the Row Error Catch RAM is considered when segment 3 is analyzed (instead of the Full Error Catch RAM). However, the row errors for segments 1 and 3 are “collapsed” together in the Row Error RAM. Because there is only one spare row available for segment 3, and the Row Error RAM contains two errors (from segment 1), the repair algorithm concludes that the part is unrepairable. If bit 5 of the User Preference Byte were set to 1 (no optimization), the Full Error Catch RAM would be used in the analysis, and the repair algorithm would correctly consider the part repairable.

Repair Table Example 1:


This device has two redundancy segments, each of which has two redundant columns. The two segments share a single redundant row.

Segment 0 contains only the even columns; segment 1 contains only the odd columns. The redundancy scrambling bit (bit 2) of the User Preference byte should be set to 1, and the Y Bit Map Scramble RAMs should be loaded as follows:

address Y BMS RAM01..

127128129

.

.255

02..

25413..

255

The X Bit Map Scramble RAMs should be linear.

The repair table for this device should be loaded as follows:

NSEG: 2 RUT: 1 SBLR: 255, 255 LROW: 255INSC: 2 RLTBL: 1, 0 SBFC: 0, 128 FCOL: 0INSR: 1 CLTBL: .FF, .FF SBLC: 127, 255 LCOL: 255CUT: 1 SBFR: 0, 0 FROW: 0 USERP: 6



This device has only one redundancy segment, with two redundant rows and two redundant columns. Eight rows are used together.

Physical rows are desired, so the physical/logical rows bit (bit 3) of the User Preference byte should be set to 1. The X Bit Map Scramble RAMs should be loaded as follows:

address X BMS RAM012..

31

08

16..

248


NSEG: 1 RUT: 8 SBLR: 255 LROW: 255INSC: 2 RLTBL

:.FF SBFC: 0 FCOL: 0

INSR: 2 CLTBL:

.FF SBLC: 255 LCOL: 255

CUT: 1 SBFR: 0 FROW: 0 USERP: .0A


0 1 2 ... ... 255 0 1 2 ... ... 2550

255

.

.

.

.D0 to D7 D8 to D15

This device has two redundancy segments, each of which has one redundant column. The two segments share a single redundant row.

Segment 0 contains errors for D0–D7; segment 1 contains errors for D8–D15. The redundancy optimization bit (bit 5) of the User Preference byte should be set to 1. Before ECCLEAR is executed, the Type Table needs to define an area as large as the area in the ECR that will be used to catch errors. The pattern should be run twice: first with D0–D7 strobes enabled and ECRSEG set to 0, then with D8–D15 strobes enabled and ECRSEG=.800. ECRSEG should be restored to 0 before the redundancy analysis. See


the description of ECRSEG in “Q2/52 PGM Error Catch Control,” above, and the next example.

Additionally, the Column Error Catch RAM must be “zeroed out” by writing 0’s to all locations.


NSEG: 2 RUT: 1 SBLR: 255, 255 LROW: 255INSC: 1 RLTBL: 1, 0 SBFC: 0, 256 FCOL: 0INSR: 1 CLTBL: .FF, .FF SBLC: 255, 511 LCOL: 511CUT: 1 SBFR: 0, 0 FROW: 0 USERP: .22


This example illustrates the use of the ECR segment mask for redundancy.

This device is a 1-Megabit DRAM with a 256Kx4 layout (9X, 9Y, and 4 data bits). Each data bit has one spare row and one spare column. Assume that the Q2/52 PGM contains an 11X 9Y one-Megabit ECR.

In order to test this part and determine its repairability, the ECR must contain unique error information for each data bit. This will require the entire one Megabit of the ECR, and will be done using the ECR segment mask. The following QTL code will test this part and analyze it (if necessary).

See “Q2/52 SPECIFIC TOPICS: Q2/52 PGM Error Catch Control” earlier in this chapter for a description of ECRSEG.


Example:

SENDPGMINSERT TYPE,0 ; ; First clear the entire ECR

PGMWORD .1FF, .7FF ; 9Y and 11XINSENDECCLEARECRSEG 0 ; Start in ECR segment 0INSERT TYPE, 0

PGMWORD .1FF, .1FF ; Part's address space is 9X, 9YINSENDINSERT TYPE, 13 ; Set strobe mask for D0

PGMBYTE 1INSENDPGOFFSET 25,FULLEC ; Run test patternINSERT TYPE, 13 ; Set strobe mask for D1

PGMBYTE 2INSENDECRSEG .20 ; Change ECR segment mask to the

; next 256K section of ECRPGOFFSET 25, FULLEC ; Run test patternINSERT TYPE, 13 ; Set strobe mask for D2


; next 256K section of ECRPGOFFSET 25, FULLEC ; Run test patternINSERT TYPE, 13 ; Set strobe mask for D3


; next 256K section of ECRPGOFFSET 25, FULLEC ; Run test patternECRSEG 0 ; IMPORTANT: Set ECR segment

; mask back to 0 before running; redundancy algorithm!

RCREPAIR ; Perform redundancy analysisBRANCH REPAIRABLE, L1 ; If the part is not repairable...GENERR ; Generate an error

L1:HALT

ENDLIST


The Repair Table for this device would be loaded as follows:

NSEG: 4 SBLR: (511, 1023, 1535, 2047)INSC: 1 SBFC: (0, 0, 0, 0)INSR: 1 SBLC: (511, 511, 511, 511)CUT: 1 FROW: 0RUT: 1 LROW: 2047RLTBL: .FF, .FF, .FF, .FF FCOL: 0CLTBL: .FF, .FF, .FF, .FF LCOL: 511SBFR: (0, 512, 1024, 1536) USERP: .02

Loading the Repair Table. All relevant fields must be loaded into the Repair Table before using the repair algorithm. In most cases, the table need not be referred to again. The Repair Table is loaded with an INSERT statement in the QTL program.

Following is an example of how to load the Repair Table. The device in this example is a 256K EEPROM which has four spare column elements grouped together in pairs consisting of two columns each, and two spare row elements grouped together in groups of four, consisting of four rows each. This part has two segments, and the redundant columns are shared between the segments.


Example:

SENDPGMREPAIR, 0

PGMBYTE 2,4,2 ; NSEG, INSC, INSRPGMWORD 2 ; CUTPGMWORD 4 ; RUTPGMBYTE .FF,.FF ; Row link entries for

segments 0 and 1INSENDINSERT REPAIR, .17

PGMBYTE 0,1 ; Col link entries for segments 0 and 1

INSENDINSERT REPAIR, .27

PGMWORD 0 ; Segment 0 first rowPGMWORD 256 ; Segment 1 first row


PGMWORD 255 ; Segment 0 last rowPGMWORD 511 ; Segment 1 last row


PGMWORD 0 ; Segment 0 first columnPGMWORD 0 ; Segment 1 first column


PGMWORD 63 ; Segment 0 last columnPGMWORD 63 ; Segment 1 last column

INSENDINSERT REPAIR, .A7

PGMWORD 0 ; FROW (first row to analyze)PGMWORD 511 ; LROW (last row to analyze)PGMWORD 0 ; FCOL (first column to analyze)PGMWORD 63 ; LCOL (last column to analyze)PGMBYTE 2 ; USERP (prefer columns first; return

; logical rows and columns)INSEND

ENDLIST

Using the Redundancy Algorithm in a Test Program. The following commands are used in combination to invoke the Redundancy Algorithm, which determines the rows and columns to be replaced. Additional commands concerning the repair procedure follow these descriptions.

RCINIT. Before using RCREPAIR (but after loading the Repair Table), the RCINIT command must be used to initialize the repair algorithm for a new device; this command must be used each time a new part is put in the socket for testing, or to restart the repair


analysis of a device from the beginning. RCINIT must not be used until after the Repair Table is loaded, because it uses values from that table.

ECCLEAR. The ECCLEAR command is used to clear the Error Catch RAM. Errors remain logged on the Error Catch RAM until it is cleared. Therefore, in order to avoid the possibility of incorrect results in a subsequent use, it is vital to clear the Error Catch RAM after each use. ECCLEAR does not execute an RCCLEAR command. ECCLEAR should be used before the start of each new device. Note: for devices that have redundant elements that do not apply for all data bits, an area larger than the DUT’s address space must be cleared—see the preceding examples. This is because ECCLEAR uses the X and Y address masks set up in the Type Table to determine the area to clear.

PGOFFSET with the FULLEC Argument. The PGOFFSET command that starts pattern execution must have FULLEC (Full Error Catch) as an argument, in order to enable the Error Catch RAM. (See the complete description of PGOFFSET earlier and the sample call sequence at the end of this section.)

RCREPAIR. Finally, the RCREPAIR command performs the repair analysis. To do partial testing and analysis of a device, use RCINIT once, then use PGOFFSET with FULLEC, and RCREPAIR as many times as is necessary until all regions of the device can be repaired.

Replacing Elements at the Conclusion of Testing. If all repairs are to be effected at the conclusion of a multiple-pattern test, the program should contain only one ECCLEAR command and one RCREPAIR command. The ECCLEAR command clears the Full Error Catch RAM prior to the entire series of PGOFFSET commands. Therefore, at the conclusion of the series of patterns, the Full Error Catch RAM contains the accumulation of all cells that failed during any pattern. After all of the PGOFFSET commands for the test, the program contains one RCREPAIR command, which analyzes the errors and generates either the list of rows and columns to replace in order to repair the device (or segment), or sets a flag indicating that the device is unrepairable. All the locations that must be replaced are logged together in the RBINs and CBINs.

The sample calling sequence below invokes the redundancy algorithm only at the conclusion of the test:


Example:

SENDPGMRCCLEAR ; Clears Row and Column ECRsECCLEAR ; Clears Error Catch RAMRCINIT ; Initializes for this DUTPGOFFSET 12,FULLEC ; Enables Full Error Catch RAM

; and starts pattern at uRAM 12PGOFFSET 30,FULLEC ; Enables Full Error Catch RAM

; and starts pattern at uRAM 30PGOFFSET 52,FULLEC ; Enables Full Error Catch RAM

; and starts pattern at uRAM 52RCREPAIR ; Performs error analysis based on

; errors collected in all three; patterns

BRANCH REPAIRABLE,L1 ; Branches if DUT is repairableGENERR ; Sets error flag if unrepairableHALT

L1: EXU 28 ; Executes actual repair sequence; beginning at location 28 in the; user area

HALTENDLIST

In this example, “EXU 28” directs the program to a user-written repair algorithm not shown here. Also, after the ENDLIST, the PGM command JUMP TRUE, label can be used to branch on the status of the logic flag.

Replacing Elements During Testing. During a multiple-pattern test, repair analysis can occur once at the end of the test, as described above, or after each pattern. Actual repairs can be made in the course of a test, before continuing with another pattern. However, once a repair has been effected by replacing a row or column with a redundant element, a procedure different from that of the original repair can be required in order to make subsequent repairs. Therefore, before failing rows and columns can be replaced, a comparison must be made to see if any of the locations have been previously repaired. If so, it may be necessary to implement an alternative repair procedure. This is a possible limitation of the device or the peripheral repair equipment, not of the tester or the redundancy algorithm.

The Redundancy Algorithm uses a temporary scratch pad data storage area to save lists of locations of repaired rows and columns. The program must contain instructions, in the form of RCREPDONE, RCDMPFIXED, and RCDMPBAD commands, that save and retrieve RBIN and CBIN data from this area during a test.

Briefly, the sequence of commands and events is as follows:

The first pattern of a test is executed, and the errors are logged in the Full Error Catch RAM. The Redundancy Algorithm is then invoked, using RCREPAIR. At the


conclusion of the error analysis, the RBIN and CBIN tables contain the locations of the rows and columns selected by the Redundancy Algorithm for replacement. If the DUT is unrepairable, the ERROR flag is set and the test program halts. If the DUT is repairable, the program branches to the user-written device repair algorithm (which directs the Q2/52 either to perform the repairs itself or to supply the necessary data to peripheral repair equipment).

After the repair algorithm has been executed, an RCREPDONE command causes the lists of rows and columns contained in the RBIN and CBIN tables to be flagged as “fixed” and saved in the temporary scratch pad area.

An RCCLEAR command clears the RBIN and CBIN tables (and sets the Row and Column Error Catch RAMs to the no-error state) and another pattern is begun. Again, errors are logged and transferred to the RBINs and CBINs by RCREPAIR. This time, however, since some of the failing locations might be in rows and columns that have already been replaced by redundant elements, comparisons must be made between the lists of currently-failing locations (in the RBIN and CBIN tables) and the lists of replaced lines. In order to do this, the failing locations are transferred by TRANSFER commands to functional bins (FBINs). RCDMPFIXED retrieves the lists of replaced lines from the scratch pad area and re-logs them in the RBINs and CBINs. They are then also transferred to FBINs. A comparison (using a COMP BIN command) is made between the FBINs containing the already-replaced lines and the FBINs containing the failing lines. If any equalities between the FBINs are detected, the program branches to another user-written repair algorithm, which effects special repairs by replacing lines already replaced.

Note: The RCINIT command clears all data from the temporary scratch pad data storage area.

Example code follows the command descriptions.

RCREPDONE. RCREPDONE flags as “fixed” all locations which were put in the RBIN and CBIN tables as it saves them in the scratch pad area. The RCREPDONE command is used after the necessary repairs have been completed on the device (whether by peripherals or by the tester itself). RCREPDONE causes the lists of replaced elements to be recorded from the RBINs and CBINs and saved in the scratch pad data area, thereby clearing the RBINs and CBINs for another test. (The Row and Column ECR’s are not cleared.)

RCDMPFIXED. The RCDMPFIXED command retrieves the lists of repaired rows and columns (i.e., all locations flagged as fixed) from the temporary scratch pad data storage area and saves that information in the RBINs and CBINs. Note that RCDMPFIXED will overwrite anything already in the RBIN and CBIN tables. RCDMPFIXED initializes the Row and Column bins completely—the only data they contain is the most recent.


RCDMPBAD. The RCDMPBAD command returns in the RBINs and CBINs all the lines that have been selected for replacement by the last call to RCREPAIR and that are not flagged as fixed. RCDMPBAD returns the same information as does the last call to RCREPAIR (assuming that no RCREPDONE command has been executed): a list of all rows and columns to be replaced from the preceding pattern. RCDMPBAD is useful for restoring data that may have been overwritten in the RBIN and CBIN tables by an RCDMPFIXED command.

Sample Call Sequence. Below is an example of a command sequence which invokes the redundancy algorithm after each pattern, throughout the test.


(load Repair Table)

SENDPGMRCINIT ; Initializes for this DUTRCCLEAR ; Clears Row and Column ECRsECCLEAR ; Clears Error Catch RAMPGOFFSET 12,FULLEC ; Enables Full Error Catch RAM and

; starts pattern at uRAM 12BRANCH NOERRORS,L1 ; Branches if no errorsRCREPAIR ; Perform error analysisBRANCH REPAIRABLE,L2 ; Branch if DUT is repairableGENERR ; Sets ERROR flag if unrepairableHALT

L2: EXU 28 ; Executes actual user-written repair ; sequence starting at location 28 in ; the user area

RCREPDONE ; Transfers locations of repaired ; elements to temporary table

RCCLEAR ; Clears Row and Column ECRsECCLEAR ; Clears error catch RAM

L1: PGOFFSET 20,FULLEC ; Enables Full Error Catch RAM and ; starts pattern at uRAM 20

BRANCH NOERRORS,L3 ; Branches if no errorsRCREPAIR ; Performs error analysisBRANCH REPAIRABLE,L4 ; Branches if DUT is repairableGENERR ; Sets ERROR flag if unrepairableHALT

L4: EXU 200 ; Executes user-written sequence ; (starting at location 200 in the user

; buffer) which checks to see if any of

; the failing elements have previously; been replaced

EXU 300 ; Executes user-written sequence ; (starting at location 300 in the user

; buffer) which determines which type ; of replacement to do: replacement of; a previously replaced element; or replacement of an original element

EXU 400 ; Executes actual user-written repair ; sequence starting at location 400 in; the user buffer

L3: HALTENDLISTFUNTEST EXQ

In this example, all EXU commands direct the program to user-written algorithm in the user buffer (not shown here).

Results Returned by RCREPAIR. Rows and columns to be replaced are returned in the RBIN and CBIN buffers (RBIN contains the rows; CBIN the columns). Entries are


grouped by segments, which are numbered starting with zero. For an unsegmented device, there is only one segment: zero. The first word of a segment’s entries is a “header” word, containing the segment number in the upper byte and the number of lines to be replaced in the lower byte. The next one or more words contain the row or column numbers to be replaced, one per word. The lower byte of the segment header word thus tells how many words after the header word contain replacement rows or columns for that segment.

Immediately following the last line to be replaced for any segment is the segment header word for the next segment (or zero if there are no more segments or replacements).

Consider the following sample device, which has two redundancy segments, each of which has two redundant columns.

Each segment contains two bad columns: columns 10 and 187 in the first segment, and columns 265 and 495 in the second segment.

After a call to RCREPAIR, the CBIN word array would contain the following:

word hex value meaning0 0002 Upper byte = 0: segment zero.

Lower byte = 2: two columns to be replaced.1 000A Entire word specifies the first column to be replaced: hex A

(decimal 10).2 00BB Entire word specifies the next column to be replaced: hex BB

(decimal 187).3 0102 Upper byte = 1: segment one.

Lower byte = 2: two columns to be replaced.4 0109 Entire word specifies the first column to be replaced in this

segment: hex 109 (decimal 265).5 01EF Entire word specifies the next column to be replaced in this

segment: hex 1EF (decimal 495).6 0000 End of data.


RBIN and CBIN are 64 words in length (each), so a maximum of 128 words can be returned.

Some device designs permit only block-replacement of 2, 4, or 8 rows or columns at a time. The user specifies the number of rows and columns in a block with the parameters RUT (rows used together) and CUT (columns used together) in the Repair Table. RCREPAIR analyzes errors for these blocks of 1, 2, 4, or 8 physical lines, and returns block numbers—not physical line numbers—in RBIN and CBIN. If RUT or CUT is not equal to 1, these block numbers will differ from the physical line numbers to be replaced, unless physical rows or columns are specified in the user preference byte.

For example, if RUT = 8, and (block) zero were returned in RBIN, the user would have physical rows 0 though 7 replaced. If (block) 9 were returned, physical rows 72 through 79 (decimal) would need to be replaced.

The preceding section Copyright 1993 by Sytest Systems Corporation.


Q2/52 PGM High Voltage Module

HVM ENABLE Enables High Voltage Module. EPM ENABLE Enables High Voltage Module as (EPROM Programming Module).HVM DISABLE Disables High Voltage Module.EPM DISABLE Disables High Voltage Module as (EPROM Programming Module).

BOOST ENABLE Enables HVM boost.BOOST DISABLE Disables HVM boost.

VRAIL voltage Sets HVM power supply level to voltage millivolts.VPULSE voltage Sets HVM voltage output pulse to voltage millivolts.IRAIL current Sets HVM supply current threshold to current microamps.

ITEST Tests state of current detect flag.PV Prints HVM VPULSE, VRAIL, IRAIL.

The High Voltage Module (HVM) Option. The HVM provides a programmable DUT power supply (VRAIL) with an output level of 2 to 32 volts, current detect capability (IRAIL), and a high voltage output pulse (VPULSE) whose upper level is programmable over a range of 2.0 to 30.0 volts. VRAIL is a positive supply that sources at least 70 ma of output current. VPULSE is a positive-going pulse output during each cycle that the pattern generator pattern contains a VPULSE mnemonic in the CHIPS statement (see “Q2/52 SPECIFIC TOPICS: Q2/52 Pattern Programming,” below). Potentiometers on the HVM allow transition times to be adjusted from 0.5 to 2.0 microseconds.

Enabling the HVM. Upon system power-up, the HVM’s power supply and pulse outputs, VRAIL and VPULSE, are tri-stated (set to a high impedance state). The HVM command enables (activates) or disables (tri-states) VRAIL and VPULSE. The EPM command is functionally identical to HVM.

HVM Boost Capability. The BOOST command enables (activates) or disables (deactivates) the HVM’s voltage boost capability. Boost capability must be enabled whenever voltages over 20 volts are required on VRAIL or VPULSE, and should be disabled whenever VRAIL and VPULSE are not being used or when they are programmed to below 20 volts. Upon power-up, boost capability is disabled.

Setting VRAIL and VPULSE. The VRAIL command programs VRAIL to a voltage in the range 2000–32,760 mv, with a resolution of 8 mv. The VPULSE command programs VPULSE to a voltage in the range 2000–30,000 mv, with a resolution of 120 mv. The low-level of the VPULSE signal is 0 v.

Setting the Current Detect Threshold. The IRAIL command programs IRAIL, the current detect threshold for power supply tests performed with VRAIL, to a current in


the range 0 to 49.14 ma, with a resolution of 12 µa. IRAIL is not a current limit: it is a threshold for supply current testing. The VRAIL supply provides at least 70 ma.

The IERROR Flag. Current from VRAIL is continuously monitored and compared with the value programmed for IRAIL. If the current exceeds IRAIL for more than 2 ms, the IERROR flag is set. The ITEST command checks the state of the IERROR flag and generates a functional test error if IERROR is set. The RESETERR command (see the description in “Q2/52 SPECIFIC TOPICS: PGM Program Flow Control,” above) resets the IERROR flag.

Printing HVM Programmed Values. The PV command prints the currently set values of VPULSE, VRAIL, and IRAIL.

Pattern Generator Programming

A pattern program consists of one to 256 microinstructions. Each microinstruction contains the following seven statements:

Statement Controls

YALU Y address generation (Y Arithmetic Logic Unit)XALU X address generation (X Arithmetic Logic Unit)COUNT Loop counterMAR MicroRAM Address RegisterCHIPS Chip Select signalsDATGEN Data generatorUDATA Microdata Field

The statements must appear in exactly the order given.

The YALU and XALU Statements. The Q2/52 provides two independent address generators: one for column addresses, controlled by the YALU statement, and one for row addresses, controlled by the XALU statement. These statements take the following form:

YALU sourceA, sourceB, carry/borrow, function, destination(s), addressout

XALU sourceA, sourceB, carry/borrow, function, destination(s), addressout

YALU and XALU “sourceA” and “sourceB” Operands. Specify the primary (sourceA) and secondary (sourceB) source inputs to the ALU.


For YALU Statements: For XALU Statements:

YMAIN Selects the YMAIN address register for input.

XMAIN Selects the XMAIN address register for input.

YBASE Selects the YBASE address register for input.

XBASE Selects the XBASE address register for input.

YFIELD Selects the YFIELD address register for input.

XFIELD Selects the XFIELD address register for input.

YUDATA Selects bits 0-11 of the Microdata Field.

XUDATA Selects bits 12-23 of the Microdata Field for input.

XCARE Selects no source input selected. The “X” does not refer to the X address generator.

XCARE Selects no source input selected. The “X” does not refer to the X address generator.

YALU and XALU “carry/borrow” Operand. Set the carry or borrow function. Some ALU functions require the carry input to be set; others require the carry input to be off. See “YALU and XALU ‘function’ Operands,” below.

The following operands force the carry/borrow function explicitly on or off, regardless of any address register value:

CON Carry forced on.COFF Carry forced off.BON Borrow forced on.BOFF Borrow forced off.XCARE Don’t care.

The following operands set the state of the carry/borrow function to be dependent on one of the registers in the other address generator (that is, in a YALU statement, the state of the carry/borrow bit can depend on one of the registers in the X address generator, and vice versa). The maximum address for each MAIN, FIELD, and BASE register is set in Bytes 0–3 of the TYPE Table. The minimum address is always 0.

Carry when value in specified register of OTHER address generator is:equal to its maximum

not equal to its maximum

equal to its minimum

not equal to its minimum

MAIN CMEQMAX CMNEMAX CMEQMIN CMNEMINFIELD CFEQMAX CFNEMAX CFEQMIN CFNEMINBASE CBEQMAX CBNEMAX CBEQMIN CBNEMIN


Borrow when value in specified register of OTHER address generator is:equal to its maximum

not equal to its maximum

equal to its minimum

not equal to its minimum

MAIN BMEQMAX BMNEMAX BMEQMIN BMNEMINFIELD BFEQMAX BFNEMAX BFEQMIN BFNEMINBASE BBEQMAX BBNEMAX BBEQMIN BBNEMIN

YALU and XALU “function” Operand. Specify the operation the ALU will perform on the register and carry/borrow inputs. The ALU has three inputs: the primary source (sourceA), the secondary source (sourceB), and the carry/borrow. The most frequently used ALU functions are programmable by means of the following operands:

COMP Complement sourceA input and output to the destination register(s).ZERO Force ALU output to zero regardless of the source input.HOLD Take no action; hold the ALU output fixed at the value of the sourceA input.ALL1S Force output of ALU to “all ones” (maximum) address regardless of the

source input. This is the inverse of the ZERO operand.ADD Add sourceA input to sourceB input; add a carry to the result. INCREMENT Add the carry to sourceA input. Thus, when a carry is generated the address

is incremented.DOUBLE Double the sourceA input, and add a carry.DECREMENT If a borrow is enabled, subtract it from the sourceA input. Use this function

with the borrow mnemonics: when a borrow is generated, the address is decremented.

SUBTRACT Subtract sourceB input from sourceA input; subtract a borrow from the result. This is the inverse of the ADD function.

OR Logical-OR the sourceA with the sourceB input. XOR Exclusive-OR the sourceA input with the sourceB input. AND Logical-AND the sourceA input with the sourceB input.

Any 74F181 ALU function can be programmed, even if a mnemonic operand is not shown. To do so, find the S0–S3 and mode values for the function on the 74F181 data sheet, and convert them to a hexadecimal number as follows:

MSB LSB

S3 S2 S1 S0 mode

Insert the resulting hex number as the function operand. Remember to prefix a “.” to indicate that it is a hex number. For example, to program the ALU function “F=source B,” use “.15” (hexadecimal) as the function operand. The data sheet specifies that for this function, S3=H, S2=L, S1=H, S0=L, and mode=H. Converting 10101 to hexadecimal results in hexadecimal 15.


YALU and XALU “destination” Operand. Specify the destination register(s) of the resulting address after the ALU has operated on the register and carry/borrow inputs. Any or all of the three address registers can be used as destination registers. Multiple destinations must be separated by commas.


DYMAIN Destination is YMAIN DXMAIN Destination is XMAINDYBASE Destination is YBASE DXBASE Destination is XBASEDYFIELD Destination is YFIELD DXFIELD Destination is XFIELDNODEST No destination specified NODEST No destination specified

YALU and XALU “addressout” Operand. Specify which address register (MAIN, BASE, or FIELD) is to be used as the source of the DUT address. The contents of the specified address register are routed through the topological scramblers to the DUT.


OYMAIN Source is YMAIN OXMAIN Source is XMAINOYBASE Source is YBASE OXBASE Source is XBASEOYFIELD Source is YFIELD OXFIELD Source is XFIELD

If no operand is specified in a YALU statement, the default is OYMAIN; if no operand is specified in a XALU statement, the default is OXMAIN.

The COUNT Statement. The COUNT statement allows a program branch to be dependent on the value of a loop counter. There are five 24-bit loop counters (COUNTA through COUNTE) and five associated 24-bit reload registers. The ALU can decrement a counter by 1 or 2, increment it by 1, or leave it unchanged.

At the start of pattern program execution, an initial value is loaded into a source counter and its associated reload register as an initial condition macro (see “Initial Conditions” below). The ALU function operates on this value during each cycle and writes the result into a destination counter. If a counter reaches zero and the autoreload function is enabled, the value in the reload register is loaded back into the associated destination counter. (A “source” in this context is defined as the counter or reload register that acts as an input for an ALU function; a “destination” is defined as the counter or reload register that receives an ALU output.)

The COUNT statement takes the following form:COUNT source, destination(s), function, autoreload

COUNT “source” Operand. Specify which loop counter is the input to the counter ALU. Following are the available operands to select the source counter input. Only one source operand is allowed.


COUNTA Selects loop counter A as source counter input.COUNTB Selects loop counter B as source counter input.COUNTC Selects loop counter C as source counter input.COUNTD Selects loop counter D as source counter input.COUNTE Selects loop counter E as source counter input.COUNTUDATA Selects the UDATA field as source counter input.NOCOUNT Selects no source counter input.

COUNT “destination” Operand. Specify the destination counter(s). Following are the available operands to select the destination counter. Multiple destination operands are allowed; they must be separated by commas.

COUNTA Selects loop counter A as destination.COUNTB Selects loop counter B as destination.COUNTC Selects loop counter C as destination.COUNTD Selects loop counter D as destination.COUNTE Selects loop counter E as destination.RELOADA Loads reload register A from the UDATA field; selects loop counter A as

destination.RELOADB Loads reload register B from the UDATA field; selects loop counter B as

destination.RELOADC Loads reload register C from the UDATA field; selects loop counter C as

destination.RELOADD Loads reload register D from the UDATA field; selects loop counter D as

destination.RELOADE Loads reload register E from the UDATA field; selects loop counter E as

destination.NOCOUNT Selects no destination counter.

COUNT “function” Operand. Specify the ALU function to operate on the source. These functions let you program loops and branches dependent on a microinstruction being executed a certain number of cycles. Following are the available operands to select the counter ALU functions. Only one function operand is allowed.

DECR Decrement: subtract one from the value in the source counter.DECR2 Decrement by two: subtract two from the value in the source counter.INCR Increment: add one to the value in the source counter.NOCOUNT No action: hold the source counter at the value present at the start of the

cycle.

COUNT “autoreload” Operands. Enable the automatic reloading of the destination counter(s) when the source counter reaches 0. Each loop counter is backed by a reload


register. If enabled, source counters are automatically reset to the value in their corresponding reload registers when they reach 0. The following operands control the autoreload feature:

AON Enable autoreload.AOFF Disable autoreload.

The MAR Statement. The MAR statement directs pattern program flow, enables the data strobes, and controls the programmable interrupt timer. The MAR (MicroRAM Address Register) contains the address of the next microinstruction in the microRAM to be executed. When a branching condition, is met, a new address is set in the MAR. When a condition is not met, the default for the MAR is to increment to the next microRAM address.

The MAR statement takes the following form:MAR branch-condition, address, strobe-control, interrupt, timer

MAR “branch-condition” Operand. Define the method of program branching (jump, call or return) and defines whether or not a condition (zero, not zero, error, or no error) must be present for the branch instruction to be executed.

There are two types of MAR branching instructions: unconditional and conditional. Unconditional branch instructions simply force the MAR to a specified address. Conditional branches require that a special condition exist before they are executed: they are based on the state of a logical flag. This flag can be set by one of the five loop counters or by the ERROR flag. Whenever the logical flag is false (that is, the condition is not met), the program defaults to the next address in the microRAM. If a conditional subroutine call or return is specified, and the condition is satisfied, the subroutine call or return operates just like an unconditional subroutine call or return. If the condition is false, the pattern program defaults to the next MAR address.

The available operands to select both conditional and unconditional branches are shown below.

CJMPZ Conditional jump on zero: program branches to specified MAR address if source counter (specified in the COUNT statement) is zero at the start of the current PGM cycle. If source counter is not zero, program flow continues at next address in microRAM.

CJMPNZ Conditional jump on not zero: program branches to specified MAR address if the source counter is not zero. If source counter is zero, the program flow continues at next address in microRAM.

CJMPE Conditional jump on error: program branches to specified MAR address when the error flag is true (that is, when an error condition is detected).CJMPE requires that the pattern not stop on functional errors, so pattern


execution should be initiated with either PATTERN PROGRAM or PGOFFSET n without an ERROR argument.Note that an error condition is not available for branching until six cycles after a strobe; to branch on a particular address, program a six-cycle wait after a READ (see “MAR ‘strobe-control ’Operands,” below) to allow the error condition to flow through the system pipeline.

CJMPNE Conditional jump on no error: program branches to specified MAR address if no error condition exists when this microinstruction is executed. See the note about the pipeline in CJMPE, above.

CSUBZ Conditional subroutine call on zero: calls the subroutine at the specified MAR address if the source counter is zero at the start of the current PGM cycle. The return address (MAR+1) is pushed onto the top of the MAR’s address execution stack and the stack pointer is decremented. If the source counter is not zero, program flow continues at next address in microRAM.

CSUBNZ Conditional subroutine call on not zero: calls the subroutine at the specified MAR address if the source counter specified in the COUNT statement is not 0 at the start of the current PGM cycle. The return address (MAR+1) is pushed on the top of the MAR’s address execution stack and the stack pointer is decremented. If the source counter is zero, the program flow continues at next address in the MAR.

CSUBE Conditional subroutine call on error: calls the subroutine starting at the specified MAR address if the error flag is true when this microinstruction is executed. The stack operates in the normal manner.

CSUBNE Conditional subroutine call on no error: calls the subroutine starting at the specified the MAR address if no error condition exists during execution of this MAR instruction. The stack operates in the normal manner.

CRETZ Conditional return on zero: sets the MAR to return address popped off the stack if the source counter is zero at the start of the cycle. The stack pointer increments.

CRETNZ Conditional return on not zero: sets the MAR to return address popped off the stack if the source counter is not zero at the start of a cycle. The stack pointer increments.

CRETE Conditional return on error: sets the MAR to return address popped off the stack if an error condition exists. The stack operates in the normal manner for a return.

CRETNE Conditional return on no error: sets the MAR to return address popped off the stack if a no error condition exists. The stack operates in the normal manner for a return.

JUMP Unconditional branch to specified microinstruction: sets the MAR to specified address.

INC Unconditional branch to next microinstruction: increments the MAR. After this microinstruction is executed, pattern program is forced to the microinstruction at the next address in microRAM, regardless of the address specified in the MAR statement.

DONE Signals to PGM that pattern is complete: PGM stops cycling.GOSUB Unconditional call to subroutine starting at the address specified in this MAR

statement.RETURN Unconditional return from subroutine: causes pattern program to return from a

subroutine to the main body of the pattern program. Pattern program resumes at


the address immediately following the call to the subroutine.

MAR “address” Operand. Set the MAR address to which the branch-condition operand refers: a value from 0 to 255. The address may be specified as a decimal value, a hexadecimal value, or a literal. Hexadecimal values are useful when debugging a pattern since the Status Buffer contains MAR values in hexadecimal.

MAR “strobe-control” Operand. The comparators in the pin electronics channels compare expect data from the PGM to the data output of the DUT. The strobe-control operand enables or disables the comparators’ data strobes. An error at the DUT can only be detected in microinstructions in which the strobe is enabled.

READ DUT output data is to be read. Enables comparator strobes to read DUT output data. If no strobe-control operand is specified, this is the default.

NOREAD Masks strobes off from the pin electronics comparators. DUT output is not read.OVER Checks for overprogrammed cells (that is, cells that are not in their erased state

but should be) in NVMs; generates an error if an overprogrammed cell is found. Underprogrammed cells are ignored.

UNDER Checks for underprogrammed cells (that is, cells that are in their erased state but should not be) in NVMs; generates an error if an underprogrammed cell is found. Overprogrammed cells are ignored.

MAR “interrupt” and “timer” Operands. These operands control the operation of the real-time programmable interrupt timer, which can be used instead of a loop counter to execute a set of microinstructions for a certain amount of time, independent of the cycle time. The interrupt timer consists of two 16-bit counters that are internally cascaded and driven from a fixed 2-MHz clock. The counters are programmed in Bytes 20–23 of the TYPE Table, or can be programmed as an initial condition (“Initial Conditions” below). The interrupt timer always counts down. When it reaches zero, it generates an interrupt pulse at its output, and is reset to the value programmed in the TYPE Table.

The interrupt operand enables the interrupt timer to generate an interrupt.

INTEN Enables interrupts: allows interrupts to occur during this microinstruction.NOINT Disables interrupts: no interrupt will occur during this microinstruction. If

no interrupt operand is specified, this is the default: no interrupts.INTADR Disables interrupts and changes interrupt address: loads the interrupt address

from microdata (UDATA) bits 0–7; also ignores interrupts.INTENADR Enables interrupts and changes interrupt address: loads the interrupt address

from microdata bits 0–7; also allows interrupts to occur during this microinstruction.

The timer operand enables the interrupt timer to count down or resets it to the programmed value.


TIMEN Enables timer to count down. If this operand is used anywhere in the first 4 machine cycles in a pattern program, the timer will begin counting down as the pattern is stepped through the pipelines at the computer’s rate (rather than the tester’s), resulting in an inaccurate timeout for the first interrupt.

RSTTMR Resets the timer to its programmed value. If no timer operand is specified, this is the default, and the timer is held inactive.

When an interrupt occurs, the pattern program address that would have been executed next is pushed onto the MAR’s address stack. The address in the interrupt address register becomes the current pattern program address. Upon completion of the interrupt routine, the stack is popped and the MAR address popped off is executed. The program continues from the address where the interrupt occurred. Only one push (or pop) on the stack is allowed in any cycle, so an interrupt cannot be serviced in the same cycle as another stack operation. If an interrupt occurs during the execution of a microinstruction in which the stack is pushed or popped, the interrupt is serviced in the next available cycle. Unserviced interrupts are held until the next cycle with no conflicting stack operations. Thus multiple calls can be serviced without losing the interrupt.

The CHIPS Statement. There are five chip select signals that control the operation of the DUT. The CHIPS statement selects or changes the polarity of these.

The CHIPS statement takes the following form:CHIPS chip-select-control, miscellaneous

If no chip selects are to be set and no other functions are required, use the following statement instead:

CHIPS NOCLKS

CHIPS “chip-select-control” Operand. These operands control the state of the chip selects during the microinstruction cycle. Each operand defines the state of one of the five chip selects. In these descriptions, “n” refers to a chip select by number. Up to five chip-select-control operands can be included in each CHIPS statement: any or all of the chip selects can be enabled in a single microinstruction. (Chip select true and false (active and inactive) are defined to be logic high or logic low in Byte 4 of the TYPE Table.)

CSnT Sets chip select n DC-true (active) for a full cycle.CSnF Sets chip select n DC-false (inactive) for a full cycle.CSnPT Pulses chip select n true. When set to pulse true, a Chip Select will be true

only after the start edge of its corresponding timing channel and will go false after the stop edge.

CSnPF Pulses chip select n false. When set to pulse false, a Chip Select will be false only after the start edge of its corresponding timing channel and will go true after the stop edge.

NOCLKS Sets all chip selects DC false.


The following operands are available for testing DRAMs.

WRITE Pulses chip select 1 true, setting up the part to write data to the memory. RAS Pulses chip select 2 true, setting up the next address as a row address.CAS Pulses chip select 3 true, setting up the next address as a column address.

The following operands are available when chip selects 1–4 are configured in Byte 4 of the TYPE Table to receive data from the DUT. In these descriptions, “n” is a number from 1 to 4.

CSnHIZ Tri-states chip select n.CSnRDT Read true data from chip select n.CSnRDF Reads false data from chip select n.

CHIPS “miscellaneous” Operands. Each CHIPS statement can include up to four miscellaneous operands.

LBDATA Sends bits 0–2 of the Microdata Field (UDATA) to the load board.RESET Resets the ERROR line.VPULSE Forces the HVM (High Voltage Module) pulse to its high state for the entire

cycle.ADHIZ Tri-states the address/data PE channels as specified in Byte 16 of the TYPE

Table.

The DATGEN Statement. The DATGEN statement controls the operation of the data generator. The data generator consists of an eight-bit data register, which can be configured, via Byte 15 of the TYPE Table, as one eight-bit byte register or two four-bit “nibble” registers. When configured in two four-bit nibbles, data can be driven continuously on the lower data field and received continuously on the upper data field. The TYPE Table also specifies which data output channels are strobed. The data register is initially loaded by either an initial condition statement (see “Initial Conditions” below) or through the Microdata Field (UDATA).

The DATGEN statement takes the following form:DATGEN datareg, yindex, equality, bckgnd, invertsense, dataout, udatajam

The DATGEN statement can generate three levels of inversion: from the equality function (equality operand), the background function (bckgnd operand), and the invert sense function (invertsense operand). Byte 19 of the TYPE Table can enable a fourth level of data inversion called “Bit 2 inversion,” which allows for the unconditional inversion of the data based on the address specified in Byte 18 in the Type Table. Bit 2 inversion can only be enabled via Byte 19 of the TYPE Table and is not affected by the DATGEN statement.

DATGEN “datareg” Operand. This operand controls the operation of the data register function.


CNTUPDR Counts up: increments the data register by one.CNTDNDR Counts down: decrements the data register by one.HOLDDR Holds data register at its present value; no action. If no datareg operand is

specified, this is the default.CMPLDR Complements the value in the data register.UDATADR Loads the value of bits 12–19 of the Microdata Field (UDATA) into the data

register.ROTRDR Rotates the data register right. The least significant bit replaces the most

significant bit and all other bits shift right. If the data register is configured as two 4-bit nibbles, a 4-bit rotate is performed on each 4 bit nibble.

ROTLDR Rotates the data register left—the inverse of the ROTRDR command. The most significant bit replaces the least significant bit and all the other bits shift left.

SHRDR Shifts the data register right and replaces the shifted bit with the fill bit. (The fill bit can be set as an initial condition (see “Initial Conditions” below), or from the Microdata Field (bit 20). The fill bit is displayed in Byte 2BH of the STATUS Buffer.) Complementing the data register complements the fill bit.

SHLDR Shifts the data register left and replaces the shifted bit with the fill bit. Complementing the data register complements the fill bit.

DATGEN “yindex” Operand. Controls the Y index functions for diagonal generation. The Y index register is used exclusively with the data equality functions XEQYPN and XEQYBPN (see “DATGEN ‘equality’ Operand,” below) to generate diagonals, as follows: the Y address value is added to the value in the Y index register; when the X address value equals this result, an inversion on the data-out is generated. The Y index value can be used to shift diagonal patterns right or left.

CNTUPYN “Count up Y index”: increments the Y index register by one every cycle (Y index = Y index + 1); used to shift diagonal patterns one position to the left.

CNTDNYN “Count down Y index”: decrements the Y index register by one every cycle (Y index = Y index-1); used to shift diagonal patterns one position to the right.

UDATAYN “UDATA to Y index”: loads the Y index register with the value in bits 8-15 of the Microdata Field (UDATA); used to shift diagonal patterns a specified number of columns.

HOLDYN No action; holds the Y index register fixed at its present value. If no yindex operand is specified, this is the default.

DATGEN “equality” Operand. Controls the data equality functions. The data specified by the dataout operand can be inverted conditionally as a function of the address generated that cycle. The following equality functions generate an inversion based on the XMAIN, YMAIN or AMAIN registers being equal, greater than, or less than another specified address register. In these descriptions, AMAIN is the address specified by the XMAIN and YMAIN registers, ABASE is the address specified by the XBASE and YBASE registers, and the “fast axis” is the least significant address axis (X or Y)—that


is, the address that is changing most rapidly. (The fast axis is important when testing dynamic RAMs, which must be refreshed to maintain proper operation.)

XYEQB Inverts a single address when AMAIN equals ABASE.YEQB Inverts an entire column when YMAIN equals YBASE.XEQB Inverts an entire row when XMAIN equals XBASE.YEQBORF Inverts an entire column when YMAIN equals either YBASE or YFIELD. If

YBASE equals YFIELD, one column is inverted; if YBASE does not equal YFIELD, two columns are inverted.

XEQBORF Inverts an entire row when XMAIN equals either XBASE or XFIELD. If XBASE equals XFIELD, one row is inverted; if XBASE does not equal XFIELD, two columns are inverted.

YLTB Inverts an entire column when YMAIN is less than YBASE. Writes a vertical section of data in the array up to but excluding YBASE.

XLTB Inverts an entire row when XMAIN is less than XBASE. Writes a horizontal section of data in the array up to but excluding XBASE.

YLEB Inverts an entire column when YMAIN is less than or equal to YBASE. Writes a vertical section of data in the array up to and including YBASE.

XLEB Inverts an entire row when XMAIN is less than or equal to XBASE. Writes a horizontal section of data in the array up to and including XBASE.

XYLTBYF Inverts a single address when AMAIN is less than ABASE, with the Y axis selected as the fast axis.

XYLEBYF Inverts a single address when AMAIN is less than or equal to ABASE, with the Y axis selected as the fast axis.

XYLTBXF Inverts a single address when AMAIN is less than ABASE, with the X axis selected as the fast axis.

XYLEBXF Inverts a single address when AMAIN is less than or equal to ABASE, with the X axis selected as the fast axis.

XEQYPN “X equals Y plus index”: inverts the data when the X address equals the Y address plus the Y index. This generates a left-to-right “barber-pole” diagonal.

XEQYBPN “X equals Y-bar plus index”: inverts the data when the X address equals the Y-bar address plus the Y index. This generates a right-to-left “barber-pole” diagonal.

EQFDIS Disables the data inversion from the equality function. If no equality operand is specified, this is the default.

DATGEN “bckgnd” Operand. Enables operation of the background function, a logic-parity function that conditionally inverts the data register output on a selected address bit(s).

In the TYPE Table, Bytes 17 and 18 select a Y and/or X address bit to be used with Byte 19, which selects logic-parity functions to operate on these two addresses. The result is a background data pattern. For example, selecting the Y0 and X0 bits and XORing them together produces a checkerboard pattern, regardless of the addressing sequence. The


background function operands can also involve topological data scrambling as specified by the Data Topological Scramble Buffer.

BCKFEN Enables the background function selected in Bytes 17, 18, and 19 of the TYPE Table.

DTOPO Enables the data topological scramble function, and disables the background function.

BCKDTOPO Enables both data topological scramble and background functions.BCKFDIS Disables the background function. If no bckfunc operand is selected, this is

the default.

DATGEN “invertsense” Operand. Unconditionally inverts the sense of the data register. Enabling this function inverts the data to the DUT regardless of the address.

INVSNS Inverts the sense of the data register output.NOTINV Disables the invert sense function. If no invertsense operand is specified,

this is the default.XORINV XORs the output of the data register with the contents of the Microdata

Field.

DATGEN “dataout” Operand. Specifies the sources of the data to the DUT for the high and low data channels. If no dataout operand is specified, the default is DATDAT.

D8–D15 (Data High) D0–D7 (Data Low)

DATDAT data register data registerDATJAM data register jam register DATBUF data register buffer memory 0-7JAMDAT jam register data registerJAMJAM jam register jam register 0-7JAMBUF jam register buffer memory 0-7BUFDAT buffer memory 8-15 data registerBUFJAM buffer memory 8-15 jam register 0-7BUFBUF buffer memory 8-15 buffer memory

DATGEN “udatajam” Operand. Loads the jam register from the Microdata Field (UDATA). If no udatajam operand is specified, the jam register is unchanged.

UDATAJAM Loads jam register from bits 0–15 of the Microdata Field.[nothing] Leave jam register unchanged.

The UDATA Statement. The UDATA statement loads the 24-bit “Microdata Field,” which is used by other microcode statements (YALU, XALU, COUNT, MAR, CHIPS,


and DATGEN) for data inputs, register loading inputs, interrupt addresses, and control data inputs, as follows:

Statement Operand Microdata Field Bit Positions

YALU YUDATA 0–10

XALU XUDATA 12–23

COUNT COUNTUDATA 0–23RELOADA 0–23RELOADB 0–23RELOADC 0–23RELOADD 0–23RELOADE 0–23

MAR INTADR 0–7INTENADR 0–7

CHIPS LBDATA 0–2

DATGEN UDATADR 12–20UDATAYN 0–7XORINV 0–15UDATAJAM 0–15

The UDATA statement takes the form:UDATA n

The single operand, n, is a hexadecimal value in the range 0 to .FFFFFF.

Initial Conditions. The pattern generator registers may be initialized to specified values before pattern execution begins, before the first microinstruction. A five-level expression stack is used to load the initial conditions into the registers. Once the registers to be initialized are specified, the stack operations are generated with the expression stack commands. The initial value is pushed onto the stack, operated on and popped into the specified register.

There are four types of initial condition statements: “register” statements, PUSH statements, “operation” statements, and POP statements.

Note: It is unnecessary to precede initial condition statements with a @ character. If used, the @ character is ignored by the PC-Host.

Initial Condition “Register” Statements. The following statements specify a register to be initialized.

YMAINXMAIN

Initializes the specified address register.


YBASEXBASEYFIELDXFIELDAMAINABASEAFIELD

Initializes the specified XY address register.

ACOUNTBCOUNTCCOUNTDCOUNTECOUNT

Initializes the specified loop counter.

ARELOADBRELOADCRELOADDRELOADERELOAD

Initializes the reload register for the specified loop counter.

JAMREG Initializes the jam register.DATREG Initializes the data register.YINDEX Initializes the Y index register.BCKBITS Initializes the background data generator address select bits.BCKFUN Initializes the background data generator function.INTADR Initializes the start address of an interrupt routine.STKPTR Initializes the stack pointer location.TIME0 Initializes the divide-by-n value in interrupt timer counter 0.TIME1 Initializes the divide-by-n value in interrupt timer counter 1.FBIN n Initializes the specified functional bin (where n is in the range 1–126).

Initial Condition PUSH and POP Statements. The PUSH statement puts a specified value onto the stack; the POP statement pops a value from the top of the stack into the specified register. The PUSH statement takes the following form:

PUSH value

where value is one of the following:

VALUE, n Where n is a value in the range 0–.FFFFFF (0–16,777,215).AMAX Maximum memory address as specified in the TYPE Table.YMAX Maximum Y address as specified in the TYPE Table.XMAX Maximum X address as specified in the TYPE Table.NUMXBITS The number of X address bits, defined in TYPE Table.NUMYBITS The number of Y address bits, defined in TYPE Table.FBIN m The contents of Functional Bin m.

The following example loads the value XMAX into the XBASE address register:XBASE


PUSH XMAXPOP

Initial Condition “Operation” Statements. Operation statements operate on the values in the stack.

PLUS Adds the top two levels of the expression stack and leaves the result on the top of the stack.

MINUS Subtracts the second level of the stack from the top level and leaves the result on the top of the stack.

SHLEFT n Shifts the value on the top of the stack left n times. This effectively multiplies the value on the top of the stack by 2n.

SHRIGHT n Shifts the value on the top of the stack right n times. This effectively divides the value on the top of the stack by 2n.

AND Logical-ANDs the top two levels of the stack and leaves the result on the top of the stack.

OR Logical-ORs the top two levels of the stack and leaves the result on the top of the stack.

XOR Logical-XORs the top two levels of the stack and leaves the result on the top of the stack.

The following example pushes the value in YMAX onto the stack, then pushes the value 2 onto the stack, then adds them together and pops the result off the stack and into the YBASE register:YBASE

PUSH YMAXPUSH VALUE, 2PLUS


POP

The URAMSTART Statement. Every pattern program must contain a URAMSTART statement to specify the address in the microRAM at which to start loading microinstructions. URAMSTART takes the following form:

URAMSTART n

where n is a value in the range 0–255 (or a literal with an assigned value in that range).

When a pattern is executed with a PGOFFSET command, the argument to PGOFFSET should be the same value as the argument to the URAMSTART statement.

Microinstruction Bit Description. Following is a byte-by-byte description of the 19 bytes that make up each microinstruction. In each byte diagram, the MSB (most significant bit) is at the left, and the LSB (least significant bit) is at the right:

MSB LSB

Microinstruction Byte 0Bits 5–7: X to Y Carry Bit 4: Invert

CarryBits 2–3: Y ALU Input B Bits 0–1: Y ALU Input A

000 = carry if XBASE = max001 = carry if XBASE<> min010 = carry if XFIELD = max011 = carry if XFIELD <> min100 = carry if XMAIN = max101 = carry if XMAIN <> min110 = force carry on111 = force carry off

0 = invert1 = don't invert

00 = YBASE01 = YFIELD10 = YMAIN11 = low microdata

00 = YBASE01 = YFIELD10 = YMAIN11 = low microdata

Microinstruction Byte 1Bits 5–7: Y Destination Enable Bits 0–4: Y ALU Function

YMAIN YFIELD YBASE S3 S2 S1 S0 M

Microinstruction Byte 2Bits 5–7: Y to X Carry Bit 4: Invert

CarryBits 2–3: X ALU Input B Bits 0–1: X ALU Input A

000 = carry if YBASE = max001 = carry if YBASE<> min010 = carry if YFIELD = max011 = carry if YFIELD <> min100 = carry if YMAIN = max101 = carry if YMAIN <> min110 = force carry on111 = force carry off

0 = invert1 = don’t invert

00 = XBASE01 = XFIELD10 = XMAIN11 = low microdata

00 = XBASE01 = XFIELD10 = XMAIN11 = low microdata

Microinstruction Byte 3Bits 5–7: X Destination Enable Bits 0–4: X ALU function

XMAIN XFIELD XBASE S3 S2 S1 S0 M


Microinstruction Byte 40 0 Bits 3–5: X Output Register Bits 0–2: Y Output Register

spare XMAIN XFIELD XBASE YMAIN YFIELD YBASE

Microinstruction Byte 5Bit 7: Reload

Register0 Bits 0–5: Counter Comparator Source

0 = don’t load reload register

1 = load reload register from UDATA

not used microdata\ E D C B A

Default: 0

Microinstruction Byte 6Bits 6–7: Counter Function Bits 0–5: Counter Destination Enable

00 = hold

01 = increment

10 = decrement by 2

11 = decrement

Auto reload\.

0 = reload if selected COUNTER = 0

1 = don’t autoreload

E D C B A

Default: 00

Microinstruction Byte 7

MAR jump/call address

Microinstruction Byte 80 Bit 6:

Interrupt enable

Bit 2: Condition\

Bit 1: Z/E\ Bit 0: NE/EQ\

not used. 0 = disallow pattern interrupts

1 = allow interrupts in pattern

011 = return in microprogram

101 = subroutine call

110 = jump in microprogram

111 = increment

0 = conditional action

1 = uncondition-al action

0 = condition is error

1 = condition is counter = 0

0 = condition is =

1 = condition is ¹

Default: 0 Default: 0


Microinstruction Byte 90 Bit 6: Over/

under- program-

ming

Bit 5: Over/ under enable

Bit 4: Read (strobe data)

Bit 3: Interrupt address change

Bit 2: Pattern

complete\ (done)

Bit 1: Reset interrupt

timer\

0

not used 0 = underprogramming check

1 = overprogramming check

0 = disabled

1 = enabled

0 = read inactive

1 = read (strobe)

0 = don’t change interrupt address

1 = load microdata 0-7 as new interrupt address

0 = complete

1 = not complete

0 = reset timer

1 = allow timer to count

not used

Default: 0 Default: 0 Default: 0 Default: 1 Default: 0

Microinstruction Byte 10Bits 4–7: Chip Select 2 Bits 0–3: Chip Select 1

READ; Strobe on

CS. Expect data

derivedfrom

polarity select

HIZ; CS pin electronics

channel drive/ receive

control.

POL TE READ; Strobe on

CS. Expect data derived from polarity

select

HIZ; CS pin electronics

channel drive/

receive control.

POL TE

0 = strobe PES\ with associated TG (read)

1 = no strobe (associated TG is DC high)

0 = active state (pulse associated TG on PEE\)

1 = inactive state (associated TG is DC high)

POL TE

0 0 = hold false (drive or expect)

0 1 = pulse true

1 0 = hold true(drive or expect)

1 1 = pulse false

0 = strobe PES\ with associated TG (read)

1 = no strobe (associated TG is DC high)

0 = active state (pulse associated TG on PEE\)

1 = inactive state (associated TG is DC high)

POL TE

0 0 = hold false (drive or expect)

0 1 = pulse true

1 0 = hold true(drive or expect)

1 1 = pulse false

Default: 1 Default: 1 Default: 1 Default: 1

Microinstruction Byte 11Bits 4–7: Chip Select 4 Bits 0–3: Chip Select 5

HIZ\ READ\ POL TE READ\ HIZ\ POL TE


Microinstruction Byte 12Bit 7:

Address and data channel drive/receive

control

Bit 6: LBDATA

Bit 5: Reset errors\

Bit 4: VPULSE

0 0 Bit 1:CS5: TE

Bit 0:CS5: POL

0 = data/address PEE\ TG (TG14) is DC high

1 = data/address PEE\ TG (TG14) is pulsing

0 = don’t write load board data bits

1 = write load board data bits

0 = reset the Q2 error line

1 = don’t reset errors

0 = HVM in low state

1 = HVM voltage in high state

not used

Default: 0 Default: 0 Default: 1 Default: 0

Microinstruction Byte 13Bits 6–7: Y index operation Bits 4–5: Data register

operationBit 3:

UDATAJAM\Bit 2:

Shift/rotate\Bits 0–1: Background

function

00 = count down

01 = count up

10 = hold

11 = load microdata

00 = count down

01 = count up

10 = hold

11 = load: microdata, complement, shift, rotate

0 = load JAM register from microdata 0-5

1 = don’t load JAM register

0 = rotate1 = shift

00 = enable background function

01 = disable functions

10 = enable BCKGND and DTOPO

11 = enable DTOPO INVERT

Default: 10. Default: 10. Default: 1. Default: 01.

Microinstruction Byte 14Bit 4–7: Equality function select. Bit 3:

Forced inversion function

Bit 2: Forced

inversion function

Bits 0–1:Data register load function

0000 = Disable equality function0001 = AMAIN = ABASE0010 = YMAIN = YBASE0011 = XMAIN = XBASE0100 = YMAIN = YBASE or YFIELD0101 = XMAIN = XBASE or XFIELD0110 = XOUT = YOUT plus INDEX0111 = XOUT = YOUT\ plus INDEX1000 = YMAIN < YBASE1001 = YMAIN £ YBASE1010 = XMAIN < XBASE1011 = XMAIN £ XBASE1100 = AMAIN < ABASE, YFAST1101 = AMAIN £ ABASE, YFAST1110 = AMAIN < ABASE, XFAST1111 = AMAIN £ ABASE, XFAST

XOR microdata with data out (XORINV):

0 = disable XOR function1 = enable XOR with microdata 0–15

Invert sense of data generator:

0 = no effect1 = invert sense

00 = shift; rotate right01 = shift; rotate left10 = load complement11 = load microdata

Default: 0000. Default: 0. Default: 0.


Microinstruction Byte 150 0 0 0 Bits 2–3: Data high output Bit1 0–1: Data low output

not used. 00 = data register output01 = JAM register output10 = data buffer memory out

00 = data register output01 = JAM register output10 = data buffer memory out

Default: 00. Default: 00.

Microinstruction Byte 16µdata 7 µdata 6 µdata 5 µdata 4 µdata 3 µdata 2 µdata 1 µdata 0

Microdata Field (UDATA), low byte.


Microdata Field (UDATA), middle byte.


Microdata Field (UDATA), high byte.

Q2/52 Bit Map Commands

The following PGM commands provide access to the Q2/52’s bit map graphics capability.

BITMAP Produces bit map of a part.BSRINIT n Initializes X and Y scramble RAMs. BSRLOAD Loads X and Y scramble RAMs.CBAR n Creates color bar with n colors.CBXPND n, n Expands color bar.CCAL Calibrates cursor.ALLERR n Counts ECR errors to FBINn.ERRCOUNT n Counts ECR errors to FBINn.ENDLEX Ends Lexidata; used after QTOLEX.HOME Sets display to home position.HTOLEX Connects PDP-11 to Lexidata.ISOLATE ONLY, n Displays only color n.ISOLATE NOT, n Displays all colors except n.ISOLATE LT, n Displays colors less than n.ISOLATE GT, n Displays colors greater than n.JOYSTICK Enables joystick interaction.LEX2FB m, n, ... Sends bit map data to FBINm, FBINn,..LLOAD Sends PLOAD signal to bit map.LSTART Resets bit map controller.


LUTDUMP Dumps color look-up table.LUTLOAD Loads color look-up table.MAPCOMMOFF Turns off bit map communication.MAPDUMP n, n, n, n, n Dumps error catch to bit map. MMINIT Initializes mode map.MMVALUE m, n Sets mode map m to n.MVINIT Initializes bit map display.P2HOST Connects PGM to PDP-11.PTOLEX Connects PGM to bit map display.QTOLEX Sends commands to bit map.

Q2/52 Reference: PGM Registers

FBINn Functional bin n; may be abbreviated n.CBINn Column bin n (0 to 63).RBINn Row bin n (0 to 63).CURMAR Current microRAM address register.MARSEGMENT MicroRAM address register segment.INTADR Interrupt address.STKPTR Stack pointer. RETADR Return address. ACOUNT A counter register.BCOUNT B counter register.CCOUNT C counter register.DCOUNT D counter register.ECOUNT E counter register.ARELOAD A counter reload register.BRELOAD B counter reload register.CRELOAD C counter reload register.DRELOAD D counter reload register.ERELOAD E counter reload register.YOUT Y address generator output.XOUT X address generator output.YMAIN Y main register.XMAIN X main register.YBASE Y base register.XBASE X base register.YFIELD Y field register.XFIELD X field register.DATREG Data register.


JAMREG JAM register.DATBUF Data buffer memory.YINDEX Y index register.DATGEN Data generator output.LBDATA Load board data.ERRADR Error address, unscrambled.SERRADR Scrambled error address.EXPECTDATA Error expect data.ACTUALDATA Actual data.ERRMAR Error micro-RAM address register.PREVADR Previous address, unscrambled.SPREVADR Scrambled previous address.PREVDATA Previous data.PREVMAR Previous micro-RAM address register.DUTADR DUT address, unscrambled.SDUTADR Scrambled DUT address.DUTDATA DUT data.DUTMAR DUT micro-RAM address register.ROWCOUNT Row (X) error counter.COLCOUNT Column (Y) error counter.

Q2/52 Reference: PGM Tables

BUFFER Data buffer memory.PROGRAM Pattern program buffer.STATUS Status buffer—see “Q2/52 Reference: The STATUS Buffer.”TYPE Type table—see “Q2/52 Reference: The TYPE Table.”USER User buffer.XTOPO X address topological scramble table.YTOPO Y address topological scramble table.Q Q buffer.DTOPO Data topological scramble table.ROWCOL Row and column error catch buffer.ECR Error Catch RAM.REPAIR Repair table.XBMSCRAMBLE X bit map scramble table.YBMSCRAMBLE Y bit map scramble table.RED Red color look-up table.GREEN Green color look-up table.BLUE Blue color look-up table.


BITMAP Bit map parameter table.

Q2/52 Reference: The TYPE Table

The TYPE Table configures the PGM for a particular testing application. It is 37 bytes long, as follows:

Byte(s) Assignment

0 YMASK (low bits)1 YMASK (high bits)2 XMASK (low bits)3 XMASK (high bits)4 CS Drive Polarity5 CS1 Drive/Receive State6 CS2 Drive/Receive State7 CS3 Drive/Receive State8 CS4 Drive/Receive State9 Y Address Strobe Mask (low bits)10 Y Address Strobe Mask (high bits)11 X Address Strobe Mask (low bits)12 X Address Strobe Mask (high bits)13 Data Low Strobe Mask14 Data High Strobe Mask15 Device Status16 Address and Data Drive/Receive Configuration17 Background Data Generator Function Bit 1 Select18 Background Data Generator Function Bit 2 Select19 Background Data Generator Function20–23 Interrupt Timer24–29 Address Formatting30–36 Data Formatting

The following is a byte-by-byte description of the TYPE Table. In each byte diagram, the MSB (most significant bit) is at the left, and the LSB (least significant bit) is at the right:

MSB LSB

Byte 0: YMASK (low bits). Enables Y Address Generator bits (lines) Y0 to Y7.


Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

1 enables a bit; a 0 disables a bit. All enabled bits must be contiguous. Y0 must be enabled if Y Address Generator is used.

Byte 1: YMASK (high bits). Enables Y Address Generator bits Y8 to Y10.

0 0 0 0 0 Y10 Y9 Y8

not used 1 enables a bit; a 0 disables a bit. All enabled bits must be contiguous. In Mode 1, Y10 is normally disabled. In Mode 3, Y8, Y9, and Y10 are all normally disabled. See “Q2/52 Reference: Pin Electronics Modes.”

Byte 2: XMASK (low bits). Enables X Address Generator bits X0 to X7.

X7 X6 X5 X4 X3 X2 X1 X0

1 enables a bit; a 0 disables a bit. All enabled bits must be contiguous. X0 must be enabled if X Address Generator is used

Byte 3: XMASK (high bits). Enables X Address Generator bits X8 to X11.

0 0 0 0 X11 X10 X9 X8

not used 1 enables a bit; a 0 disables a bit. All enabled bits must be contiguous. In Mode 2, X11 must be disabled. See “Q2/52 Reference: Pin Electronics Modes.”


Byte 4: CS DRIVE POLARITY. Sets the Chip Select Drive polarities.

CSnB strobe enable

CSnA strobe enable

0 CS5 CS4 CS3 CS2 CS1

1 = CS strobes on A Chip Select PE channels enabled.

0 = disabled.

Only pertains to Modes 1 & 2; Mode 3 has no B Chip Selects.

1 = CS strobes enabled on A Chip Select PE channels

0 = disabled.

not used 1 = CS Drive to be active at logic high;0 = CS Drive to be active at logic low.

See “Q2/52 Reference: Pin Electronics Modes.”

Byte 5: CS1 DRIVE/RECEIVE STATE. Determines Chip Select 1 Drive/Receive State.

Bits 6–7: CS1 strobe select Bit 5: CS1 expect data true polarity

Bits 0–4: CS1 I/O control select.

0 = Disable strobing on CS11 = Enable strobing on CS12 = Timing generator 23 = Timing generator 34 = Timing generator 45 = Timing generator 56 = Timing generator 117 = Timing generator 12

0 = Expect (read) true is active low1 = Expect (read) true is active high

0 = Drive continuously1 = Tri-state for the entire cycle2 = Tri-state between START 2 and STOP 23 = Tri-state between START3 and STOP34 = Tri-state between START4 and STOP45 = Tri-state between START5 and STOP56 = Tri-state between START11 and STOP117 = Tri-state between START12 and STOP128 = Receive continuously9 = Drive for the entire cycle10 = Drive between START2 and STOP211 = Drive between START3 and STOP312 = Drive between START4 and STOP413 = Drive between START5 and STOP514 = Drive between START11 and STOP1115 = Drive between START12 and STOP12

The default Drive/Receive state of CS1 can be configured to be either normally Drive or normally Receive.

· In the normally Drive state (codes 0-7), the PE channel is set to the Receive (Tri-state) state between the start and stop edges of the indicated TG in cycles containing a CS1RDT, CS1RDF, or CS1HIZ mnemonic in the CHIPS statement of the pattern program.

· In the normally Receive state (codes 8-15), the PE channel is set to the Drive state between the start and stop edges of the indicated TG in cycles containing a CS1T, CS1F, CS1PT, or CS1PF mnemonic and remains in the Receive state in cycles containing a CS1RDT, CS1RDF, or CS1HIZ mnemonic.

Strobing on CS1 is invoked with a CS1RDT or CS1RDF mnemonic in a pattern program, with true/false Expect Data set above. During a CS1 read, the CS1 Pin Electronics channel is set to the Receive (Tri-state) state based on the CS1 I/O control bits described above. The strobe is active between the start and stop edges of the selected timing generator when using codes 2–7 in bits 5, 6, and 7.

CAUTION: Care should be taken to ensure that the start edge of each Timing Generator is programmed before (in front of) its corresponding stop edge. Otherwise, the polarity of the cycle may be opposite to what is expected.











Strobing on CS2 is invoked with a CS2RDT or CS2RDF mnemonic in a pattern program with true/false Expect Data set above. During a CS2 read, the CS2 Pin Electronics channel is set to the Receive (Tri-state) state based on the CS2 I/O control bits described above. The strobe is active between the start and stop edges of the selected timing generator when using codes 2–7 in bits 5, 6, and 7.

CAUTION: Care should be taken to ensure that the start edge of each Timing Generator is programmed before (in front of) its corresponding stop edge. Otherwise, the polarity of the cycle may be opposite to what is expected.











Strobing on CS3 is invoked with a CS3RDT or CS3RDF mnemonic in a pattern program with true/false Expect Data set above. During a CS3 read, the CS3 PE channel is set to the Receive (Tri-state) state based on the CS3 I/O control bits described above. The strobe is active between the start and stop edges of the selected timing generator when using codes 2–7 in bits 5, 6, and 7.

NOTE: Care should be taken to ensure that the start edge of each Timing Generator is programmed before (in front of) its corresponding stop edge. Otherwise, the polarity of the cycle may be opposite to what is expected.









In the normally Drive state (codes 0-7), the PE channel is set to the Receive (Tri-state) state between the start and stop edges of the indicated TG in cycles containing a CS4RDT, CS4RDF, or CS4HIZ mnemonic in the CHIPS statement of the pattern program.

In the normally Receive state (codes 8-15), the PE channel is set to the Drive state between the start and stop edges of the indicated TG in cycles containing a CS4T, CS4F, CS4PT, or CS4PF mnemonic and remains in the Receive state in cycles containing a CS4RDT, CS4RDF, or CS4HIZ mnemonic.

Strobing on CS4 is invoked with a CS4RDT or CS4RDF mnemonic in a pattern program, with true/false Expect Data set above. During a CS4 read, the CS4 PE channel is set to Receive (Tri-state) state based on the CS4 I/O control bits described above. The strobe is active between the start and stop edges of the selected timing generator when using codes 2–7 in bits 5, 6, and 7, of Byte 8.

NOTE: Care should be taken to ensure that the start edge of each Timing Generator is programmed before (in front of) its corresponding stop edge. Otherwise, the polarity of the cycle may be opposite to what is expected.


Byte 9: Y ADDRESS STROBE MASK (low bits). Enables the error strobe for the PE channels of the lower eight Y address bits.

38-Y7-IO7 37-Y6-IO6 36-Y5-IO5 35-Y4-IO4 34-Y3-IO3 33-Y2-IO2 32-Y1-IO1 31-Y0-IO0

PE channel strobed - Mode 1 PE strobe function - Data-on-address mapped bit

(See “Q2/52 Reference: Pin Electronics Modes.”)

A 1 bit enables the error strobe for the corresponding data bit mapped on to the Y address bit. A 0 disables the error strobe for the corresponding data bit mapped on to the Y address bit.

Bytes 9–12 provide the capability to test devices configured with a data-on-address bus. For testing a device with separate pins for address and data, this byte should be assigned all zeroes. For testing a data-on-address device, the bits that correspond to data bits mapped on to address bits should be enabled.


Byte 10: Y ADDRESS STROBE MASK (high bits). Enables the error strobe for the PE channels of the upper two Y address bits.

0 0 Bit 5: Row Error Buffer function

select

Bit 4: Column Error Buffer function

select

0 0 29-Y9-IO9 30-Y8-IO8

not used 0 = Row Error Buffer records locations of rows where functional errors have been detected.

1 = Row Error Buffer masks data strobes at row addresses where the value stored in the buffer is a 0.

0 = Column Error Buffer records locations of columns where functional errors have been detected.

1 = Column Error Buffer masks data strobes at column addresses where the value stored in the buffer is a 0.

not used PE channel strobedMode 1 PE strobe functionData-on-address mapped bit


For the corresponding data bit mapped on to the Y address bit: 1 = enables error strobe; 0 = disables error strobe.

Bytes 9-12 allow testing of devices configured with a data-on-address bus. For testing a device with separate pins for address and data, these bits should be set to 0. For testing a data-on-address device, the bits that correspond to data bits mapped on to address bits should be enabled for strobing.


Byte 11: X ADDRESS STROBE MASK (low bits). Enables error strobe for the PE channels of the lower eight X address bits.

8-X7-IO8 7-X6-IO9 6-X5-IO10 5-X4-IO11 4-X3-IO12 3-X2-IO13 2-X1-IO14 1-X0-IO15

PE channel strobed - Mode 1 PE strobe function - Data-on-address mapped bit


For the corresponding data bit mapped onto the X address bit: 1 = enables error strobe; 0 = disables error strobe.

Bytes 9–12 provide the capability to test devices configured with a data-on-address bus. For testing a device with separate pins for address and data, this byte should be set to 0. For testing a data-on-address device, the bits that correspond to data bits mapped on to address bits should be enabled.


Byte 12: X ADDRESS STROBE MASK (high bits). Enables the error strobe for the PE channels of the upper four X address bits.

0 0 0 0 40-X11-IO4 39-X10-IO5 10-X9-IO6 9-X8-IO7

not used PE channel strobed - Mode 1 PE strobe function - Data-on-address mapped bit


For the corresponding data bit mapped onto the X address bit: 1 = enables error strobe; 0 = disables error strobe.

Bytes 9-12 provide the user with the ability to test devices configured with a data-on-address bus. For testing a device with separate pins for address and data, these bits should be set to 0. For testing a data-on-address device, the bits which correspond to data bits mapped on to address bits should be enabled for strobing.


Byte 13: DATA LOW STROBE MASK. Enables the error strobe for the lower eight DUT output data bits.

28-D7 27-D6 26-D5 25-D4 24-D3 23-D2 22-D1 21-D0

PE channel strobed - PE strobe function

For corresponding DUT output data bit: 1 = enables error strobe; 0 = disables error strobe.

Byte 14: DATA HIGH STROBE MASK. Enables the error strobe for the upper eight DUT output data bits.

20-D15 19-D14 18-D13 17-D12 16-D11 15-D10 30-D9 29-D8

PE channel strobed - PE strobe function, mode 3 only


For corresponding DUT output data bit: 1 = enables error strobe; 0 = disables error strobe.

This byte is needed for mode 3 only—Modes 1 and 2 are configured for a maximum of 8 DUT output data bits. For testing devices in modes 1 and 2, this byte should be set to all zeroes. See “Q2/52 Reference: Pin Electronics Modes.”

Byte 15: DEVICE STATUS.

Bit 7:PEA21-30

drive voltage rail

select

Bits 5–6: PGM mode (tester configuration) select

Bit 4: Fast (least

significant) axis *

Bit 3: NVM blank state

Bit 2: PE channel data I/O

type

Bit 1: Data register

word width

Bit 0: Data word width at DUT **

0 =PEA21-30 connected to VIH1/VIL1

1 =PEA21-30 connected to VIH2/VIL2

0 = Mode 1(12X, 10Y, 8 data, 5 Chip Selects)

1 = Mode 2(2 times 11X on Y, 4D, 5CS)

2 = Mode 3(12X, 8Y, 16 data, 4 Chip Selects)

See “Q2/52 Reference: Pin Electronics Modes.”

0 = Y is fast axis

1 = X is fast axis

0 = Blank state is 0

1 = Blank state is 1

If DUT is not an NVM, set this bit to 0.

0 = Separate I/O data

1 = Common I/O data

0 = Two4-bit-wide words

1 = One8-bit-wide word

0 = 1 to 8 bits wide

1 = 9 to 16 bits wide

* Used to display address information correctly and when loading registers with a SETADDRESS command or a full address initial condition (AMAIN, ABASE, AFIELD).

** If the tester mode is changed after the X or Y topo data is loaded, the data must be reloaded because the PGM OS Release 3.0 or above relinearizes the X and Y topo RAMs after the tester mode is changed.

Byte 16: ADDRESS AND DATA DRIVE/RECEIVE CONFIGURATION. This byte, in conjunction with the ADHIZ mnemonic used in the CHIPS statement in the pattern microcode, controls the Drive/Receive state of address and data PE channels. In these descriptions, “Receive” means that the Driver is off and the tester output on these lines is tri-stated. Strobing of the outputs, if desired, is controlled separately.

Bit 7:Shorts tests

Bits 4–6: Data drive/receive select 0 Bit 2: Expect data polarity

(common I/O)

Bits 0–1: Address drive/receive select

0 = Normal 000 = Receive continuously. Data drivers are not 0 = Formatted 00 = Drive continuously.


testing mode

1 = Force all PE channels specified in USED-CHANNEL list into the Drive mode. This is used when performing a shorts test on the DUT.

never enabled. ADHIZ and the START14 and STOP14 edges have no effect on these lines. This setting is usually used for ROM testing.

001 = Receive between START14 and STOP14. Data lines default to a Drive state. In cycles using the ADHIZ, data lines are tri-stated between START14 and STOP14.

010 = Drive between START14 and STOP14. Data lines default to tri-state. In cycles using ADHIZ, data lines are in Drive mode between START14 and STOP14. Note that in this case, ADHIZ actually selects Drive state, not Hi-Z or tri-state.

011 = Receive for the entire cycle. These data lines Receive (tri-state) for entire cycle if ADHIZ is used; otherwise, they Drive for the entire cycle. START14 and STOP14 do not affect the timing.

100 = ADHIZ has no effect. Drive on Drive Data Pin Electronics and Receive on Expect Data Pin Electronics.

101, 110, and 111 are invalid.

used data is unchanged

1 = On cycles containing a READ, force the data\ portion of the signal formatting to be data. Drive Data may be Surround-By-Complement while Expect Data is unformatted.

Address drivers are always enabled; ADHIZ and the START14 and STOP14 edges have no effect on these lines.

01 = Receive between START14 and STOP14. Address lines default to Drive state. In cycles using ADHIZ, address lines are tri-stated between START14 and STOP14.

10 = Drive between START14 and STOP14. Address lines default to tri-state. In cycles using ADHIZ, address lines are in Drive mode between START14 and STOP14. Note that in this case, ADHIZ actually selects Drive state, not Hi-Z or tri-state.

11 = Receive continuously. Address drivers are never enabled; ADHIZ and the START14 and STOP14 edges have no effect on these lines.

Byte 17: BACKGROUND DATA GENERATOR FUNCTION BIT 1 SELECT.

0 0 0 Bits 0–4: First of two address bits for data generator background functions.

not used 0–10 = Y0 through Y10; 12–23 = X0 through X11

Byte 18: BACKGROUND DATA GENERATOR FUNCTION BIT 2 SELECT.

0 0 0 Bits 0–4: Second of two address bits for data generator background functions.

not used 0–10 = Y0 through Y10; 12–23 = X0 through X11

Byte 19: BACKGROUND DATA GENERATOR FUNCTION. The background data function of the data generator uses the addresses selected in Bytes 17 and 18, and the function selected in Byte 19, to generate an inversion on the output of the data register. All of the background functions controlled in Byte 19 except the Bit 2 function enable are enabled on-the-fly via the DATGEN statement of a pattern program.


Bit 7:“Bit 2”

function enable

Bit 6: Data topological scramble

table function select

Bit 5:Invert Bit 2

Bit 4:Invert Bit 1

Bit 3: Parity Bits 0-2: Background Function Select

0 = Disable inversion of data register output on address selected in Bit 2 (Byte 18).

1 = Enable inversion of data register output on address selected in Bit 2 (Byte 18).

0 = Invert data on X address AND Y address.

1 = Invert data on X address XOR Y address.

Topological inversion of data is enabled on-the-fly via DTOPO mnemonic in the DATGEN statement of a pattern.

0 = Do not invert if Bit 2 condition is true.

1 = Invert if Bit 2 condition is true

0 = Do not invert if Bit 1 condition is true.

1 = Invert if Bit 1 condition is true

0 = Invert if even parity.

1 = Invert if odd parity.

Parity functions are satisfied whenever the sum of the bits that are set in the selected address register is odd or even.

0 = Force data inversion for all addresses.

1 = Invert if Bit 1 (Byte 17) is true.

2 = Invert if Bit 1 (Byte 17) AND Bit 2 (Byte 18) is true.

3 = Invert if Bit 1 (Byte 17) OR Bit 2 (Byte 18) is true.

4 = Invert if Bit 1 (Byte 17) XOR Bit 2 (Byte 18) is true.

5 = Invert when parity of the Y address matches parity* selected in Bit 3.

6 = Invert when parity of the X address matches parity* selected in Bit 3.

7 = Invert when parity of the X and Y addresses matches parity* selected in Bit 3.

* Parity is generated on the unscrambled addresses.

Bytes 20-23: INTERRUPT TIMER. The real-time programmable interrupt timer consists of two 16-bit counters that are internally cascaded and driven from a fixed 2-MHz clock. The values assigned in TYPE Table Bytes 20-23 are loaded into the indicated portion of the counter, as follows:

Interrupt Timer 1 Interrupt Timer 0

MSB LSB MSB LSB

Byte 23 Byte 22 Byte 21 Byte 20

The minimum values for programming are 2 microseconds for Timer 0 and 4 microseconds for Timer 1. The maximum value for either timer is 65535. The actual delay is based on both timers, as follows:

Timer 0 value Real time programmed delay (in microseconds)

2 Timer 1 value4 2 x Timer 1 value8 4 x Timer 1 value

etc. etc.

When programming small interrupt time intervals (£ 25 microseconds), you should actually measure the time on a scope and compare it to the programmed value. As the intervals become smaller the accuracy decreases. This is because the interrupt timer runs asynchronously to the pattern cycle time and there is always a delay of at least one


pattern program cycle for interrupt setup time. For the correct timeout while the patterns are initialized in the PGM pipelines, the interrupt timer should not be enabled in the first three machine cycles of a pattern program.

The interrupt timer can also be programmed as an initial condition of a pattern program.

Bytes 24-29: ADDRESS FORMATTING. These six bytes enable the address formatting circuitry on the PGM. Each byte represents one edge of a timing generator, as follows:

leading / falling / START edge trailing / rising / STOP edge

TG1 Byte 24 (“START1”) Byte 27 (“STOP1”)



Each edge generates an address transition at the DUT address inputs at a programmed time. Each edge (byte) is enabled by one of the following byte codes:

0 = No change (ignore timing generator edge)1 = Address (for multiplexed address, ADDRESS implies Y address)2 = Address complement (for multiplexed address, ADDRESS implies Y address)3 = Zero (force a zero)4 = One (force a one)5 = X address multiplexed on Y PE channel (for Mode 2 only)6 = X complement on Y PE channel (for Mode 2 only)7 = Data on Address (for multiplexed data-on-address)8 = Data\ on Address (for multiplexed data-on-address)

See “Q2/52 Reference: Q2/52 Pin Electronics Modes” later in this section for information on channel assignments in Mode 2.

The START edge of TG1 executes the byte code in Byte 24 to be executed, regardless of the relative positions of any other edges. Similarly, the START edge of TG2 executes the code in Byte 25, etc.

Edges of Timing Generators 1, 2, and 3 that are used for address formatting should be programmed to occur in time as follows:


A byte code of 0 masks the associated edge in the timing generator. Edges not used for address formatting may therefore be placed out of the timing sequence shown above with no effect on the address formatting. If not used for address formatting, either TG2 or TG3 may be defined to determine a Chip Select’s Drive/Receive state, or to set a Chip Select’s formatting. (See Bytes 5 through 8.)

Note that the start of TG1 is automatically set at t=0 by the PGM when TRULES are invoked. See “BASIC PROGRAM COMPONENTS: Test Blocks: Additional Setup,” in this QTL Programming section for more information.

Bytes 30-33: DRIVE DATA FORMATTING. These four bytes enable the drive data formatting circuitry on the PGM. Each byte represents one edge of a timing generator, as follows:




Each edge generates a Drive Data transition at the DUT data pins at a programmed time. Each edge (byte) is enabled by one of the following byte codes:

0 = No change (ignore timing generator edge)1 = Data2 = Data Complement3 = Zero (force a zero)4 = One (force a one)

The START edge of TG4 executes the byte code in Byte 30, regardless of the positions of all other edges. Similarly, the start edge of TG5 executes the byte code in Byte 31, etc.

Edges of Timing Generators 4 and 5 that are used for Drive Data formatting should be programmed to occur in time as follows:

A byte code of 0 masks the associated edge in the timing generator. Bytes that correspond to timing generator edges not used for Drive Data formatting should be programmed with byte code 0.

A byte code of zero masks off the associated edge in the pattern generator. Therefore, edges not used in the Drive Data formatting may be placed out of timing sequence with


no effect on the Drive Data formatting. If not used for Drive Data formatting, either TG4 or TG5 can be used for Expect Data formatting, or can be assigned by the user to define a Chip Select's Drive/Receive state or to format a Chip Select. (See Bytes 5 through 8.)

Bytes 34–36: EXPECT DATA FORMATTING (Separate I/O Only). These three bytes enable the expect data formatting circuitry on the PGM. These edges need only be programmed for devices configured with separate I/O data; see Byte 16 for information on expect data formatting for devices configured with common I/O. Each byte represents one edge of a timing generator, as follows:


TG5 [See discussion of Drive Data Formatting, above.]

Byte 34 (“STOP5”) only if STOP5 isn't used for Drive Data. If STOP5 is used for Drive Data, set Byte 34 to 0 and

program STOP5 via Byte 33.]


For separate I/O data devices, Drive Data and Expect Data are transmitted on different pin electronics channels, so more edges are required. In addition, edges used to format Expect Data must occur before the strobe edge. Separate I/O Expect Data formatting is done in one of two ways:

1. If all 4 edges of TG4 and TG5 (Bytes 30-33) are used for formatting Drive Data, set Byte 34 to 0 and use Bytes 35 and 36 to control START14 and STOP14.

2. If STOP5 is not used to format Drive Data, then Expect Data can be formatted with three edges: STOP5, START14, and STOP14. This allows Expect Data to be formatted independently of Drive Data. (This is useful for such applications as nibble mode testing where two DUT cycles are to be simulated in one tester cycle.) In this case, set Byte 33 to 0 and control STOP5 with Byte 34.

Each edge generates an Expect Data transition at a programmed time. Each edge (byte) is enabled by one of the following byte codes:

0 = No change (ignore timing generator edge)1 = Data2 = Data Complement3 = Zero (force a zero)4 = One (force a one)

For common I/O data devices, the same pin electronics channels transmit Drive Data and receive Expect Data. START14 and STOP14 are provided to switch the data PE channels to and from the Drive and Receive states, as determined in Byte 16 of the TYPE Table. Bytes 35 and 36 should be programmed to 0 for testing common I/O data devices when using TG14 to switch between Drive and Receive.


Q2/52 Reference: The STATUS Buffer

The STATUS Buffer stores all PGM registers and counters. The STATUS Buffer can be modified via an INSERT command or interactively via a Q-Monitor EDIT command. Whenever a pattern single-step command (XPSTEP or XPNSTEP) is executed, the entire STATUS Buffer is updated from the data in the microprogrammed PGM. The STATUS Buffer is not updated when XSTEP or XPESTEP is executed.

The STATUS Buffer is not updated by normal execution of a pattern program. Thus, when pattern execution stops due to a failure, the STATUS Buffer may not contain valid information. To update the STATUS Buffer, use the interactive XPSTEP 0 command to update the STATUS Buffer without actually stepping the pattern program or modifying the PGM.

Most bytes of the STATUS Buffer can be modified from the QTL program or the Q-Monitor; exceptions are indicated below. Whenever the STATUS Buffer is edited, all user-programmed bytes are transferred from the STATUS Buffer to their corresponding registers in the PGM.

The Status Buffer is 95 bytes long. A byte-by-byte description follows.

Byte 0:CURRENT MAR. The value currently in the MAR (the next microinstruction to be executed). Microinstruction addresses range from 0 to FF hex (255 decimal).

Byte 1:CURRENT MAR SEGMENT. Shows which of the four 256-word MAR segments is currently in use. Segments 0 through 2 are available for user-written patterns (768 microinstructions total). Segment 3 (256 microinstructions) is reserved for the PGM operating system.

Byte 2:INTERRUPT ADDRESS. The value currently in the interrupt address register. This is the microinstruction to which the pattern program would jump if an interrupt occurred.

Byte 3:STACK POINTER. The value presently in the microprogram stack pointer. The stack is 16 levels deep. The stack pointer starts at 0, decrements each time a stack push occurs, and increments each time a stack pop occurs. Stack operations are caused by microprogram GOSUBS, RETURNS, and interrupts.

Byte 4:RETURN ADDRESS. The return address currently being pointed to by the stack pointer. This byte cannot be edited by the user.

Bytes 5–7: LOOP COUNTER A. Current value of loop counter A. Low byte 5, middle byte 6, high byte 7.


Bytes 8–A: LOOP COUNTER B. Current value of loop counter B. Low byte 8, middle byte 9, high byte A.

Bytes B–D: LOOP COUNTER C. Current value of loop counter C. Low byte B, middle byte C, high byte D.

Bytes E–10: LOOP COUNTER D. Current value of loop counter D. Low byte E, middle byte F, high byte 10.

Bytes 11–13: LOOP COUNTER E. Current value of loop counter E. Low byte 11, middle byte 12, high byte 13.

Bytes 14–16: RELOAD REGISTER A. Current value of reload register A. Low byte 14, middle byte 15, high byte 16.

Bytes 17–19: RELOAD REGISTER B. Current value of reload register B. Low byte 17, middle byte 18, high byte 19.

Bytes 1A–1C: RELOAD REGISTER C. Current value of reload register C. Low byte 1A, middle byte 1B, high byte 1C.

Bytes 1D–1F: RELOAD REGISTER D. Current value of reload register D. Low byte 1D, middle byte 1E, high byte 1F.

Bytes 20–22: RELOAD REGISTER E. Current value of reload register E. Low byte 20, middle byte 21, high byte 22.

Bytes 23–24: Y ADDRESS GENERATOR OUTPUT. Y address out of pipeline level 2. Low byte 23, high byte 24.

Bytes 25–26: X ADDRESS GENERATOR OUTPUT. X address out of pipeline level 2. Low byte 25; high byte 26.

Bytes 27–28: YMAIN. YMAIN out of pipeline level 2. Low byte 27; high byte 28.

Bytes 29–2A: XMAIN. XMAIN out of pipeline level 2. Low byte 29; high byte 2A.

Byte 2B–2C: YBASE. YBASE out of pipeline level 2. Low byte 2B; high byte 2C.

Byte 2D–2E: XBASE. XBASE out of pipeline level 2. Low byte 2D; high byte 2E.

Byte 2F–30: YFIELD. YFIELD out of pipeline level 2. Low byte 2F; high byte 30.

Byte 31–32: XFIELD. XFIELD out of pipeline level 2. Low byte 31; high byte 32.


Byte 33: DATA REGISTER. The value of the 8-bit data register out of pipeline level 2.

Byte 34–35: JAM REGISTER. The value of the 16 bit jam register out of pipeline level 3. Low byte 34, high byte 35.

Byte 36–37: DATA BUFFER. The value of the data buffer memory out of pipeline level 3. Low byte 36, high byte 37.

Byte 38–39: YINDEX REGISTER. The value of the 12 bit YINDEX register out of pipeline level 2. Low byte 38, high byte 39.

Byte 3A–3B: DATA GENERATOR OUTPUT. Data into pipeline level 4. This shows the data word after all levels of conditional inversion. Low byte 3A, high byte 3B. These bytes cannot be edited.

Byte 3C: DATA GENERATOR CONDITIONAL INVERT BITS. Shows which inversion functions are presently active out of pipeline level 3:

Bit 7: Data register shift/fill

bit value

0 Bit 5: Data topo

inversion

Bit 4: XORINV

Bit 3:“BIT 2” function select

Bit 2: Equality function

Bit 1: INVSNS

Bit 0: BCKFEN

0 = Shift/fill 0 into the data register

1 = Shift/fill 1 into the data register.

not used

XOR invert w/microdata

Set in the TYPE Table

Invert sense Background function

(Can be edited.) 1 indicates that the associated inversion function is active; 0 indicates that it is inactive.

Only the shift/fill bit can be edited; the other bits cannot.

Byte 3D–3F: LOADBOARD DATA. The value of LBDATA presently at the load board. Low byte 3D, middle byte 3E, high byte 3F.

Byte 40–42: ERROR ADDRESS, UNSCRAMBLED. The unscrambled address at which the DUT first failed when the PGM was instructed to run a pattern and stop on error. These bytes cannot be edited. Low byte 40, middle byte 41, high byte 42.

Byte 43–45: ERROR ADDRESS, SCRAMBLED. The scrambled address at which the DUT first failed when the PGM was instructed to run a pattern and stop on error. These bytes cannot be edited. Low byte 43, middle byte 44, high byte 45.

Byte 46–47: ERROR EXPECT DATA. The data expected from the DUT in the first failing cycle when the PGM was instructed to run a pattern and stop on error. These bytes cannot be edited. Low byte 46, high byte 47.


Byte 48–49: ERROR ACTUAL DATA. The actual data put out by the DUT in the first failing cycle when the PGM was instructed to run a pattern and stop on error. These bytes cannot be edited. Low byte 48, high byte 49.

Byte 4A: ERROR MAR. The microprogram address of the first failing cycle when the PGM was instructed to run a pattern and stop on error. This byte cannot be edited.

Byte 4B–4D: PREVIOUS ADDRESS, UNSCRAMBLED. The unscrambled address from the cycle previous to the cycle in which the DUT first failed when the PGM was instructed to run a pattern and stop on error. These bytes cannot be edited. Low byte 4B, middle byte 4C, high byte 4D.

Byte 4E–50: PREVIOUS ADDRESS, SCRAMBLED. The scrambled address from the cycle previous to the cycle in which the DUT first failed when the PGM was instructed to run a pattern and stop on error. These bytes cannot be edited. Low byte 4E, middle byte 4F, high byte 50.

Byte 51–52: PREVIOUS DATA. The data driven to and/or expected from the DUT in the cycle previous to the cycle in which the DUT first failed when the PGM was instructed to run a pattern and stop on error. These bytes cannot be edited. Low byte 51, high byte 52.

Byte 53: PREVIOUS MAR. The microprogram address from the cycle previous to the cycle in which the DUT first failed when the PGM was instructed to run a pattern and stop on error. This byte cannot be edited.

Byte 54–56: DUT ADDRESS, UNSCRAMBLED. The unscrambled address associated with the address presently at the DUT. These bytes cannot be edited. Low byte 54, middle byte 55 , high byte 56.

Byte 57–59: DUT ADDRESS, SCRAMBLED. The scrambled address currently at the DUT. These bytes cannot be edited. Low byte 57, middle byte 58, high byte 59.

Byte 5A–5B: DUT DATA. The data currently being driven to and/or expected from the DUT. These bytes cannot be edited. Low byte 5A, high byte 5B.

Byte 5C: DUT MAR. The microprogram address associated with the address and data currently at the DUT. These bytes cannot be edited.

Byte 5D: ROW (X) ERROR COUNTER. The value in the row error counter.

Byte 5E: COLUMN (Y) ERROR COUNTER. The value in the column error counter.

Q2/52 Reference: Pin Electronics Modes


This section contains Pin Electronics Channel Functional Assignments for each of the three P.E. Modes.

Mode 1: 8-Bit-Wide Data and Data-on-Address. Mode 1 provides 8 P.E. channels for data, 22 channels for address, and 10 channels for chip select pins. (If not all the available address channels are needed, unused bits may be masked off.)

Mode 2: RAMs in Parallel. Mode 2 provides two separate sets of PE channels, each containing four data channels, 11 address channels, and five chip selects. (If not all the available address channels are needed, the unused bits may be masked.) Mode 2 is used only for devices configured with a multiplexed address bus.

Mode 3: 16-Bit-Wide Data. Mode 3 provides 16 PE data channels, 20 address channels (12 X and 8 Y), and 4 chip select channels. (If not all the available address channels are needed, the unused bits may be masked off.)


MODE 1 Common I/O data Separate I/O DataP. E. Channel Symbol Signal name Symbol Signal name

1 X0 X Address 0 X0 X address 02 X1 X Address 1 X1 X address 13 X2 X Address 2 X2 X address 24 X3 X Address 3 X3 X address 35 X4 X Address 4 X4 X address 46 X5 X Address 5 X5 X address 57 X6 X Address 6 X6 X address 68 X7 X Address 7 X7 X address 79 X8 X Address 8 X8 X address 8

10 X9 X Address 9 X9 X address 911 CS1 Chip Select 1 CS1 Chip Select 112 CS2 Chip Select 2 CS2 Chip Select 213 CS3 Chip Select 3 CS3 Chip Select 314 CS4 Chip Select 4 CS4 Chip Select 415 CS5 Chip Select 5 CS5 Chip Select 516 CS1X Chip Select 1X CS1X Chip Select 1X17 CS2X Chip Select 2X CS2X Chip Select 2X18 CS3X Chip Select 3X CS3X Chip Select 3X19 CS4X Chip Select 4X CS4X Chip Select 4X20 CS5X Chip Select 5X CS5X Chip Select 5X21 IO0 Input/Output 0 DD0 Drive Data 022 IO1 Input/Output 1 DD1 Drive Data 123 IO2 Input/Output 2 DD2 Drive Data 224 IO3 Input/Output 3 DD3 Drive Data 325 IO4 Input/Output 4 ED0 Expect Data 026 IO5 Input/Output 5 ED1 Expect Data 127 IO6 Input/Output 6 ED2 Expect Data 228 IO7 Input/Output 7 ED3 Expect Data 329 Y8 Y Address 8 Y8 Y Address 830 Y9 Y Address 9 Y9 Y Address 931 Y0 Y Address 0 Y0 Y Address 032 Y1 Y Address 1 Y1 Y Address 133 Y2 Y Address 2 Y2 Y Address 234 Y3 Y Address 3 Y3 Y Address 335 Y4 Y Address 4 Y4 Y Address 436 Y5 Y Address 5 Y5 Y Address 537 Y6 Y Address 6 Y6 Y Address 638 Y7 Y Address 7 Y7 Y Address 739 X10 X Address 10 X10 X Address 1040 X11 X Address 11 X11 X Address 11


MODE 2 Common I/O data Separate I/O DataP. E. Channel Symbol Signal name Symbol Signal Name

1 A0B Addr. 0 - DUT B A0B Addr. 0 - DUT B2 A1B Addr. 1 - DUT B A1B Addr. 1 - DUT B3 A2B Addr. 2 - DUT B A2B Addr. 2 - DUT B4 A3B Addr. 3 - DUT B A3B Addr. 3 - DUT B5 A4B Addr. 4 - DUT B A4B Addr. 4 - DUT B6 A5B Addr. 5 - DUT B A5B Addr. 5 - DUT B7 A6B Addr. 6 - DUT B A6B Addr. 6 - DUT B8 A7B Addr. 7 - DUT B A7B Addr. 7 - DUT B9 A8B Addr. 8 - DUT B A8B Addr. 8- DUT B

10 A9B Addr. 9 - DUT B A9B Addr. 9 - DUT B11 CS1A C. S. 1 - DUT A CS1A C. S. 1 - DUT A12 CS2A C. S. 2 - DUT A CS2A C. S. 2 - DUT A13 CS3A C. S. 3 - DUT A CS3A C. S. 3 - DUT A14 CS4A C. S. 4 - DUT A CS4A C. S. 4 - DUT A15 CS5A C. S. 5 - DUT A CS5A C. S. 5 - DUT A16 CS1B C. S. 1 - DUT B CS1B C. S. 1 - DUT B17 CS2B C. S. 2 - DUT B CS2B C. S. 2 - DUT B18 CS3B C. S. 3 - DUT B CS3B C. S. 3 - DUT B19 CS4B C. S. 4 - DUT B CS4B C. S. 4 - DUT B20 CS5B C. S. 5 - DUT B CS5B C. S. 5 - DUT B21 IO0A Input/Output 0A DD0 Drive Data 0A22 IO1A Input/Output 1A DD1A Drive Data 1A23 IO2A Input/Output 2A DD0B Drive Data 0B24 IO3A Input/Output 3A DD1B Drive Data 1B25 IO0B Input/Output 0B ED0A Expect Data 0A26 IO1B Input/Output 1B ED1A Expect Data 1A 27 IO2B Input/Output 2B ED0B Expect Data 0B28 IO3B Input/Output 3B ED1B Expect Data 1B29 A8A Addr. 8 - DUT A A8A Addr. 8 - DUT A30 A9A Addr. 9 - DUT A A9A Addr. 9 - DUT A31 A0A Addr. 0 - DUT A A0A Addr. 0 - DUT A32 A1A Addr. 1 - DUT A A1A Addr. 1 - DUT A33 A2A Addr. 2 - DUT A A2A Addr. 2 - DUT A34 A3A Addr. 3 - DUT A A3A Addr. 3 - DUT A35 A4A Addr. 4 - DUT A A4A Addr. 4 - DUT A36 A5A Addr. 5 - DUT A A5A Addr. 5 - DUT A37 A6A Addr. 6 - DUT A A6A Addr. 6 - DUT A38 A7A Addr. 7 - DUT A A7A Addr. 7 - DUT A39 A10A Addr. 10- DUT A A10A Addr. 10- DUT A40 A10B Addr. 10- DUT B A10B Addr. 10- DUT B


MODE 3 Common I/O data Separate I/O dataP. E. Channel Symbol Signal name Symbol Signal name

1 X0 X Address 0 X0 X address 02 X1 X Address 1 X1 X address 13 X2 X Address 2 X2 X address 24 X3 X Address 3 X3 X address 35 X4 X Address 4 X4 X address 46 X5 X Address 5 X5 X address 57 X6 X Address 6 X6 X address 68 X7 X Address 7 X7 X address 79 X8 X Address 8 X8 X address 8

10 X9 X Address 9 X9 X address 911 CS1 Chip Select 1 CS1 Chip Select 112 CS2 Chip Select 2 CS2 Chip Select 213 CS3 Chip Select 3 CS3 Chip Select 314 CS4 Chip Select 4 CS4 Chip Select 415 IO10 Input/Output 10 DD6 Drive Data 616 IO11 Input/Output 11 DD7 Drive Data 717 IO12 Input/Output 12 ED4 Expect Data 418 IO13 Input/Output 13 ED5 Expect Data 519 IO14 Input/Output 14 ED6 Expect Data 620 IO15 Input/Output 15 ED7 Expect Data 721 IO0 Input/Output 0 DD0 Drive Data 022 IO1 Input/Output 1 DD1 Drive Data 123 IO2 Input/Output 2 DD2 Drive Data 224 IO3 Input/Output 3 DD3 Drive Data 325 IO4 Input/Output 4 ED0 Expect Data 026 IO5 Input/Output 5 ED1 Expect Data 127 IO6 Input/Output 6 ED2 Expect Data 228 IO7 Input/Output 7 ED3 Expect Data 329 IO8 Input/Output 8 DD4 Drive Data 430 IO9 Input/Output 9 DD5 Drive Data 531 Y0 Y Address 0 Y0 Y Address 032 Y1 Y Address 1 Y1 Y Address 133 Y2 Y Address 2 Y2 Y Address 234 Y3 Y Address 3 Y3 Y Address 335 Y4 Y Address 4 Y4 Y Address 436 Y5 Y Address 5 Y5 Y Address 537 Y6 Y Address 6 Y6 Y Address 638 Y7 Y Address 7 Y7 Y Address 739 X10 X Address 10 X10 X Address 1040 X11 X Address 11 X11 X Address 11


Q2/62 SPECIFIC TOPICS

The Q2/62 Pattern Execution Module (PEM)

PEM (Pattern Execution Module) buffers are memory locations on the PEM in which patterns and PEM configuration and status information is stored.

INSERT buffer [address] Inserts to buffer starting at address (number or label). If no address is supplied, inserts starting at 0.

INSEND Ends INSERT data.QINSERT buffer, address, register [,register...] Inserts register(s) to buffer, starting at

address (number or label).PGMBYTE byte1 [,byte2 ... , byteN] Sends bytes to PEM buffer.PGMWORD word1 [,word2 ... , wordN] Send word(s) (16 bits) to PEM buffer.DISPLAY buffer Displays buffer on the monitor screen in

readable ASCII format.

Loading a PEM Buffer. The INSERT statement starts loading data into a PEM table at a specified address. (If no address is supplied, data is inserted starting at address 0.) The data to be loaded can be either 8-bit bytes (with PGMBYTE) or 16-bit words (with PGMWORD). The INSEND statement terminates the data insertion.

The QINSERT statement also loads data into a PEM table starting at a specified address. The data is read from one to eleven specified registers or literals. The registers can be byte, word, doubleword, or string registers, but only one byte is loaded from each register. No SENDPGM is required. Caution: the QINSERT statement generates a lot of code, and should be used sparingly. Additionally, use of QINSERT in a QTL program reduces the number of available byte registers by 14.

The PEM tables that may be loaded with INSERT or QINSERT are as follows:

MASK Mask Table. Contains a one-to-one mapping of DUT pins to pattern memory; specifies which pins can be learned by LEARN commands. The Mask Table is 40 bytes long.

OFFSET Offset table.PATTERN Pattern memory. Storage for functional patterns. The pattern memory is 4096

(4K) vectors long; each vector is 96 bits (six 16-bit words) wide. The first 16-bit word of each vector is the control word; the remaining words are the user-defined pattern data bits (PD1 through PD80).

PEL Pin Electronics Logic Table. Describes the relationship between DUT pins and the corresponding data bits in the pattern memory. (This information is used by


the DISPLAY FAILDATA, LEARN, and KILLSTROBES commands.) The PEL Table is 40 bytes long.

PES Pin Electronics Strobe Table. Describes the relationship between DUT pins and the corresponding strobe control bits in the pattern memory. (This information is used by the DISPLAY FAILDATA, LEARN, and KILLSTROBES commands.) The PES Table is 40 bytes long.

SRCPORTS Signal Routing Card ports.TYPE TYPE Table. Configures the PEM for a particular testing application. The

TYPE Table is 9 bytes long, and is described in detail below.USER User Area. Stores 8080 PEM commands that can be used repeatedly.

Displaying a PEM Buffer. The DISPLAY command displays a specified PEM buffer on the monitor screen. All of the PEM tables listed above can be displayed with DISPLAY, as can the following PEM buffers and registers:

NEXT The next failing address.SEQADD The address sequencer register.STATUS Status Buffer. Stores the contents of PGM registers.

The Q Buffer

SENDPGM Begins a list of instructions for the Q Buffer.SENDPGM label Like SENDPGM, but the list begins at label.ENDLIST Ends list.

All commands for the Q2/62’s Pattern Execution Module, or PEM, are loaded into a special buffer call the Q Buffer. These commands are only executed when a FUNTEST EXQ statement or a FUNJIF EXQ statement is executed. (See “Test Blocks: Functional Tests,” under Basic Program Components earlier in this section, for information on FUNTEST and other functional test statements.) The Q Buffer is 256 bytes long.

PGM Lists. A list of instructions for the PEM is called a “PGM list.” Every PGM list begins with a SENDPGM statement and ends with an ENDLIST statement. (“SENDPGM” is not a mistake: there is no such thing as a SENDPEM statement.) If a label is used, the ENDLIST statement appears at the end of the remote list. Each PGM list overwrites the entire Q Buffer, so each must be executed before another is loaded. That is, only one SENDPGM statement can appear between FUNTEST or FUNJIF statements.

The SENDPGM statement does not execute the PEM list that follows it—SENDPGM just sends the instructions to the Q Buffer. They are executed only when a FUNTEST EXQ or FUNJIF statement is reached.


Q2/62 PEM Control

With one exception, the following commands in this section are not QTL statements. They are PEM-specific commands that must be loaded into the Q Buffer within PGM lists. The QPLOAD statement alone is a QTL statement that cannot be included in a PGM list.

BEGIN Initializes PEM.

QPLOAD [address,] register Loads pattern whose name is in the 14-byte string register, starting at address. If no address is supplied, loads starting at address 0. Note: QPLOAD is a QTL statement. Do not include it in a PEM list.

PLOAD [address,] file Loads pattern file, starting at address in pattern memory. If no address is supplied, loads starting at address 0.

PATTERN file Loads and executes pattern file. Not recommended; looping on a test will cause repeated PLOADs.

RUN [address] Executes pattern starting at address. If no address is supplied, executes starting at address 0.

SETUP [address] Executes pattern starting at address, masking errors. If no address is supplied, executes starting at address 0.

EX8080 [address] Execute 8080 code from the User Area, starting at address. If no address is supplied, executes from the User Area starting at address 0.

RESETSTOP address1, address2 Resets the end of test bit in Pattern Memory from address1 to address2.

LEARN [address] Starts learning pattern at address. If no address is supplied, starts learning at address 0.

SAVE address1, address2, <file> Saves pattern from address1 to address2 in file. The angle brackets surrounding the filename are optional.

SRCDATA A, byte Sends byte to SRC port A.SRCDATA B, byte Sends byte to SRC port B.SRCREAD register, A Read SRC port A into byte register.SRCREAD register, B Read SRC port B into byte register.

Initializing the PEM. BEGIN initializes the PEM and displays a sign-on message indicating the PEM Operating System version number.

Loading a Pattern. There are two ways to load a pattern file into pattern memory without executing it. The QPLOAD statement, which must used directly from QTL, not in a PGM list, loads a pattern whose name is in a specified 14-byte string register into pattern memory.

The PLOAD command, which must appear within a PGM list, loads a pattern from a specified file on disk into pattern memory. Double-quotes (") or angle brackets (< >) can be used to quote unusual filenames, but are not generally necessary.


Both QPLOAD and PLOAD load the pattern starting at a specified address; if no address is supplied, the pattern is loaded starting at address 0. The PATTERN command loads a pattern from a specified file on disk into pattern memory and then starts executing it, as described below.

Executing a Pattern. There are several ways to execute a pattern. The RUN command initializes the address sequencer to the specified address (or to 0 if no address is specified), enables error detection circuitry, and then executes the pattern currently resident in the pattern memory. The SETUP command is identical to the RUN command, except that errors are inhibited. It is usually used to initialize the PEM pipeline latches and any multiple-cycle TG channels.

Loading and Executing a Pattern. The PATTERN command loads a specified pattern file and then begins execution immediately. Use of this command is not recommended; since PATTERN performs a PLOAD, looping on the test will result in many repeated PLOADs.

Executing 8080 Code in the User Area. The EX8080 command executes the 8080 code in the USER Buffer, starting at a specified location. The USER Buffer is loaded via an INSERT sequence in the QTL program.

Resetting the Stop Bit. The RESETSTOP command clears all the stop (ENDOFTEST) bits in the pattern memory between the specified addresses, then sets the stop bit at the second of the two specified addresses.

Learning and Saving a Pattern. The LEARN command modifies the functional pattern currently in pattern memory to match the actual response from the DUT. The learn function starts at the specified address (or address 0 if none is specified) and continues until it reaches a stop (ENDOFTEST) bit in the pattern. Note: The address argument always determines where in the pattern the learn function begins, but if Byte 9 of the TYPE Table is set, the address argument also determines where pattern execution begins. See “Q2/62 Reference: The TYPE Table,” below.

The SAVE command saves the contents of the pattern memory between the specified addresses into a file on disk and in the POB, along with a checksum and file length. The number of words read from each PEM address is specified by the word width set in Byte 0 of the TYPE Table. If the first character of the filename is an ampersand (&), the file is sent only to the POB, where the ampersand is changed to the tester number (0–3).

Communicating with the SRC (Signal Routing Card). The SRC commands provide access to SRC ports A and B from within QTL. SRCDATA sends a byte of data to an SRC port. SRCREAD reads a byte of data from an SRC port into a byte register in the system controller. (Note: SRCREAD only works with PEM Software Version 2.7.)


Q2/62 POB Control

The PC-Host’s POB software implements Pattern Overlay Buffer (POB) functions. The amount of POB space available for pattern storage depends on the RAM installed in the computer; see “PC-POB Software” in the introduction section of this manual.

LPP file Transfers ROM code in file (in Intel hexadecimal format) from disk to the POB.

LPP register Transfers ROM code in the file whose name is in a specified 14-byte string register from disk to the POB.

POBDELETE <file> Deletes file in POB. The angle brackets (< >) are optional.POBDIRECTORY Displays directory of files in POB.

BEXLPP bit1, ...bit8, start, end, increment, LPPstart, LPPincrement

Fills pattern data bit1 through bit8 from the POB. Start, end, and increment specify the exact vectors to be edited; LPPstart and LPPincrement specify the location in the POB of the source data.

POBSELFCHECK Executes the POB selfcheck.

Managing Files in the POB. The LPP command loads a ROM-code file from disk into the POB. The filename can be specified either directly or through a 14-byte string register. In the POB, the ROM code is stored in a file named %LPP.TMP. The POBDELETE command deletes a specified file from the POB, and the POBDIRECTORY command displays a listing of all files in the POB.

Loading ROM Code from POB to Pattern Memory. The BEXLPP command transfers functional pattern data from the POB to the pattern in memory. The fill data is taken from the file %LPP.TMP. The LPPstart argument specifies the byte address in the POB file from which the first 8 data bits are taken; the LPPincrement argument specifies the step size between data bytes in the POB file that are transferred to the PEM. The range of PEM vector addresses affected are specified by start and end arguments; the increment argument specifies the step size between addresses. (For example, if “3,2047,4” is specified for start, end, increment, then every fourth PEM vector address from 3 to 2047 is filled with data from the POB.) The POB data is inserted into pattern data bits bit1 through bit8 in each of the affected vectors. Eight pattern data bit arguments are required; use hexadecimal FF if fewer than eight pattern data bits are used.

Example:BEXLPP 17,18,19,20,21,22,23,24, 3,2047,4, 0,1

Q2/62 Reference: The TYPE Table

The TYPE Table configures the PEM for a particular testing application. It is nine bytes long, as follows:


Byte Assignment

0 Pattern memory word width. Set this byte to the total number of 16-bit words in each line of the functional pattern(s). Each line must contain one control word and one to five pattern words, as follows:

Word 1: Control wordWord 2: Pattern data bits 1–16Word 3: Pattern data bits 17–32Word 4: Pattern data bits 33–48Word 5: Pattern data bits 49–64Word 6: Pattern data bits 65–80

Note: whenever pattern data bits 65–80 are unused, the compiler assumes a five-word-wide pattern memory. If Byte 0 of the TYPE Table is not set, it defaults to 6, and the pattern cannot be loaded.

1 Unused.2–3 Software time-out for sync-loop sequences. Set this word (Byte 2 = LSB) to the

number of milliseconds that the PEM CPU will wait for the DUT to sync up with the pattern after a hardware time-out. If the DUT and pattern are still not synchronized after this delay, the PEM generates a TIMEOUT and then executes the last address of the most recent PLOAD. (The PEM assumes that the last address of a functional pattern disables all strobes.) The default setting upon initialization is 0.

4 Inhibit enable. This byte has two settings:FF = If the Stop on Error switch on the front panel is set, then error detection is

inhibited within a few vectors after the first error is detected. (Default)00 = Disables the Stop on Error switch on the front panel.

5–7 Unused.8 Early exit switch. This byte has two settings:

FF = Pattern execution halts on error. The PEM stores the error status, then executes the last address of the most recent PLOAD. (The PEM assumes that the last address of a functional pattern disables all strobes.)

00 = Pattern execution continues regardless of errors. (Default)9 Learning switch. This byte has two settings:

FF = The address argument to the LEARN command determines the address in the functional pattern where the learn function begins, and the previous RUN, SETUP, or PATTERN command determines the address where pattern execution begins.

00 = The address argument to the LEARN command determines the starting address of both the learn function and pattern execution. (Default)

QTL PROGRAMMING - SKY284 Specific Topics 146

SKY284 SPECIFIC TOPICS

The SKY284 Vector Generator

VG (Vector Generator) buffers are memory locations on the VG in which pattern configurations and status information are stored.

INSERT buffer [address] Inserts to buffer starting at address (number or label). If no address is supplied, inserts starting at 0.

INSEND Ends INSERT data.QINSERT buffer, address, register [,register...] Inserts register(s) to buffer, starting at

address (number or label).PGMBYTE byte1 [,byte2 ... , byteN] Sends bytes to PEM buffer.PGMWORD word1 [,word2 ... , wordN] Send word(s) (16 bits) to PEM buffer.DISPLAY buffer Displays buffer on the monitor screen in

readable ASCII format.

Loading a VG Buffer. The INSERT statement starts loading data into a VG table at a specified address. (If no address is supplied, data is inserted starting at address 0.) The data to be loaded can be either 8-bit bytes (with PGMBYTE) or 16-bit words (with PGMWORD). The INSEND statement terminates the data insertion.

The QINSERT statement also loads data into a VG table starting at a specified address. The data is read from one to eleven specified registers or literals. The registers can be byte, word, doubleword, or string registers, but only one byte is loaded from each register. No SENDPGM is required. Caution: the QINSERT statement generates a lot of code, and should be used sparingly. Additionally, use of QINSERT in a QTL program reduces the number of available byte registers by 14.

The VG tables that may be loaded with INSERT or QINSERT are as follows:

PATTERN Pattern memory. Storage for functional patterns. The pattern memory is 128K or 256K vectors long. There are 16 pattern control bits and 4 pattern data bits per pin.

TYPE TYPE Table. Configures the VG for a particular testing application. The TYPE Table is 9 bytes long, and is described in detail below.

FORMAT PEL, PEE, PES format table.DELAY Clock Distribution Module (CDM) delay.


Displaying a VG Buffer. The DISPLAY command displays a specified VG buffer on the monitor screen. All of the VG tables listed above can be displayed with DISPLAY, as can the following VG buffers and registers:

STATUS Status Buffer. Stores the contents of PGM registers.

The Q Buffer

SENDPGM Begins a list of instructions for the Q Buffer.SENDPGM label Like SENDPGM, but the list begins at label.ENDLIST Ends list.

All commands for the SKY284's Vector Generator are loaded into a special buffer called the Q Buffer. These commands are only executed when a FUNTEST EXQ statement or a FUNJIF EXQ statement is executed. (See “Test Blocks: Functional Tests,” under Basic Program Components earlier in this section for information on FUNTEST and other functional test statements.)

PGM Lists. A list of instructions for the VG is called a “PGM list.” Every PGM list begins with a SENDPGM statement and ends with an ENDLIST statement. If a label is used, the ENDLIST statement appears at the end of the remote list. Each PGM list overwrites the entire Q Buffer, so each must be executed before another is loaded. That is, only one SENDPGM statement can appear between FUNTEST or FUNJIF statements.

The SENDPGM statement does not execute the VG list that follows it—SENDPGM just sends the instructions to the Q Buffer. They are executed only when a FUNTEST EXQ or FUNJIF statement is reached.

VG Control

With one exception, the following commands in this section are not QTL statements. They are VG-specific commands that must be loaded into the Q Buffer within PGM lists. The QPLOAD statement alone is a QTL statement that cannot be included in a PGM list.

BEGIN Initializes VG.

QPLOAD [address,] register Loads pattern whose name is in the 14-byte string register, starting at address. If no address is supplied, loads starting at address 0. Note: QPLOAD is a QTL statement. Do not include it in a PEM list.

PLOAD [address,] file Loads pattern file, starting at address in pattern memory. If no address is supplied, loads starting at address 0.

PATTERN file Loads and executes pattern file. Not recommended;


looping on a test will cause repeated PLOADs.

RUN [address] Executes pattern starting at address. If no address is supplied, executes starting at address 0.

SETUP [address] Executes pattern starting at address, masking errors. If no address is supplied, executes starting at address 0.

RESETSTOP address1, address2 Resets the end of test bit in Pattern Memory from address1 to address2.

LEARN [address] Starts learning pattern at address. If no address is supplied, starts learning at address 0.

SAVE address1, address2, <file> Saves pattern from address1 to address2 in file. The angle brackets surrounding the filename are optional.

SRCDATA A, byte Sends byte to SRC port A.SRCDATA B, byte Sends byte to SRC port B.SRCREAD register, A Read SRC port A into byte register.SRCREAD register, B Read SRC port B into byte register.

Initializing the VG. BEGIN initializes the VG and displays a sign-on message indicating the VG revision number.

Loading a Pattern. There are two ways to load a pattern file into pattern memory without executing it. The QPLOAD statement, which must used directly from QTL, not in a PGM list, loads a pattern whose name is in a specified 14-byte string register into pattern memory.

The PLOAD command, which must appear within a PGM list, loads a pattern from a specified file on disk into pattern memory. Double-quotes (") or angle brackets (< >) can be used to quote unusual filenames, but are not generally necessary.

Both QPLOAD and PLOAD load the pattern starting at a specified address; if no address is supplied, the pattern is loaded starting at address 0. The PATTERN command loads a pattern from a specified file on disk into pattern memory and then starts executing it, as described below.

Executing a Pattern. There are several ways to execute a pattern. The RUN command initializes the address sequencer to the specified address (or to 0 if no address is specified), enables error detection circuitry, and then executes the pattern currently resident in the pattern memory. The SETUP command is identical to the RUN command, except that errors are inhibited. It is usually used to initialize the VG pipeline latches.

Loading and Executing a Pattern. The PATTERN command loads a specified pattern file and then begins execution immediately. Use of this command is not recommended; since PATTERN performs a PLOAD, looping on the test will result in many repeated PLOADs.


Resetting the Stop Bit. The RESETSTOP command clears all the stop (ENDOFTEST) bits in the pattern memory between the specified addresses, then sets the stop bit at the second of the two specified addresses.

Learning and Saving a Pattern. The LEARN command modifies the functional pattern currently in pattern memory to match the actual response from the DUT. The learn function starts at the specified address (or address 0 if none is specified) and continues until it reaches a stop (ENDOFTEST) bit in the pattern. Note: The address argument always determines where in the pattern the learn function begins. See “SKY284 Reference: The TYPE Table,” below.

The SAVE command saves the contents of the pattern memory between the specified addresses into a file on disk, along with a checksum and file length. The number of words read from each VG address is specified by the word width set in Byte 0 of the TYPE Table.

SKY284 ROM Code Loading

The following commands are available for loading ROM codes:

LPP file Transfers ROM code in file (in Intel hexadecimal format) from disk to the VG.

LPP register Transfers ROM code in the file whose name is in a specified 14-byte string register from disk to the VG.

BEXLPP bit1, ...bit8, start, end, increment, LPPstart, LPPincrement

Fills pattern data bit1 through bit8 from the VG. Start, end, and increment specify the exact vectors to be edited; LPPstart and LPPincrement specify the location in the VG of the source data.

Loading ROM Code from a LPP file to Pattern Memory. The BEXLPP command transfers functional pattern data from the LPP to the pattern in memory. The LPPstart argument specifies the byte address in the LPP file from which the first 8 data bits are taken; the LPPincrement argument specifies the step size between data bytes in the LPP file that are transferred to the VG. The range of VG vector addresses affected are specified by start and end arguments; the increment argument specifies the step size between addresses. (For example, if “3,2047,4” is specified for start, end, increment, then every fourth VG vector address from 3 to 2047 is filled with data from the LPP file.) The LPP data is inserted into pattern data bits bit1 through bit8 in each of the affected vectors. Eight pattern data bit arguments are required; use hexadecimal FF if fewer than eight pattern data bits are used.

Example:BEXLPP 17,18,19,20,21,22,23,24, 3,2047,4, 0,1


SKY284 Reference: The TYPE Table

The TYPE Table configures the VG for a particular testing application. It is nine bytes long, as follows:

Byte Assignment

0 Pattern memory word width. Set this byte to the total number of 16-bit words in each line of the functional pattern(s). Each line must contain one control word and one to twenty-one pattern words. One word holds the pattern data for four pins.Note: If Byte 0 of the TYPE Table is not set, it defaults to 22.

1 Unused.2–3 Software time-out for sync-loop sequences. Set this word (Byte 2 = LSB) to the

number of milliseconds that the VG will wait for the DUT to sync up with the pattern after a hardware time-out. If the DUT and pattern are still not synchronized after this delay, the VG generates a TIMEOUT and then executes the last address of the most recent PLOAD. (The VG assumes that the last address of a functional pattern disables all strobes.) The default setting upon initialization is 0.

4–9 Unused.

QTL PROGRAMMING - SKY284 And Q2/62 Functional Programming 151

SKY284 AND Q2/62 FUNCTIONAL PROGRAMMING

SKY284 and Q2/62 pattern files are written and compiled independently from the QTL program, but the same general rules of form apply. Comments begin with semicolons. Multiple arguments to commands can be separated by commas, blanks, or tabs.

With the Q2/62, up to 4096 vectors may be used; each vector can contain up to 80 bits. With the SKY284, there are 128K or 256K vectors. Each vector includes 16 control bits plus 4 bits per pin.

PEMDEF bit1 bit2 ... Defines mapping from source code to PEM bits.[SET] F bitpattern Generates one vector consisting of bitpattern.[SET] FC n bitpattern Generates one vector consisting of bitpattern that is executed

n times.[LSET] register bitpattern Sets M or D register to bitpattern. The command “LSET” is

optional.ENABLE register [register] Selects an M or D register.STARTLOOP n [SYNC] Starts a pattern loop that repeats n times. If the SYNC

argument is used, the pattern loop iterates until the DUT is synchronized with the pattern, or until the pattern has looped n times.

ENDLOOP Ends a pattern loop.SAMPLEERROR Enables error sampling inside a sync loop.LSUBR label [n] Begins defining subroutine label. If n is included, it specifies

the number of iterations when the subroutine is executed.LEND Ends defining subroutine.LCALL label Calls subroutine at label.ENDOFTESTENDTEST

Ends pattern.

END Ends source file (optional). This command may appear as .END.

REM Introduces a remark (comment) line; generates no source code.

Mapping Source Code to PEM Bits. The PEMDEF statement defines the mapping of the pattern file source code to the PEM bits, and hence to the DUT. The mapping for a particular program is determined by the user-configured hardware on the Signal Routing Card (SRC). The following arguments can be used:


F1 through F80 SET F bits 1 through 80.D1 through D80 LSET D bits 1 through 80.M1 through M80 LSET M bits 1 through 80.X No mapped bit.1 Always 1.0 Always 0.

In the first PEMDEF statement, the first argument specifies the code bit for the first pattern memory data bit (PD1), the next argument specifies the code bit for the second pattern memory data bit (PD2), and so on. Subsequent PEMDEF statements resume where the first leaves off. Each block of PEMDEF statements defines bits contiguously beginning with bit 0. There is no limit to the number of arguments that can appear with a single PEMDEF statement, but for readability, several PEMDEF statements are usually used. See the example at the end of this section.

Example:PEMDEF F1 F2 F3 F4 F9 F10 F11 F12 F17 F18 F19 F20PEMDEF D1 X X X M1 M2 M3 M4PEMDEF F5 F6 F7 F8

In this example, F bits 1 through 4 are mapped to pattern memory bits 1 through 4; F 9 through 12 are mapped to pattern memory bits 5 through 8; F 17 through 20 are mapped to pattern memory bits 9 through 12, D 1 is mapped to pattern memory bit 13; pattern memory bits 14 through 16 are unmapped; M 1 through 4 are mapped to pattern memory bits 17 through 20; and F 5 through 8 are mapped to pattern memory bits 21 through 24.

The following operators are available to perform logical operations on one or more pattern data bits. They are evaluated in the order listed; parentheses can be used to force other evaluation orders.

- inversion& checks for logical equality^ logical AND| logical OR% logical XOR

Pattern Data. The SET F and SET FC statements generate vectors: streams of 1’s and 0’s. Each SET F or SET FC statement can be followed by 1 to 80 bits. Each bit can be 1, 0, or X (don’t care). The SET FC statement generates vectors that are executed multiple times: its number argument (from 1 to 1,048,576) specifies how many times. See the example at the end of this section.


The hardware has an 8-bit SET FC counter; the compiler will automatically generate multiple vectors for counts above 256.

M and D Registers. There are 100 M (strobe mask) registers: MA through MZ or M0 through M99. There are also 100 D (driver enable) registers: DA through DZ or D0 through D99. M1 through M26 are the same as MA through MZ. D1 through D26 are the same as DA through DZ. The registers are 80 bits long. Both M and D registers are set via the LSET statement. Each ENABLE command can enable one M register, one D register, or both. See the example at the end of this section.

Loops. The STARTLOOP command begins a pattern loop that will repeat a specified number of times. Loops may be nested; however, the practical limit to the number of levels, as well as the number of iterations, depends on the Q2/62 PEM’s two 8-bit loop counters. Loop counts above 256 and nested loops more than two levels deep consume vectors rapidly.

The ENDLOOP command ends the loop. Certain restrictions apply:

· If the first vector in a loop is a SET FC, the loop count must be the same as the SET FC count.

· If two STARTLOOP commands are used in a single cycle, they must have the same count.

· Loops must contain at least two vectors.· If the SYNC argument is used, the SAMPLEERROR command can be used

within the loop to enable error sampling. If SAMPLEERROR is not used, the tester will not recognize errors.

Subroutines. The LSUBR command begins defining a subroutine with a specified label; the LEND command ends the subroutine. At any point, the subroutine can be called with the LCALL command. Subroutines are implemented as macros by the compiler, not in the hardware, so they can consume vectors rapidly.

Ending the Pattern. The pattern must be terminated by an ENDOFTEST or ENDTEST command.


Example Pattern:PEMDEF F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16PEMDEF D1 D2 D3 D4 D5 D6 D7 D8PEMDEF M1 M2 M3 M4 M5 M6 M7 M8

LSET MA 11111111LSET MB 00000000

LSET DA 11111111LSET DB 00000000

ENABLE MA,DA

STARTLOOP 8 SYNC

SET F 10101010 1010 1 0 1 0SET FC 900 01010101 0101 0 1 0 1SAMPLEERRORSET F 10101010 1010 1 0 1 0ENDLOOP

STARTLOOP 200SET F 10101010 1010 1 0 1 0STARTLOOP 250SET F 01010101 0101 0 1 0 1SET FC 10101010 1010 1 0 1 0ENDLOOPENDLOOP

SET F 01010101 0101 0 1 0 1

ENDTEST

END

TESTER OPERATION - Q-Monitor Basics 157

TESTER OPERATION: THE Q-MONITOR

Q-MONITOR BASICS

The PC-Host Q-Monitor (“Q”) program incorporates all of the features of the PDP-11-based Q, SuperQ, and Q2CCL. All tester operation, calibration, and selfchecks should be run from the PC-Host Q-Monitor. At some installations, the AUTOEXEC.BAT file is modified to start the Q-Monitor automatically when the computer is booted.

To start the Q-Monitor, move to the \PCHOST directory (C:\PCHOST) and type Q at the DOS system prompt:

C:\PCHOST> Q

The Q-Monitor prompt appears:

Q2>

(If “C:\PCHOST” is in the path, type Q at the DOS system prompt in any directory.)

To exit the Q-Monitor, press Control-C.

Q-Monitor Command Formats

Filenames in Q Commands. Some Q commands accept filenames as arguments. These are always DOS filenames, not RT-11 or TSX filenames. PDP-11 device names such as DK:, SY:, DL:, DL0:, DL1:, DL2:, and DL3: are ignored. The device name LP: (printer) will be converted to LPT1: (printer port) and the device name TT: (terminal) will be converted to CON: (console).

Strings and Hex Characters in Q Commands. Strings (in Q commands that accept them as arguments) can be entered in any of three formats: <string>, "string", or 'string'.

Hexadecimal characters may be included within a string in any format. For example: <string<0A><0D>>, "string\0A\0D", or 'string\0A\0D'.

The following C escape sequences are also accepted within "string" or 'string' format strings, but not within <string> format strings:


\a bell \f form feed \r carriage return \v vertical tab\b backspace \n new line \t tab \\ backslash

Comments in Q Commands. Comments can be entered from the keyboard, but are usually used only in Q macros and command files. Comments can take any of the following four formats:

! Comment to the end of the line.; Comment to the end of the line.(* ... *) Comment within a line.(< ... >) Comment on a line by itself. This type of comment is displayed on console

during execution, and is often used within a Q macro to instruct an operator to perform a setup sequence before proceeding.

Comment formats can be freely mixed within a Q macro or command file.

Expressions in Q Commands

Within Q commands that accept expressions, the following operators can be used:

Relational Arithmetic and Logical

= Equal + Add (lowest precedence)<> Not equal - Subtract< Less than * Multiply> Greater than / Divide

<= Less than or equal & AND>= Greater than or equal | OR

<< Shift Left>> Shift Right- Minus~ Not (highest precedence)

The arithmetic and logical operators are listed in order of increasing precedence (from lowest to highest). Use parentheses to force other evaluation orders.

In addition, the following special CCL-like functions are available in expressions:

MIN(registers) MAX(registers)


Use commas to separate registers within each set.

Variables in Q Commands

The following special variables are available in expressions:

COUNTER The time, in picoseconds, from the start edge to the stop edge, taken from the HP 5370 or GT200 counter.For example, the following code would create a Q program variable called DELTA, take reading from the counter, and assign the value read to DELTA:

LONG DELTAASSIGN DELTA = COUNTER

COUNTER_TYPE The type of counter in use: “5370” if the counter in use is an HP5370, or “200” if the counter in use is a GT200 counter.

PERIOD_START The counter’s start period, in picoseconds.PERIOD_STOP The counter’s stop period, in picoseconds.

LINE, COLUMN The current line and column of the cursor on the console screen.

STARTn The start edge of timing generator n, in picoseconds.STOPn The stop edge of timing generator n, in picoseconds.OSTARTn The start edge offset of timing generator n, in picoseconds.OSTOPn The stop edge offset of timing generator n, in picoseconds.

V1, V2, and V3 Programmed values for DUT power supplies at the load board, in millivolts.

VIH1, VIH2, VIL1, VIL2 Programmed high and low rails for pin electronics channels, in millivolts.

VIHC, VILC Programmed additional reference voltages, in millivolts.VOH, VOL, VOUT Programmed output reference voltages for functional tests, in

millivolts.VPAR Programmed voltage for parametric tests, in millivolts.VBIAS Programmed voltage on the load board, in millivolts.

TESTER OPERATION - The Q Setup Command 160

THE Q SETUP COMMAND

SETUP Set download and upload modes, host and tester baud rates, and printer type.

Use the SETUP command only if the default settings are incorrect for your setup. It requests settings for the following options. Once set, these parameters are saved in the file \PCHOST\Q.SET and need not be reentered.

Down load options. The default is B - Down Load Binary or ASCII Files.

Down Load Options Are: A - Down Load Only ASCII Files B - Down Load Binary or ASCII FilesEnter Selection:

Up load options. The default is A - Up Load Only ASCII Files. To upload binary files, the program CP.SAV must be installed on the PDP-11 host system disk. To obtain a copy of this program, contact Skyline Test Equipment.

Up Load Options Are: A - Up Load Only ASCII Files B - Down Load Binary or ASCII FilesEnter Selection:

Tester Baud Rate. The default is 19200 baud.

Tester Baud Rate: 19200 9600 4800 2400 1200Enter Selection:

Host Baud Rate. The default is 9600 baud.

Host Baud Rate: 19200 9600 4800 2400 1200Enter Selection:

TESTER OPERATION - The Q Setup Command 161

Printer Type. Two printer types are available: ASCII standard character set for all types of printers, and IBM extended character set for PC printers with the full 256-character set. The default is 0 - ASCII Standard Character Set.

Printer Type: 0 - ASCII Standard Character Set 1 - IBM Extended Character SetEnter Selection:

TESTER OPERATION - Q-Monitor Commands 162

Q-MONITOR COMMANDS

Q Commands for Program Loading and Execution

AUTOSTART option See “Access to I/O Ports” in “QTL PROGRAMMING: Additional Test Programming Commands.”

B file Execute BEGIN: initializes PGM and sets all PGM FBINs to 0; outputs to file, or to the console screen if no file is specified. See “Q2/52 PGM Control” in “QTL PROGRAMMING: Q2/52 Specific Topics.”

BLOAD file Loads binary program from file. The default file name extension is .BIN: if no extension is specified, the program looks for file.BIN.

DEBUG=n Repeats functional test block every n milliseconds.DISCONNECT option If option is OLD, the DISCONNECT command operates the “old”

way: the pins in the USEDCHANNEL list are connected before each test block is executed. If option is NEW, the DISCONNECT command operates the “new” way: the pins are not connected, so a DISCONNECT command executed in a previous test block is still in effect. The default is DISCONNECT OLD.See the section on PE channel connections in “Test Blocks: Setup for Functional Tests” in “QTL PROGRAMMING: Basic Program Components.”

DUMP n file Dumps the first n bytes of the QTL program to file.EDIT address Allows the currently loaded executable program to be edited in op-

code format, beginning at address. If no address is specified, the edit starts at the beginning. Although sometimes used to modify the load board ID (the fourth byte of every QTL program), the EDIT command is not recommended.

EXU Executes the contents of USER Buffer, starting at the beginning. See the section on executing from the USER Buffer in “Q2/52 PGM Program Flow Control” in “QTL Programming: Q2/52 Specific Topics.”

HP Indicates that a host is present. This command is seldom used for Q2/52 and Q2/62 applications.

LF option If option is F, sets the logical flag to false; if option is T, sets the logical flag to T. See the description of the logical flag in “Flow Control” in “QTL PROGRAMMING: Additional Test Programming Commands.”

LOAD file Loads hexadecimal or binary program from file. The type of file (binary or hexadecimal) determines the type of load. If file has no extension, the LOAD command will look for, in order: file.BIN, file.SAV, and then file.OBJ.

LOADU file Loads the USER Buffer from file. The default file name extension


is .OBJ; if no extension is specified, the program looks for file.OBJ. This command is not supported by Skyline's ESCape package.

NHP Indicates that no host is present. This command is seldom used for Q2/52 and Q2/62 applications.

PE file Prints errors to file.PRINT option file If option is E, prints errors to file; if option is S, prints status to file.

If no file is specified, prints to the console screen.PROM For Q-8000 applications only, returns to PROM-based operation.

This command is not used for Q2/52 and Q2/62 applications.READY Ready. Puts the tester in Ready mode.RELAY Display current relay open and close times.RELAY m n Specify relay opening time of m microseconds and relay closing

time of n microseconds. The default for both values is 0.RESET If used without Skyline’s ESCape package, performs a software

reset of the Q2. The Q2 is initialized, and the currently loaded QTL program is left loaded. However, the first byte of the QTL program is set to hexadecimal FF. After reset, the console screen displays a “NO QTL FOUND” error message, and the TEST NUMBER display on the front panel shows bd. To bring the Q2 back to Ready mode, edit byte 0 of the QTL program to hexadecimal 50, or reload the QTL program.If used with Skyline’s ESCape package, performs a true hardware reset of the tester, similar to pressing the RESET button on the back of the tester, but leaving the loaded QTL program intact. After the reset, just execute a BEGIN command to resume execution.

RUN Cancels debug mode.S file Prints summary information to file, or to the console screen if no

file is specified.SET=value Sets the “SET” variable to value. (The SET variable is initially set

to 0, 1, 2, or 3 depending on the lowest two bits of the load board ID.)

SF option If option is C, sets the sequence flag to CONTINUE; if option is R, sets the sequence flag to RETURN. See the description of the sequence flag in “Flow Control” in “QTL PROGRAMMING: Additional Test Programming Commands.”

SUMMARY option If option is OFF, disables standard summary output; if option is ON, enables standard summary output. See the section on displaying bins in “Q2/52 PGM Control” in “QTL PROGRAMMING: Q2/52 Specific Topics.”

UDUMP n file Dumps the first n bytes of the USER Buffer to file, or to the console screen if no file is specified. This command is not supported by Skyline's ESCape package.

UEDIT Allows the User Buffer to be edited in op-code format. This command is not supported by Skyline's ESCape package.


Q Commands for Front Panel Functions

The following commands duplicate the functions of the tester’s front panel:

AE ERROR MODE: ACCUMULATE ERRORS. Enables error latching on functional tests throughout the functional test. Pin errors displayed on the front panel ERROR ON PIN display or by the PE (“print errors”) command include all pins that failed during the test.

SOE ERROR MODE: STOP ON ERROR. Prevents error latching on functional tests after the first DUT cycle in which errors are detected. Pin errors displayed on the front panel ERROR ON PIN display or by the PE (“print errors”) command include only those pins that failed during the first failing DUT cycle. If other pins failed later in the functional test, they are not displayed.

STE ERROR MODE: STEP TO ERROR. If executed while in the Ready mode, QTL program execution starts, continues until a failing test is reached, and then loops on the failing test. If executed while already looping on a test, the QTL program proceeds as if the test had passed. Execution continues until the next failing test, whereupon the program again begins to loop.

FSTE Restarts test program execution when looping on a test. The QTL program proceeds as if the test had failed. (There is no front panel switch equivalent.)

DON DISPLAY MODE ON. Enables output of Summary information to the console screen and disk files when a Summary is executed.

DOF DISPLAY MODE OFF. Prevents summary information from being displayed on the console screen or sent to disk files when a Summary is executed.

DDE DISPLAY MODE: DETAIL. Enables automatic output of detail information (test result, binning information, DUT number, and failing pins) to the console screen after each execution of the QTL program. Also enables output of Summary information to the console screen and disk files when a Summary is executed.

PD Same as DDE.PO Same as DOF.PS SUMMARY. Performs a summary. The MESSAGE statement in the QTL

program is displayed on the console screen, followed by summary information if the DISPLAY MODE switch is in the ON or DETAIL positions, or if a DON or DDE Q-Monitor command has been executed. If the DISPLAY MODE switch is set to OFF, or if a DOF Q-Monitor command has been executed, standard summary data is not displayed—only the user-defined summary block will be displayed. Bin counts are not cleared.

OHH OPENS HALT: HALT ON N. Halts testing when the number of consecutive opens failures reaches the number set ).

OHC OPENS HALT: CONTINUE. Takes the Q2 out of halt mode caused by opens failures exceeding the number set in the PROM on the interface board (normally 10) and puts it in Ready mode.

OHR OPENS HALT: RUN. Continues testing regardless of the number of consecutive opens failures detected.

DSS Enters debug single step mode. Executes one QTL command each time Enter is pressed, and displays the next one.


SSR SINGLE STEP: READY. Returns to Ready mode if looping on a test.SSS SINGLE STEP: STEP. The QTL program executes one test at a time. If the Q2 is

in Ready mode, it steps to the first test and loops on it. Subsequent SSS commands cause the program to advance one test at a time, looping on each. Branching on test results proceeds as if every test passed.

CR Same as SSR.CS Same as SSS.CC No action; as if the from panel calibrate switch were in the middle position

between RUN and STEP.

T Tests. This command functions exactly like the Test button on the front panel.T=t Loops on test t.TT Tests and displays test time.R Retests. This command functions exactly like the Retest button on the front

panel.

LOCK Locks out all front panel switches. The RESET button on the rear panel is not affected.

LOCKX Locks out all front panel switches except BEGIN, RESET, TEST, and SUMMARY.

UNLOCK Unlocks front panel.

Breakpoints

The following commands are available to set and administer breakpoints:

BKPRINT Prints all currently set breakpoints.BK PRINT Same as BKPRINT.BKDUMP file Same as BKPRINT, but outputs to file.

BKPT=test Sets a breakpoint at test, breaks, and branches according to the DUT result.

BKPT=test,BD Same as BKPT=test.BKPT=test,BF Sets a breakpoint at test, breaks, and branches as if the DUT failed.BKPT=test,BP Sets a breakpoint at test, breaks, and branches as if the DUT

passed.BKPT=test,ND Sets a breakpoint at test, doesn't break, and branches according to

the DUT result.BKPT=test,NF Sets a breakpoint at test, doesn't break, and branches as if the DUT

failed.BKPT=test,NP Sets a breakpoint at test, doesn't break, and branches as if the DUT

passed.BKPT=test,NM Sets a breakpoint at test and measures all tests, but doesn't break.BKPT=test,M Same as BKPT=test,NM.BKPT=test,NK Sets a breakpoint at test and measures all failing tests, but doesn't


break.BKPT=test,MF Same as BKPT=test,NK.

* Executes current test once.LOOP Loops on current test. To continue execution, use a READY,

CDUT, CFAIL, CPASS, or CTABLE command.CDUT Continues after breakpoint, branching according to the DUT result.CFAIL Continues after breakpoint, branching as if the DUT failed.CPASS Continues after breakpoint, branching as if the DUT passed.CTABLE Continues after breakpoint, branching according to the type of

breakpoint set.

DEL BK test Deletes breakpoint at test.CBK Clears (deletes) all breakpoints.

TEST test Clears (deletes) breakpoints, sets a breakpoint at test, tests, breaks, and loops on test. The same thing could be accomplished by the following sequence: READY, CBK, BKPT=test, T, LOOP.

Registers

The Q program maintains a symbol table so that registers in the test may be accessed by their symbolic names rather than their physical addresses. For fast access, the symbol table is stored in RAM. The symbol table has a capacity of 4095 symbols. The following Q commands are available for accessing registers:

CREG Clears All Registers.

n Prints the value of register n.PRINTR name Prints register n, regardless of register type, using currently

loaded symbol table.PRINT Bnumber Prints byte register n (0 to 255).PRINT Wn Prints word register n (0 to 255).PRINT Dn Prints doubleword register n (0 to 255).PRINT M Prints the MOD register.

ASSIGN n= Assigns the value 0 to register n. The keyword ASSIGN may be omitted.

ASSIGN n=expression Assigns the value of expression to register n. The keyword ASSIGN may be omitted.

BREGn=value Sets byte register n to value.WREGn=value Sets word register n to value.DREGn=value Sets doubleword register n to value.STORE n, <string> Stores string in register n.

LONG v Declares Q “long” (doubleword) variable v with value 0. (The total number of Q long variables and byte, word, and


doubleword registers can total up to 1024.)LONG v= Declare Q long (doubleword) variable v with value 0.LONG v=n Declare Q long (doubleword) variable v with value n.

SYMBOL file Loads the symbol table from file. The default file name extension is .SYM: if no extension is specified, the program looks for file.SYM.

Ports

The following commands are available for accessing test ports:

port=n Send hex data byte n to port. Available ports are FPORTA, FPORTB, LPORTA, and LPORTB. The “=” is optional. Note: Although the QTL port commands allow you to send registers to ports, the Q-Monitor port commands do not—only hex data bytes can be sent.

EMULATE AUXPORT Use PC communications port to emulate AUXPORT.EMULATE WPORT Use PC communications port to emulate WPORT.EMULATE NONE Disable emulation.EMULATE Display current emulation status.

SENDBYTE p n Send byte n (hexadecimal) to port p (hexadecimal).SENDWORD p n Send word n (hexadecimal) to port p (hexadecimal).

GETBYTE p Display tester port p (hexadecimal).GETWORD p Display tester port p (hexadecimal).

To fully emulate the Q2 WPORT port using a PC port you must:

1. Use the DOS MODE command on the PC port. For example:MODE COM2: 9600 E 7 2

2. Execute the SETUP command in Q (only band rate and character set matter).3. Execute the Q command in Q to tell the system which port to use. For example:

Q 2to select COM2

4. Execute the EMULATE WPORT command in Q.

Steps 2 and 3 write a configuration file called Q.SET that Q reads every time it starts up. The EMULATE command can be put in Q.BAT for automatic execution. A null modem is required when moving a cable from the Q2's WPORT to a PC communications port.


Also see the section on sending data to tester ports in “Access to I/O Ports” in “QTL Programming: Additional Test Programming Commands.”

SKY284 Pin Electronics (PE84) Specific Commands

The following commands are available from Q:

PESTATUS Display PE84 temperatures and voltages.P84TEMP Display PE84 temperature map.

Interface Board Configuration

The Q program's IB command is used to configure the interface board and is only available with ESCape. This command, if required, should be placed in the \PCHOST\Q.BAT file so it is executed every time the Q program is entered. The command has up to 7 arguments which are described below.

Default Value Function

10 Two digit count of number of opens permitted in opens halt mode in decimal.0 Interface bin configuration in hexadecimal.

5 Time delay in milliseconds from TE (approximate end of test) to the leading edge of interface EOT (End of Test) signal in decimal.

15 Delay from TE to trailing edge of EOT in milliseconds (decimal).

0 Delay from TE to leading edge of all sort signals in milliseconds (decimal).

21 Delay from TE to trailing edge of all sort signals in milliseconds (decimal).

1 Maximum number of tester generated retests on any part (decimal).

Example:

IB 10 0 5 15 0 21 1 0 0 4D 0 4D

Typing IB with no arguments displays the current settings.

Wafer Mapping

The following commands are available for wafer mapping:


MAP option If option is ON, enables wafer mapping. If option is OFF, disables wafer mapping. If option is QTL, enables wafer mapping from QTL (via the LOADMAP statement) only.

WAFER file Displays wafer map data in file on monitor screen.

This command can be used with the SCREEN command to create files of wafer maps. For example, the following macro opens a list file, generates a wafer map on the monitor screen from a wafer map data file, sends the screen display to the new list file, and then closes it.

macro wmnoechocreate lst ^1.lstwafer ^1.mapscreenclose lstecho

end

Also see the section on wafer map data in “Access to I/O Ports” in “QTL Programming: Additional Test Programming Commands.”

DC Level and Supply Commands

See “Test Blocks: Voltage and Current Setup” in “QTL Programming - Basic Program Components” for detailed descriptions.

Displaying Voltage and Current Parameters. The following commands are available from Q:

PARDUMP file Dumps leakage current offset table to file. If file is omitted, the output is to the monitor screen. This command has no QTL equivalent.

PV file Prints HVM values: VPULSE, VRAIL, and IRAIL.PRINT V file Prints all voltages and currents.

I1,I2, I3 Displays value of I1, I2, or I3.IPAR Displays value of IPAR.IV1, IV2, IV3 Same as I1, I2, I3.V1, V2, V3 Displays value of DUT power supplies V1, V2, or V3 (available at the

load board).


VBIAS Displays value of VBIAS power supply.VIH1, VIH2, VIL1, VIL2

Displays value of pin electronics channel rail VIH1, VIH2, VIL1, or VIL2.

VIHC, VILC Displays value of load board reference voltage VIHC or VILC.VOH, VOL, VOUT Displays value of output reference level VOH, VOL, or VOUT.VPAR Displays value of parametric test unit voltage VPAR.VRAIL Displays value of VRAIL power supply.

Setting Voltage and Current Parameters. The following commands are available from Q. If no units are specified, the defaults are milliamps and millivolts.

I1=m Sets current detect threshold I1 to m milliamps.I2=m Sets current detect threshold I2 to m milliamps.I3=m Sets current detect threshold I3 to m milliamps.IPAR=m Sets parametric test unit current to m milliamps. This command also accepts

values in microamps (UA) and nanoamps (NA).IV1=m Sets current detect threshold I1 to m milliamps. This command also accepts

values in microamps (UA) and nanoamps (NA).IV2=m Sets current detect threshold I2 to m milliamps. This command also accepts

values in microamps (UA) and nanoamps (NA).I3V=m Sets current detect threshold I3 to m milliamps. This command also accepts

values in microamps (UA) and nanoamps (NA).V1=m Sets power supply V1 to m millivolts.V2=m Sets power supply V2 to m millivolts.V3=m Sets power supply V3 to m millivolts.

VBIAS=m Sets VBIAS power supply to m millivolts.VIH1=m Sets rail supply VIH1 to m millivolts.VIH2=m Sets rail supply VIH2 to m millivolts.VIHC=m Sets rail supply VIHC to m millivolts.VIL1=m Sets rail supply VIL1 to m millivolts.VIL2=m Sets rail supply VIL2 to m millivolts.VILC=m Sets rail supply VILC to m millivolts.VOH=m Sets reference level VOH to m millivolts.VOL=m Sets reference level VOL to m millivolts.VOUT=m Sets both VOH and VOL to m millivolts.VPAR=m Sets parametric test unit voltage to m millivolts.VRAIL=m Sets VRAIL power supply to m millivolts.


Programmable Timing Generator Commands

See “Test Blocks: Timing Setup” in “QTL Programming - Basic Program Components” for detailed descriptions.

Note: Any PTG command issued preceded by a “]” character is sent directly to the PTG without processing by the Q program or the system control firmware.

Displaying and Adjusting Individual Edges. The following commands are available from Q:

STARTn Displays start edge n in nanoseconds.STARTn=time Sets start edge n to time, in nanoseconds.STARTn,m=time Sets start edges m through n to time, in nanoseconds.TG0=t Sets start edge of Timing Generator 0 to time, in nanoseconds.STOPn Displays stop edge n in nanoseconds.STOPn=time Sets stop edge n to time, in nanoseconds.STOPn,m=time Sets stop edges m through n to time, in nanoseconds.

SSTARTn Display start value of super TG for pin n. (SKY284 only)SSTARTn=t Set start edge of super TG for pin n to t ns. (SKY284 only)SSTARTn,m=t Set start edge of super TG for pins n-m to t ns. (SKY284 only)SSTOPn Display stop value of super TG for pin n. (SKY284 only)SSTOPn=t Set stop edge of super TG for pin n to t ns. (SKY284 only)SSTOPn,m=t Set stop edge of super TG for pins n-m to t ns. (SKY284 only)

TGSTATUSn file Dumps status of Timing Generator n to file. If no file is specified, data is displayed on the monitor screen.

CSTARTn Tweaks start offset of Timing Generator n with the “,” and “.” and Enter keys.

CSTOPn Tweaks stop offset of Timing Generator n with the “,” and “.” and Enter keys.

TSTARTn Tweak start edge n with the “,” and “.” and Enter keys.TSTOPn Tweak stop edge n with the “,” and “.” and Enter keys.

OSTARTn=time Sets offset for start edge n to time, in nanoseconds.OSTARTm,n=time Sets offset for start edges m through n to time, in nanoseconds.OSTOPn=time Sets offset for stop edge n to time, in nanoseconds.OSTOPm,n=time Sets offset for stop edges m through n to time, in nanoseconds.OTIMES file Dumps start and stop edge offset values to file. If no file is

specified, data is displayed on the monitor screen.

BASEn=t Sets base time for Timing Generator n to t nanoseconds.


EARLYn=t Sets early time for Timing Generator n to t nanoseconds.LATEn=t Sets late time for Timing Generator n to t nanoseconds.

Displaying and Adjusting PTG Cycle Times and Delays. The following commands are available from Q:

CYCLE Displays the cycle time (period) in nanoseconds.CYCLE=time Sets the cycle time (period) to time, in nanoseconds.TCYCLE Tweaks the cycle time with the “,” and “.” and Enter keys.

DELAY=time Sets delay to time. For Q2/62 programs only.DELAYM=mode Sets delay to mode, which must be one of the following: INH (or

INHIBIT), SYNC, or TG0. For Q2/62 programs only.TDELAY Tweaks delay with the “,” and “.” and Enter keys. For Q2/62

programs only.

Accessing PTG Timing Calibration Data. The following commands are available from Q:

PTD Programs calibration timing data into PROMs.TDUMP file Dumps timing calibration data to file. If no file is specified, data is

displayed on the monitor screen.TLOAD file Loads timing calibration data from file.

Accessing PTG Offsets. The following commands are available from Q:

OFFSET=n Loads resident offset table n. (Offset tables are generated during offset calibration and can be stored in memory on the PGM or SRC.)

FDUMP file Dumps PGM/PEM offsets to file.FLOAD file Loads PGM/PEM offsets from file.

Additional PTG Access and Control. The following commands are available from Q:

HEXTIME time Converts time, in nanoseconds, to hexadecimal value for insertion in compiled program. It is recommended that the time value be changed in the QTL program and then recompiled.

PFD Programs PGM/PEM functional data into PROMs.PTD Programs timing calibration data into PROMs.

TP1=NONE Disconnects test point 1 on the load board. Used for some calibration operations.

TP1=connection Connects test point 1 on the load board to connection, which must be one of the following: SYNC (i.e., scope sync), T0, TG0, or


TMAX/2. (Q2 only). Connects to T0, CYCLE, or ERROR (SKY284 only).

TRULES 22 Selects Q2/22 timing rules.TRULES 42 Selects Q2/42 timing rules.TRULES OFF Disables timing rules.

TIMES file Dumps PTG setup information to file. If no file is specified, data is displayed on the monitor screen.

DSTARTn=t Set start delay counter of TG n to t counts. (SKY284 only).DSTOPn=t Set stop delay counter of TG n to t counts. (SKY284 only).VSTARTn=t Set start vernier delay of TG n to t counts. (SKY284 only).VSTOPn=t Set stop vernier delay of TG n to t counts. (SKY284 only).

IMAGES file Dumps internal timing image data to file. If no file is specified, data is displayed on the monitor screen.

TGSTATUS Display TG84 temperatures and voltages.TGSTATUSn Display status of timing generator n.TGTEMP Display TG84 temperature map.REV Display TG84 hardware revision.

REVISION Displays PTG software revision.

Q2/52 PGM Specific Commands

The X commands may be abbreviated to the extent that they remain unambiguous. For example, the shortest form of XEDIT is XED.

Number Base. The following commands are available from Q:

XBASE Displays current default number base.XDECIMAL Sets default number base to decimal.XHEX Sets default number base to hexadecimal.

The Q Buffer. See “The Q Buffer” in “QTL Programming - Q2/52 Specific Topics” for more information. The following command is available from Q:

XQcommand Loads PGM command into the Q Buffer.

PGM Control. See “Q2/52 PGM Control” in “QTL Programming - Q2/52 Specific Topics” for more information. The following commands are available from Q:


XBEGIN Initializes PGM. Sets all PGM FBINs to 0.XSUMMARY Displays contents of all PGM Row, Column, and Functional Bins

(RBINs, CBINs, and FBINs).

PGM Buffers. See “PGM Buffers” in “QTL Programming - Q2/52 Specific Topics” for more information. The following commands are available from Q:

XDISPLAY buffer,c,d Displays addresses c through d of buffer on the monitor screen in readable ASCII format.

XWRITE buffer,c,d file Writes addresses c through d of buffer to file in Intel hex format. If no file is specified, outputs to the monitor screen.

XSELECTBUF n Selects Data Buffer segment n.XDUTLOAD Learns ROM code to DATA buffer.XCSLOAD Learns chip select polarity to TYPE Table.

XCHECKSUM GENERATE Generates checksum of the contents of the DATA Buffer.XCHECKSUM COMPARE Compares last-generated checksum with that of the DATA

Buffer's current contents.XCHECKSUM LOAD, value Loads DATA Buffer checksum with value.

XEDIT buffer,c,d Edits addresses c through d of buffer.

Parametric Test Setup. See “PGM Parametric Test Setup” in “QTL Programming - Q2/52 Specific Topics” for more information. The following commands are available from Q:

XLBDATA n Sets load board control bits to n.

XOUTHIGH b Searches for DUT address with high (logic one) bit n.XOUTLOW b Searches for DUT address with low (logic zero) bit n.

XSETADDRESS address Sets address outputs to address.XSETCHIPSON cs1,cs2... Sets chip selects to active (true).XSETDATA value Sets data outputs to value.

PGM Pattern Loading and Execution. See “PGM Pattern Loading and Execution” in “QTL Programming - Q2/52 Specific Topics” for more information. The following commands are available from Q:


XMARSEGMENT n Selects MAR segment n (0, 1, or 2).

XPLOAD PROGRAM Loads PATTERN program buffer into the MicroRAM, but does not execute it.

XPATTERN PROGRAM Loads and executes pattern.XPATTERN PROGRAM, ERROR [, DISPLAY] Loads and executes pattern, halts on

error; optionally displays state of PGM.

XPGOFFSET n Executes pattern at address n.XPGOFFSET n, ERROR [,DISPLAY] Executes pattern at address n; halts

on error; optionally displays STATUS buffer.

XPGOFFSET n COLUMN [,COUNT] Executes pattern at address n; enables Column ECR; optionally decrements Column Error Counter on error.

XPGOFFSET n ROW [,COUNT] Executes pattern at address n; enables Row ECR; optionally decrements Row Error Counter on error.

XPGOFFSET n ROW, COLUMN Executes pattern at address n; enables both Row and Column ECRs.

XPGOFFSET n, FULL[EC] [,NOERROR] Executes pattern at address n; enables Full ECR; optionally doesn't scan for errors after pattern execution.

XPGOFFSET n, NOCLOCK[S] Sets MAR to address n, but doesn't execute.

XSTARTPATTERN Loads and executes pattern.XSTARTPGOFFSET n Starts executing pattern program at

location n in the MicroRAM.XSTOPPATTERN Halts execution of pattern program.

XSTEP n Steps pattern n times, no error display.

XPSTEP n Steps pattern n times, stopping if pattern completes; error display at each step.

XPESTEP n Steps pattern to nth error, stopping if pattern completes; complete error display.

XPNSTEP n Steps pattern n times, stopping if pattern completes; displays errors once after stepping.

Loading a Pattern Program. See “Test Blocks: Additional Setup” in “QTL Programming - Basic Program Components” for more information. The following commands are available from Q:


LPP file Loads hexadecimal pattern program from file. The type of file (binary or hexadecimal) determines the type of load. If file has no extension, the LPP command will look for, in order: file.BIN, file.SAV, and then file.OBJ.

BLPP file Loads binary pattern program from file. The default file name extension is .BIN: if no extension is specified, the program looks for file.BIN.

PGM Program Flow Control. See “PGM Program Flow Control” in “QTL Programming - Q2/52 Specific Topics” for more information. The following commands are available from Q:

XGENERR Sets ERROR flag; generates a functional error.XRESETERR Clears ERROR flag; clears functional errors.XEXU n Executes contents of USER Buffer, starting at location n.

PGM Error Catch Control. See “PGM Error Catch Control” in “QTL Programming - Q2/52 Specific Topics” for more information. The following commands are available from Q:

XROWCLEAR Clears row ECR.XCOLCLEAR Clears column ECR.XRCCLEAR Clears both row and column ECRs.XROWDUMP Transfers row ECR to RBINs.XCOLDUMP Transfers column ECR to CBINs.

HVM. See “Q2/52 PGM High Voltage Module” in “QTL Programming - Q2/52 Specific Topics” for more information. The following commands are available from Q:

XHVM ENABLE Enables HVM (high voltage module).XHVM DISABLE Disables HVM (high voltage module).

XBOOST ENABLE Enables HVM voltage boost.XBOOST DISABLE Disables HVM voltage boost.

XVPULSE voltage Sets HVM voltage output pulse (VPULSE) to voltage millivolts.XVRAIL voltage Sets HVM power supply level (VRAIL) to voltage millivolts.XIRAIL current Sets HVM supply current threshold (IRAIL) to current

microamps.

XITEST Tests state of current detect (IERROR) flag.XPV Displays HVM voltages and currents (VPULSE, VRAIL, and

IRAIL).

Selfcheck. The following commands are available from Q for individual selfchecks:XOSCHECKSUM Selfchecks PGM controller PROM checksum.


XRAM Selfchecks PGM controller RAM.XSDTOPO Selfchecks data topological scramble.XSERCAT Selfchecks error catch RAM.XSSCRAM Selfchecks error catch scramble RAM.XSTOPO Selfchecks address topological scramble.XROWCOL Selfchecks row and column error RAMs.

Q2/62 PEM Specific Commands





Displaying a PEM Buffer. See “The Q2/62 Pattern Execution Module” in “QTL Programming - Q2/62 Specific Topics” for more information. The following commands are available from Q:

XDISPLAY MASK Displays Mask Table on the monitor screen in readable ASCII format.

XDISPLAY NEXT Displays the next failing address on the monitor screen in readable ASCII format.

XDISPLAY PATTERN a,b Displays vectors a through b in pattern memory on the monitor screen in readable ASCII format.

XDISPLAY PEL Displays PEL (Pin Electronics Logic) table on the monitor screen in readable ASCII format.

XDISPLAY PES Displays PES (Pin Electronics Strobe) table on the monitor screen in readable ASCII format.

XDISPLAY QBUFFER a,b Displays addresses a through b of the Q Buffer on the monitor screen in readable ASCII format.

XDISPLAY SEQADD Displays the address sequencer register on the monitor screen in readable ASCII format.

XDISPLAY SRCPORTS Displays SRC ports on the monitor screen in readable ASCII format.


XDISPLAY STATUS Displays the Status buffer on the monitor screen in readable ASCII format.

XDISPLAY TYPETABLE a,b Displays bytes a through b of the TYPE Table on the monitor screen in readable ASCII format.

XDISPLAY FAILDATA a,n This command displays the failing bits and addresses from the start address a until the number of failing addresses reaches n, or until a STOP (ENDOFTEST) bit is encountered.*

SDISPLAY Displays pattern source. (Not implemented.)XPOINTER Displays the value of the Q Buffer's pointer.

* PEL and PES tables must exist for this command to execute properly.

Inserting to PEM Tables. See “The Q2/62 Pattern Execution Module” in “QTL Programming - Q2/62 Specific Topics” for more information. The following commands are available from Q:

XINSERT MASK address Inserts to the Mask Table starting at address (number or label). If no address is supplied, inserts starting at 0.

XINSERT PATTERN address Inserts to pattern memory starting at address (number or label). If no address is supplied, inserts starting at 0.

XINSERT PEL address Inserts to PEL (Pin Electronics Logic) Table starting at address (number or label). If no address is supplied, inserts starting at 0.

XINSERT PES address Inserts to PES (Pin Electronics Strobe) Table starting at address (number or label). If no address is supplied, inserts starting at 0.

Editing PEM Tables. The following commands are available from Q:

XEDIT MASK address Edits Mask Table starting at address.XEDIT PATTERN address,bit Edits bit of address of pattern memory.XEDIT PEL address Edits PEL starting at address.XEDIT PES address Edits PES starting at address.XEDIT QBUFFER address Edits Q Buffer starting at address.XEDIT TYPE address Edits TYPE Table starting at address.SEDIT Edits pattern source. (Not implemented.)

PEM Control. See “Q2/62 PEM Control” in “QTL Programming - Q2/62 Specific Topics” for more information. The following commands are available from Q:


XBEGIN Initializes PEM; displays PEM revision number.XPLOAD [address,] file Loads pattern file, starting at address in pattern

memory. If no address is supplied, loads starting at address 0.

XPATTERN file Loads and executes pattern file. XRUN [address] Executes functional pattern starting at address. If no

address is supplied, executes starting at address 0.XRERUN n Runs the pattern n times.XSETUP [address] Executes pattern starting at address, masking errors.

If no address is supplied, executes starting at address 0.

XRESETSTOP address1, address2 Resets the end of test bit in Pattern Memory from address1 to address2.

XLEARN [address] Starts learning pattern at address. If no address is supplied, starts learning at address 0.

XSAVE address1, address2 file Saves pattern from address1 to address2 in file.XSRCDATA A, byte Sends byte to SRC port A.XSRCDATA B, byte Sends byte to SRC port B.XKILLSTROBES address1, address2 Clears strobes from address1 to address2.SSYM Loads pattern symbol table. (Not implemented.)

Direct PEM Access. The following command is available from the Q-Monitor:

X Goes online to the PEM: subsequent commands are passed directly to PEM without processing by PC-Host software. Enter STOP to exit direct access mode and return to Q.

POB Control. See “Q2/62 POB Control” in “QTL Programming - Q2/62 Specific Topics” for more information. The following commands are available from Q:

XPOBDELETE file Deletes file in POB.XPOBDIRECTORY Displays directory of files in POB.XPOBSELFCHECK Executes the POB selfcheck.XEXLPP bit1, ...bit8, start, end, increment, LPPstart, LPPincrement

Fills pattern data bit1 through bit8 from the POB. Start, end, and increment specify the exact vectors to be edited; LPPstart and LPPincrement specify the location in the POB of the source data.

POBRESET Resets the POB.



XBASE Displays current default number base.XDECIMAL Sets default number base to decimal.XHEX Sets default number base to hexadecimal.SBASE n Specifies the number base for SEDIT and SDISPLAY operations.

(Not implemented.)

Selfcheck Commands. The following commands are available from Q:

XADDSEQCHECK Checks the PEM address sequencer.XLOADCHECK Checks the checksum for the pattern file.XMEMORYCHECK Checks the pattern memory.XOSCHECKSUM Checks PEM software PROMs' checksum.XRAMCHECK Checks the PEM controller's RAM memory.

SKY284 Vector Generator (VG84) Specific Commands


Loading Signal Routing Tagle.

SRT file Loads signal routing table.




XEXLPP... Execute LPP.

Displaying a VG84 Buffer. The following commands are available from Q:

XDISPLAY CONTROL a,b Display pattern control memory for vectors a through b.XDISPLAY COUNT a,b Display pattern count memory for vectors a through b.XDISPLAY DELAY Display delay.


XDISPLAY FORMAT Display format.XDISPLAY PATTERN a,b Displays vectors a through b in pattern memory on the

monitor screen in readable ASCII format.XDISPLAY PEE a,b Display PEE (Pin Electronics Enable) table for vectors a

through b.XDISPLAY PEL a,b Displays PEL (Pin Electronics Logic) table for vectors a

through b.XDISPLAY PES a,b Displays PES (Pin Electronics Strobe) table for vectors a

through b.XDISPLAY Q a,b Displays addresses a through b of the Q Buffer.XDISPLAY STATUS Displays the Status buffer.XDISPLAY TYPE a,b Displays bytes a through b of the TYPE Table .XPOINTER Displays the value of the Q Buffer's pointer.

Inserting to VG84 Tables. The following commands are available from Q:

XINSERT DELAY pin Insert to delay table starting at pin.XINSERT FORMAT pin Insert to format table starting at pin.XINSERT PATTERN address Inserts to pattern memory starting at address (number or

label). If no address is supplied, inserts starting at 0.XINSERT TYPE address Insert to type table starting at address.

Editing VG84 Tables. The following commands are available from Q:

XEDIT CONTROL address Edit pattern control memory starting at address.XEDIT COUNT address Edit pattern count memory starting at address.XEDIT DELAY pin Edit delay table starting at pin.XEDIT FORMAT pin Edit format table starting at pin.XEDIT PATTERN address,bit Edits bit of address of pattern memory.XEDIT PEE address Edits PEE starting at address.XEDIT PEL address Edits PEL starting at address.XEDIT PES address Edits PES starting at address.XEDIT Q address Edits Q Buffer starting at address.XEDIT STATUS address Edits Status buffer starting at address.XEDIT TYPE address Edits TYPE Table starting at address.

VG84 Control. The following commands are available from Q:


XADDCOM Display RAM address.XADDCOM a Compare RAM address to a.XBEGIN Displays VG84 revision number.XCYCLE Display VG84 cycle time.XCYCLE n Set VG84 cycle time to n nanoseconds.XCYCLE OFF Turn off VG84 cycle, turn on TG cycle.XCYCLE ON Turn on VG84 cycle, turn off TG cycle.XKILLSTROBES address1, address2 Clears strobes from address1 to address2.XLEARN [address] Starts learning pattern at address. If no address is

supplied, starts learning at address 0. XPATTERN file Loads and executes pattern file. XPESTEP n Steps pattern to nth error, stopping if pattern

completes; complete error display.XPGOFFSET n Executes pattern at address n.XPGOFFSET n, NOCLOCK[S] Sets MAR to address n, but doesn't execute.XPLOAD [address,] file Loads pattern file, starting at address in pattern

memory. If no address is supplied, loads starting at address 0.

XPNSTEP n Steps pattern n times, stopping if pattern completes; displays errors once after stepping.

XPSTEP n Steps pattern n times, stopping if pattern completes; error display at each step.

XRERUN n Runs the pattern n times.XRESETSTOP address1, address2 Resets the end of test bit in Pattern Memory from

address1 to address2.XRUN [address] Executes functional pattern starting at address. If no

address is supplied, executes starting at address 0.XSAVE address1, address2 file Saves pattern from address1 to address2 in file.XSETUP [address] Executes pattern starting at address, masking errors.

If no address is supplied, executes starting at address 0.

XSRCDATA A, byte Sends byte to SRC port A.XSRCDATA B, byte Sends byte to SRC port B.XSTARTPATTERN Loads and executes pattern.XSTARTPGOFFSET n Starts executing pattern program at location n in the

MicroRAM.XSTEP n Steps pattern n times, no error display.XSTOPPATTERN Halts execution of pattern program.XSUMMARY Display summary.



XBASE Displays current default number base.XDECIMAL Sets default number base to decimal.XHEX Sets default number base to hexadecimal.

Selfcheck Commands. The following commands are available from Q:

VGSTATUS Display VG84 temperatures and voltages.VGTEMP Display VG84 temperature map.XFORCEERROR Generate functional error.XRAMCHECK Compare RAM to previously loaded pattern file.XRESETERROR Reset functional error.XSELFSTEP n Step pattern n times, no error display.

Datalogging Commands

See “I/O and Host Functions” and “Data Logging” in “QTL Programming - Additional Test Programming Commands” for detailed descriptions. The following commands are available from the Q-Monitor:

CREATE DAT file Creates and opens DAT file.CREATE LST file Creates and opens LST file.CREATE ERR file Creates and opens ERR file. If an error files is open, all error

messages (from the tester as well as those generated by selfcheck and calibration procedures) are written to it along with the date and time.

CREATE LOG file Creates and opens LOG file. If a log file is open, all output to the console is also written to it.

APPEND DAT file Appends to DAT file.APPEND LST file Appends to LST file.APPEND ERR file Appends to ERR file.APPEND LOG file Appends to LOG file.

CLOSE DAT Closes DAT file.CLOSE LST Closes LST file.CLOSE ERR Closes ERR file.CLOSE LOG Closes LOG file.CLOSE Closes all open DAT, LST, ERR, or LOG files.

PARAM Specifies parameters for subsequent datalogging. For a list of available parameters, see “Data Logging” in “QTL Programming - Additional Test Programming Commands.”


LOG Logs specified parameters to currently open DAT or LST file.SHOWPARAMS Shows parameters currently specified for datalogging.

PRINT DAT expression Prints expression to DAT file.PRINT LST strings Prints strings to LST file.PRINT ERR strings Prints strings to ERR file.

SCREEN Dumps console screen to LST file.S/LOG Sends summary to datalog file.

Characterization Commands

Searches. Before a search can be executed from the Q-Monitor, the required parameters must be set via ASSIGN statements. See “Searches” in “QTL Programming - Additional Test Programming Commands” for more information. The following commands are available from the Q-Monitor:

LSEARCH parameter Performs a linear search on parameter. BSEARCH parameter Performs a binary search on parameter. TSEARCH parameter Performs a binary search on parameter, and then

assigns parameter to the SEARCH register.

Schmoos. Before a schmoo can be executed from the Q-Monitor, the required parameters must be set via PARAM statements. See “Schmoos” in “QTL Programming - Additional Test Programming Commands” for more information. The following commands are available from the Q-Monitor:

TPARAM title Specifies a title for a subsequent schmoo.PPARAM pins Specifies pins to be schmooed in a subsequent

schmoo.XPARAMn parname min max [#steps] Sets up nth X schmoo parameter. The number of

steps (that is, the width of the plot in columns) is optional. Always specify units.

YPARAMn parname min max [#steps] Sets up nth Y schmoo parameter. The number of steps (that is, the length of the plot in rows) is optional. Always specify units.

XPARAMn Deletes nth X schmoo parameter. (XPARAM1 may be abbreviated XPARAM; other XPARAMn commands may be abbreviated Xn.)

YPARAMn Deletes nth Y schmoo parameter. (YPARAM1 may be abbreviated YPARAM; other YPARAMn commands may be abbreviated Yn.)


QSCHMOO Performs “quick” schmoo with parameters set in preceding TPARAM, PPARAM, XPARAM, and YPARAM statements; directs output to the file QSCHMOO.LST. (May be abbreviated QS.)To ensure accuracy, always specify units.Example1: V1 schmooed against V2:

Q2> XPARAM IV1 0MA 100MAQ2> YPARAM V1 3V 7VQ2> QS

Example 2: V1 schmooed against a timing parameter:

Q2> XPARAM1 START11 0NS 1000NSQ2> XPARAM2 STOP11 50NS 1050NSQ2> YPARAM1 V1 3V 7VQ2> QS

QSCHMOO file Like QSCHMOO, but directs output to file.QSCHMOO/OK Performs “quick” schmoo without pausing for

operator “OK” after each parameter.QSCHMOO/OK file Like QSCHMOO/OK, but directs output to file.

For example, to schmoo V1 vs. IV1, you could use the following command sequence:

Q2> XPARAM IV1 0MA 100MA Q2> YPARAM V1 3V 7V Q2> QS

Or, to schmoo V1 vs. a timing parameter, you could use the following command sequence:

Q2> XPARAM1 START11 0NS 1000NSQ2> XPARAM2 STOP11 50NS 1050NSQ2> YPARAM1 V1 3V 7VQ2> QS

Additional Characterization Commands. The following commands are available from the Q-Monitor:

MEASURE Measures all parametric tests.MEASURE FAIL Measures only failing parametric tests.MEASURE OFF Does not measure parametric tests.

TESTER OPERATION - Q Program Commands 186

Q PROGRAM COMMANDS

Command Files. The following commands are available from the Q-Monitor:

MENU Clears the screen.CLEAR Clears the screen.

BOX x y Draws a box down and to the right from the cursor x lines by y columns.

BOXBOX x y Draws a double box down and to the right from the cursor x lines by y columns.

COLOR Displays available screen colors.COLOR color Sets foreground of screen to color. Available colors are RED,

GREEN, YELLOW, BLUE, MAGENTA, CYAN, BLACK, and WHITE.

COLOR BACK color Sets background of screen to color.

CURSOR Turns cursor on.CURSOR ON Turns cursor on.CURSOR OFF Turns cursor off.CURSOR x y Moves cursor to line x (1–25) and column y (1–80).

PRINTLN string Prints string on the display at where the cursor is.PRINTLN x y string Prints string on the display starting at line x and column y.TRIPLE string Draws string in triple-high characters.WINDOW m n Defines lines m through n as display window.MSG message Displays message and waits for return key. The effect is the same

as a PRINTLN command with no argument followed by a WAIT.

CALL file Calls (executes) a file of commands (file); returns when done. CALL commands cannot be nested.

CALL/NOERROR file Calls (executes) a file of commands (file); returns when done; doesn't generate an error if file doesn't exist.

DO file Calls (executes) a file of commands (file); never returns. “DO” files can and often do contain CALL commands.

DO/NOERROR file Calls (executes) a file of commands (file); never returns; doesn't generate an error if file doesn't exist.

@file Executes command file (file); returns when done. @file commands cannot be nested.

CRT Halts execution of command file. Use COM to resume.COM Resumes execution of command file (stopped with CRT).

ECHO Echoes commands.NOECHO Stops echoing commands.


GOTO Go to user specified label.GOTO label Go to label.GOTO label expression Go to label if expression is true.:LABEL Label.

WAIT Waits for return key to be pressed.PAUSE Like WAIT: waits for return key to be pressed.PAUSE string Prints string, then waits for return key to be pressed. The effect is

the same as that of MSG.PAUSE OFF Disables pause at MSG, PAUSE, and WAIT commands.PAUSE ON Enables pause at MSG, PAUSE, and WAIT commands.

PROMPT prompt Changes prompt to prompt. For example, “PROMPT Q8000>” would change the prompt to “Q8000>” .

PANEL Enables or disables tester front panel display. The front panel display uses the top five lines of the console. This command sets a scrolling window for lines 6 to 25. When using the console monitor in 50-line mode, you should use the command “WINDOW 6 50” after the panel command.

General Q-Monitor Input and Control. The following commands are available from the Q-Monitor:

INPUT BATCH Reads QTL input commands from an open batch file.INPUT CONSOLE Reads QTL input commands from the console keyboard (default).

SUSPEND n Suspends Q-Monitor execution for n microseconds.

EXIT Exits (quits) Q-Monitor.QUIT Exits (quits) Q-Monitor.

DUMB Puts Q-Monitor in “dumb” mode: the program functions like a dumb terminal, passing entries directly to the tester without processing. To exit dumb mode and return Q-Monitor functionality, type ^C (control-C). Note: the PC-Host does not support a “file” option.

MODEL Displays tester model type.MODEL OLD Set model to old (non-ESC) when using the ESC key.

VER Displays Q-Monitor version number.

Error Messages. The following commands are available from the Q-Monitor:

ERROR Displays all error messages.ERROR n Display error message n.

Miscellaneous Commands. The following commands are available from the Q-Monitor:


SUM file Calculates checksum for file.

PDPPATH path Specifies path to replace PDP-11 device names. By default, PDP-11 device names (DK:, etc.) are deleted. Use this command to specify a path with which to replace the PDP-11 device name. For example, “PDPPATH \ROM\” would cause the file DK:CODE.OBJ to be converted to \ROM\CODE.OBJ.

SETUP Sets up baud rates, printer type, and upload and download modes. See “The Q Setup Command” in “Tester Operation: The Q-Monitor” for details.

On-Line Help. The following command is available from the Q-Monitor:

HELP subject Displays on-line help for subject.

The HELP command displays on-line help concerning the requested subject. The Q-Monitor recognizes the following subject names:

BREAK Breakpoints PEM PEM commandsBSEARCH Binary searches PGM PGM commandsCAL Calibration PORT Tester port commandsCCL CCL PTG PTG commandsCHAR Characterization Q Q-MonitorDC DC control commands REG RegistersDOS DOS SELF SelfcheckFP Front panel commands 52TSC1 Q2/52 selfcheck module 1HOST Host commands 52TSC2 Q2/52 selfcheck module 2HP5370 HP-5370 counter setup instructions 52TSC3 Q2/52 selfcheck module 3LOAD Some load and execute comands 52TSC4 Q2/52 selfcheck module 4LOG Datalogging 52TSC5 Q2/52 selfcheck module 5LSEARCH Linear searches 62TSC1 Q2/62 selfcheck module 1MACRO Macros 62TSC2 Q2/62 selfcheck module 2

Serial Communication with the Tester. The tester number is saved in the file \PCHOST\Q.SET until it is changed again, so this command need only be used once.

Q Displays current tester port.Q 0 Changes to tester port LP2.Q 1 Changes to tester port COM1 (default).Q 2 Changes to tester port COM2.Q 3 Changes to tester port COM3.Q 4 Changes to tester port COM4.Q 5 Changes to tester port LPT1.

TESTER OPERATION - DOS, UNIX, and RT-11 Like Commands 189

DOS, UNIX, AND RT-11 LIKE COMMANDS

Commands Passed Directly to DOS. The following commands are available from the Q-Monitor. Specify additional arguments as required.

ATTRIB [arguments] Executes DOS ATTRIB command.DOS program [arguments] Executes program. Up to three additional arguments can be

passed.DIR [arguments] Executes DOS “DIR” command.MEM [arguments] Executes DOS “MEM” command to check memory usage. PATH [arguments] Executes DOS “PATH” command to display or set PATH

variable. REM [arguments] Executes DOS “REM” command to include a non-executing

comment in a batch file. TREE [arguments] Executes DOS “TREE” command to display the directory

structure of a disk or path.

Directory Manipulation Commands. The following commands are available from the Q-Monitor:

CHDIR Displays current directory.

CD directory Changes to directory.CHDIR directory Changes to directory.

MD directory Makes directory.MKDIR directory Makes directory.

PWD Print working directory.

RD directory Remove directory.RMDIR directory Removes directory.

File Manipulation Commands. The following commands are available from the Q-Monitor:

TYPE file Displays file.MORE file Displays file, pausing after each screenful.HEAD file Displays first 23 or 48 lines of file, depending on whether the

monitor is in 25- or 50-line mode, respectively.PRINT file Sends file to the printer. Note: If file is Bn, Dn, DAT, E, ERR, LN,

LST, M, R, S, V, or Wn (where n is a number), the PRINT command will be recognized as a tester command or a Q program command instead of a DOS command.

TESTER OPERATION - DOS, UNIX, and RT-11 Like Commands 190

COPY file1 file2 Copies file1 to file2.CP file1 file2 Copies file1 to file2.

REN file1 file2 Renames file1 to file2.

DEL file Deletes file.DELETE file Deletes file.ERASE file Deletes file.RM file Deletes file.

COMP file1 file2 Compares file1 to file2.FC file1 file2 Compares file1 to file2.

Miscellaneous Commands. The following commands are available from the Q-Monitor:

DATE Displays the date.TIME Displays time of day.PAUSE Pauses for return key to be pressed.CLS Clears screen.ECHO OFF Disables command echo.ECHO ON Enables command echo.HEXBIN file(s) Converts file(s) from Intel hexadecimal format to Q2 binary. Up to

four files can be specified.drive: Changes default drive to drive:.

TESTER OPERATION - Macros 191

MACROS

A macro is a sequence of commands. By defining macros for commonly used sequences of commands, tester operation may be simplified.

MACRO macro [parameters] Begins defining macro. Up to 15 parameters (^1 through ^9 and ^A through ^F) can be passed.

ENDMAC Ends macro definition.MACROFILE file Loads a file of macros.EXECUTE n macro Executes macro n times.MENU macro Executes macro until EXIT is not equal to 0.IF expression macro Executes macro if expression is true.IF expression variable=value Assigns value to variable if expression is true.MACROPRINT macro Displays macro.MACROPRINT Displays list of defined macros.

Macro Limits and Restrictions. The following general rules of macro usage apply:

· Up to 512 macros may be loaded at one time. They may be defined from the keyboard or loaded from one or more macro files.

· Each macro may be up to 32K bytes long.

· Since macros on the PC are stored in RAM for quick access, the total sum of all macros may not exceed available memory.

· Macros may be nested up to 8 levels deep.

· Macro calls may have up to 15 parameters (^1 through ^9 and ^A through ^F).

· Comments of the type (< ... >) within macros are displayed on the console during execution, and so are often used to direct an operator to perform a setup sequence before proceeding.

Macro Definition. Every macro definition begins with a MACRO command and ends with an ENDMAC command. Macros my be defined directly from the keyboard or may be loaded from a file with the MACROFILE or DO command.


Macro Parameters. Parameters passed in the macro call can be inserted into the macro when it is executed. For example, a macro named “CHECK” may include the following line in its definition:

S ^1.LST

If the “CHECK” macro is called with the command line:

CHECK TEMPDATA

The parameter “TEMPDATA” is substituted into the macro when executed, yielding the following:

S TEMPDATA.LST

The special parameter ^? causes the Q-Monitor to read a parameter (followed by an Enter) from the keyboard. For an example, see the sample macro at the end of this section.

Displaying Macros. The enhanced MACROPRINT command may be used to display a specified macro. With no parameters, MACROPRINT displays a list of all currently defined macros.

Macro Example. Here is a very simple example of a macro for production menus:


noechocls

macro MENU_LOTcursor 1 12assign LOT = ^?println 5 1 ' '

end

macro MENU_ERRORprintln 5 1 'Enter Lot Number Please'

end

macro MENU_SUMMARYS SUMMARY.LSTCOPY SUMMARY.LST LPT1

end

macro MENU_EXITassign EXIT=1

end

macro MENU_MAINwaitif (LINE=1) MENU_LOTif (LINE=2) & (LOT=0) MENU_ERRORif (LINE=2) & (LOT=1) MENU_SUMMARYif (LINE=3) MENU_EXIT

println 1 1 'Lot Number'println 2 1 'Summary'println 3 1 'Exit'

long LOT

menu MENU_MAIN

clsecho

SELFCHECK AND TIMING CALIBRATION - Introduction to Q2 Selfcheck 195

SELFCHECK AND TIMING CALIBRATION

INTRODUCTION TO Q2 SELFCHECK

Q2 Selfcheck is provided to exercise various tester components and to verify tester functionality. It is recommended that Selfcheck be run daily to verify that the Q2 is completely functional.

PC-Host Selfcheck tests the following test system components:

Programmable Timing GeneratorPattern Execution Module (Q2/62 only)Pattern Generator Module (Q2/52 only)Parametric UnitPower SuppliesPin ElectronicsPC-Host Computer

PC-Host Selfcheck consists of a series of numbered diagnostic tests of all the tester’s logic, memory, power supplies, and cable interfaces. The Selfcheck Test Listings in this section contain a complete list of all Selfcheck tests with their numbers and brief descriptions.

Selfcheck reports failing tests by test number. For each failing Selfcheck test, refer to the Selfcheck Test Listings to determine which board(s) might be causing the failure. Examine each suspect board for obvious problems, reseat it in the Q2 motherboard, and then run Selfcheck again. If the same Selfcheck test still fails, try swapping in spare boards one at a time, running Selfcheck after each, until you can identify the bad board. Continue until Selfcheck passes.

SELFCHECK AND TIMING CALIBRATION - Selfcheck Requirements 196

SELFCHECK REQUIREMENTS

Selfcheck: Calibration Status

The Q2 need not be deskewed before Selfcheck is run, but the PTG’s EPROMs must contain a valid Calibration Table. (The only exception is Q2/52 Selfcheck Module #3, which does require that the tester be deskewed.)

Selfcheck: Hardware Requirements

The computer and all interface ports and cables must be functioning properly. If they are not, Selfcheck may not be able to run.

Either one CSC40 loadboard or two Selfcheck load boards are required for both Q2/52 and Q2/62 Selfcheck, as follows:

CSC40 Load Board: All Q2/52 and Q2/62 Selfcheck and Calibrationprocedures

Selfcheck Load Board #1: Q2/62 Selfcheck Module #1Q2/52 Selfcheck Modules #1, #2, #3, and #5

Selfcheck Load Board #2: Q2/62 Selfcheck Module #2Q2/52 Selfcheck Module #4

For Q2/62s, a Selfcheck SRC is also required.

Selfcheck: Software Requirements

Q2/62 Selfcheck requires two modules; Q2/52 Selfcheck requires five modules. The following files are not supplied with the PC-Host software, but must be present in the \PCHOST directory:

Q2/62 only: Q2/52 only:62TSC1.OBJ or 62TSC1.BIN 52TSC1.OBJ or 52TSC1.BINZEROS.OBJ 52TSC2.OBJ or 52TSC2.BINONES.OBJ 52TSC3.OBJ or 52TSC3.BINADDBUS.OBJ 52TSC5.OBJ or 52TSC5.BINCOLUMN.OBJBITS.OBJRUN001.OBJRUN002.OBJRUN004.OBJSEQ.OBJ

SELFCHECK AND TIMING CALIBRATION - Running Selfcheck 197

RUNNING SELFCHECK

Follow this sequence of steps for each Selfcheck module.

1. Turn the Q2 power off.

2. Q2/62 only: remove the SRC from the tester and install the Selfcheck SRC.

3. Remove the load board from the tester and install the appropriate Selfcheck load board. The thumbwheel switch on Selfcheck load board #1 must be set to “F.”

4. Power up the tester.

5. Execute the appropriate Q command from the list below to load the desired Selfcheck module. A message will be displayed on the screen when the Selfcheck module has been loaded and begins execution.

(Selfcheck may also be run the “old” way: by entering “LOAD module” to load each Selfcheck module and then pressing the test button or entering T to execute it.)

Selfcheck Q Commands

The following commands are provided to execute the Selfcheck modules:

Selfcheck Q Command Description Load board

52TSC Loads and executes Q2/52 Selfcheck modules #1, #2, #3, #4, and #5

CSC40

62TSC Loads and executes Q2/62 Selfcheck modules #1 and #2 CSC4052TSC123 Loads and executes Q2/52 Selfcheck modules #1, #2, and #3 152TSC1 Loads and executes Q2/52 Selfcheck module #1 152TSC2 Loads and executes Q2/52 Selfcheck module #2 152TSC3 Loads and executes Q2/52 Selfcheck module #3 152TSC4 Loads and executes Q2/52 Selfcheck module #4 252TSC5 Loads and executes Q2/52 Selfcheck module #5 162TSC1 Loads and executes Q2/62 Selfcheck module #1 162TSC2 Loads and executes Q2/62 Selfcheck module #2 2CSC40 Loads and executes CSC40 Selfcheck CSC40

Each command loads the appropriate Selfcheck module, executes it once, and displays a summary. The results are also logged to a list file of the same name as the command, with the extension .LST. For example, the command 52TSC1 logs its results to the list file 52TSC1.LST.


Execute a Selfcheck Q command as follows:

C:\PCHOST > Q [At the DOS prompt in the \PCHOST directory, type Q.]

Q2> 62TSC1 [At the interactive monitor prompt (Q2>), type the name of the command. It is not necessary to use a .BIN or .OBJ extension.]

The following commands are provided for reviewing the results of Selfcheck modules after they are run. Each one reads the corresponding list (.LST) file and displays a pass/fail summary:

Selfcheck Review Q Command

Description

/52TSC1 Reads 52TSC1.LST and display pass/fail result./52TSC2 Reads 52TSC2.LST and display pass/fail result./52TSC3 Reads 52TSC3.LST and display pass/fail result./52TSC4 Reads 52TSC4.LST and display pass/fail result./52TSC5 Reads 52TSC5.LST and display pass/fail result./62TSC1 Reads 62TSC1.LST and display pass/fail result./62TSC2 Reads 62TSC2.LST and display pass/fail result.

These Selfcheck review commands are executed from the interactive monitor prompt (Q2>) in the same manner as the Selfcheck commands shown above. The /52TSCn and /62TSCn commands also log status messages to the datalogging ERR file, if one is open. (See the section on datalogging for more information on ERR files.)

CSC40 Load Board Commands

The CSC40 load board can be used for all Q2 Selfcheck and timing calibration procedures described in this section. It replaces Selfcheck load boards #1 and #2 and the Cal Mux load board.

Troubleshooting

Occasionally, the system control board may be malfunctioning and preventing Selfcheck from loading or executing properly. To test the system control board’s memory (both RAM and ROM):

1. Make sure that the computer is up and running the interactive monitor (Q).

2. Power down the tester.

3. While holding down the RETEST switch on the front panel, power the tester back up again.


Any memory problems detected will be displayed on the screen. This test takes about 30 seconds.

SELFCHECK AND TIMING CALIBRATION - Selfcheck Test Listings 200

SELFCHECK TEST LISTINGS

Test Listing for Q2/62 Selfcheck Module #1

Test # Description and Possible Causes of Failure

PEM tests begin here. Set Selfcheck load board #1 ID to “C,” “F,” or “1.”

11–12 Basic CPU and I/O test—checks that the PEM can communicate with the Q2. This test will not fail, but the tester will hang and stop testing if there is a problem. If this happens, the following boards could be at fault: system control card, buffer board, PEM, or Q2 back plane. Power down the tester and reseat these boards in the back plane, then run Selfcheck again.

13 PEM operating system checksum verification—executes the OSCHECKSUM command. Cause of failure: PEM microprocessor card.

14 Checks the PEM’s CPU RAM (user area only). Cause of failure: PEM microprocessor card.15 Address sequencer read/write test. Cause of failure: PEM.16 Test of entire pattern memory (march test)—executes the MEMORYCHECK command.

Cause of failure: PEM.21 Test of loading simple pattern. Causes of failure: PEM, cables, or PC-Host computer. Error

messages on the screen may help localize the problem.22 Memory check of first pattern load (checksum). Causes of failure: same as #21.23–26 Pattern load and load check of files. Causes of failure: same as #21.27 Test of a pattern-save execution. Causes of failure: same as #21.28 Reloads pattern just saved. Causes of failure: same as #21.29 Causes the PC-Host to execute its “POBSELFCHECK.” This test is only selected if the

Selfcheck load board #1 ID is “C.”30–31 Provides setup conditions for tests that follow.32 PEM stop-bit check, first run of pattern, first use of master clock on PEM. Causes of failure:

PEM sequencer logic, or completely nonfunctional PTG.33 Load of complex pattern with loops. Cause of failure: PEM.34 Checks out loop counters. Cause of failure: PEM.35 Checks out address sequencer during loops. Cause of failure: PEM.41 Checks out PEM-to-SRC interface and SRC Port A for read/write integrity. Cause of failure:

PEM.42 Checks out PEM-to-SRC interface and SRC Port B for read/write integrity. Cause of failure:

PEM.43 Checks that all 96 pipeline latch bits will toggle. Cause of failure: PEM.44–48 Checks FPORTA (Port 10) and FPORTB (Port 11) for read/write integrity. Causes of failure:

PEM, PTG buffer board, SRC.


Tests 63–79: System Power Supply tests. Q2/62 Selfcheck Module #1

63 Supply: GROUND Problem: too high Tolerance: +100mV64 Supply: GROUND Problem: too low Tolerance: -100mV66 Supply: +5v Problem: too high Tolerance: +300mV67 Supply: +5v Problem: too low Tolerance: -200mV69 Supply: +12v Problem: too high Tolerance: +200mV70 Supply: +12v Problem: too low Tolerance: -200mV72 Supply: +28v Problem: too high Tolerance: +200mV73 Supply: +28v Problem: too low Tolerance: -200mV75 Supply: -12v Problem: too high Tolerance: +200mV76 Supply: -12v Problem: too low Tolerance: -200mV78 Supply: -24v Problem: too high Tolerance: +200mV79 Supply: -24v Problem: too low Tolerance: -200mV

Tests 80–88: VPP tests

80 Sets VPP to 5 volts81 Connects VPP82 Fails if VPP > 5.26 volts83 Fails if VPP < 4.74 volts84 Sets VPP to 25 volts85 Fails if VPP > 26 volts86 Fails if VPP < 24 volts87 Sets VPP to 5 volts88 Disconnects VPP

Programmable Timing Generator (PTG) tests begin here. Set the Selfcheck load board #1 ID to “D,” “F,” or “1.” (There are 24 TGs, as follows: TGs 1–14 are single-cycle; TGs 15–24 are multiple-cycle.)

Tests 89 though 954 check the PTG for complete functionality. Should any of these tests fail, power down the tester, remove the Selfcheck SRC and the PEM. Reset the PTG by pulling up on the black ZIF connector handle (located on the right side of the tester next to the PTG), and by pulling up on the PTG. Reassemble the tester and rerun Selfcheck. If it consistently fails at the same test, the PTG is probably bad.

89–90 Initializes the user area of CPU memory table on the PEM for use in timing generator tests. Causes of failure: Blank PTG calibration table in PTG EPROMs, system bus contention.

91 Checks basic operation plus early/late bits on all 24 TGs. With channels off, check for zeros.92 Checks basic operation plus early/late bits on all 24 TGs. With channels off, check for ones.101–124 Checks for a high output with enable-high on all 24 TGs151–174 Checks for edges with enable-low on all 24 TGs.201–224 Checks for a high with enable-high and ENC active.251–274 Checks for edges with enable-low and ENC active.301–324 Checks all TGs for edges on Ramp 0.351–374 Checks all TGs for different edges on Ramp 0.401–424 Checks all TGs for different edges on Ramp 0.451–474 Checks all TGs for edges on Ramp 1.


501–524 Checks all TGs for different edges on Ramp 1.551–574 Checks all TGs for different edges on Ramp 1.601–624 Checks all TGs; start Ramp 0, stop Ramp 1.651–674 Checks all TGs; enable-clocked by T-zero’s rising edge.701–724 Checks all TGs; enable-clocked by T-zero’s failing edge.751–774 Checks all TGs; start Ramp 1, stop Ramp 0.801–824 Checks all TGs; enable-clocked by T-zero’s rising edge.851–874 Checks all TGs; enable-clocked by T-zero’s failing edge.905–914 Checks out TGs 15–24 over 16 cycle boundaries.915–924 Checks out TGs 15–24 over 13 cycle boundaries.925–934 Checks out TGs 15–24 over 11 cycle boundaries.935–944 Checks out TGs 15–24 over 0 cycle boundaries.945–954 Checks out TGs 15–24 over 16 cycle boundaries.

NOTE: Test numbers restart at 401 here. Q2/62 Selfcheck Module #1

Mainframe tests begin here. Set the Selfcheck load board #1 ID to “E,” “F,” “0,” or “1.”

Tests 401–416 check for leakage with the drivers on and off. Causes of failure: Selfcheck load board, front panel board, pin electronics cards, PMU, Q2/62 back plane.

401–406 Leakage. Disconnect drivers by PE analog switches. Force six voltages: 20v, 15v, 10v, 5v, 0v, and -5v.

411–416 Leakage. Disconnect one driver, connect the other 39 drivers. Force six voltages: 20v, 15v, 10v, 5v, 0v, and -5v.

421 Low leakage and PARCAL. Disconnects drivers by PE analog switches. Forces -5v, 0v, +5v, +10v, +15v, +20v; checks to see if any of the 40 channels are exceeding ±250na by using the voting algorithm and storing the leakage current value into an offset table.

422 Low leakage and IACC75. Disconnects drivers by PE analog switches. Forces voltages from -5v to +20v in 1-volt increments; checks to see if any of the 40 channels are exceeding ±75na by using the voting algorithm only.

423 Low leakage and IACC10. Disconnects drivers by PE analog switches. Forces voltages from -5v to +20v in 1-volt increments; checks to see if any of the 40 channels are exceeding ±10na by using the voting algorithm and the offset table.

441–442, Verify the ability of the PTU to select pins, one at a time, via the front panel. These tests 451–452 multiplex and test for the resistor on that pin. They force negative current, then test voltage to

be less (test #441) or greater (test #442) than the programmed value. They force voltage, then test current to be within the negative current limit (test #451) or not within the current limit (#452). Causes of failure: PMU, front panel, back plane.

Tests 461–468 check the PEL array and pin electronics. Causes of failure: Selfcheck load board, PEM, pin electronics boards, buffer board (on PTG), Q2/62 back plane, PS1 board.

461–464 Verifies driving PEL low, PELX high, PEL high, and PELX low.465–466 Checks for PEL-to-PES and PELD-to-PELC shorts.467–468 Checks for PEE tri-state.

Tests 501–561 check the power supply 2 board. Causes of failure: power supply 2 board, Selfcheck load board, front panel board, Q2/62 back plane.

501–506 V1 current detect.511–516 V2 current detect.


551–561 V3 current detect.

Q2/62 Selfcheck Module #1Tests 601–634 are pin electronics board tests. Causes of failure: PE boards, power supply 1 board, Selfcheck load board, Q2/62 back plane. There are 10 PE channels per PE board, as follows:

PE board 1: channels 1–5, 11–15PE board 2: channels 6–10, 16–20PE board 3: channels 21–25, 31–35PE board 4: channels 26–30, 36–40

601–610 Tests low-level driver accuracy, all 40 PE channels.611–620 Tests high-level driver accuracy, all 40 PE channels.621–630 Comparator input current, drivers tri-stated.631–634 50-Ohm driver output impedance checks.

Tests 701–770 continue the PE tests. Causes of failure: PE board, Selfcheck loadboard, PEM, Q2/62 back plane.701–732 Comparator functional tests.741–760 Comparator precision DC accuracy tests.761–770 PEL, PELX, PEE, PELC, and PELD walk tests.

Tests 771–780 verify dual comparator accuracy. These tests check whether a voltage VPAR programmed above VOL and below VOH will not produce an error on any pin.

771–780 Drivers off, expect zero, VPAR values -1.70v, -0.74v, -0.24v, 0.76v, 1.26v, 1.76v, 2.26v, 2.76v, 3.76v, 4.76v.

Tests 781–790 force fail data for VOH comparator accuracy. These tests check whether a voltage VPAR programmed above VOL and below VOH will not produce an error on any pin.

781–790 Drivers off, expect one, VPAR values -1.70v, -0.74v, -0.24v, 0.76v, 1.26v, 1.76v, 2.26v, 2.76v, 3.76v, and 4.76v.

Tests 791–800 force fail data for VOL comparator accuracy. These tests check whether a voltage VPAR programmed above VOL and below VOH will not produce an error on any pin.


Tests 801–810 force pass data for VOL comparator accuracy. These tests check whether a voltage VPAR programmed below VOL and below VOH will not produce an error on any pin.


Tests 811–820 force pass data for VOH comparator accuracy. These tests check whether a voltage VPAR programmed above VOL and above VOH will not produce an error on any pin.

811–820 Drivers off, expect one, VPAR values -1.70v, -0.74v, -0.24v, 0.76v, 1.26v, 1.76v, 2.26v, 2.76v, 3.76v, and 4.76v.

End of Test Listing for Q2/62 Selfcheck Module #1.



Tests 31–52 are PEM sequencer tests. Causes of failure: PEM.

31 PEM setup for sequencer tests; enable pattern run circuitry.32 Loads RUN003.OBJ, puts no-ops in addresses 0 to FFE.33 Address incrementer test. Checks to see that the address sequencer will run a pattern through

all 4096 addresses.34 Pattern sequencer “STOP” execution.35 Tests write/read of burst and loop counters (file RUN004.OBJ).36 Checks that loop counters do not engage when inactive, and that loop counters can be set to

00.37 PEM self-test pattern for checking out pipeline latches.38 Verifies sequencer loop logic. Verifies that outer loop will execute a full 257-count loop

correctly. Also verifies that the outer loop counter start address latch will hold a 000.39–43 Checks that the outer loop will return to start addresses FFF, 333, 555, 050, F0F.44 Verifies that the inner loop will execute a full 257-count loop correctly. Also verifies that the

inner loop counter start address latch will hold a 000.45–49 Checks that the loop will return to start addresses FFF, 333, 555, 0F0, and F0F.50 Checks clock burst operation. Checks that it will execute a full 257-count burst correctly.51–52 Checks squared-loop and sync-loop operation.

End of PEM sequencer tests. Q2/62 Selfcheck Module #2

Tests 801–854 check the Parametric Test Unit. Causes of failure: Selfcheck load board, PTU board, Q2/62 back plane. (Use Selfcheck load board #2 only.)

801–824 PTU accuracy: force voltage.831–854 PTU accuracy: force current.

End of parametric board check tests.

Tests 901–942 check the accuracy of the high and low clock rails and the VBIAS supply on the power supply 1 board. Causes of failure: power supply 1 board, parametric board, Selfcheck load board, Q2/62 back plane.

901–916 VIHC accuracy.921–930 VILC accuracy.931–942 VBIAS accuracy.

Tests 951–979 check the current detect circuits on the power supply 2 board. Causes of failure: power supply 2 board, parametric board, Selfcheck load board.

951–954 V1 current detect accuracy.955–956 V1 opens.961–964 V2 current detect accuracy.965–966 V2 opens.971–976 V3 current detect accuracy.977–979 V3 opens.981-986 Verifies the maximum currents that may be drawn from V1, V2 and V3.




Tests 51–53: System Power Supply tests.

51 Supply: 28V Problem: too high Tolerance: +200mV52 Supply: 28V Problem: too low Tolerance: -200mV53 Supply: -24V Problem: too high Tolerance: +200mV54 Supply: -24V Problem: too low Tolerance: -200mV55 Supply: -12V Problem: too high Tolerance: +200mV56 Supply: -12V Problem: too low Tolerance: -200mV57 Supply: 12V Problem: too high Tolerance: +100mV58 Supply: 12V Problem: too low Tolerance: -100mV59 Supply: 5V Problem: too high Tolerance: +150mV60 Supply: 5V Problem: too low Tolerance: -200mV61 Supply: Vpp @ 5V Problem: too high Tolerance: +260mV62 Supply: Vpp @ 5V Problem: too low Tolerance: -260mV63 Supply: Vpp @ 25V Problem: too high Tolerance: +1000mV64 Supply: Vpp @ 25V Problem: too low Tolerance: -1000mV.

Test 66: PTG tests.

66 PTG O.S. checksum test.

Tests 71–157: PGM tests.

71 Checks test block port.72 Executes Q instruction buffer.76 Causes error on PGM error line.77 Resets PGM error line.81 PGM O.S. checksum test.82 PGM RAM test.86 Forces MAR values.87 Runs a march on all microRAM.88 Tests single-step ability in PGM.91–93 Tests INC, JUMP, and GOSUB instructions in MAR.94 Tests stack RAMs.95 Tests loop counters.96–100 Tests counter/reload registers A–E.101 8086 load of counter/reload register.102 Tests ALU NOCOUNT instruction.103 Tests counter/comparator ALUs.104 Loop counter auto-reload test.106–109 Tests BADCC PROM.111 Conditional JUMP with no error.112–113 Tests CJMPE and CJMPNE, error true.114 Conditional call with no error.


115–116 Tests CSUBE and CSUBNE, error true.117 Conditional return with no error.118–119 Tests CRETE and CRETNE, error true.121 Interrupt address register test.122 Conditional BRANCH/FALSE with INT.123 GOSUB/return with interrupts.124 JUMP/CALL address to stack.126 Tests interrupt timer accuracy.127–128 Checks to verify that the timer times out before loop counter decrements to 0.129–130 Checks to verify that loop counter decrements to 0 before timer times out.131–133 Tests YMAIN, XMAIN, XOUT, YOUT; XBASE and YBASE; FIELD address registers.134–135 Microdata inputs and address out path in Address Generator.136 Initial condition load clocks.137 Tests Address Generator address masks.138 Tests sets on address-out F/F's.139 Tests carries in Address Generator.140 MAX detect in Address Generator.141 Address Generator MAX detect.142 Tests all remaining ALU functions.151 Tests JAM register and 74S135s.152 Tests portion of equality functions.153 Tests the A<B and A>B outputs plus YEQB and XEQB signal paths.154 Fast AXIS equality functions.156 Data Topo RAM inversion tests.157 Runs a march pattern on the Data Topological Inversion RAMs.

Tests 976–985: PTG tests. Q2/52 Selfcheck Module #1

976–977 Tests edge detect F/F’s high and low.978 Tests for 24R Q outputs high.979–985 Tests PTG ramps and channels for basic function in seven ranges: 6400 ns, 3200 ns, 1600 ns,

800 ns, 400 ns, 200 ns, and 100 ns.

End of Test Listing for Q2/52 Selfcheck Module #1



141 Walks a 1 across the previous MAR and DATA of the error pipeline.142 Walks a 1 across the previous X and Y address fields.143 Walks a 0 across the DATA and MAR portions of the error pipeline.144 Walks a 0 across the previous X and Y address fields.151 Checks the DC function of the topological scramblers.152 Static check of scramblers using PGM addresses.


153 March pattern on topological address scramblers.

Q2/52 Selfcheck Module #2

Note: All true test block failures from here on will require that the tester be power-cycled before retest.

Tests 201–316: PGM, Pin Electronics tests.

201–280 Verifies that pin electronics channels 12B5, 12B9, 12C5, 12C9, 12D5, 12D9, 12E5, 12E9, 12F5, 12F9, 12G5, 12G9, 12H5, 12H9, 12J5, 12J9, 12K5, 12K9, 12L5, 12L9, 12M6, 12M8, 12N6, 12N8, 12P6, 12P8, 12Q6, 12Q8, 12R5, 12R9, 15N14, 15P14, 15Q14, 15R14, 15T14, 15S14, 18Q3, 18Q6, 18Q8, and 18Q11 are high while all other channels are low.

281–316 Checks function codes 1 and 5; microinstructions 0–7; PEL low and high.


321–330 Verifies that CS1, CS2, CS3, CS4, and CS5 are high while other remaining CS are low.331 Verifies that CS PEL are low without the pattern running.332 All chip selects true.333–342 Tests each CS (1–5) for high level; test remaining CS for low level.381 Walks a 1 and 0 across LBDATA latches.382 Tests LBDATA pipeline.

Mainframe tests begin here.

Tests 401–423 are Pin Electronics leakage tests. They check for leakage on the Pin Electronics channels with the drivers first connected and then disconnected except for the driver under test. Causes of a failure: Selfcheck load board, front panel, Pin Electronics boards, PTU, backplane.

401–406 Leakage, drivers disconnected by PE analog switches; VPAR=20v, 15v, 10v, 5v, 0v, and -5v.411–416 Leakage, one driver disconnected, the other 39 connected; VPAR= 20v, 15v, 10v, 5v, 0v, and

5v.421–423 Leakage, -5V to 20v: PARCAL, IACC75, and IACC10 on all 40 channels.

Tests 441–452: PTU accuracy tests. Cause of failures: PTU, front panel, backplane.

441 Forces negative current-test voltage to be less than programmed amount.442 Forces negative current-test voltage to be greater than programmed amount.451 Forces voltage; pass if in negative current limit.452 Forces voltage; pass if not in current limit.

Tests 501–561: DUT Power Supply tests. Cause of failures: power supply 2, Selfcheck load board, front panel, backplane.

501–506 V1 supply current detect.511–516 V2 supply current detect.521–526 V2 supply current detect.551–561 V3 supply current detect.



Tests 601–630 are Pin Electronics tests. Causes of failures: PE boards, power supply 1, Selfcheck load board, PGM or Q2 backplane. There are 10 PE channels per PE board, as follows:

PE board 1: channels 1–5, 11–15PE board 2: channels 6–10, 16–20PE board 3: channels 31-35, 21-25PE board 4: channels 36-40, 26-30

601–610 Tests low level driver accuracy, all 40 PE channels.611–620 Tests high level driver accuracy, all 40 PE channels.621–630 Comparator input current, drivers tri-stated.

Tests 631–700: PGM and PTG.

631–634 Checks 50-Ohm driver output impedance.641 Tests channels for tri-state with TG14 high.642 Tests channels for drive received while TG14 is low.643 Verifies no tri-state while TG14 is high.644 Verifies all channels driving while TG14 low.645–647 Tests for tri-stated data lines while TG14 is low, tri-stated upper data lines and driving lower

data lines.648–649 No tri-state; no driver (TG14 high).650 Address tri-stated with TG14 low.651 CS lines still driving.652–654 Address lines driving and receiving.655–662 Verifies CS1A, CS1B in tri-state; CS2-CS4 driving; CS2A, CS2B in tri-state; CS1, CS2, CS4

driving; CS3A,CS3B in tri-state; CS1, CS2, CS4 driving; CS4A, CS4B in tri-state; and CS1-CS3 driving.

663–670 CS1 is driving; CS2-CS4 are tri-stated; CS2 is driving; CS1, CS3, CS4 are tri-stated; CS3 is driving; CS1, CS2, CS4 are tri-stated; CS4 is driving; and CS1, CS2, CS3 are tri-stated.

671–676 All CS lines tri-stated while TG2, TG3, TG4, TG5, TG11, and TG12 is high.677–682 CS1 should tri-state with TG2, TG3, TG4, TG5, TG11, and TG12 low.683–688 CS2 should tri-state with TG2, TG3, TG4, TG5, TG11, and TG12 low.689–694 CS3 should tri-state with TG2, TG3, TG4, TG5, TG11, and TG12 low.695–700 CS4 should tri-state with TG2 , TG3, TG4, TG5, TG11, and TG12 low.

Tests 701–770 continue the PE tests. Causes of failure: PE board, Selfcheck load board, Q2 back plane.

Tests 701–732 are comparator functional tests.

701–704 Verifies that no error occurs when strobe TG is disabled and strobes are masked.711–712 Strobes all data and address lines while forcing pass data low and high.721–722 Forces error on one pin at a time, expect high and low.731 Strobes all pins that have pass data.732 Forces fail data on one pin at a time, then strobe all pin with pass data.



Tests 741–761 are comparator DC accuracy tests. VPAR is used to force voltage on the data pins. Each of the 16 PE channels assigned as a receive channel is tested individually. If a channel fails a test (no error generated) the number of the failed channel appears in the UNITS PASSED display on the front panel.

741–750 Forces a failure on one pin at a time, checking that an error will be generated if a voltage greater than VOUT is forced on a data pin when the expected data is 0.

751–759 Forces a failure on one pin at a time, checking that an error will be generated if a voltage less than VOUT is forced on a data pin and the expected data is 1.

760 Forces a failure on one pin at a time to fail by driving it just below the comparator threshold with the PTU.

761 Verifies inhibit errors (FDMI) functions properly.

Tests 771–780 are dual comparator functional tests. They check whether a voltage (VPAR) programmed above VOL and below VOH will produce an error on only the pin under test. The pin electronic drivers are turned off. Each of the PE channels assigned to receive data is strobed individually. If a PE channel fails a test (no error is generated) the number of the failed channel is shown in the UNITS PASSED display on the front panel.

Expected Data VOH VOL VPAR771 0 -1.40v -1.50v -1.45v772 1 1.40v -1.50v -1.45v773 0 0.05v 0.05v 0.00v774 1 0.05v -0.05v 0.00v775 0 1.80v 1.70v 1.75v776 1 1.80v 1.70v 1.75v777 0 3.55v 3.45v 3.50v778 1 3.55v 3.45v 3.50v779 0 5.05v 4.95v 5.00v780 1 5.05v 4.95v 5.00v

Tests 781–790 are force-fail-data, VOH-comparator accuracy tests. They check that a voltage VPAR programmed below VOH but above VOL will produce and error on only the pin under test. The pin electronic drivers are turned off.

Expected Data VOH VOL VPAR781 1 -1.40v -1.50v -1.45v782 1 0.45v -0.55v -0.50v783 1 0.05v 0.05v 0.00v784 1 1.05v 0.95v 1.00v785 1 1.55v 1.45v 1.50v786 1 2.05v 1.95v 2.00v787 1 2.55v 2.45v 2.50v788 1 3.05v 2.95v 3.00v789 1 4.05v 3.95v 4.00v790 1 5.05v 4.95v 5.00v



Tests 791–800 are force-fail-data, VOL-comparator accuracy tests. They check that a voltage VPAR programmed above VOL but below VOH will produce an error on only the pin under test. Pin electronics drivers are turned off.

Expected Data VOH VOL VPAR791 0 -1.40v -1.50v -1.45v792 0 0.45v -0.55v -0.50v793 0 0.05v 0.05v 0.00v794 0 1.05v 0.95v 1.00v795 0 1.55v 1.45v 1.50v796 0 2.05v 1.95v 2.00v797 0 2.55v 2.45v 2.50v798 0 3.05v 2.95v 3.00v799 0 4.05v 3.95v 4.00v800 0 5.05v 4.95v 5.00v

Tests 801–810 are force-pass-data, VOL accuracy tests. They check whether a voltage VPAR programmed below VOL and VOH will not produce an error on any pin. Only the pins specified in the current pin list will be forced by VPAR.

VOH VOL VPAR801 -1.42v -1.50v -1.62v802 -0.48v 0.50v -0.62v803 0.08v 0.00v -0.12v804 1.08v 1.00v 0.88v805 1.58v 1.50v 1.38v806 2.08v 2.00v 1.88v807 2.58v 2.50v 2.38v808 3.08v 3.00v 2.88v809 4.08v 4.00v 3.88v810 5.08v 5.00v 4.88v

Tests 811–820 are force-pass-data, VOH-comparator accuracy tests. They check whether a voltage VPAR programmed above VOL and VOH will not produce an error on any pin. Only the current pins specified in the pin list will be forced by VPAR.

VOH VOL VPAR811 -1.42v -1.50v -1.30v812 -0.50v 0.58v -0.38v813 0.00v -0.08v 0.12v814 1.00v 0.92v 1.12v815 1.50v 1.42v 1.62v816 2.00v 1.92v 2.12v817 2.50v 2.42v 2.62v818 3.00v 2.92v 3.12v819 4.00v 3.92v 4.12v820 5.00v 4.92v 5.12v

Tests 821–964: PGM and PTG tests.

821–824 Strobes CS1B–CS4B, expect a failure; verify other CS lines were not strobed.825–832 Strobes CS1A–CS4A and CS1B–CS4B, expect a pass; verify other CS lines were not strobed.833–856 Strobes CS1A, CS2A, CS3A, and CS4A with TG2, TG3, TG4, TG5, TG11, and TG12.861–864 Checks over-programming’s and under-programming’s ability to control and mask strobes.865 Verifies that normal read works regardless of data into over/under bit circuit.


866 Verifies that the upper 8 bits of the OVUND bus are always disabled when not in mode 3.871–878 With rail 1 and 2 and forced 0 and 1 channels should be below and above VPAR.881 Checks Row and Column Error Catch RAM address lines via error address.882 Verifies ability to insert to the Error Catch RAMs.883 Tests ability to reset error line from both the microcode and error catch mode.884 Checks Row and Column Error Catch RAMs.885 Checks the error counters for the ability to load and independence of the output pins.886 Verifies operation of Error Catch circuit during patterns.887 Verifies ability of Row and Column Error Catch RAMs to mask off strobe.888 Verifies ability of circuit to catch errors.889 Checks stop-on-error capability of error pipe.

Tests 951–964: System Power Supply tests. Q2/52 Selfcheck Module #2

951 Tests 28v supply to be less than 28.2v.

952 Tests 28v supply to be more than 27.8v.

953 Tests -24v supply to be less than -23.6v.

954 Tests -24v supply to be more than -24.4v.

955 Tests -12v supply to be less than -11.6v.

956 Tests -12v supply to be more than -12.4v.





961 Tests Vpp is less than +5.26v.

962 Tests Vpp is more than +4.74v.

963 Tests Vpp is less than +26v.

964 Tests Vpp is more than +24v.



Tests 101–117: PTG.

101–102 Tests edge detect F/F’s high and low.103 Tests for 24R Q outputs high.104–117 Tests PTG ramp 0–1, 6400, 3200, 1600, 800, 400, 200, and 100 ns ranges.

Tests 201–216: PGM, Data Register Board. Q2/52 Selfcheck Module #3

201 Checks for data generator ID.202 Walks a 1 across the data register and dataout.203 Checks the data register rotate functions.


204 Checks the shift functions of the data register.205 Tests the ability of the data register to complement its contents.206 Checks the increment and decrement functions of the data register.207 Tests all data register functions with data register configured two 4 bit halves.208–209 Walks a 1 and a 0 across the index register.210 Walks a 1 and a 0 across the X and Y address lines while verifying the correct outputs from

the index ALU’s.211 Checks the index register’s ability to count up and down.212 Checks the independence of BIT1 and BIT2 background functions.213 Walks a 1 across the address lines.214 Checks basic function of the background functions.215–216 Walks a 1 across the Y and X addresses to check bit independence of the parity generators.

Tests 301–388: PGM, Buffer Memory Piggyback tests.

301 Checks to see if Buffer Memory Board is present.302–305 Walks a 1 across the lower 4 bits, bits 4-7, bits 8-11, and upper 4 bits of the Buffer Memory

RAM.306 Walks a 1 and a 0 across the RAM address lines, using both the PGM addresses and Buffer

Memory segment masks.307 Verifies the functionality of the Buffer Memory in an 8 bit wide configuration.308 Buffer Memory march pattern to complete the check of RAM.351 Checks to see if Error Catch Board is present.352 Performs march test on the Error Catch RAM.353–368 Tests the Error Catch RAM’s write-enable WE0–WE15.369 Completes the error address independence tests.370 Checks the speed of the address lines and Error Catch RAM by running a pattern that utilizes

many address inversions. A failure can be the result of slow RAMs or slow address buffers on the Error Catch Board or slow address latches on the PGM.

371–373 Tests single, dual, and triple error catching.374 Tests the address and RAM speed of the Error Catch Board.375–386 Verifies that Segmasks 0–11 on the Error Catch Board can go high.387 Performs a march test on the Topological Scramble RAMs located on the Error Catch Board.388 Tests the bit map display communications port if bitmap board is present.

Tests 401–427: PGM, High Voltage Module tests.

401 Checks to see if High Voltage Module is present.402–403 Sets up and checks the ability of VRAIL to tri-state.404–409 Checks VRAIL to be below 5.2v, above 4.8v, below 12.7v, above 12.3v, below 24.2v, and

above 23.8v.410 Checks VRAIL without boost VRAIL for less than 28v.411–412 Checks VRAIL to be below 32.96v and above 32.56v.413 Pulse not enabled, so VPULSE should be below .4v.414–421 Checks VPULSE to be below 5.56v, above 4.6v, below 12.9v, above 12.1v, below 25.4v,

above 24.6v, below 30.4v, and above 29.6v.422–427 Checks IRAIL detect accuracy IRAIL=1.55mA; 1.45mA, expect fail; 4.55mA; 4.55mA,

expect fail; 9.93mA; 9.83mA, expect fail.


Tests 501–509: PGM tests. Q2/52 Selfcheck Module #3

501 Tests the increment instruction in the MAR.502 Verifies the operation, at 10 MHz, of each loop counter.503 Checks functionality of the interrupt timer, also provides second check of loop counter

function.504 Tests GOSUB and RETURN circuits at full speed, includes MAR and STACK functions.505 Checks conditional GOSUBs and RETURNs at full speed.506 Checks microprogram enabling of timer interrupts.507 Tests address ALUs and carries with the decrement function.508–509 Tests address maximum and minimum detect.

Tests 601–754: PGM (lower board) tests.

601 Checks lower board inversion functions.602–604 Verifies forced inversion, microdata inversion, and function inversion reached pipeline level

4.605 Verifies no inversion occurred.606 Verifies Chip Select polarities reach device level at 10 MHz.651 Checks equality functions.652–653 Formatter shift registers clocked at maximum rate with 1 AS data and with 0 AS Data.654–655 Pulse width tests for formatters A-E and for all non-CS PELs.656 Checks speed of error pipe and Error Catch circuit.701 Checks speed of background inversion functions.702 Verifies index register finished at correct value and created a data inversion.703 Verifies that with a different final value, index register did not create a data inversion.704 Verifies data register functions At 10 MHz.705 Verifies a single cycle inversion from the background functions can reach pipeline level 4 at

10 MHz.706 Verifies a single cycle change in data polarity in the data register can propagate through

pipelines 3 and 4.751 Verifies background function at 10 MHz.752 INDEX register function and inversion at 10 MHz.753 Checks data register data bus speed by shifting zeroes into the register and verifying the

output.754 Checks the speed of the data generator output 374s at 10 MHz enabled 1 cycle only.

Tests 801–852: PGM, PE card tests.

801–802 Verifies single cycle of low and high data reached PELs from the DBM.851 Checks Buffer Memory addressing and Chip Selects at 10 MHz.852 Checks the ability of Buffer Memory Output ALS374s to be enabled on the fly at 10 MHz.




Tests 801–834: PTU accuracy tests.

801–824 PTU accuracy, force voltage.831–854 PTU accuracy, force current.

Tests 901–942: Power Supply 1, PTU tests.



951–954 V1 current detect accuracy.955–956 V1 opens.961–964 V2 current detect accuracy.965–966 V2 opens.971–976 V3 current detect accuracy.977–979 V3 opens.981–986 Verifies maximum currents that can be drawn from V1, V2, and V3.



Tests 301–308: PGM, Buffer Memory Piggyback tests.

301 Checks to see if Buffer Memory Board is present.302–305 Walks a 1 across the lower 4 bits, bits 4-7, bits 8-11, and the upper 4 bits of the Buffer

Memory RAM.306 Walks a 1 and a 0 across the RAM address lines, using both the PGM addresses and Buffer

Memory segment masks.307 Verifies the functionality of the Buffer Memory in a 8 bit wide configuration.308 Buffer Memory march pattern to complete the check of RAM.

Test 401: Miscellaneous new tests.

401 Verifies that FUNTEST EXQ, NOERROR works.

Tests 801–802; 851–852: PGM, PE card.

801–802 Verifies single cycle of low and high data reached PELs from the DBM.851 Checks Buffer Memory addressing and Chip Selects at 10 MHz.852 Checks the ability of Buffer Memory output ALS374s to be enabled on the fly at 10 MHz.



Test Listing for Q8000 Selfcheck

Tests 401–416: Checks for leakage with the drivers on and off. Causes of failure: Selfcheck load board, front panel board, pin electronics cards, PMU, back plane.

401-406 Leakage. Disconnect drivers by PE analog switches. Force six voltages: 20v, 15v, 10v, 5v, 0v, and -5v.

411-416 Leakage. Disconnect one driver, connect the other 39 drivers. Force six voltages: 20v, 15v, 10v, 5v, 0v, and -5v.

441–442, Verify the ability of the PTU to select pins, one at a time, via the front panel. These tests 451–452 multiplex and test for the resistor on that pin. They force negative current, then test voltage to

be less (test #441) or greater (test #442) than the programmed value. They force voltage, then test current to be within the negative current limit (test #451) or not within the current limit (#452). Causes of failure: PMU, front panel, back plane.

Tests 501–561: DUT Power Supply tests. Cause of failures: power supply 2, Selfcheck load board, front panel, backplane.

501–506 V1 supply current detect.511–516 V2 supply current detect.551–561 V3 supply current detect.Tests 601–754 are pin electronics board tests. Causes of failure: PE boards, power supply 1 board, Selfcheck load board, back plane. There are 10 PE channels per PE board, as follows:

PE board 1: channels 1–5, 11–15PE board 2: channels 6–10, 16–20PE board 3: channels 21–25, 31–35PE board 4: channels 26–30, 36–40

601–606 Tests low-level driver accuracy, all 40 PE channels, VIL connected.611–614 Tests high-level driver accuracy, all 40 PE channels VIH connected.621–624 Tests comparator input current, drivers tri-stated.631–634 Checks 50-Ohm driver output impedance.701–704 Comparator, force pass data, no strobes.711–712 Comparator, force pass data, strobe each pin.721–722 Comparator, force fail data, strobe each pin.731–732 Comparator, force fail data, strobe each pin.741–754 Comparator, VOUT accuracy tests.

Tests 801–834: PTU accuracy tests.

801–824 PTU accuracy, force voltage.831–854 PTU accuracy, force current.




951–954 V1 current detect accuracy.955–956 V1 opens.


961–964 V2 current detect accuracy.965–966 V2 opens.971–976 V3 current detect accuracy.977–979 V3 opens.

End of Test Listing for Q8000 Selfcheck Module.

Test Listing for CSC40 Load Board Diagnostic

Tests 101–973: Test the CSC40 Load Board

101–112 Tests leakage from -5 volts to 20 volts.151– 192 Measures leakage at 20 volts on each pin.200 Tests programmable load board ID.301–340 Verifies that each pin can be individually connected to the PTU.400–640 Test calibration relays.700–740 Verifies that pins can be connected in parallel, four groups of 10 pins.751–756 Verifies that LSEARCH and BSEARCH return accurate results.771–786 Verifies that V1, V2 and V3 can be individually disconnected/reconnected.801–822 PTU accuracy.901–904 VIHC accuracy.921–925 VILC accuracy.931–932 VBIAS accuracy.951, 953 V1 current detect accuracy.961, 963 V2 current detect accuracy.971, 973 V3 current detect accuracy.

SELFCHECK AND TIMING CALIBRATION - DC Calibration 217

DC CALIBRATION

All programmable power supplies and parametric measurement hardware are referenced to a single digital-to-analog converter (DAC) via a sample-and-hold system. The entire DC subsystem is calibrated by adjusting the zero and full scale value of the DAC to the prescribed voltage.

Equipment Required

· 1 Selfcheck Load Board #1 or CSC40· 1 digital voltmeter, 4½ digits minimum· 1 Phillips screwdriver· 1 small slotted screwdriver

1. Turn off the power to the Q2 and remove the top cover.2. Unplug both of the power cables located near the left rear corner of the PGM or

PEM.3. Open the front door and carefully lift the PGM or PEM off of the PTG. Lift and

support the back of the PGM or PEM while sliding it out through the front of the tester. Failure to support the back of the PGM while removing it from, or installing it into, the tester may result in damage to the PTG.

4. Switch on the Q2 and allow the power supplies to warm up for at least 30 minutes, then perform the following:

Q2> LOAD DCCAL.OBJQ2> T=11

The Q2 is now looping on test 11. VPAR has been set by the program to 0.000 volts.

5. Connect the voltmeter negative lead to the pin labeled "RG" on the Power Supply 1 board. The pin "RG" is about 1 inch below the two trimpots.

6. Connect the voltmeter positive lead to the pin labeled "VPARIN" on the Power Supply 2 board. This pin is located on top of the board, right of center.

7. Adjust the left trimpot on top of the Power Supply 1 board so the voltmeter reads 0.0000 volts. When this is done, type T=21 to step to the next adjustment.

Q2> T=21

8. Now adjust the right trimpot on the Power Supply 1 board so the voltmeter reads 19.995 volts.

9. Turn off the Q2 and carefully reinstall the PGM or PEM and top cover.

SELFCHECK AND TIMING CALIBRATION - Intro to Q2 Timing Calibration 218

INTRODUCTION TO Q2 TIMING CALIBRATION

For optimal test accuracy and minimal test program guardbanding, the Q2 should be calibrated regularly. Timing calibration on the Q2 consists of the following procedures:

• Counter and Interface Setup

• PTG Verify and PTG Calibration

• Driver Deskew Verify and Driver Deskew Calibration

• Strobe Deskew Verify and Strobe Deskew Calibration

Note: when using the CSC40 load board, all PTG, Driver Deskew, and Strobe Deskew Verify procedures can be executed with one command. After reading the methodology described in this section, refer to “CSC40 LOAD BOARD COMMANDS,” for a command list.

Calibration: Hardware Requirements

The calibration may be performed with either of the following counter/probe combinations:

1 HP 5370B or 5370A Time Interval Counter with2 Oscilloscope probes: either

Tektronix P6106 1M-Ohm 1-meter,Philips PM 8911/09 50-Ohm, orStack CP-264 50-OhmStack CP-265 50-Ohm

1 GPIB Interface Board1 GPIB cable

or1 Guide Technology GT200 Counter with2 Probes: either

Philips PM 8911/09 50-Ohm orStack CP-264 50-OhmStack CP-265 50-Ohm

The Q2 must be equipped with:

1 Load board: eitherQ2 Calibration load board (Selfcheck load board #1 may be used instead)

SELFCHECK AND TIMING CALIBRATION - Intro to Q2 Timing Calibration 219

Q2 “Cal Mux” load board (CSC40 load board may be used instead)

In addition, Q2/62s must be equipped with:

1 Cal Mux SRCor

1 PTG Cal SRC and1 Deskew SRC

Calibration: Software Requirements

Prior to executing any PC-Host calibration commands, a calibration command library must be selected—there is no default. The following commands are available to select calibration command libraries:

62REG Selects regular-style Q2/62 calibration library.52REG Selects regular-style Q2/52 calibration library.62MUX Selects mux-style Q2/62 calibration library (for use with Mux load board

and Mux SRC, but not the CIU).52MUX Selects mux-style Q2/52 calibration library (for use with Mux load board,

but not the CIU).52CSC Selects CSC40 style Q2/52 calibration library.62CSC Selects CSC40 sytle Q2/62 calibration library.

Any library selection command can be included in the /PCHOST/Q.BAT startup file or entered at the Q monitor prompt (Q2>). Selecting a library interactively from the Q2> prompt takes precedence over the setting in the Q.BAT file.

SELFCHECK AND TIMING CALIBRATION - Calibration: Setup 220

CALIBRATION: COUNTER AND GPIB INTERFACE SETUP

GT200 Counter

If the GT200 Counter and 50-Ohm probes are used, the PC-Host will complete the necessary setup. Since the GT200 is a board inside the PC, there are no cables.

HP 5370 Counter

Use the GPIB cable to connect the counter’s GPIB connector to the PC’s GPIB Interface Board. To minimize the possibility of ground loops, the 5370 counter should be plugged into the same AC outlet as the Q2 test system.

If the HP 5370 Counter is used, set its front panel start and stop inputs as follows:

input impedance: 1MEG OHM or 50 OHM (to match probes)input attenuation: X1input coupling: DCinput amp direction control: SEP (not “START COM”)

All the other front panel switches and knobs will be set by the PC-Host.

The address switch on the back of the 5370 chassis should be set to 1011 (addressable; not “Talker Only”), as follows:

1 ON ON ON

0 OFF OFF OFF OFF

A1

The oscillator switch on the back of the 5370 should be set to internal, not external, as follows:

EXT * INT

Selecting the Counter Type

The following commands are available to select the counter type:

/HP5370 Selects the HP 5370 counter (default). When executed interactively, also resets the counter.


/GT200 Selects the GT200 counter and resets it. When executed interactively, also resets the counter.

Either counter selection command can be included in the Q.BAT startup file or entered at the Q monitor prompt (Q2>). Specifying the counter type interactively from the Q2> prompt takes precedence over the setting in the Q.BAT file. (When entered interactively, either counter command can be abbreviated to as little as a / and one letter.)

Resetting the Counter

The following command is available to reset the counter and prepare for calibration:

/RESET Resets the counter.

If the 5370 counter is being used, and is set up correctly, it will display “0.15 0.15” in its front panel when the /RESET command is executed. If the 5370 doesn’t respond to the /RESET command, recheck the cables, the GPIB Interface Board, and the address settings on the back of the 5370.

If the counter type was specified interactively (above), it is not necessary to execute a /RESET command—the /HP5370 and /GT200 commands automatically execute a /RESET.

Counter Diagnostic Check

The following command is available for an additional (optional) diagnostic check of the counter:

HPTEST Tests 5370 or GT200 counter for proper operation.

Note: Despite the “HP” in the command name, the HPTEST command works for both HP 5470B and GT200 counters.

The HPTEST command prints messages that describe the counter switch settings and probe connections, and then instructs you to connect the counter’s START probe to TP1 on the load board and the counter’s STOP probe to TP2. Press Enter after completing each instruction.

After the probes have been connected as instructed, the HPTEST program will make a series of measurements, from which it will determine whether the 5370 is functioning properly. If it is, the program will print out “PASS”; proceed to the PTG calibration (following). If a problem was detected, the program will print out “FAIL.” If the


HPTEST fails, check all connections, and then try again. If it still fails, consult the counter’s documentation for troubleshooting instructions.

The following command is also available for an additional diagnostic check of the counter:

GTTEST Tests and calibrates the GT200 counter.

The GTTEST command is identical to the HPTEST command. However, to improve measurement accuracy, it also measures the offset between the start and stop probes.

SELFCHECK AND TIMING CALIBRATION - PTG Calibration 223

PTG CALIBRATION

This section describes:

• “PTG Verify,” the procedure for verifying that the Q2’s Programmable Timing Generator (PTG) meets system accuracy specifications.

• “PTG Calibration,” the procedure for recalibrating the PTG, if PTG Verify shows it to be necessary.

Note: Like all boards in the Q2, the PTG is static-sensitive. Handle and ship it with static protection and ensure proper seating before applying power.

PTG Verify

The PTG Verify procedure verifies that the PTG is operating within the Q2’s accuracy specifications. PTG Verify should be performed monthly, or whenever there is any doubt about the system’s timing accuracy. Log files should be kept to allow tracking of system accuracy trends.

Perform PTG Verify as follows:

1. Make sure the counter and, for 5370 counters, the PC’s GPIB Interface Board and cable, are set up and checked out as described in the preceding section.

2. For Q2/62s, install the PTG Cal SRC or Cal Mux SRC on the PEM.

3. Install the load board (Calibration, Cal Mux, Selfcheck #1, or CSC40) in the load board test deck.

4. Power up the Q2, and let it thermally stabilize for at least 30 minutes.

5. At the interactive monitor prompt (Q2>), execute the appropriate PTG Verify command, 62MVER or 52MVER, as follows:

Q2> 62MVER

or

Q2> 52MVER

The MVER command displays instructions for setting up the counter switches and connecting the counter probes. It pauses so you can carry out the instruction; when you are ready to continue, press Enter.


The MVER command then prompts you to set up the switches on the front panel of the 5370 (if used), place the counter’s STOP probe in the socket on the SRC (for Q2/52s, use the socket on the PGM), and place the counter’s START probe on TP1 (the socket on the left hand side of the load board). (Note: With probes in the socket, no ground wire is necessary.) Press Enter as you complete each step.

After you have connected the probes and pressed Enter, PTG Verify will begin. All characterization data generated will be written to the files 62MVER.LST and 62MVER.DAT (or 52MVER.LST and 52MVER.DAT), which can be viewed on the screen or printed out. A sample appears below.

The output from PTG Verify always shows the actual worst-case variation between the 24 channels in each particular range and the two channels which are furthest apart. If the actual worst-case for a range exceeds the system specification, the PTG must be recalibrated at that range; if the worst-cases for all ranges exceed the system

Tester ___________________ Verified by __________________

100 200 400 800 1600 3200 6400 |--------------------------------------------------------| | | | | | | | +2 ns +2 ns +3 ns +6 ns +12 ns +20 ns +40 ns | |________________________________________________________| | # # | | # # # | | # # # | | # # # # # | | # # # # # # # | |~~~~#~~~~~~~#~~~~~~~#~~~~~~~#~~~~~~~#~~~~~~~#~~~~~~~#~~~| | # # # # | | # # # | | # # | | # | |--------------------------------------------------------| | -2 ns -2 ns -3 ns -6 ns -12 ns -20 ns -40 ns | | | | | | | | | |--------------------------------------------------------| 10/27/92 PTG Verify 14:55:57

Tester meets specification of +/- 2.00 ns in 100 ns range Worst case is +/- 1.64 ns, Minimum TG is 22, Maximum TG is 21



. . .


specification, the PTG must be completely recalibrated. See “PTG Calibration,” below, for instructions.

PTG Verify on a Single Range

PTG Verify, as executed by the 62MVER or 52MVER command, characterizes all 24 channels of the PTG at seven different cycle-time ranges: 100 ns, 200 ns, 400 ns, 800 ns, 1600 ns, 3200 ns, and 6400 ns. In optimal conditions, if a single tester is communicating with the PC-Host, each range takes about two minutes to characterize completely; the entire process takes about 16 minutes.

If PTG Verify reports that one or several ranges are failing, those ranges can be individually recalibrated (see “PTG Calibration,” below), and then PTG Verify run on just those ranges. The following commands are available to run PTG Verify on one or all ranges:

62MVER Runs Q2/62 PTG Verify for all seven ranges.62V100 Runs PTG Verify just like 62MVER, but for 100 ns range only.62V200 Runs PTG Verify just like 62MVER, but for 200 ns range only.62V400 Runs PTG Verify just like 62MVER, but for 400 ns range only.62V800 Runs PTG Verify just like 62MVER, but for 800 ns range only.62V1600 Runs PTG Verify just like 62MVER, but for 1600 ns range only.62V3200 Runs PTG Verify just like 62MVER, but for 3200 ns range only.62V6400 Runs PTG Verify just like 62MVER, but for 6400 ns range only.52MVER Runs Q2/52 PTG Verify for all seven ranges.52V100 Runs PTG Verify just like 52MVER, but for 100 ns range only.52V200 Runs PTG Verify just like 52MVER, but for 200 ns range only.52V400 Runs PTG Verify just like 52MVER, but for 400 ns range only.52V800 Runs PTG Verify just like 52MVER, but for 800 ns range only.52V1600 Runs PTG Verify just like 52MVER, but for 1600 ns range only.52V3200 Runs PTG Verify just like 52MVER, but for 3200 ns range only.52V6400 Runs PTG Verify just like 52MVER, but for 6400 ns range only.

PTG Calibration

Note: The PTG must be recalibrated only if PTG Verify (above) shows it to be necessary.

Like PTG Verify, PTG Calibration calibrates each timing generator at seven different cycle-time ranges, from 100–199 ns to 6,400–12,768 ns (each range is calibrated at its minimum and maximum values). Under optimal conditions, if a single tester is communicating with the PC-Host, it takes about 45 minutes to calibrate all timing generators at all the ranges.


If the PTG failed PTG Verify in all seven ranges, PTG Calibration must be performed to recalibrate the entire PTG. Otherwise, it is only necessary to perform PTG Calibration for those ranges that failed PTG Verify.

The following commands are available to perform PTG Calibration on one or all ranges:

62MCAL Runs Q2/62 PTG Calibration on all seven ranges.62C100 Runs PTG Calibration just like 62MCAL, but for 100 ns range only.62C200 Runs PTG Calibration just like 62MCAL, but for 200 ns range only.62C400 Runs PTG Calibration just like 62MCAL, but for 400 ns range only.62C800 Runs PTG Calibration just like 62MCAL, but for 800 ns range only.62C1600 Runs PTG Calibration just like 62MCAL, but for 1600 ns range only.62C3200 Runs PTG Calibration just like 62MCAL, but for 3200 ns range only.62C6400 Runs PTG Calibration just like 62MCAL, but for 6400 ns range only.52MCAL Runs Q2/52 PTG Calibration on all seven ranges.52C100 Runs PTG Calibration just like 52MCAL, but for 100 ns range only.52C200 Runs PTG Calibration just like 52MCAL, but for 200 ns range only.52C400 Runs PTG Calibration just like 52MCAL, but for 400 ns range only.52C800 Runs PTG Calibration just like 52MCAL, but for 800 ns range only.52C1600 Runs PTG Calibration just like 52MCAL, but for 1600 ns range only.52C3200 Runs PTG Calibration just like 52MCAL, but for 3200 ns range only.52C6400 Runs PTG Calibration just like 52MCAL, but for 6400 ns range only.

Regardless of how many ranges are to be calibrated, the procedure for performing PTG Calibration is the same:

1. For Q2/62s only, install the PTG Calibration or Cal Mux SRC on the PEM, and push down until it is seated properly.

2. Install one of the four load boards (see “Hardware Requirements”). For selfcheck load board #1 set the thumbwheel switch on the front to “F.”

3. If it is not already on, power up the Q2, and let it thermally stabilize for at least 30 minutes.

4. At the interactive monitor prompt (Q2>), execute the appropriate MCAL command. For example, to run the complete PTG Calibration on a Q2/62 (via 62MCAL), type:

Q2> 62MCAL

The MCAL command then prompts you to set up the switches on the front panel of the 5370 (if used); place the counter’s STOP probe in the socket on the SRC, or, for Q2/52s, the PGM; and place the counter’s START probe on TP1 (the socket on the left hand side of the load board). (Note: With probes in the socket, no ground wire is necessary.) Press


the Enter key when you complete this step.

At the conclusion of the steps and pauses, PTG Calibration will begin. When it concludes, the interactive monitor prompt (Q2>) will return.

Storing Calibration Data in the PTG

The PTG Calibration routine saves all calibration data to the file CAL62.PTG (or Q52PTG.CAL). Before the calibration can be verified, the three 2716 EPROMs in the PTG must be replaced with blanks, and the calibration data from the CAL62.PTG (or Q52PTG.CAL) file loaded into them.

To replace the 2716 EPROMs:

1. Power down the Q2.

2. Open the front panel and remove the top cover.

3. For Q2/62s, remove the PEM, the large board mounted horizontally in the tester, as follows: Gently lift up on the front of the PEM. Once it has popped up, pull it forward a few inches. Disconnect the two cables from the back of the PEM, noting their orientation and leaving their other ends attached to Q2’s back panel. Pull the PEM completely out of the front opening of the Q2/62, and set it aside. For Q2/52s, remove the PGM in a similar manner.

4. Remove the PTG. The PTG is the set of boards connected with a black metal bracket with two green connectors between the boards. The PTG is held in the tester by a ZIF connector at the base of the motherboard. Release this ZIF connector by pulling up on the black handle on the right side of the PTG (as you face the tester). Keep holding this handle up with your right hand while you gently pull the PTG up with your left hand. Lift it out of the Q2 and lay it on a static-protected surface, component-side up.

5. Locate and replace the three 2716 EPROMs in which timing calibration data will be stored. The top board of the PTG is the smallest and has an 8086 mounted on it. The 2716s are located in the upper right corner of the board immediately below the small board, and are accessible without removing the top board. Remove all three 2716s, and either erase them in an EPROM eraser for at least 30 minutes or replace them with new blank 2716s. Replace the 2716s, taking special care not to bend the leads when plugging them back in.

6. Return the PTG to its slot in the Q2 as follows: Pull up on the black handle on the right side of the PTG to open the ZIF connector. Seat the PTG in the connectors, and then push down on the black ZIF connector to lock the PTG in place.

7. For Q2/62s, replace the PEM, reconnecting the two flat cables to the back of the PEM as they were originally installed. The top cable goes to the left side of the PEM (as you face the Q2/62). Push the PEM back until it lines up with the two


posts that protrude from the TG, then push the PEM down over these posts. Make sure that the PEM mates solidly with the connectors on top of the PTG. For Q2/52s, replace the PGM.

Loading the calibration data from the CAL62.PTG (or CAL52.PTG) file into the 2716s is a two-step process. First the data must be loaded from the file into RAM on PTG, and then it must be loaded from RAM into the EPROMs.

After replacing the 2716 EPROMs in the PTG, proceed as follows:

1. Power up the Q2.

2. At the DOS prompt in the \PCHOST directory (C:\PCHOST >), type Q to run the interactive monitor.

3. At the interactive monitor prompt (Q2>), type TLOAD CAL62.PTG (or TLOAD Q52PTG.CAL). This loads the calibration data from the CAL62.PTG (or Q52PTG.CAL) file back into RAM on the PTG.

4. Now load the calibration data from PTG RAM into the EPROMs on the PTG, as follows:

Q2> PTDPROGRAM PTD? YARE YOU SURE? Y

When the Q2> prompt returns (about 6 minutes later), the calibration data has been saved in the EPROMs. The 62CAL.PTG (or Q52PTG.CAL) file can be saved as a backup.

If “ERROR 14” or “ERROR 15” appears, the EPROMs in the PTG are probably not blank. Turn off the tester and repeat the procedure given above for installing three blank 2716 EPROMs in the PTG. Turn the tester back on and repeat the steps for loading the calibration data into the EPROMs.

Verifying the New Calibration

Calibration alone does not guarantee that the PTG meets its timing specifications. After storing the new calibration data in the EPROMs, reset the tester and then run PTG Verify again to verify the accuracy of the new calibration.

SELFCHECK AND TIMING CALIBRATION - Driver Deskew and Calibration 229

Q2 DRIVER DESKEW VERIFY AND CALIBRATION

Note: when using the CSC40 load board, all PTG, Driver Deskew, and Strobe Deskew Verify procedures can be executed with one command. After reading the methodology described in this section, refer to “CSC40 LOAD BOARD COMMANDS,” for a command list.

The Q2 has 40 bi-directional pin electronics channels. Both the rising and falling edges of the drivers are deskewable. The delays are set as follows:

Q2/52 driver delays:

pinsmodes 1 and 2falling and rising edges

mode 3falling and rising edges

1–10: 68.0 ns 68.0 ns12: 44.0 ns 44.0 ns13: 48.0 ns 48.0 ns14: 44.0 ns 44.0 ns15: 44.0 ns 68.0 ns16: 48.0 ns 68.0 ns17: 44.0 ns 68.0 ns18: 48.0 ns 68.0 ns

19–20: 44.0 ns 68.0 ns21–40: 68.0 ns 68.0 ns

Q2/62 driver delays:

falling and rising edges

all pins 48.0 ns


• “Driver Deskew Verify,” the procedure for verifying that the pin electronics drivers meet system deskew specifications: delay ±0.5 ns.

• “Driver Deskew Calibration,” the procedure for recalibrating drivers if Driver Deskew Verify shows it to be necessary. This procedure calibrates drivers at delay ±0.3 ns.

The techniques described in this section ensure a generalized deskew of the Q2, independent of any particular load board (or, for Q2/62s, any particular SRC). Once the


tester has been deskewed as described, different load boards (or SRCs) can be installed without having to deskew the tester again.

Driver Deskew: Requirements

The counter (and, for 5270 counters, the GPIB interface) must be set up properly.

The PTG must be calibrated and verified.

The Driver Deskew Verify and Calibration procedures also require:

1 Potentiometer adjustment (“Trimpot”) tool1 Load board: either

Q2 Calibration load board (Selfcheck load board #1 may be used instead)Q2 “Cal Mux” load board (CSC40 load board may be used instead)


1 SRC: eitherCal Mux SRC, orDeskew SRC

Load Board, Library, and Probe Placement Summary

The extent to which the operator is involved in probe placement during deskew verify and calibration depends on the calibration library and load board in use, as follows:

Calibration library Load board SRC Probe placement

52MUX CSC40 or Cal Mux n/a Automatic52REG Selfcheck #1 or Cal n/a Operator moves PEA probe only62MUX CSC40 or Cal Mux Cal Mux Automatic62REG CSC40 or Cal Mux Deskew Operator moves PELX probe only62REG Selfcheck #1 or Cal Deskew Operator moves both probes

Driver Deskew Verify

This procedure uses the counter to measure the driver delays through the Q2, from the PELX pins on the Deskew SRC (for Q2/52s, the PEL pins on the PGM) out to the PEA pins on the load board. The driver deskew verify ranges are the delays shown at the beginning of the section, ±0.5 ns.


The following commands are available to run Driver Deskew Verify:

62DVER Runs Q2/62 Driver Deskew Verify.52DVER1 Runs Q2/52 Driver Deskew Verify for modes 1 and 2.52DVER3 Runs Q2/52 Driver Deskew Verify for mode 3.

Perform Driver Deskew Verify as follows:


2. Make sure that the load board is installed and calibrated properly.

3. For Q2/62s, install the Deskew or Cal MUX SRC on the PEM.

4. At the interactive monitor prompt (Q2>), execute the appropriate Driver Deskew Verify command. For example:

Q2> 62DVER

For those load board calibration library combinations that require operator placement of the counter probes, the DVER command displays instructions for connecting the probes. It pauses at each step so that you can carry out the instruction; when you are ready to continue, press Enter.

When the DVER command instructs you to connect the counter’s START probe to PELX1, look on the Deskew SRC for the orange “X1” on the left side of the white plastic insert closest to the front of the tester. On the both the PGM and Cal Mux SRC there is a socket for a scope probe. Connect the ground for this probe to one of the ground pins (marked “GND” in black on the inserts). The same ground connection must be maintained for all the deskew measurements.

If the load board/calibration library combination requires operator placement of the counter’s STOP probe, the DVER command will instruct you to connect it to PEA1 on the load board. The PEA pins are the 40 test points in the center of the load board; pin 1 is at the far left. Connect the ground for this probe to the AGND pin socket on the load board. It is important that the same ground is maintained for the entire deskew process. Slip the flexible pin probe tip on the scope probe, and insert it in the pin socket for PEA Channel 1 (marked “1”). After the program makes measurements for channel 1, it will ask that the probes be moved to channel 2, and so on up to channel 40. At this point the program will evaluate the data taken, and indicate on the computer screen whether all 40 channels are within the deskew verify range.

If all the channels are within ±0.5 ns of the deskew delay value (for example, if all the Q2/62 channels are between 47.5 ns and 48.5 ns), the Q2’s drivers meet specification and the Driver Deskew Verify procedure is complete—no deskew calibration is necessary. If not, examine the list file 62DVER.LST or the data file 62DVER.DAT (or 52DVER.LST or


52DVER.DAT) to determine which channels need adjustment, and proceed to the Driver Deskew Calibration procedure.

A sample of the output of Driver Deskew Verify appears below.

Driver Deskew Calibration

The Driver Deskew Calibration procedure aligns the delays of all 40 pin electronics drivers from the SRC (for Q2/52s, from the PGM) to the load board. The driver deskew calibration ranges are the delays shown at the beginning of the section, ±0.3 ns.

This Driver Deskew Calibration procedure need be performed only if Driver Deskew Verify (above) shows it to be necessary.

Tester _____________________________ Verified by ______________________________

10/27/92 PEL Deskew Verify 14:43:05

+500ps________________________________________________________________________________

# # # # # # # # # # # # # # # #~#~~~~~~~~#~~~#~#~~~~~~~#~~~#~#~~~#####~~~~#~~~~~~~~#~~~~~~~~~~~~~~~~~~~~~~~~~~~# #### ### # # #### ### # # ## ## # ## # # #### ###### # # # # # # # # # # ##

---------------------------------------------------------------------------------500ps

1 1 1 1 1 1 1 1 1 1 2 3 3 3 3 3 2 2 2 2 2 3 3 3 3 4 2 2 2 2 31 2 3 4 5 1 2 3 4 5 6 7 8 9 0 6 7 8 9 0 1 2 3 4 5 1 2 3 4 5 6 7 8 9 0 6 7 8 9 0

6 6 6 6 6 4 4 4 4 4 6 6 6 6 6 4 4 4 4 4 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 68 8 8 8 8 8 4 8 4 4 8 8 8 8 8 8 4 8 4 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8

Tester passed 52DVER specification of +/- 0.500 ns


To begin the Driver Deskew Calibration procedure, execute one of the following commands at the interactive monitor prompt (Q2>):

62PELX Performs Q2/62 Driver Deskew Calibration.62PELX n Performs Q2/62 Driver Deskew Calibration, starting at pin n.52PEL1 Performs Q2/52 Driver Deskew Calibration for modes 1 or 2.52PEL1 n Performs Q2/52 Driver Deskew Calibration for modes 1 or 2, starting at pin n.52PEL3 Performs Q2/52 Driver Deskew Calibration for mode 3.52PEL3 n Performs Q2/52 Driver Deskew Calibration for modes 3, starting at pin n.

Each of these Driver Deskew Calibration commands instructs you in connecting the counter’s START and STOP probes, and then displays a map of the potentiometers on the pin electronics board. The potentiometer in need of adjustment will appear as a flashing Q. The program will also indicate which direction to turn each potentiometer. The potentiometers are 20-turn, but they will continue to turn once the end of their range is reached. (The front door of the Q2 may be removed to allow easier access to the potentiometers.)

There are 10 pin electronics channels on each of four pin electronics boards. The deskew procedure begins with the front board, then proceeds to the second, third, and fourth boards. Thus, the channels are deskewed in traditional Q2 channel order, as shown on the Deskew Verify output, not strict numerical order.

To aid you in deskewing each channel precisely, the real-time measurement values are displayed on the computer screen. The number written will be the delta in nanoseconds from the specified delay. A sample display is shown below:

-3 -2 -1 0 +1 +2 +3| | | | | | |

^ .09

Use a potentiometer adjustment tool to turn the potentiometer in the indicated direction until the marker (^ is below the 0, then press Enter. The counter will then make a measurement to see how close to the delay value it has been brought. If it within ±0.3 ns, the program will move on to the next potentiometer. If the measurement is not with ±0.3 ns, the program will not advance to the next adjustment.

To abort the adjustment, press Esc. To abort the Driver Deskew Calibration, press Control-C (^C) once.

When the last channel has been calibrated, the program will exit and return to the Q monitor.


After each adjustment, the last measurement made is logged to the file 62DVER.DAT or 52DVER.DAT. The command /62DVER or /52DVER may be used to read the file and display the pass/fail status. Thus, it is possible to verify that the driver deskew calibration was performed correctly without having to run the driver deskew verify procedure.

SELFCHECK AND TIMING CALIBRATION - Strobe Deskew and Calibration 235

Q2 STROBE DESKEW VERIFY AND CALIBRATION

The Q2 has 40 bi-directional pin electronics channels. Both the rising and falling edges of the strobes are deskewable. The delays are set as follows:

Q2/52 strobe delays:

pinsmodes 1 and 2 falling edges

modes 1 and 2 rising edges

mode 3falling edges

mode 3 rising edges

1–10: 40.0 ns 33.0 ns 40.0 ns 33.0 ns11–14: 53.0 ns 46.0 ns 53.0 ns 46.0 ns

15: 40.0 ns 33.0 ns 40.0 ns 33.0 ns16–19: 53.0 ns 46.0 ns 40.0 ns 33.0 ns20–40: 40.0 ns 33.0 ns 40.0 ns 33.0 ns

Q2/62 strobe delays:

falling edges rising edges

all pins 26.0 ns 19.0 ns


• “Strobe Deskew Verify,” the procedure for verifying that the pin electronics strobes meet system deskew specifications: delay ±1.0 ns.

• “Strobe Deskew Calibration,” the procedure for recalibrating strobes if Strobe Deskew Verify shows it to be necessary. This procedure calibrates strobes at delay ±0.35 ns.

The techniques described in this section ensure a generalized deskew of the Q2, independent of any particular load board (or, for Q2/62s, any particular SRC). Once the tester has been deskewed as described, different load boards (or SRCs) can be installed without having to deskew the tester again.

Strobe Deskew: Requirements

The counter (and, for 5270 counters, the GPIB interface) must be set up properly.

The PTG must be calibrated and verified.

The Strobe Deskew Verify and Cal procedures also require:


1 Potentiometer adjustment (“Trimpot”) tool1 Load board: either

Q2 Calibration load board (Selfcheck load board #1 may be used instead)Q2 “Cal Mux” load board (CSC40 load board may be used instead)


1 SRC: eitherCal Mux SRC, orDeskew SRC

The Strobe Deskew Verify and Calibration procedures require that the TP1 signal (or a buffered version of TP1) be connected to the input of each pin electronics comparator to simulate DUT data. When using the Calibration load board or Selfcheck load board #1, always attach this jumper to the same pin on the load board to which the counter probe is attached. (The CSC40 and Cal Mux load boards connect this signal automatically.)

Load Board, Library, and Probe Placement Summary

The extent to which the operator is involved in probe placement during deskew verify and calibration depends on the calibration library and load board in use, as follows:

Calibration library Load board SRC Probe placement

52MUX CSC40 or Cal Mux n/a Automatic52REG Selfcheck #1 or Cal n/a Operator moves PEA probe only62MUX CSC40 or Cal Mux Cal Mux Automatic62REG CSC40 or Cal Mux Deskew Operator moves PELX probe only62REG Selfcheck #1 or Cal Deskew Operator moves both probes

Strobe Deskew Verify

This procedure uses the counter to measure the strobe delays through the Q2, from the PES pins on the Deskew SRC (for Q2/52s, on the PGM) out to the PEA pins on the load board. The driver deskew verify ranges are the delays shown at the beginning of the section, ±1.0 ns.

The following commands are available to run Strobe Deskew Verify:


62DVST Runs Q2/62 Strobe Deskew Verify.52DVST1 Runs Q2/52 Strobe Deskew Verify for modes 1 and 2.52DVST3 Runs Q2/52 Strobe Deskew Verify for mode 3.

Perform Strobe Deskew Verify as follows:


2. Make sure that the load board is installed and calibrated properly.

3. For Q2/62s, install the Deskew SRC on the PEM.

4. At the interactive monitor prompt (Q2>), execute the appropriate Strobe Deskew Verify command. For example:

Q2> 62DVST

For those load board/calibration library combinations that require operator placement of the counter probes, the DVST command displays instructions for connecting the probes. It pauses at each step so that you can carry out the instruction; when you are ready to continue, press Enter.

When the DVST command instructs you to connect the counter’s START probe to PES1, look on the Deskew SRC for the blue “S1” on the left side of the white plastic insert closest to the rear of the tester. On both the PGM and Cal Mux SRC there is a socket for a scope probe. Connect the ground for this probe to one of the ground pins (marked “GND” in black on the inserts). The same ground connection must be maintained for all the deskew measurements.

If the load board/calibration library combination requires operator placement of the counter’s STOP probe, the DVST command will instruct you to connect it to PEA1 on the load board. The PEA pins are the 40 test points in the center of the load board; pin 1 is at the far left. Connect the ground for this probe to the AGND pin socket on the load board. It is important that the same ground is maintained for the entire deskew process. Slip the flexible pin probe tip on the scope probe, and insert it in the pin socket for PEA Channel 1 (marked “1”). After the program makes measurements for channel 1, it will ask that the probes be moved to channel 2, and so on up to channel 40. At this point the program will evaluate the data taken, and indicate on the computer screen whether all 40 channels are within the deskew verify range.

If all the channels are within ±1.0 ns of the deskew delay value (for example, if all the Q2/62 falling edge channels are between 25.0 ns and 27.0 ns), the Q2’s strobes meet specification and the PES Deskew Verify procedure is complete—no deskew calibration is necessary. If not, examine the list file 62DVER.LST or the data file 62DVER.DAT (or


52DVST.LST or 52DVST.DAT) to determine which channels need adjustment, and proceed to the Strobe Deskew Calibration procedure.

All results of the Strobe Deskew Verify measurements are written to the file Q2CCL.LOG, which can be viewed on the screen or printed out. A sample follows.

Strobe Deskew Calibration

The Strobe Deskew Calibration procedure aligns the delays of all 40 pin electronics drivers from the SRC (for Q2/52s, from the PGM) to the load board. The driver deskew calibration ranges are the delays shown at the beginning of the section, ±0.35 ns.

This Strobe Deskew Calibration procedure need be performed only if Strobe Deskew Verify (above) shows it to be necessary.

To begin the Strobe Deskew Calibration procedure, execute one of the following commands at the interactive monitor prompt (Q2>):

Tester _____________________________ Verified by ______________________________

10/27/92 PES Deskew Verify 14:45:35

+1000ps________________________________________________________________________________

# ## # ## ## # # # # # # ## ## ### # # # ### # # # # # # # # # # # ###~#~~~###~~~~~~~~~~#~#~#~##~~~~~##~###~#~#~#~#~#~#~~~~~#~#~#~#~#~#~#~#~#~#~~~#~ # # # ## # # #

---------------------------------------------------------------------------------1000ps

1 1 1 1 1 1 1 1 1 1 2 3 3 3 3 3 2 2 2 2 2 3 3 3 3 4 2 2 2 2 31 2 3 4 5 1 2 3 4 5 6 7 8 9 0 6 7 8 9 0 1 2 3 4 5 1 2 3 4 5 6 7 8 9 0 6 7 8 9 0

Tester passed 52DVST specification of +/- 1.000 ns


62PES Performs Q2/62 Strobe Deskew Calibration.62PES n Performs Q2/62 Strobe Deskew Calibration, starting at pin n.52PES1 Performs Q2/52 Strobe Deskew Calibration for modes 1 or 2.52PES1 n Performs Q2/52 Strobe Deskew Calibration for modes 1 or 2, starting at pin n.52PES3 Performs Q2/52 Strobe Deskew Calibration for mode 3.52PES3 n Performs Q2/52 Strobe Deskew Calibration for mode 3, starting at pin n.

Each of these Strobe Deskew Calibration commands instructs in connecting the counter’s START and STOP probes, and then displays a map of the potentiometers on the pin electronics board. The potentiometer in need of adjustment will appear as a flashing Q. The program will also indicate which direction to turn each potentiometer. The potentiometers are 20-turn, but they will continue to turn once the end of their range is reached. (The front door of the Q2 may be removed to allow easier access to the potentiometers.)

There are 10 pin electronics channels on each of four pin electronics boards. The deskew procedure begins with the front board, then proceeds to the second, third, and fourth boards. Thus, the channels are deskewed in traditional Q2 channel order, as shown on the Deskew Verify output, not strict numerical order.

To aid you in deskewing each channel precisely, the real-time measurement values are displayed on the computer screen.

-3 -2 -1 0 +1 +2 +3| | | | | | |

^

.09

Use a potentiometer adjustment tool to turn the potentiometer in the indicated direction until the marker ^ is below the 0, then press Enter. The counter will then measure the delay. If it is within the 0.35 ns (350 ps) tolerance, the program will move on to the next edge. If the delay is not within the tolerance, the program will not advance to the next adjustment.

To abort the adjustment, press Esc. To abort the Strobe Deskew Calibration, press Control-C (^C) once.

When the last channel has been calibrated, the program will exit and return to the Q monitor.

After each adjustment, the last measurement made is logged to the file 62DVST.DAT or 52DVST.DAT. The command /62DVST or /52DVST may be used to read the file and display the pass/fail status. Thus, it is possible to verify that the strobe deskew


calibration was performed correctly without having to run the strobe deskew verify procedure.

SELFCHECK AND TIMING CALIBRATION - Q2/52 Offset Calibration 241

Q2/52 OFFSET CALIBRATION

Definition

Offset calibration adjusts system delays to enable the test programmer to think and operate in the DUT time frame. Times programmed in QTL can then represent the specifications of the DUT. The Offset Calibration program will measure these offsets for all Q2/52 user programs and load boards. The entire measurement process takes approximately 10 minutes.

A Q2/52 offset is a timing offset that adjusts the start and stop edges of timing generators to compensate for hardware delays through the Q2/52 and the load board.

Q2/52 offset calibration measures delays in a timing generator path as it travels through the PGM, the PE channels, down through the load board (for PEL and PEE) or the error latch (for PES). For example, if the effect of a timing generator providing the PEL signal CS1 takes 48 nanoseconds to travel through the Q2/52 down to the DUT, then the start and stop edges would be offset by -48 nanoseconds. When timing values are programmed for this timing generator, the system will automatically start the edges 48 nanoseconds early to compensate for the system delay. The actual start and stop times desired are programmed in the DUT time frame.

Any measured offset is partially due to load board delays. Therefore, a new offset table should be constructed for each load board that introduces significantly different delays. For example, all load boards with a cable length of 20 centimeters could use the same offset table. Cable load boards with a different cable length, say 40 centimeters, should have a different offset table since the delay through these load boards is different than those with 20 centimeter cables.

Falling and Rising Edge of PEL Offsets

PEL signals require offset measurements to be made for both rising and falling edges. The start edge offset is the delay from the TG falling edge at the PGM to the falling edge at the load board. The stop edge offset is the delay from the TG rising edge at the PGM to the rising edge at the load board.


Falling and Rising Edge of PES Offsets

The PES falling edge offset is the delay between the PES line going low and the error line being latched. This offset is the result of expect data being different from the input data. To simulate DUT data, TP1 is used.

To calibrate the start or falling edge, the expect data is set to 1. The start edge of the TG being calibrated is searched. The search terminates with the TG start edge set such that the strobe at the pin electronics comparator (PES) is falling just when TP1 is rising at the comparator.

The PES rising edge offset is the delay between the PES line going high and the error line being latched. This is the result of expect data being different from the input data.

For stop edge offset calibration, the expect data is set to 0 and the TG stop edge is searched.

Falling and Rising Edge of PEE Offsets

PEE signals require offset measurements to be made for both rising and falling edges. The PEE offset to be measured is the delay from the TG output, which causes PEE to go high, to the activation point of the driver at the load board. The technique used to measure this transition is to drive a 1 into a grounded 75 ohm resistor at the load board. When the driver begins to tri-state, the level at the load board will be pulled down to ground.

The start edge offset is the delay from the TG falling edge at the PGM to the rising edge at the load board. The stop edge offset is the delay from the TG rising edge at the PGM to the falling edge at the load board.

Requirements

The tester must be deskewed before measuring offsets. Otherwise, when the tester is subsequently deskewed, it will invalidate any offsets taken prior to deskew.

In addition to the equipment required for PTG and deskew calibration, the following items are also necessary:


l 75 ohm resistor

l Jumper clip lead

l User load board

Offset Calibration Procedure

The tester and counter should be warmed up for 30 minutes before beginning the offset calibration.

To perform the offset calibration, begin the Q program and have a calibration library loaded, either 52CSC, 52MUX, or 52REG. The 52OFST command is used to begin offset calibration. For example:

Q2> 52MUX

Q2> 52OFST

Set the counter switches as follows:1M OHM or 50 OHM to match probesDIV/1 not DIV/10DC not ACSEP not START COMPress ENTER to continue.

There are 3 possible offset calibration options:1 - Separate data in and data out2 - Common I/O data, including ROMs, EPROMs, etc.3 - Data on addressEnter option number representing type of DUT (1/2/3)? 1

Attach START probe to PSOCKETAttach JUMPER to PEA 31Remove JUMPER from PEA 31Connect PEA 25 to GROUNDDisconnect the GROUND from PEA 25Is CS1 used on this load board (Y/N)? YIs CS2 used on this load board (Y/N)? YIs CS3 used on this load board (Y/N)? YIs CS4 used on this load board (Y/N)? YIs CS5 used on this load board (Y/N)? YAre any CS pins being used as a strobe (Y/N)? YAttach JUMPER to PEA 11Is TG2 being used as a strobe (Y/N)? YIs TG3 being used as a strobe (Y/N)? Y


Is TG4 being used as a strobe (Y/N)? YIs TG5 being used as a strobe (Y/N)? YIs TG11 being used as a strobe (Y/N)? YIs TG12 being used as a strobe (Y/N)? YRemove JUMPER from PEA 11Are any CS pins being used as a driver enable (Y/N)? YConnect a 75 ohm resistor from PEA 11 to GROUNDIs TG2 being used as a driver enable (Y/N)? YIs TG3 being used as a driver enable (Y/N)? YIs TG4 being used as a driver enable (Y/N)? YIs TG5 being used as a driver enable (Y/N)? YIs TG11 being used as a driver enable (Y/N)? YIs TG12 being used as a driver enable (Y/N)? YDisconnect the 75 ohm resistorAttach STOP probe to TP 16Attach STOP probe to TP 23Attach STOP probe to TP 24Attach STOP probe to TP 25

Instructions will be displayed for performing the offset calibration procedure for the chosen option. The procedure references PEA channels. You must translate the PEA reference to DUT pin numbers for each load board to be calibrated.

PEE calibration requires the use of a 75 ohm resistor. The program will prompt the user to insert the resistor from PEA 11 to ground which enables the correct voltage to be set across the timing generator being calibrated. The program will also prompt the user to remove the resistor following the PEE calibration portion.

Upon completion of the entire procedure, the program will store the data just taken in RAM on the PTG and on disk in the file 52CAL.OFF.

Storing Offsets

When the offset program is completed, the offset table is resident in RAM on the PTG. You should program this table into the offset PROMs located on the PGM. The offset PROMs are programmed with the PFD command.

Q2> FLOAD 52CAL.OFFQ2> PFDPROGRAM PFD? Y (do not press return. The PFD command

automatically displays the next instruction)ENTER TABLE # 2 (table number: 0 - 149)ARE YOU SURE? Y (do not press return. The PFD command

automatically displays the next instruction)


You may program any table number from 0 to 149. It is also possible to write over existing table numbers. If an existing table number is written over, the old offset table will be lost. A maximum of 36 offset tables may be stored in EPROM.

If an Error 14 (No blank EPROM) or an Error 15 (Programming Error) appears, the offset EPROMs on the PGM are either full or defective. Save the offset tables by performing an FDUMP commands.

Q2> OFFSET= (table number)Q2> FDUMP (filename)

The offset tables are now resident on the designated disk under the file names given.

Turn off Q2 power, remove the top cover. Unplug the power cables located near the left rear corner of the PGM. Open the front door and carefully lift the PGM off the PTG. Lift and support the back of the PGM while sliding it out through the front of the tester. Failure to support the back of the PGM while removing or replacing it may cause damage to the PTG. Carefully place the PGM down. Remove the bottom front cover of the PGM. Install blank 2716 EPROMs. Replace the PGM cover and carefully reinstall the PGM. Replace the top cover and power up the tester.

Use the FLOAD and PFD commands as described above to load the offsets and program them into the EPROMs.


CSC40 LOAD BOARD COMMANDS

The CSC40 load board can be used for all Q2 Selfcheck and timing calibration procedures described in this section. It replaces Selfcheck load boards #1 and #2 and the Cal Mux load board.

When using the CSC40, Q2/52 Selfcheck and timing calibration requires only one tester setup, and can be executed from a single command. Q2/62 Selfcheck and timing calibration requires only two setups: one for Selfcheck and one for timing calibraiton. (Using other load boards required four hardware setups, three of which required that the tester be powered down. To comply strictly with the Q2 specifications, each power-down was to be followed by a 30-minute warm-up period.) With the CSC40 load board, a Q2/52 need only be powered down once, and a Q2/62 need only be powered down twice.

The following commands automate the procedures described in this section. They can only be used with the CSC40 load board.

52VER1 Performs Q2/52 PTG Verify, Driver Deskew Verify, and Strobe Deskew Verify for modes 1 and 2.

52VER3 Performs Q2/52 PTG Verify, Driver Deskew Verify, and Strobe Deskew Verify for mode 3.

62VER Performs Q2/62 PTG Verify, Driver Deskew Verify, and Strobe Deskew Verify.

52CSC1 Performs Q2/52 Selfcheck (52TSC) and PTG Verify, Driver Deskew Verify, and Strobe Deskew Verify (52VER1) for modes 1 and 2.

52CSC3 Performs Q2/52 Selfcheck (52TSC) and PTG Verify, Driver Deskew Verify, and Strobe Deskew Verify (52VER3) for mode 3.

To abort any Calibration or Verify procedure, press Control-C (^C) once.

SELFCHECK AND TIMING CALIBRATION - Command Summary 247

Q2 CALIBRATION: COMMAND SUMMARY

Commands to select a calibration library (required):

62REG Selects regular-style Q2/62 calibration library.52REG Selects regular-style Q2/52 calibration library.62MUX Selects mux-style Q2/62 calibration library (for use with Mux load board

and Mux SRC, but not the CIU).52MUX Selects mux-style Q2/52 calibration library (for use with Mux load board,

but not the CIU).52CSC Selects Q2/52 calibration library for use with the CSC40 load board.62CSC Selects Q2/62 calibration library for use with the CSC40 load board and

MUX SRC.

Commands to select counter type (optional):

/HP5370 Selects the HP 5370 counter (default). When executed interactively, also resets the counter.

/GT200 Selects the GT200 counter and resets it. When executed interactively, also resets the counter.

Command to reset the counter (optional):

/RESET Resets the counter.

Command to test the counter (optional):

HPTEST Tests 5370 or GT200 counter for proper operation.GTTEST Tests and calibrates the GT200 counter.

Commands to run PTG Verify:

62MVER Runs Q2/62 PTG Verify for all seven ranges.62V100 Runs PTG Verify just like 62MVER, but for 100 ns range only.62V200 Runs PTG Verify just like 62MVER, but for 200 ns range only.62V400 Runs PTG Verify just like 62MVER, but for 400 ns range only.62V800 Runs PTG Verify just like 62MVER, but for 800 ns range only.62V1600 Runs PTG Verify just like 62MVER, but for 1600 ns range only.62V3200 Runs PTG Verify just like 62MVER, but for 3200 ns range only.62V6400 Runs PTG Verify just like 62MVER, but for 6400 ns range only.52MVER Runs Q2/52 PTG Verify for all seven ranges.


52V100 Runs PTG Verify just like 52MVER, but for 100 ns range only.52V200 Runs PTG Verify just like 52MVER, but for 200 ns range only.52V400 Runs PTG Verify just like 52MVER, but for 400 ns range only.52V800 Runs PTG Verify just like 52MVER, but for 800 ns range only.52V1600 Runs PTG Verify just like 52MVER, but for 1600 ns range only.52V3200 Runs PTG Verify just like 52MVER, but for 3200 ns range only.52V6400 Runs PTG Verify just like 52MVER, but for 6400 ns range only.

Commands to run PTG Calibration:

62MCAL Runs Q2/62 PTG Calibration on all seven ranges.62C100 Runs PTG Calibration just like 62MCAL, but for 100 ns range only.62C200 Runs PTG Calibration just like 62MCAL, but for 200 ns range only.62C400 Runs PTG Calibration just like 62MCAL, but for 400 ns range only.62C800 Runs PTG Calibration just like 62MCAL, but for 800 ns range only.62C1600 Runs PTG Calibration just like 62MCAL, but for 1600 ns range only.62C3200 Runs PTG Calibration just like 62MCAL, but for 3200 ns range only.62C6400 Runs PTG Calibration just like 62MCAL, but for 6400 ns range only.52MCAL Runs Q2/52 PTG Calibration on all seven ranges.52C100 Runs PTG Calibration just like 52MCAL, but for 100 ns range only.52C200 Runs PTG Calibration just like 52MCAL, but for 200 ns range only.52C400 Runs PTG Calibration just like 52MCAL, but for 400 ns range only.52C800 Runs PTG Calibration just like 52MCAL, but for 800 ns range only.52C1600 Runs PTG Calibration just like 52MCAL, but for 1600 ns range only.52C3200 Runs PTG Calibration just like 52MCAL, but for 3200 ns range only.52C6400 Runs PTG Calibration just like 52MCAL, but for 6400 ns range only.

Commands to run Driver Deskew Verify:

62DVER Runs Q2/62 Driver Deskew Verify.52DVER1 Runs Q2/52 Driver Deskew Verify for modes 1 and 2.52DVER3 Runs Q2/52 Driver Deskew Verify for mode 3.

Commands to run Driver Deskew Calibration:

62PELX Performs Q2/62 Driver Deskew Calibration.62PELX n Performs Q2/62 Driver Deskew Calibration, starting at pin n.52PEL1 Performs Q2/52 Driver Deskew Calibration for modes 1 or 2.52PEL1 n Performs Q2/52 Driver Deskew Calibration for modes 1 or 2, starting at pin n.52PEL3 Performs Q2/52 Driver Deskew Calibration for mode 3.52PEL3 n Performs Q2/52 Driver Deskew Calibration for modes 3, starting at pin n.


Commands to perform Strobe Deskew Verify:

62DVST Runs Q2/62 Strobe Deskew Verify.52DVST1 Runs Q2/52 Strobe Deskew Verify for modes 1 and 2.52DVST3 Runs Q2/52 Strobe Deskew Verify for mode 3.

Commands to perform Strobe Deskew Calibration:

62PES Performs Q2/62 Strobe Deskew Calibration.62PES n Performs Q2/62 Strobe Deskew Calibration, starting at pin n.52PES1 Performs Q2/52 Strobe Deskew Calibration for modes 1 or 2.52PES1 n Performs Q2/52 Strobe Deskew Calibration for modes 1 or 2, starting at pin n.52PES3 Performs Q2/52 Strobe Deskew Calibration for mode 3.52PES3 n Performs Q2/52 Strobe Deskew Calibration for mode 3, starting at pin n.

Commands to automate Verify and Selfcheck procedures when using the CSC40 load board:

52VER1 Performs Q2/52 PTG Verify, Driver Deskew Verify, and Strobe Deskew Verify for modes 1 or 2.

52VER3 Performs Q2/52 PTG Verify, Driver Deskew Verify, and Strobe Deskew Verify for mode 3.

62VER Performs Q2/62 PTG Verify, Driver Deskew Verify, and Strobe Deskew Verify.

52CSC1 Performs Q2/52 Selfcheck (52TSC) and PTG Verify, Driver Deskew Verify, and Strobe Deskew Verify (52VER1) for modes 1 and 2.

52CSC3 Performs Q2/52 Selfcheck (52TSC) and PTG Verify, Driver Deskew Verify, and Strobe Deskew Verify (52VER3) for mode 3.

SELFCHECK AND TIMING CALIBRATION - PC-Host/CCL Equivalencies 250

PC-HOST/CCL EQUIVALENCIES

The following PC-Host commands are available to create custom calibration procedures:

ADJUST n Adjust pot to n picoseconds.ADJUST n m Adjust pot to n picoseconds ±m picoseconds.ADJUST n m c Adjust pot to n ± m picoseconds, while executing tester command c

continuously during the adjustment.(If STARTn or STOPn is specified as the command, a BSEARCH STARTn or BSEARCH STOPn command is executed during the adjustment. If a test number t is specified as the command, a T=t command is executed during the adjustment.)

CLEAR Clear screen.CLOCK n Clock PEM bits.DRIVERTOL n Set driver tolerance to n picoseconds.DRIVERTOL==n Set driver tolerance to n picoseconds.DRIVERTOL Display current driver tolerance.OSTARTn==t Set the start edge offset for TG n to t picoseconds.OSTARTn,m==t Set the start offset for TG’s n though m to t picoseconds.OSTOPn==t Set the stop edge offset for TG n to t picoseconds.OSTOPn,m==t Set the stop offset for TGs n through m to t picoseconds. PEMBIT n Set, reset or clock PEM bits. This command works by modifying the

first 2 pattern vectors in the PEM; a pattern must be running in order for this to have any effect.

PROBE START n Wait until start probe period is n ns ±0.4%.PROBE STOP n Wait until stop probe period is n ns ±0.4%.RESET n ... Reset PEM bits.SENDQ command Same as command.SENDPGM Send bits set with SET, RESET and CLOCK to PEM.SET n ... Set PEM bits.SLOPE s Set start and stop slopes. The argument, s, can be / or R for rising, and \

or F for falling.SLSTART s Set start slope. The argument, s, can be / or R for rising, and \ or F for

falling.SLSTOP s Set stop slope. The argument, s, can be / or R for rising, and \ or F for

falling.STARTn==t Set start edge of TG n to t picoseconds.STARTn,m==t Set start edge of TG n though m to t picoseconds.STOPn==t Set stop edge of TG n to t picoseconds.STOPn,m==t Set stop edge of TG n through m to t picoseconds.STROBETOL n Set strobe tolerance to n picoseconds.

SELFCHECK AND TIMING CALIBRATION - PC-Host/CCL Equivalencies 251

STROBETOL==n Set strobe tolerance to n picoseconds.STROBETOL Display current strobe tolerance.TRIGGER v Set start and stop triggers to v.TRSTART v Set start trigger to v.TRSTOP v Set stop trigger to v.USERDATA LOG Creates LOG file called "Q2CCL.LOG."

VERIFY c u t [p] Verify time, given c, the column in which to display the result; u, the display resolution (in picoseconds), and t, the expected time (in picoseconds), and (optionally) p, the period (in picoseconds). The period is used to correct edges near cycle boundaries to make them conform to the expected result. If a period is not specified, it is assumed to be 399 picoseconds. The expected value, actual value and error value are logged to the DAT file, if one is open. (See the section on datalogging for more information.)

/52DVER Read 52DVER.DAT and display pass/fail status.

/52DVST Read 52DVST.DAT and display pass/fail status.

/52MVER Read 52MVER.DAT and display pass/fail status.

/62DVER Read 62DVER.DAT and display pass/fail status.

/62DVST Read 62DVST.DAT and display pass/fail status.

/62MVER Read 62MVER.DAT and display pass/fail status.

/AUTOMATIC Automatic deskew mode enable. When used with mux-style calibration libraries (52MUX and 62MUX), this command combines the features of Verify and Deskew Calibration. When executed before a Strobe Deskew Calibration command (52PEL1, 52PEL3, 52PES1, 52PES3, 62PELX, or 62PES), the program will not pause at passing pins.

/CIU Set counter default trigger levels to -1.3.

/ERRORS Display PTG calibration error report.

/FLIP Flip start and stop probes.

/GT200 Select GT200 counter.

/HP5370 Select HP 5370 counter.

/PERIOD Period display for start and stop.

/RESET Reset counter.

/STATISTICS Counter statistic display.

/TTL Set counter default trigger levels to 0.15.

All commands that begin with a slash (/), except those listed below, may be abbreviated to as short as a slash followed by one letter. The /52DVER, /52DVST, /52MVER, /62DVER, /62DVST and /62MVER commands may not be abbreviated.

SELFCHECK AND TIMING CALIBRATION - Converting CCL Programs 252

CONVERTING CCL PROGRAMS

The Q program's CCL command automatically converts a CCL program into a Q program batch file and executes it.

CCL file Converts file.CCL to file.BAT and executes it.

Some of the conversions made by the CCL translator are described in the table below:

CCL Q(........................<><.......................><.......................>);

(<........................>)(<........................>)(<........................>)

TRSTART 1.5;TRSTOP 1.5;

TRSTART .15TRSTOP .15

PELCO2 := DUTPIN2/[^49] => TG3/;

SLSTART /PEMBIT +-49SLSTOP /MSG 'Attach START probe to DUTPIN2' MSG 'Attach STOP probe to TG3'LONG PELC02 = COUNTER

TWEAK START5 FROM 50 TO 150;PELCO2 := STROBE PES1\ => PIN5/;

LOWLIMIT = 50NSHIGHLIMIT = 150NSTSEARCH START5SLSTART \SLSTOP /MSG 'Attach START probe to PES1'MSG 'Attach STOP probe to PIN5'LONG PELC02 = COUNTER

ADJUST DUTPIN2\=>DUTPIN3/ TO 50;

SLSTART \SLSTOP /MSG 'Attach START probe to DUTPIN2'MSG 'Attach STOP probe to DUTPIN3'ADJUST 50000

ADJUST DUTPIN2\=>DUTPIN3/ TO 50WITHIN .5 BY MOVING OSTART2

SLSTART \SLSTOP /MSG 'Attach START probe to

SELFCHECK AND TIMING CALIBRATION - Converting CCL Programs 253

FROM OSTART17; DUTPIN2'MSG 'Attach STOP probe to DUTPIN3'macro SEARCH J = J + 50000 - COUNTER OSTART2 == Jendlong J = OSTART17OSTART2 == OSTART17exe 4 SEARCH

PERIOD := TG3/; SLSTOP /MSG 'Attach STOP probe to TG3'PERIOD = PERIOD_STOP

PELCST := MIN PELC02,PELC03; PELCST := MAX PELC02,PELC03;PELCST := MID PELC02,PELC03;

LONG PELCST = MIN(PELC02,PELC03)LONG PELCST = MAX(PELC02,PELC03)LONG MAX# = MAX(PELC02,PELC03)LONG MIN# = MIN(PELC02,PELC03)LONG PELCST = (MAX# + MIN#) / 2

USERSKIP;SKIPTO LABEL; SKIPLESS VALUE1 VALUE2 LABEL;

Control flow is implemented with if statements and macro calls.

TIMESOTIMES 17;PTG17RA = START17;PTG17FA = OSTART17;

The TIMES and OTIMES commands are ignored. STARTn, STOPn, OSTARTn and OSTOPn are read from the tester whenever they occur in an expression.

NOSTART ...NOSTOP ...

No equivalent

CCL programs tend to be very repetitive. By using Q macros, CCL programs usually may be made much smaller.

UTILITIES - Host Access 255

UTILITIES

HOST ACCESS

These commands are available for accessing the host:

Command Description

DL file Down-Load Host file to PC file

DL host pc Down-Load Host file to PC file

DOWNLOAD file Down-Load Host file to PC file

DOWNLOAD host pc Down-Load Host file to PC file

H Go On-line to Host UL file Up-Load PC file to Host

file UL pc host Up-Load PC file to Host

file UPLOAD file Up-Load PC file to Host

file UPLOAD pc host Up-Load PC file to Host

file

Files may be down loaded from the Megahost or Patternhost with the DOWNLOAD or DL command. The DOWNLOAD command has two arguments, the remote host file name and the local PC file name. If both file names are the same, then it is only necessary to enter the file name once.

The Q program SETUP command allows the down load to operate in one of two modes. In mode 'A' ASCII files may be down loaded at approximately 1000 bytes per second. Mode 'B' allows binary or ASCII files to be down loaded. Data transfer rate in mode 'B' is approximately 250 bytes per second. No special software is required on the Megahost or Patternhost for down loading.

Files may be uploaded to the Megahost or Patternhost with the UPLOAD or UL command. The UPLOAD command has two arguments, the local PC file name and the remote host file name. If both file names are the same, then it is only necessary to enter the file name

UTILITIES - Host Access 256

once. One of two upload modes may be selected with the SETUP command. In mode 'A' only ASCII files may be up loaded and lower case characters are converted to upper case during uploading. In mode 'B' any file may be uploaded. To use mode 'B' the program CP.SAV must be installed on the PDP-11 host system disk. This program is available from Skyline Test Equipment.

To transfer files, the host console port must be connected to the host and the port must be available for command entry. The prompt must be the normal "." prompt.

If the prompt is not a "." then the following TSX command should be executed:

SET PROMPT '.'

It is usually a good idea to check the connection by going on-line to the host first with the H command.

UTILITIES - Megahost Terminal Emulation 257

MEGAHOST TERMINAL EMULATION

Features of the Megahost or Patternhost not yet implemented on the PC-HOST may be accessed via the terminal emulator. These programs include: SCHMOO, DPLOT, BIT MAP, and KED.

Most VT100 control sequences are accepted by the PC-HOST software, including the following:

Command Description

SO Shift Out SIESC 7ESC 8ESC DESC EESC MESC ( 0ESC ( B ESC [ A ESC [ B ESC [ C ESC [ D ESC [ H ESC [ J ESC [ K ESC [ c ESC [ f ESC [ m ESC [ n ESC [ r ESC [ s

Shift InSave CursorRestore CursorIndexNew LineReverse IndexSelect Graphics CharactersSelect Regular Characters Cursor Up Cursor DownCursor Right Cursor LeftDirect Cursor Addressing Erase ScreenErase Line What Are You (VT100) Direct Cursor Addressing Character Attributes Report Cursor or Status Scrolling Region Save Cursor

ESC [ u Restore Cursor

The alternate character set matches the VT100 as closely as possible using the available PC character set. The alternate characters may be selected with SO (14 decimal) or ESC(0. To return to regular characters use SI (15 decimal) or ESC(B.

The following VT100 control sequences are not supported:

UTILITIES - Megahost Terminal Emulation 258

Command Description

ESC # Double High, Fill ScreenESC ) G1 Character Set ESC = Keypad Applications Mode ESC > ESC H ESC c ESC g ESC q ESC y ESC [ h

Keypad Numeric ModeSet Tab ResetClear Tab Program LED'sInvoke Tests Set Mode

ESC [ l Reset Mode

The use of the KED editor is described on the following page.

To exit the host on-line mode press the ESC key.

UTILITIES - PC-Ked 259

PC-KED

The KED editor may be used while in the host on-line mode. Substantial differences between the PC keyboard and DEC keyboards necessitate a change in the way KED is used. However, modern user interface technology has been applied here and you may find that PC-KED is actually easier to use that the original KED editor. The following table summarizes the available commands:

Key Command Description

Home Top Moves cursor directly to top of fileEndPgUpPgDnIns

BottomBackup SectionAdvance SectionInsert Blank

Moves cursor directly to end of fileMoves cursor up one section (16 lines)Moves cursor down one section (16 lines)Insert a blank character at the cursor

Del Delete Char Delete the cursor under the cursor

Alt-A Append Erase select range, append paste bufferAlt-B Bline Moves cursor to beginning of lineAlt-C Cut Erase select range, store paste bufferAlt-D Delete Line Delete through end of lineAlt-E EOL Move cursor to end of lineAlt-F FindType search

model then press enter

Alt-G GoldGoldAlt-H HelpHelp

display, use enter to exit help

Alt-I Insert SpecialInsert special character

Alt-J Justify Reformat select range (KED fill command)

Alt-K Kill to EOL Delete up to end of lineAlt-L Change

CaseChange lower to upper and upper to lower

Alt-N Next Find next occurrence of search modelAlt-O Open Line Insert new line at cursor's rightAlt-P Paste Insert string from the paste buffer


Alt-R Reset Cancel select rangeAlt-S Select Mark beginning of a select rangeAlt-W Word Move cursor to the beginning of a wordAlt-X Del Word Delete to first character of next word

F1 Command

Ctrl-J Erase Word Erase the word to the left of the cursorCtrl-U Erase BOL Erase the line to the left of the cursorCtrl-W Repaint Repaints the screen

The up, down, left, right and backspace keys work as you expect.

Special DEC graphics characters such as F/F C/R and L/F are displayed as a bar.

The following KED commands are unavailable: PAGE, ADVANCE, BACKUP, CHAR, SUBSTITUTE, REPLACE, UNDELCHAR, UNDELWORD, UNDELLINE, CTRL/C.


HEXADECIMAL TO BINARY CONVERSION

The PC-Host software package includes a program, HEXBIN, for converting files from Intel hexadecimal format to Megatest binary format. The HEXBIN program accepts one argument to specify the hexadecimal input file and the binary output file. For example:

C:\Q2>HEXBIN MYPROG

will read the hexadecimal file "MYPROG.OBJ" and produce the binary file "MYPROG.BIN".

HEXBIN may also be used to link pattern files to QTL programs. This is done by specifying the pattern name or names after the QTL name on the command line. For example:

C:\Q2>QTL62 /Q PAL

C:\Q2>PAT62 CODE1234

C:\Q2>HEXBIN PAL CODE1234

In this case HEXBIN reads the symbol table "CODE1234.SYM", reads the QLINK formated file "PAL.OBJ", and then writes the binary file "PAL.BIN".

If there were three patterns, then the command might look something like this:

C:\Q2>HEXBIN PAL CODE123A CODE123B CODE123C

APPENDIX - PC-Host Software and Documentation 263

APPENDIX

PC-HOST SOFTWARE AND DOCUMENTATION

The PC-HOST software includes the following documentation and software:

· PC-Host Manual (this document).

· PC-Host Software diskette containing the files:

File Description

284CAL.BIN SKY284 calibration program284CAL.OBJ SKY284 calibration pattern284CAL.SYM SKY284 calibration symbols284TSC.BIN SKY284 selfcheck, binary284TSC.OBJ SKY284 selfcheck, pattern file284TSC.SYM SKY284 selfcheck, symbol table52CAL.LIB Q2/52 calibration macro library52OFST.BIN Q2/52 offset calibration QTL, binary52OFST.OBJ Q2/52 offset calibration QTL, hexadecimal52OFST.SYM Q2/52 offset calibration QTL, symbol table52TSC1.BIN Q2/52 ESCape compatible selfcheck module 1,

binary52TSC1.OBJ Q2/52 ESCape compatible selfcheck module 1,

hexadecimal52TSC1.SYM Q2/52 ESCape compatible selfcheck module 1,

symbol table52TSC2.BIN Q2/52 ESCape compatible selfcheck module 2,







binary


52TSC4.OBJ Q2/52 ESCape compatible selfcheck module 4, hexadecimal

52TSC4.SYM Q2/52 ESCape compatible selfcheck module 4, symbol table

52TSC5.BIN Q2/52 ESCape compatible selfcheck module 5, binary

52TSC5.OBJ Q2/52 ESCape compatible selfcheck module 5, hexadecimal

52TSC5.SYM Q2/52 ESCape compatible selfcheck module 5, symbol table

62MUX.LIB Q2/62 mux style calibration macro library 62MXSC.BIN Q2/62 mux load board selfcheck, binary62MXSC.OBJ Q2/62 mux load board selfcheck, hexadecimal62MXSC.SYM Q2/62 mux load board selfcheck, symbol table62REG.LIB Q2/62 Old style calibration macro library62TSC1.BIN Q2/62 ESCape compatible selfcheck module 1,



symbol table62TSC1A.OBJ Q2/62 selfcheck 1 pattern file62TSC1B.OBJ Q2/62 selfcheck 1 pattern file62TSC1C.OBJ Q2/62 selfcheck 1 pattern file62TSC1D.OBJ Q2/62 selfcheck 1 pattern file62TSC1E.OBJ Q2/62 selfcheck 1 pattern file62TSC2.BIN Q2/62 ESCape compatible selfcheck module 2,



symbol table62TSC2A.OBJ Q2/62 selfcheck 2 pattern file62TSC2B.OBJ Q2/62 selfcheck 2 pattern fileCAL52.BIN Q2/52 calibration QTL program, binaryCAL52.OBJ Q2/52 calibration QTL program, hexadecimalCAL52.SYMCAL62.BIN

Symbol table for CAL52.OBJ Q2/62 calibration QTL program, binary

CAL62.OBJ CAL62.SYM CAP62.OBJ CCL.EXE

Q2/62 calibration QTL program, hexadecimalSymbol table for CAL62.OBJ Q2/62 calibration pattern CCL to Q conversion program

CSC40.BIN CSC40 load board diagnostic, binaryCSC40.OBJ CSC40 load board diagnostic, hexadecimalCSC40.SYM CSC40 load board diagnostic, symbol table


DCCAL.BIN Q2 DC calibration, binaryDCCAL.OBJ Q2 DC calibration, hexadecimalDCCAL.SYM Q2 DC calibration, symbol tableEMPTY.EXE Check addresses used by PCQ and POB boardsESC.EXE ESCape hardwae diagnosticHELP.EXE Q help programHEXBIN.EXEHexadecimal to binary conversion HEXBIN.PIF HEXBIN program information file IBT.BIN Interface board test program, binaryIBT.OBJ Interface board test program, hexadecimalIBT.REF Interface board test program, reference fileIBT.SYM Interface board test program, symbol tableINSTALL.EXE PC-Host installation program MUXSRC.BIN Q2/62 mux SRC selfcheck, binaryMUXSRC.OBJ Q2/62 mux SRC selfcheck, hexadecimalMUXSRC.SYM Q2/62 mux SRC selfcheck, symbol tablePAT62.EXE PAT62.PIF PCHOST.REV

Q2/62 pattern compiler PAT62 program information file PC-Host software revision history

PCQ.EXE PCQ board diagnostic program PLOAD.BIN Q2/62 pattern load and save diagnostic, binaryPLOAD.OBJ Q2/62 pattern load and save diagnostic, hexadecimalPLOAD.SYM Q2/62 pattern load and save diagnostic, symbol tablePOB.EXE POB board diagnostic programQ.EXE Q programQ.LIB Q program macro libraryQ.PIF Q program information file Q2CAL.LIB Q2 calibration macro libraryQ8000.BIN Q8000 ESCape compatible selfcheck,binaryQ8000.OBJ Q8000 ESCape compatible selfcheck, hexadecimalQ8000.SYM Q8000 ESCape compatible selfcheck, symbol tableQTL.EXE Q2/62 QTL compilerQTL.PIF QTL program information fileQTL52.EXE Q2/52 QTL compiler QTL52.PIF QTL52 program information file


QTL62.EXE Q2/62 QTL compiler preprocessor QTL62.PIF QTL62 program information file S15.EXE S15 vector conversion programSPEED.BIN System controller speed diagnostic, binarySPEED.OBJ System controller speed diagnostic, hexadecimalSPEED.SYM System controller speed diagnostic, symbol tableTIME.BIN Measure individual QTL instruction times, binaryTIME.OBJ Meaure individual QTL instruction times,

hexadecimalTIME.SYM Measure individual QTL instruction times, symbol

table

· The software is distributed on one 3.5 inch 1.44 megabyte diskette.

· The software package also includes a hardware key that attaches to the PC's parallel port.

APPENDIX - Warranty 267

WARRANTY

Skyline Test Equipment warrants to the original purchaser in the United States of America that this product will be free of defects in material or workmanship for one year from the date of purchase under normal use.

Skyline Test Equipment's sole and exclusive liability for defects in material and workmanship shall be limited to repair or replacement at its authorized service center. This warranty does not obligate Skyline Test Equipment to bear the cost of transportation charges in connection with the repair or replacement of defective parts.

This warranty is invalid if the damage or defect is caused by accident, act of God, customer abuse, unauthorized alteration or repair, vandalism or misuse.

Any implied warranties arising out of the sale of the product including the implied warranties of merchantability and fitness for a particular purpose are limited to the above one year period. Skyline Test Equipment shall in no event be liable for incidental, consequential, contingent or any other damages.

This warranty gives you specific legal rights, and you may have other rights which vary from State to State. Some states do not allow the exclusion or limitation of incidental or consequential damages or limitations on how long an implied warranty lasts, so the above limitations or exclusions may not apply to you.

INDEX 267

INDEXCommands, registers, parameters, functional tests, etc. are listed here in all capital letters.552CSC1, 246, 24952CSC3, 246, 24952DVER.DAT, 234, 25152DVER1, 231, 24852DVER3, 231, 24852DVST.DAT, 239, 25152DVST1, 237, 24952DVST3, 237, 24952MCAL, 226, 24852MUX, 219, 230, 236, 247, 25152MVER, 223, 224, 225, 24852MVER.DAT, 25152PEL1, 233, 248, 25152PEL3, 233, 249, 25152PES1, 239, 249, 25152PES3, 239, 249, 25152REG, 219, 230, 236, 24752TSC4.BIN, 26352TSC4.OBJ, 26352VER1, 246, 24952VER3, 246, 249

662DVER, 231, 232, 237, 24862DVER.DAT, 234, 25162DVST, 237, 24962DVST.DAT, 239, 25162MCAL, 226, 24862MUX, 219, 230, 236, 247, 25162MVER, 223, 224, 225, 24762MVER.DAT, 25162PELX, 233, 248, 25162PES, 239, 249, 25162REG, 219, 230, 236, 24762TSC2.BIN, 26462TSC2.OBJ, 26462TSC2A.OBJ, 26462VER, 246, 249

88080 code, executing, 143

AACOUNT, 61ADJUST, 252ALU, inputs, 96

INDEX 268

ALU, programmable functions, 96ANSI.SYS, installation, 11APPEND, 54, 55, 259ASCII, 255ASCII files, 255ASSIGN, 21, 47, 48, 52, 53, 54AUTOEXEC.BAT file, modifications to, 11AUTOSTART, 49AUTOSTART ON, 50Auxiliary serial port, 51AUXPORT, 51

BBASE, 38Base, number, 18BCOUNT, 61BEGIN, 29, 61BEXLPP, 144, 150BIN, 61BIN commands, 60Bin counters, 51Binary searches, 52Bins, branching on, 71Bins, displaying, 61Bins, PGM, 61Bit description, microinstructions, 110BIT MAP, 116Bit map, 257Bit map commands, 114BITMAP, 114Block-replacement, 91Boca Research, 14BOCARAM/AT, 12, 14BOOST, 93BRANCH, 70, 71Breakpoints, 165BSEARCH, 23, 52, 53, 54BSEARCH, requirements, 53BSRINIT, 114BSRLOAD, 114BYTE, 61Byte registers, 47, 48

CCALIBLOCK, 23, 28, 29Calibration blocks, 28, 29Calibration command summary, 247Calibration macro library, 263Calibration, hardware requirements, 218Calibration, software requirements, 219CALL, 23, 45, 46CALL FALSE, 45Call sequence, sample, 89CALL TRUE, 45

INDEX 269

Calling sequence, example, 86CASE, 45, 46CASE CONTINUE, 45Case sensitivity, 17CBAR, 114CBIN, 74, 115CBXPND, 114CCAL, 114CCL, 252CCL equivalences, 250CCL programs, 253CCOUNT, 61Channel lists, examples, 35Character set, 257, 258Characterization Commands, 184CHECKSUM, 63Checksums, 65CHIPS statement, 102CLEARBINS, 49, 51CLOSE, 54COLCLEAR, 74COLCOUNT, 116COLDUMP, 74COLOR, 116COLUMN, 68COM1 through COM4 I/O addresses, 9, 10Command execution, ending PGM, 73COMP, 70COMP commands, 72COMPARE, 47, 48Compiler switches, 19Compilers, 18Compiling, error messages, 19CONFIG.SYS file, modifications for expanded memory, 12, 13CONFIG.SYS file, sample, 11CONMESS, 28, 29Continuation of message, 29CONTINUE, 44, 46Control flow, 253Control sequences, those not supported, 257Control sequences, VT100, 257Conversion, hexadecimal to binary format, 261Conversion, QTL programs from PDP-11 to PC-Host, 21Converting CCL programs, 252COUNT, 69COUNT statement, 97COUNTER, 115Counter, 60Counter diagnostic check, 221Counter, reset command, 247Counter, resetting, 221Counter, test command, 247CP.SAV, 255CREATE, 54, 55

INDEX 270

CREG, 47, 48CSC40 load board, 196, 197, 218, 219, 223, 229, 230, 236CSC40 load board commands, 198, 246, 249CSC40 selfcheck, 216CSC40, execute the selfcheck, 197CSC40.BIN, 264CSC40.OBJ, 264CSLOAD, 65CSLOAD, execution requirements, 65CURMAR, 115CURRENT, 47Current parameters, 32CYCLE, 36, 53

DDATA buffer, 64Data logging, 56Data logging, files, 55Data logging, parameters, 56Datalogging commands, 183DATE, 56DATGEN statement, 103DC Calibration, 217DCOUNT, 61DELAY, 38DETAIL, 57Detect threshold, 93DISCONNECT, 43DISFB, 62, 64DISPLAY, 62, 64, 141, 148DL, 255DMA connectors, 10Documentation, PC-Host, 263DOS commands, 189DOS, receommended versions, 11DOSUMMARY, 49DOTEST, 29DOUBLEWORD, 47, 61DOWNLOAD, 255DPLOT, 59, 257Driver deskew calibration, 232Driver deskew calibration commands, 248Driver deskew calibration procedure, 229Driver deskew requirements, 230Driver deskew verify, 230Driver deskew verify and calibration, 229Driver deskew verify commands, 248Driver deskew verify example, 232Driver deskew verify procedure, 229DRIVERTOL, 250DUT addresses, searching for, 66DUTLOAD, 62, 64DUTLOAD, execution requirements, 64DVER, 231

INDEX 271

DVST, 237DXMAIN, 21DYMAIN, 21

EEARLY, 38ECCLEAR, 82, 86ECOUNT, 61ECRs, clearing row and column, 74ECRSEG, 75, 82Elements, replacing during testing, 87EMM386, 12, 13EMM386 device driver, 12Emulate, 167ENDLEX, 114ENDLIST, 31, 32, 36, 60, 71, 87, 141, 148ENDLOOP, 154ENDMAC, 45, 46ENDREPEAT, 70ENDTEST, 29, 45, 46, 54, 56EPM, 93EPSILON, 53Erase terminal commands, 257ERROR, 45, 68ERROR CATCH, 116Error Catch RAM, 74ERROR flag, setting and clearing, 73ERROR MODE, TEST STATION SWITCH, 164ERROR MODE, Test Station Switch, 164ERROR parameters, 57ERROR statements, 46ESC.EXE, 264Ethernet interface, 9Executing a pattern, 143, 149Executing from buffers, 72EXIT, 258EXIT help, 259Expanded memory installation, 12Expanded memory, page frame placement, 12EXQ, 24, 70EXU, 70

FFALSE, 23, 45FBIN, 61, 115Features, PC-Host, 7FLOAD, 37, 38Flow control commands, 45Flow control, PGM program, 70FORCEV, 39, 42FORCEV, pass condition ranges, 41FULL, 69FULLEC, 86Functional bins, 64

INDEX 272

FUNJIF, 44, 46, 60FUNJIF EXQ, 43, 44, 60FUNTEST, 44, 53, 54, 60, 141, 148FUNTEST EXQ, 43, 44, 60

GGENERR, 70, 72, 73GETBYTE, 22, 49, 51GETREG, 47, 48, 61GETSTRING, 50, 51GETTIME, 56GETTIME example, 56GPIB, 14GPIB board, installation, 14GT200, 218, 221, 222, 247, 251GT200 counter board, installation, 16GT200 counter setup, 220GTTEST, 222

HHALT, 70, 73HEADER, 26Header, 26HEADER 2SCOMP, 26HEADER OLD, 17, 26, 52Header Q8000, 26Hexadecimal numbers, 18Hexadecimal to binary conversion, 261HEXBIN, 261, 264HEXBIN, link pattern files, 261High Voltage Module commands, 93HIGHLIMIT, 54HOME, 114Host baud rate, 160HP 5370, 218, 221, 237, 247, 251HP 5370 counter setup, 220HP5370, 15HPTEST, 221, 222, 247HTOLEX, 114HVM, 93

IIACC10, 39IBCONF program for GPIB configuration, 14IBIN, 60, 61IBIN commands, 60IERROR flag, 94Include statements, QTL62, 20INCREMENT, 54Increment, 60Index command, 257Initial conditions of pattern generators, 107Initializing the PEM, 142, 149INITOFF, 38

INDEX 273

INPUT, 55INSEND, 62, 63, 140, 147INSERT, 62, 63, 74, 84, 129, 140, 147, 259INSERT, PEM tables used with, 140, 147INSFB, 62, 64Installation, GPIB board, 14Intel hexadecimal format, 19, 261INTERRUPT, 115IPAR, 22, 35, 41, 54IRAIL, 93ISOLATE, 114ITEST, 93

JJNSET, 46JOYSTICK, 114JSET, 45, 46JUMP, 45JUMP FALSE, 45JUMP TRUE, 45, 87

KKED, 257KED editor description, 259Key, 9, 11Key, installation, 11

Llabel, 60Labels and reserved words, 23Labels, requirements, 17LATE, 38LBDATA, 65, 66, 116Leakage current, 39Leakage current offset table, 39Leakage offset values, 39LEARN, 62LEX2FB, 114LFLAG, 45, 46LFLAG FALSE, 23LFLAG TRUE, 45Linear search, example, 54Linear searches, 52, 53LLOAD, 114Load board, 26, 196, 197, 198, 218, 219, 221, 223, 224, 226, 229, 230, 231, 232, 235, 236, 237, 238, 246, 247, 249LOADBOARD, 26LOADMAP, 50, 52LOG, 56, 57Logic flag, 45, 46LONG, 47, 61Loops, PGM repeat, 73LOWLIMIT, 54LPP, 37, 144

INDEX 274

LPT1 and LPT2 I/O addresses, 9, 10LSEARCH, 52, 54LSEARCH, requirements, 53LSTART, 114

MMACRO, 45, 46, 253Macros, 191Macros, for selfcheck, 197MAP, 50MAP OFF, 52MAP ON, 52MAP QTL, 52MAPCOMMOFF, 115MAPDUMP, 115MAR Statement, 99MARSEGMENT, 67, 68, 115MATCH, 47, 48MEASURE, 59Measure, during tests, 59Megahost, 257Megahost, downloading/uploading files, 255MESSAGE, 28, 50, 198MESSAGE statements, 28, 29MicroRAM segment, specifying, 68MMINIT, 115MMVALUE, 115MVER, 223MVINIT, 115MYPROG.OBJ, 261

NNational Instruments, GPIB board supplier, 14NOERROR, 44NOP, 45NOSTART, 253NOSTOP, 253

OOFFSET, 37, 38Offset calibration, 241Offset tables, 38ONLYTESTSUPPLY, 43, 44OPENPSTEST, 40, 41OSTART, 38OSTOP, 38OUTHIGH, 65, 66OUTLOW, 65OXMAIN, 97OYMAIN, 97

PP2HOST, 115Page frame placement, 12

INDEX 275

PARALLEL, 42Parallel parametric tests, 41Parallel port, 265PARAM, 56Parameters, multiple settings, 34Parameters, reset, 35Parametric test delay, 39PARCAL, 39, 42PARCAL, excess leakage current, 39PARDUMP, 39PARTEST, 39, 41, 42, 53PARTEST FORCEI, 40, 41, 42PARTEST FORCEV, 40, 41PARTEST TESTSUPPLY, 40, 41PARTIME, 22, 39, 40PASS, 46, 57PASSNCL, 41PASSNICL, 41PASSPCL, 41PASSVG, 42PASSVL, 42PATTERN, 20Pattern compiler, 264Pattern file, loading, 38Pattern program, loading and executing, 68Patternhost, 8, 257Patternhost, downloading/uploading files, 255Patternhost, POB, 8Patterns, 68Patterns, looping, 69PAUSE, 44PC-HOST directory, 11PC-Host installation, 11PC-Host software files, 263PC-KED commands, unavailabe, 260PC-KED editor commands, 259PC-KED editor description, 259PC-POB software, functions, 8PC62 interface board, description of, 10PCQ, 264PCQ interface board, description of, 9PDELAY, 70PE channel connections, 43PE84 Specific Commands, 168PEM buffer, displaying, 141, 148PEM buffers, 140, 147PEM commands, 177PEM commands, loaded in Q buffer, 142, 148PERIOD, 252PERROR, 70, 73PGM, 60PGM buffers, 62PGM buffers, displaying, 64PGM buffers, loading, 63

INDEX 276

PGM commands, 173PGM control, 60PGM ECR commands, 73PGM flags, branching on, 71PGM list, 141, 148PGM Lists, 60PGM pattern loading and execution, 67PGM pipeline, 69PGM registers, 61, 115PGM tables, 116PGM, initializing, 61PGMBYTE, 62, 64PGMNOP, 70, 71PGMWORD, 62, 64PGOFFSET, 67, 68, 74, 86Pin Electronics modes, 133PINCONNECT, 43PINLIST, 31PIPECLEAR, 67PLOAD, 20, 67, 68, 142, 148PLOAD PROGPAT, 20POB, 264POB emulation, via PC62 Interface Board, 10POB software, general description, 8POB, managing files in, 144POB, transferring data from, 144, 150POBDELETE, 22, 144POBDIRECTORY, 144POP statements, 109Ports, 167Ports, bit definitions, 52Power supply connections, 43Power supply pin tests, 41PPARAM, 57PRINT, 54, 55, 57PRINTDB, 54, 55, 57PRINTLN, 54, 55, 57Product header, 27Product header, definition, 27Program header, 26PROMPT, 256PSCONNECT, 42PSTEP, 67PTG calibration, 223, 225PTG calibration commands, 248PTG commands, 171PTG verify, 223PTG verify commands, 247PTG verify on a single range, 225PTG verify output, 224PTG, storing calibration data in, 227PTOLEX, 115PTU, operating region, 35PTUCONNECT, 43

INDEX 277

PUSH statements, 109PV, 93

QQ Buffer, 60Q buffer, 44, 141, 148Q Program commands, 186Q program, adding custom features, 12Q program, memory used, 12Q-Monitor, command formats, 157Q2/52 selfcheck module #1 test listing, 205Q2/52 selfcheck module #2 test listing, 207Q2/52 selfcheck module #3 test listing, 211Q2/52 selfcheck module #4 test listing, 214Q2/52 selfcheck module #5 test listing, 214, 216Q2/62 selfcheck module #1 test listing, 200Q2/62 selfcheck module #2 test listing, 204Q8000 selfcheck, 215Q8000 selfcheck module test listing, 215QEMM, 12, 13QINSERT, 140, 147QINSERT, PEM tables used with, 140, 147QLINK format, producing output files in, 19QPLOAD, 142, 148QPLOAD PROGPAT, 20QSCHMOO, 57, 58QTL.EXE, 18QTL52.EXE, 18QTL62.EXE, 18QTOLEX, 115Quarterdeck Expanded Memory Manager, 12, 13

RRBIN, 74, 115RCCLEAR, 74, 88RCDMPBAD, 87, 89RCDMPFIXED, 87, 88, 89RCINIT, 85, 86, 88RCREPAIR, 76, 77, 85, 86, 87, 91RCREPAIR results, 90RCREPDONE, 87, 88Ready block, 29, 49, 50, 57, 58, 59READY block, enabling, 50Redundancy algorithm, 85, 87Redundancy analysis, 75Register Arrays, 47Register names, 17, 23Register sizes, 47, 48Register, FLOAD, 38Register, voltages, 31REGISTERS, 66Registers, 37, 45, 46, 47, 49, 51, 53, 54, 55, 56, 166Registers, assigning values, 48Registers, declaring, 48

INDEX 278

Registers, expressions, 48Registers, min/max values, 58Registers, used as arguments, 61RELAY, 163Repair table, 77, 82Repair table, loading, 84REPEAT, 70, 73Requirements, PC-Host computer, 9Reserved words, 21, 23Reserved words, Q2/52, 24RESET, 221, 247RESETERR, 70, 72, 73Restore cursor command, 257RETESTCLEAR, 50RETQ, 70RETURN, 45, 46ROM code, loading into DATA buffer, 64ROW, 69ROWCLEAR, 74ROWCOUNT, 116ROWDUMP, 74RT-11 commands, 189

SSave cursor command, 257SCHMOO, 59, 257Schmoo, defining title, 58Schmoo, generating, 58Schmoo, output, 58Schmoos, 57SCRAMBLE, 27, 28Scramble table, 27Scratch pad data, 88Searches, binary and linear, 52SELECTBUF, 62, 64Selfcheck Q commands, 197Selfcheck requirements, 196Selfcheck, introduction, 195Selfcheck, review macros, 198Selfcheck, running, 197Selfcheck, troubleshooting, 198SENDBYTE, 50, 51SENDPGM, 60, 141, 148SENDPGM, appearing with FUNTEST/FUNJIF, 141, 148SENDREG, 47, 48, 61SENDSTRING, 50, 51SENDWORD, 50, 51SEQUENCE, 27Sequence and binning, 28Sequence and binning table, example, 30Sequence blocks, 29Sequence flag, 46Sequential parametric tests, 41Set variable, 27, 29, 34, 46

INDEX 279

SETADDRESS, 65, 66SETCHANNEL, 31, 35SETCHANNEL, channel list, 32SETCHIPSON, 66SETDATA, 66SETJAM, 66SETLEVEL, 31SETPIN, 31, 40, 41, 42SETTIME, 22, 36, 37SETTIMES, 22SETUP, 255SFLAG CONTINUE, 45, 46SFLAG RETURN, 45, 46Sign magnitude arithmetic, 17, 26SKIPTO, 45, 253SKY284 Specific Topics, 147SPEED.BIN, 265SRC, communicating with, 144SSET, 45, 46START, 36STARTLOOP, 154STARTPATTERN, 67STARTPGOFFSET, 69STARTTEST, 49, 50Statements of pattern programming, 94STATUS buffer, 129Status Buffer, 101STEP, 67STEP TO ERROR, Position of ERROR MODE Switch, 164STOP, 36, 57STOP ON ERROR, Position of ERROR MODE Switch, 164STORE, 22, 47, 48STOREBIN, 49, 51STRING, 47, 61String, insert, 259Strings, 17, 22, 29, 48, 51, 58Strings, examples, 18Strobe deskew calibration, 238, 239, 251Strobe deskew calibration commands, 249Strobe deskew calibration procedure, 235Strobe deskew requirements, 235Strobe deskew verify, 236Strobe deskew verify and calibration, 235Strobe deskew verify commands, 249Strobe deskew verify example, 238Strobe deskew verify procedure, 235STROBETOL, 251Subroutines, commands, 154SUMMARY, 29, 52, 61SUMSTATE, 49, 51SYMBOL, 37Symbol table, 19, 20, 261, 264Symbol table, loading, 38

INDEX 280

TTerminal commands, 257Terminal emulation, 257Terminal emulation, problems, 11Test blocks, additional setup, 37Test blocks, functional test setup, 42Test blocks, functional tests, 43Test blocks, parametric test setup, 39Test blocks, parametric tests, 40Test blocks, pin setup, 31Test blocks, timing setup, 36Test blocks, voltage and current setup, 31Tester baud rate, 160Tester ports, 51Tester ports, sending data, 51TESTNUMBER, 44TESTPIN, 43, 44TESTSUPPLY, 44TIME, 47TIME.BIN, 265Timing calibration, introduction, 218Timing channel, resetting, 37Timing list, 36TIMINGGROUP, 27TNOP, 44TP1, 38TPARAM, 57, 58TRANSFER, 61, 62, 88Transfer files, 255TRSTART, 252TRSTOP, 252TRUE, 45TRULES, 37TRULES, on/off, 38TRULES, override, 38Two's complement arithmetic, 17, 26, 52TYPE table, 117TYPE table, description, 118TYPE Table, Q2/62, 145, 151

UUDATA statement, 107UL, 255UNIX commands, 189UPLOAD, 255USEDCHANNEL, 27, 28, 43User preference byte, 78USERSKIP, 253

VVBIAS, 54VG84 commands, 180VIH, 54VIHC, 54

INDEX 281

VIL, 54VILC, 54VOH, 17, 54VOL, 17, 21, 54VOLTAGE, 47Voltage parameters, 32VOLTEST, 21VOUT, 54VPAR, 35, 41, 54VPULSE, 93VRAIL, 93, 170

WWafer map port, 51Wafer mapping, 52Wafer Mapping commands, 168Wafer mapping, disabling, 52Wafer mapping, enabling, 52Warranty, 266WIDTH, 54WORD, 47, 61WPORT, 51WRITE, 62, 64

XXALU Statements, 94XPARAMn, 57XPESTEP, 129XSTEP, 129

YYALU Statements, 94YMAIN, 21YPARAM, 57

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