s/labs’ tiny system cache delivers faster boot times and ...€¦ · 1 4.1 components employed in...

Synaptic Labs'Tiny System Cache (CMS-T003)Tutorial

T001A: Boot from On-chip Flash: A Qsys based Nios II Reference design based on S/Labs' Tiny System Cache IP and Intel's On-chip Flash Memory Controller

"S/Labs’ Tiny System Cache delivers faster boot times and easily up to 4x faster software execution times over using Altera's Flash Accelerator.”

This tutorial describes a simple reference design for S/Labs Tiny System Cache IP and Intel's On-chip Flash memory controller targeted specifically to HyperMAX MAX 10 evaluation board. This tutorial describes key aspects of a pre-configured .qsys reference project and then walks through the process of generating and compiling that .Qsys project. This tutorial then describes how to compile the example Nios II source code, download the firmware into the on-chip flash memory device and then run the reference design on the development board.

“Excellent for XIP applications"The reference project for this Tutorial is bundled with a

Free Trial License for S/Labs Tiny System Cache.That Quartus License Key never expires.

Synaptic Labs 2017 i [email protected] V1.0 page 1

mailto:[email protected]


Table of Contents

T001A: Boot from On-chip Flash: A Qsys based Nios II Reference design based on S/Labs' Tiny System Cache IP and Intel's On-chip Flash Memory Controller...............................................................1Set-Up Requirements:................................................................................................................................3Step 1: Obtain core materials.....................................................................................................................3Step 2: License Setup.................................................................................................................................31. Contents of the reference project...........................................................................................................42. Open the reference Quartus Project.......................................................................................................53. Open the reference Qsys project............................................................................................................54. Explore and configuring the reference Qsys project..............................................................................64.1 Components employed in the reference project...................................................................................64.2 Nios II/f processor configuration.........................................................................................................74.3 Configuring S/Labs Tiny System Cache..............................................................................................84.4 Configuration of Altera’s On-Chip Memory......................................................................................104.5 Configuration of Altera’s On-chip Flash Memory (UFM) controller................................................115. Generating the Qsys Design.................................................................................................................126. Synthesize and assemble the Design....................................................................................................137. Preparing the firmware.........................................................................................................................147.1 Open the NIOS II Software Built Tools for Eclipse...........................................................................147.2 Create a simple application and BSP.................................................................................................157.3 Configure the Board Support Package (BSP)....................................................................................177.4 Generate the BSP and clean the project.............................................................................................217.5 Build the Nios II Application.............................................................................................................217.7 Generate memory initialization files..................................................................................................228. Program the firmware into the On-chip Flash memory device............................................................238.1 Generating .pof Programming Files in the Quartus II Software........................................................238.2 Programming the FPGA Bitstream and Firmware on the On-chip Flash using the Quartus II Programmer and .pof Files.......................................................................................................................2610. Run the nios2-terminal application....................................................................................................28




Setup your development environment:

1 Obtain core materials

1. Download and install the latest version of Quartus Prime Lite Edition or Standard Edition (18.x at the time of publication) on your PC, please ensure that your PC meets the required minimum specification.

2. Create a folder/directory for your work. We suggest: C:\prj\

3. For devboards HyperMAX boards: :

◦ Download reference design Boot_from_Onchip_Flash_Project_MAX10 from:https://synaptic-labs.s3.amazonaws.com/pub/2017-Designs/SynapticLabs- CMS- T003-Tutorial-001/Boot_from_Onchip_Flash_Project_max10.zip

◦ Extract to: C:\prj\

2 Read the License Agreement and Setup your License Key

• This version of the tutorial is bundled with:

◦ A copy of the full edition of S/Labs HBMC IP found in the ip folder◦ A Free Trial License Credential with Embedded Quartus License Key for S/Labs

HBMC IP that never expires. • Before you Use the HBMC IP, please read the License Agreement and related files in this

bundle:...-LA-IDX-...-Agreement.pdf

and

...LA-ID-...-ExtendedTerms.pdf

• Please install (copy and paste) the entire License Credential with Embedded License Key into Quartus Prime:

...-LC-ID-...-Full-Edition-HBMC-For-Intel-Devices.txt

• If required, search the phrase:

“Intel FPGA Software Installation and Licensing Quick Start”

on the Internet to find instructions on how to install License Keys into Quartus Prime.


http://media.synaptic-labs.com/pub/2017-Designs/SynapticLabs-HBMC-Tutorial-001/HyperNios_Project_C10LP.zip







1. Contents of the reference projectSynaptic Labs' Boot from On-chip Flash Reference design projects includes the following files and directories:

• The root folder of the reference project contains the Quartus Prime and Qsys project files for the first reference project.

• The ip folder contains S/Labs HBMC encrypted IP and License Key.• The software folder is used as the workspace folder for Eclipse• The source folder contains sample code that can replace the simple hello_world.c

application found.

Note: Synaptic Labs' Tiny System Cache (CMS-T003) IP can ONLY be simulated with Altera's Modelsim Simulator. Please contact Synaptic Labs for a simulation model if required.




2. Open the reference Quartus Project • In the menu bar of Quartus Prime, select File → Open Project…

• Select the file NIOS_example.qpf in the project directory

• Click the [ Open ] button. •

3. Open the reference Qsys project• In the menu bar of Quartus Prime, select Tools→Platform Designer• Select the file hypernios.qsys in the project directory• Click the [ Open ] button.




4. Explore and configuring the reference Qsys project

1 4.1 Components employed in the reference projectThe reference Qsys project in this tutorial employs a NiosII/f processor, Synaptic Labs' Tiny System (CMS-T003) IP, Intel’s On-chip Memory module to store data in on chip SRAM, Intel’s User Flash Memory Controller and various peripherals such as Altera’s JTAG UART and timer modules as illustrated below. All these Qsys components are connected together.




2 4.2 Nios II/f processor configurationIn this example, the Nios II/f Reset Vector is mapped to the MAX 10 On-chip Flash memory. The Nios II/F Exception vectors is mapped to the on-chip_memory as illustrated below. This means that the Nios II/f processor will look for the boot code in the On-chip Flash memory whilethe exception handling / interrupt code in the on-chip_memory module.

As illustrated below, the instruction cache of the Nios II/f core is set to 4Kbytes in size while thedata cache have been set to 2Kbytes in size to accelerate software performance. The instruction and data caches have both been configured with their burstcount signal disabled to reduce resource usage.




3 4.3 Configuring S/Labs Tiny System CacheSynaptic Labs' Tiny System Cache has been pre-configured in this reference project.

• In the Port and Conduit configuration tab :

◦ Set the Enable read-only code target port [x] (this will generate a read only Avalon port iavs_code to be connected t Nios II instruction master)

◦ Set the Enable read-write data target port [x] (this will generate a read-write Avalon port iavs_data to be connected t Nios II data master)

• In the Arbitration Scheme configuration tab :

◦ Set the Arbitration mode to [True artbitration mode] (Use the Nios II/e arbitration only with the Nios II/e processor. For the Nios II/f processor, use the True Arbitrationmode).

• In the Cache configuration tab, the main cache parameters are configured as :

◦ Total cache line storage capacity is set to 1 kilobytes. (This is the size of the cache)

◦ Storage partition scheme is set to Unified code and data partition. (This is the partition mode of the cache. Depending on the application, different parameters might offer better software acceleration.)

◦ Cache associativity is set to Direct Mapped . (The other option is to select a set associative cache).




◦ Cache line width in words is set to 8 (this will set the number of words to be fetched from memory for every cache miss occurance). This has to match the maximum burst size selected in Intel on-chip flash memory controller.

No other parameters needs to be changed.

More info about how to configure S/Labs’ Tiny System Cache can be found in document

SynapticLabs-TinySystemCache-CA-CMS-T003-tutorial.pdf. This document can be found in the ip bundle.




4 4.4 Configuration of Altera’s On-Chip MemoryIn this reference project, Altera's On-Chip Memory is configured as a 40 Kilobyte single port RAM. There is no need to setup this memory to be initialized by the Nios II SBT for Eclipse

• Please ensure that:

◦ [ ] Initialize memory content is UnTicked

◦ [ ] Enable non-default initialization file is UnTicked

◦ [] User created initialization file is left empty




5 4.5 Configuration of Altera’s On-chip Flash Memory (UFM) controller

.

In Altera On-chip Flash IP parameter editor,

• set the Data Interface to Parallel

• set the Read Burst Mode to Incrementing.

• set the Read Burst Count to 8

• set the Configuration Mode to Single Uncompressed Image.

Make sure the Initialize flash content option is left unchecked. Initializing the on-chip flash during device programming feature is currently not supported.




5. Generating the Qsys DesignOnce the Qsys project has been correctly configured, press the [ Generate HDL… ] button on the bottom right hand side of the Qsys window.

• In the Synthesis section, set the Create HDL design files for synthesis field to Verilog.

• In the Simulation section, set the Create simulation model field to None.

• Then click on the [ Generate ] button.

• You may see a Save System window. Click the [ Close ] button to close the save window.

• Generating the .qsys project updates the .SOPC file which will be used by the Nios II Software Build Tools (SBT) environment.

• Click the [ Close ] button to close the generate window.

• You may want to close the Qsys window.




6. Synthesize and assemble the Design• Go to the Quartus Prime window.

• In Quartus II software, click on • Assignment -> Device -> Device and Pin Options -> Configuration. • Set Configuration mode: to Single Uncompressed Image .

• In the menu bar, select:Processing → Start Compilation

• The assembler step will create the SRAM FPGA Bitstream file (.SOF) .




7. Preparing the firmware

1 7.1 Open the NIOS II Software Built Tools for Eclipse• In Quartus Prime, go to the menu bar and select

Tools → NIOS II Software Built Tools for Eclipse.

• Click the [Browse…] button. A new file selector window will open. In this tutorial we are going to select the software folder located inside the project folder as the workspace and then click the [ OK ] button.

• Be sure to leave the [ ] Use this as the default field unticked.

• Click the [ OK ] button.


MAX10_HyperNios_Project/softwareHyperNios_EPCQ_Project_C10LP/softwareBoot_from_onchipFlash_Project/software



2 7.2 Create a simple application and BSPThe software folder in the reference project is empty. This is because problems can be experienced when moving the Eclipse Workshop folder between Windows and Linux Systems. We need to create a Nios II application, and Nios II board support package for that Nios II application:

• In the Eclipse window, go the menu bar and select: File → New → NIOS II Application and BSP from Template

• A new window will pop up: (most of the fields below will initially be empty)




• In the Target hardware information, click on the […] button• A file browser window will open. Locate and select the hypernios.sopcinfo file

generated by Qsys and stored in the project directory. Click [Open].

• It may take around 30 seconds for the Eclipse application to parse the .sopcinfo file.

• Select a Project name. In this example, we are using HelloWorld as the project name.

• Ensure that: [x] Use default location is ticked.

• We now need to select a template from the Project Template list. In this example, select the Hello World template.

• Press the [ Finish ] button to complete the current step.

The Nios II SBT will now generate:

• a HelloWorld application folder that contains the hello_world.c file. We will replace that hello_world.c file with a custom program that later in this tutorial.

• a HelloWorld_bsp folder that contains the Nios II Board Support Package (BSP) hardware abstraction layer (HAL).


hypernios.sopcinfo



3 7.3 Configure the Board Support Package (BSP)The Nios II BSP must be configured before we can compile the source code.

• In the Project Explorer tab, right click on: HelloWorld_bsp → Nios II -> BSP Editor...




In the Main Tab of the BSP editor, in the panel on the left hand side, select:

Settings → Common

• Set the sys_clk_timer field to timer_0 This is used to generate a recurring system clock interrupt for the hardware abstraction layer.

• Set the timestamp_timer field to interval_timer This field is used to enable the hardware abstraction layer to perform fine precision timing.

• The Newlib ANSI C standard library can be configured as small or normal

• Generally, when mapping code and data to on-chip memory:◦ Tick the [x] Enable small C library field to reduce the size of the executable code

generated by the hardware abstraction layer (HAL). Ticking this option also reduces the functionality and performance of the HAL. Please note that the inbuilt memset() and memcpy() routines will be very slow.

• Generally, when mapping code to On-chip Flash:◦ Untick the [ ] Enable small C library field to increase the functionality and

performance of the executable code generated by the hardware abstraction layer (HAL). The inbuilt memset() and memcpy() routines will achieve good performance. However, the executable code will be considerably larger.

• We recommend UnTick the [ ] Enable small C library for this specific tutorial.


https://en.wikipedia.org/wiki/Newlib



In the Main Tab of the BSP editor, in the panel on the left hand side, select:

Settings → Advanced → hal.linker

For the purpose of this tutorial, the following configuration will generally work:

• Tick [x] allow_code_at_reset• Tick [x] enable_alt_load• Tick [x] enable_alt_load_copy_rodata• Tick [x] enable_alt_load_copy_rwdata• Tick [x] enable_alt_load_copy_exception• UnTick [ ] enable_exception_stack

However, this specific configuration may not be the best configuration for your project’s needs.

Please refer to Altera’s documentation for detailed information on how to setup the hal.linker fields:

Generic Nios II Booting Methods User Guide, UG-20001, 2016.05.24https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/niosii_generic_booting_methods.pdf


https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/niosii_generic_booting_methods.pdf

https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/niosii_generic_booting_methods.pdf



Select the Linker Script Tab of the BSP editor.

For this tutorial example, we are going to:• Map the reset vector (.reset) to the On-chip Flash memory (onchip_flash_0_data).

This is generated by Qsys and depends on the location of the Nios II reset vector.

• Map the exception vector (.exceptions) to the on-chip memory (onchip_memory2_0). This is generated by Qsys and depends on the location of the Nios II exception vector.

• Map the instruction code (.text) in the On-chip Flash memory (onchip_flash_0_data)

• Map all other data regions (.bss, .heap, .rodata, .rwdata, .stack) to the on-chip memory (onchip_memory2_0) )

This will map all memory regions generated by the GCC tools to the respective memory regions.For more information see: Nios II Gen2 Software Developer's Handbook, NII5V2Gen2, 2017.05.08 Section 5, Nios II Software Build Tools https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/nios2/n2sw_nii5v2gen2.pdf

Now:

• Click on the [ Exit ] button on the bottom right hand corner of the BSP Editor window.

• Then click on the [Yes, Save] button on the Save Changes window to save the BSP settings.


https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/nios2/n2sw_nii5v2gen2.pdf



4 7.4 Generate the BSP and clean the projectThe software developer must re-generate the BSP every time the Qsys project is regenerated. This ensures that the device drivers and addresses of peripherals are reflected correctly in the hardware abstract library. To (re)generate the BSP:

• Go to the Nios II eclipse window.

• Right click on HelloWorld_bsp project then select Nios II then select Generate BSP.

• Right click on the HelloWorld_bsp project then select Clean Project to delete any intermediate files generated by the gcc compiler for this application library.

• Right click on the HelloWorld project then select Clean Project to delete any intermediate files generated by the gcc compiler for this application folder.

5 7.5 Build the Nios II ApplicationWe now want to run the compiler and linker:

• Go to the Nios II eclipse window.

• Go to the menu bar and select: Project ->Build All

• If the project produces warning / error messages, you may need to build the project twice.

The HelloWorld executable firmware (.ELF) is now generated.

However, the .ELF file cannot be programmed directly into the On-chip Flash memory. To do that, we need to convert the .ELF file into one or more memory initialization files.




6 7.7 Generate memory initialization files If we want to embed the firmware into the EPCQ memory, we need to generate “memory initialisation” .hex files from the .elf file.

• In the Project Explorer tab, right click on: HelloWorld -> Make Targets → Build…

• A Make Targets window will open.

• Select mem_init_generate and click on the Build button.

• New hex files will be generated.

These files will be located in Project_dir → Software → HelloWorld → mem_init

The file onchip_flash_0.hex can be programmed into the On-chip Flash memory as described inthe next section.




8. Program the firmware into the On-chip Flash memory deviceNow we need to convert the hex file generated by the Eclipse toolkit into a format that can be used by the Quartus programmer.

7 8.1 Generating .pof Programming Files in the Quartus II Software

In Quartus Prime, open the Convert Programming files utility.

• Quartus Prime → File → Convert Programming files. A new window will open.

The following parameters need to be set:

• Programming File type to pof

• Mode to Internal Configuration

• File name to onchip_flash_helloworld.pof




Click on Options/Boot info..., the MAX 10Device Options dialog box appears.

Choose Load memory file for UFM source:option.

Browse to the generated Altera On-chip FlashHEX file (onchip_flash_0.hex) in the File path:.

Click OK.




In the Input files to convert section,

• Select the SOF Data and click on the Add File Tab (a new window will open). Select the.sof file Hello_example.sof previously generated by Quartus. This is located in Project_dir/output directory.

Press the generate button. A new file (onchip_flash_helloworld.pof) will be generated.




8.2 Programming the FPGA Bitstream and Firmware on the On-chip Flash using the Quartus II Programmer and .pof FilesTo program the on-chip flash configuration devices with .pof file, you must perform the following steps:

1. When the .pof file conversion is complete, add the .pof file to the Quartus II programmerwindow ◦ Connect the MAX 10 Evaluation kit to the USB port of your computer◦ In the Tools menu, choose Programmer◦ The Chain1.cdf dialog box appears. ◦ If any programming file has been automatically loaded, use the Delete button to

remove it. Make sure there is no programming file present inside the dialog box.

◦ Click Add File

◦ In the Select Programming File dialog box, browse to the .pof file.

◦ Click Open




◦ Program the on-chip flsh device by turning on the corresponding Program/Configure box,

◦ click Start

◦ The firmware is now programmed to the On-chip Flash memory

◦ Close the Programmer




10. Run the nios2-terminal applicationOnce programmed, the software firmware will start executing on power up. To see any messagesfrom the JTAG uart, follow these steps :

• In Linux: Open a Linux command shell / terminal• In Windows: Run the Nios II Command Shell application from the Windows start

menu.

• Run the nios2-terminal command from the terminal. • Messages similar to the one below should be displayed in the command shell.




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