sleep transistor circuits for fine-grained power switch-off with short power-down times
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Sleep Transistor Circuits for Fine-Grained Power Switch-Off with Short Power-Down Times. Mohammad Hashem Haghbayan Technical Faculty of Tehran University VLSI Seminar Dr.Fakhraie - PowerPoint PPT PresentationTRANSCRIPT
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Sleep Transistor Circuits for Fine-Grained Power Switch-Off with Short Power-Down Times
Mohammad Hashem Haghbayan
Technical Faculty of Tehran University
VLSI Seminar Dr.Fakhraie
St. Henzler1, Th. Nirschl1,2, S. Skiathitis1,3, J. Berthold2, J. Fischer1, Ph. Teichmann1, F. Bauer1, G. Georgakos2, D. Schmitt-Landsiedel1
1 Technical University Munich, Munich, Germany2 Infineon Technologies, Munich, Germany3 now with IBM, Böblingen, Germany
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Outline
Concept of fine-grained sleep transistor scheme
16 bit Multiply-Accumulate-Unit as demonstrator
Measurement methodology & techniques for
minimum power-down time reduction
Fractional switch activation for slow operation mode
Double switch scheme for fast block activation
Conclusion
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Footer and Header fine-grain sleep transistorimplementation in NAND gate [1]
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Coarse-Grain Sleep Transistors[1]
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Grid style sleep transistor implementations[1]
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Ring style sleep transistor implementations[1]
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Concept of Fine-Grained Power Switch-Off
SOC with large blocks
- individual activity profile
- varying frequency requirements
Block level MTCMOS
Fine-grained MTCMOS
- small sub-blocks
- short power-down times
SOC
ApplicationProcessor
DSP
technology scalingincreases leakage
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16 bit MAC System Overview
16 bit MAC as representative SOC building block
Two stage pipeline
- booth(2) precoding stage
- Han Carlson adder stage
High threshold PMOS sleep transistor (3 x 128 x 1.5m)
Input / output cache and BIST for full speed testing
Standard-cell based design using multi-Vth option
130nm low-power CMOS technology
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Multiply-Accumulate-Unit[2]
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Measurement of Max. Frequency[2]
5 % speed degradation and 8.5 % area overhead
9.5 % speed degradation and 2.8 % area overhead
1 1.2 1.4 1.6
400
600
800
1000
supply voltage [V]
max
imum
freq
uenc
y [M
Hz] no switch
large switchsmall switch
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0.5 1 1.510
-10
10-9
10-8
10-7
10-6
10-5
10-4
leak
age
curr
ent [
A]
supply voltage VDD
[V]
active switchinactive switchSC: V
GS=1.8V-V
DD
SC: VGS
=300mV
Leakage Reduction[2]
85 °C
GIDL
Super cut-off (SC):dramatically reduced leakage for appropriateunderdrive valuesachievable
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Frequency vs. Leakage Features[2]
max frequency leakage reduction (1.2V)
no switch 1GHz @1.6V 1x
large switch 950MHz 192x 86x
– with boosting 970 MHz 192x 86x
– super cut-off 0.3V 950 MHz 1179x 5508x
– SC: VGS=1.8V–VDD 950MHz 675x 2628x
small switch 905 MHz ILEAK (large switch) / 3
25 °C 85 °C
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0 10 20 30 40
0
0.2
0.4
0.6
0.8
1
1.2
virt
ual r
ail p
oten
tial [
V]
time after cut-off [s]
Leakage Reduction & Overhead[2]
what is the minimumpower-down time?
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Minimum Power-Down Time[2]
0 20 40 60 80 1000
1
2
3
4leakage for system always in active mode
leakage without switching overhead
leakage for system always in sleep mode
minimum sleep time
block activation frequency fa [kHz]
supp
ly c
urre
nt [
A]
5.8 s
Proposed measurement setup for experimental determination of minimum power-down time
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0 0.5 1 1.5 20.4
0.5
0.6
0.7
0.8
0.9
1
1.1
power-down time (norm.)
sup
ply
curr
ent (
norm
.)
VDD
=1.2V, T=25C
VDD
=1.2V, T=85C
VDD
=1.8V, T=25C
VDD
=1.8V, T=85C
ideal value
Temperature & Supply Voltage Dependence[2]
leakage currents ( e.g. temperature, VDD, Vth )
minimum power-down time
convergence time
crossover
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Switching Overhead[2]
turn off turn on
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Charge Recycling Scheme[2]
turn off turn on
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Efficiency of Charge Recycling[2]
2 3 4 5 6 7
-2
0
2
4
power-down time [s]
save
d en
ergy
[pJ]
25%
noCR
CR
with charge recyclingwithout charge recycling
T
T
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Impact of Virtual Supply Reduction[2]
200 400 600 8004
6
8
10
12
14
16
frequency [MHz]
dyna
mic
pow
er [m
W]
17.6%
6.8%
small switchlarge switch
Further reduction of minimum power-down time by fractional switch activation in slow mode of operation
Also observed: reduction of dynamic power
1.2V, 25 °C
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Power Impact of Adaptive Supply[2]
Quadratic impact on dynamic
power consumption:
Reasonable overhead only for
large logic blocks
VDD
t
fast
med
ium
slow
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Virtual Supply Reduction[2]
Reduced switching power min. power-down time
Linear impact on dynamic power consumption:
Lower power saving but negligible overhead
VDD
t
fast
med
ium
slow
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Power-Up Process Current spikes during block activation can cause
timing violations in surrounding blocks
Two contributors:
- Recharging of internal circuit nodes
- Uncontrolled transient glitching activity
Double switch scheme suppresses glitching
- Activate gates in two phases
- Demonstrated for filter circuit with NMOS sleep
transistors in 90nm low-power CMOS
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Double Switch Scheme[2]
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Impact of Double Switch Scheme[2]
0 10 20 30 40
0
4
time [ns]
i act
ivat
e [m
A]
38.8 %
0
4
8i a
ctiv
ate [m
A]
no double switch
double switch
Measured results for filter circuit with NMOS sleep transistors
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Conclusion[2] 130nm CMOS 16-bit mixed Vth pipelined MAC
PMOS sleep transistor results in up to 5500 x leakage reduction with only 8.5% area overhead and 5% frequency reduction
Accurate measurement methodology for minimum power-down time characterization
Charge recycling & fractional switch activation for reduction of minimum power-down time
Double switch scheme for reduction of current spikes during block activation
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References
1- Sleep transistor design and implementation – simple concept yet challenges to be optimum
Kaijian Shi, David Howard
2- sleep transistor circuits for fine-grained power switch-off with short power down times
St. Henzler1, Th. Nirschl1,2, S. Skiathitis1,3, J. Berthold2, J. Fischer1, Ph. Teichmann1, F. Bauer1, G. Georgakos2,
D. Schmitt-Landsiedel1