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TRANSCRIPT
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AGEN
DA
1. Overview of 8051 Architecture, Timing, On-chip Resources, Instruction Set etc. Derivative products
2. Programming the 8051: Basic techniques, tips & tricks.
3. Development Support: Development Boards, Emulators, EPROM Programmers, Compilers, etc.
4. I2C, a simple Multi-master 2-wire serial bus.
5. ACCESS.Bus, an I2C-based protocol for connecting peripherals to workstations/PCs.
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THE
8051
An 8-bit Microcontroller optimized for control applications.
A Microcontroller derivative family based on the 8051 core.
A Microcontroller because you can make a one-chip system with the one chip containing:
Program & Data Memory
I/O Ports
Serial Communication
Counters/Timers
Interrupt Control logic
A-to-D and D-to-A convertors
& so on ...
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FEATURES OF
THE 8051- 8 Bit data path and ALU.
- Easy interfacing.
- 12 to 30 MHz versions available.
( 1 sec to 400 ns for single cycleinstructions).
- Full instruction set including:
Multiply and Divide.
Bit set, reset, and test (Booleaninstructions).
- Variety of addressing modes.
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FEATURES OF THE
8051 (CONT'D)
- 4K X 8 ROM - Program memory.
- 128 x 8 RAM - Data memory.
- Special function registers.
- Serial I/O port.
- 32 I/O lines.
- Two 16-bit counter/timers.
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8051 LOGIC
SYMBOL
VSS VCC RST
P0.7P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
P
O
R
T
0
ADDRESS
AND
DATA BUS
XTAL1
XTAL2
AL E
EA
PSEN
P3.7
P3.6
P3.5
P3.4
P3.3P3.2
P3.1
P3.0
RxD
TxD
INT0
INT1
T0T1
WR
RD
SECONDARY
FUNCTIONS
P
O
R
T
3
P2.7
P2.6
P2.5
P2.4
P2.3P2.2
P2.1
P2.0
P
O
R
T
2
ADDRESS
BU S
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P
O
R
T
1
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80C51 BLOCK
DIAGRAM
Interrupt Control
External Interrupts
CPU
OSC
Timer 1
Timer 0
SerialPort
I/O PortsBusControl
CounterInputs
P0 P3P1
4k byteROM
128 byteRAM
P2(Address/Data)
TXD RXD
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ADDRESSING
SPACE
- 64K X 8 ROM - Program memory.
- 64K x 8 RAM - External data memory.
- 256 x 8 RAM - Internal data memory.
- 128 x 8 Special function registers (SFRs).
- Bit addressing of 16 RAM locations
and 16 SFRs.
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PROGRAM
MEMORY- 16 bit Program Counter (PC).
- 16 bit Data Pointer (DPTR).
- 64K byte address space each forProgram & Data.
- Table lookup using relative addressing:
PC + ACC (Move).
DPTR + ACC (Move and jump).
- EA pin disables internal ROM and
activates external program memory
and addressing.
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INTERNAL DATA
MEMORY- 128 bytes of RAM.
- Directly addressable range:
00 to 7F hexadecimal.
- Indirectly addressable range:
00 to FF hexadecimal.
- Bit addressable space:
20 to 2F hexadecimal .
- Four register banks:
00 to 1F hexadecimal.
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INTERNAL DATA
MEMORY7F
30
2F
20
R0
R1
R2
R3
R4
R5
R6
R7
REGISTER BANK 1
REGISTER BANK 2
END 8051 RAM
BIT ADDRESSABLE
REGISTER BANK 3
00
1F
0F
17
18
08
07
20
REGISTER BANK 0
07 . . . . . . . . . 00
FF . . . . . . . . . F8
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EXTERNAL DATA
MEMORY- 64K byte address space.
- Indirectly addressable via R0 and R1
in 256 byte segments.
- Entire space is indirectly addressable
via the data pointer DPTR.
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EXTERNAL BUS
EXPANSION
PORT 2
PORT 0
ALE
P3.7
P3.6
PSEN
8051
A15 - A8: High byte of address
AD7 - AD0: Data and low byte
address
ALE: Address latch enable
RD: Read strobe
WR: Write strobe
PSEN: Program store enable
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8051
TIMINGState 1 State 2 State 3 State 4 State 5 State 6 State 1 State 2
XTAL2
ALE
_____PSEN
P0
P2
Datasampled
PCL out PCL out
Datasampled
PCL out
Datasampled
PCH out PCH out
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
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PROGRAM
MEMORY
8051
PORT2
ALE
PORT0
PSEN
ADDRESS
LATCH
ROM(S)
ADDRESSINPUTS
DATA
OUTPUTS
OE
A15 - A8
A7 - A0
D7 - D0
AD7 - AD0
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EXTERNAL
DATA MEMORY 64K byte adress space.
Indirectly addressable via R0 and R1
in 256 byte segments.
Entire space in indirectly addressable
via the data pointer DPTR.8051
PORT 2
ALE
PORT 0
WR
RD
RAM(S) orI/O
CE
DATAOUTPUTS
ADDRESSINPUTS
R/W
OE
ADDRESSLATCH
DECODE
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SE
T RST pin is Schmitt trigger input. External reset is asychronous to the internal clock. RST pin must be high for at least two machine cycles while the oscillator is
running.
Internal RAM not affected by reset, but indeterminate on power up.
Port pins in random state until oscillator starts and algorithm write 1's to them.
Reset sets PC to 0000.
Typical circuits:
8051
RST
+5V
8.2K
10uF
80C51
RST
+5V
2.2uF
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SPECIAL FUNCTION
REGISTER SPACE
- 128 byte address space, directlyaddressable as 80 to FF hex.
- 16 addresses are bit addressable:
Set, Clear, AND, OR, MOV
(those ending in 0 or 8).
- This space contains:
Special purpose CPU registers.
I/O control registers.
I/O ports.
SPECIAL FUNCTION
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SPECIAL FUNCTION
REGISTER MAPF8
F0 BE8
E0 ACC
D8
D0 PSW
C8
C0
B8 IP
B0 P3
A8 IE
A0 P2
98 SCON SBUF
90 P1
88 TCON TMOD TL0 TL1 TH0 TH1
80 P0 SP DPH DPL PCON
Bit Addressable
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SPECIAL FUNCTION
REGISTERSCPU registers:
- ACC : Accumulator.
- B : B register.
- PSW : Program Status Word.
- SP : Stack Pointer.
- DPTR : Data Pointer (DPH, DPL).
Interrupt control:
-IE : Interrupt Enable.-IP : Interrupt Priority.
I/O Ports:
- P0 : Port 0.
- P1 : Port 1.
- P2 : Port 2.
- P3 : Port 3.
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SPECIAL FUNCTION
REGISTERS (CONT'D)TImers:
- TMOD : Timer mode.- TCON : Timer control.
- TH0 : Timer 0 high byte.
- TL0 : Timer 0 low byte.
- TH1 : Timer 1 high byte.
- TL1 : Timer 1 low byte.
Serial I/O:
- SCON : Serial port control.
- SBUF : Serial data registers.
Other:
- PCON : Power control & misc.
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PSW : PROGRAM
STATUS WORDCY AC F0 RS1 RS0 OV ---- P
- CY : Carry Flag.
- AC : Auxiliary Carry Flag.
- F0 : Flag 0 (available for user).
- RS1 : Register Select 1.
- RS0 : Register Select 0.
- OV : Arithmetic Overflow Flag.- P : Accumulator Parity Flag.
RS1 RSO Register Bank Address
0 0 0 00h - 07h
0 1 1 08h - 0Fh
1 0 2 10h - 17h
1 1 3 18h - 1Fh
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PORT
S- Four 8-bit I/O ports.
- Most have alternate functions.
- Quasi-bidirectional:
Soft pull-up when port latch
contains a 1. Can be used as
inputs (30Kohm average pullup).
Strong pull-up for 2 CPU cyclesduring 0 to 1 transitions.
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CONFIGURAT
ION
N M O S2 .PERIODS
Q
PORTPIN
FROMPORTLATCH
PORTPIN
QFROMPORTLATCH
2 OSC.PERIODS
P1 P2 P3
VCC
VCC
VCC
N
INPUTDATA
READ
PORTPIN
C M O S
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RT
0- As an I/O port:No strong pull-up, outputs act asopen drain.
- As a multiplexed data bus:
Tristate bus with strong pull-ups.
8-bit instruction bus, strobed by PSEN.
Low byte of address bus, strobed by ALE.
8-bit data bus, strobed by WR and RD.
- 3.2 mA outputs (about 8 LSTTL loads).
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RT
1As an I/O port:Standard quasi-bidirectional.
- Alternate functions:
Only on some derivatives.
- 1.6 mA outputs (about 4 LSTTL loads).
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RT
2- As an I/O port:Standard quasi-bidirectional.
- Alternate functions:
High byte of address bus for externalprogram and data memory accesses.
- 1.6 mA outputs (about 4 LSTTL loads).
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RT
3- As an I/O port:
Standard quasi-bidirectional.
- Alternate functions:
Serial I/O - TXD, RXD
Timer clocks - T0, T1Interrupts - INT0, INT1
Data memory - RD, WR
- 1.6 mA outputs (about 4 LSTTL loads).
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COUNTER /
TIMERS- Two 16-bit Counter/Timers:
Up counters, can interrupt on overflow.
- Counts:
CPU cycles (crystal/12).
External input (max. half CPU rate).
- Four Operation Modes.
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TIMER
MODES- Timer Mode 0 :
Emulates 8048 counter/timer (13-bits).8-bit counter (TL0 or TL1).
5-bit prescaler (TH0 or TH1).
- Timer Mode 1 :
Simple 16-bit counter.
- Timer Mode 2 :
8-bit auto-reload.
Counter in TL0 or TL1.
Reload value in TH0 or TH1.
Provides a periodic flag or interrupt.
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TIMER
MODES (CONT'D)- Timer Mode 3 :
Splits timer 0 into two 8-bit counter/timers.
First counter (TLO) acts like mode 0,
without prescaler.
Second counter (TH0):
Counts CPU cycles.
Uses TR1 (timer 1 run bit) as enable.
Uses TF1 (timer 1 overflow bit) as flag.Uses Timer 1 interrupt.
Timer 1 (when timer 0 is in mode 3 ):
Counter stopped if in mode 3.
Running in mode 0, 1, or 2.
Has gate (INT1) and external input (T1),
but no flag or interrupt.
May be used as a baud rate generator.
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COUNTER/TIMER IN
16-BIT (MODE 1)
Osc. 1Osc.
TL18-bits
TF1TH18-bits
Int er rupt
Cont rol
T1 (Pi n)
TR1
Gat e
INT1 (Pin)
The Gate input controls whether the Counter runs while gated by the interrupt signal or not.
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TMOD : COUNTER/TIMER
MODE REGISTER
- GATE : Permits INTx pin to enable/disable counter.
- C/T : Set for counter operation, reset for timer operation.
- M1, M0 :
00 : Emulate 8048 counter/timer (13-bits).
01 :16-bit counter/timer.
10 : 8-bit auto-reload mode
11 :Timer 0 = two 8-bit timers.
Timer 1 Counting disabled. Timing functionallowed. Can be used as Baud Rategenerator.
GATE C/T M1 M0 GATE C/T M1 M0
Timer 1 Timer 0
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TCON : COUNTER/TIMER
CONTROL REGISTER
- TF1, TF0 : Overflow flags for Timer 1 and Timer 0.
- TR1, TR0 : Run control bits for Timer 1 and Timer 0. Set torun, reset to hold.
- IE1, IE0 : Edge flag for external interrupts 1 and 0. *
Set by interrupt edge, cleared when interrupt is processed.
- IT1, IT0 : Type bit for external interrupts. *
Set for falling edge interrupts, reset for 0 level interrupts.
* = not related to counter/timer operation.
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
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INTERFAC
E- Full duplex UART.
- Four modes of operation:Synchronous serial I/O expansion.
Asynchronous serial I/O with variable
baud rate.
Nine bit mode with variable baud rate.
Nine bit mode with fixed baud rate.
- 10 or 11 bit frames.- Interrupt driven or polled operation.
- Registers:
SCON - Serial port control register.
SBUF - Read received data.
- Write data to be transmitted.PCON - SMOD bit.
SERIAL INTERFACE
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SERIAL INTERFACE
MODES OF OPERATIONTXD and RXD are the serial output and input pins (Port 3, bits 1 and 0).
Mode 0: Shift Register Mode. Serial data is transmitted/received on RXD. TXD outputs shift clock. Baud
Rate is 1/12 of clock frequency.
Mode 1: 10-bits transmitted or received. Start (0), 8 data bits (LSB first), and a stop bit (1). Baud RateClock is variable using Timer 1 overflow or external count input. Can go up to 104.2KHz (20MHz
osc.).
Mode 2: 11-bits transmitted or received. Start (0), 8 data bits (LSB first), programmable 9th bit, and stop bit(1). Baud Rate programmable to either 1/32 or 1/64 oscillator frequency (625KHz for 20MHzosc.).
Mode 3: 11-bit mode. Baud Rate variable using Timer 1 overflow or external input. 104.2 KHz max. (20
MHz osc.).
MULTI DROP
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MULTI-DROP
COMMUNICATIONSerial Communication Modes 2 and 3 allow one "Master" 8051 to control several "Slaves":
The serial port can be programmed to generate an interrupt if the 9th data bit = 1.
The TXD outputs of the slaves are tied together and to the RXD input of the master. The RXD inputs of theslaves are tied together and to the TXD ouput of the master.
Each slave is assigned an address. Address bytes transmitted by the master have the 9th bit = 1.
When the master transmits an address byte, all the slaves are interrupted. The slaves then check to see ifthey are being addressed or not.
The Addressed slave can then carry out the master's commands.
SCON : SERIAL
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SCON : SERIAL
CONTROL REGISTER
- SM0, SM1 = Serial Mode:
00 = Mode 0 : Shift register I/O expansion.
01 = Mode 1 : 8-bit UART with variable baud rate.
10 = Mode 2 : 9-bit UART with fixed baud rate.
11 = Mode 3 : 9-bit UART with variable baud rate.
- SM2 :
Mode 0 : Not used.Mode 1 : 1 = Ignore bytes with no stop bit.
Mode 2,3 : 0 = Set receive interrupt (RI) on all bytes.
: 1 = Set RI on bytes where bit 9 = 1.
- REN = Enables receiver.
- TB8 = Ninth bit transmitted (in modes 2 and 3).
- RB8 = Ninth bit received:Mode 0 : Not used.
Mode 1 : Stop bit.
Mode 2,3 : Ninth data bit.
- TI = Transmit interrupt flag.
- RI = Receive interrupt flag.
SMO SM1 SM2 REN TB8 RB8 TI RI
INTERRUPT
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INTERRUPT
SYSTEM- 5 Interrupt Sources (in order of priority):
External Interrupt 0.Timer 0.
External Interrupt 1.
Timer 1.
Serial Port.
- Each interrupt type has a separate
vector address.
- Each interrupt type can be programmed
to one of two priority levels.
- External interrupts can be programmed
for edge or level sensitivity.
IE INTERRUPT
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IE : INTERRUPT
ENABLE REGISTER
- EA : Global interrupt enable.
- ES : Serial interface.
- ET1 : Timer 1.
- EX1 : External interrupt 1.
- ET0 : Timer 0.
- EX0 : External interrupt 0.
- 0 = Disabled.
- 1 = Enabled.
EA ---- ---- ES ET1 EX1 ET0 EX0
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VECTOR
ADDRESSESSource AddressIE0 03H
TF0 0BH
IE1 13H
TF1 1BH
RI&TI 23H
The 8051 starts execution at 0000H after Reset.
IP INTERRUPT
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IP: INTERRUPT
PRIORITY REGISTER
- PS : Serial interface.
- PT1 : Timer 1.
- PX1 : External interrupt 1.- PT0 : Timer 0.
- PX0 : External interrupt 0.
- 0 = Low priority.
- 1 = High priority.
----- ----- ----- PS PT1 PX1 PT0 PX0
80C51(CMOS) VS
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80C51(CMOS) VS.
8051(NMOS)
Controlled Power Reduction
Idle State
Power down state
Power savings in CMOS ports
General purpose software flags
Higher speed versions in 80C51(up to 30MHz)
Static versions in development
PCON POWER
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PCON : POWER
CONTROL REGISTER
- POWER DOWN OPERATION
Setting PD bit stops oscillator.RAM contents are saved.
Exit via Reset.
Some (newer) 80C51 derivativesallow Power-Down wakeup viaInterrupt.
SMOD ---- ---- ---- GF1 GF0 PD IDL
PCON POWER
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PCON : POWER
CONTROL REGISTER- IDLE MODE OPERATION
Setting IDL gates clocks off, leaves oscillator running.All register and RAM contents are saved.
Interrupt sources remain active:
Serial interface.
External interrupts.
Timers.
Exit with any enabled interrupt or Reset.
- GF0, GF1 are general purpose software flags.
- SMOD serial interface control bit.
Doubles baud rate in modes 1,2, and 3.
- Only SMOD available on NMOS parts.
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ADDRESSING
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ADDRESSING
MODESThere are basically 5 ways of specifying source/destination operand addresses:
1. Particular On-chip Resources:This includes the Accumulator (A), the Stack Pointer (SP), the Data Pointer (DP), the ProgramCounter (PC), and the Carry (C). Other On-chip Registers are Memory-mapped while thesehave special Op-codes.
2. Immediate operands:
The # sign is the designator. These are 8-bits except for DPTR contents (16-bits).
3. Register operands:
Designated as Rn, where n is 0..7. One of the four Register Banks is used (PSW selected).
4. Direct Operands:
From 00 to FF Hex, specifies one of the internal data addresses.
5. Indirect Address:
Designated as @Ri, where i is 0 or 1, uses the contents of R0 or R1 in the selected RegisterBank to specify the address. Other form is @A, using Accumulator contents.
INSTRUCTION SET :
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INSTRUCTION SET :
ARITHMETICMnemonics Operands Bytes/Cycles
ADD A, Rn 1/1
ADDC A, direct 2/1
SUBB A, @Ri 1/1
A, #data 2/1
INC A 1/1DEC Rn 1/1
direct 2/1
@Ri 1/1
INC DPTR 1/2
MUL AB 1/4
DIV AB 1/4
DA A 1/1
INSTRUCTION
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INSTRUCTION
SET : LOGICMnemonic Operands Bytes/Cycles
ANL A, Rn 1/1
ORL A, direct 2/1
XRL A, @Ri 1/1
A, #data 2/1
direct, A 2/1
direct, #data 3/2C, bit 2/2
C, /bit 2/2
CLR A 1/1
CPL C 1/1
bit 2/1
INSTRUCTION SET :
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INSTRUCTION SET :
LOGIC (CONT'D)Mnemonic Operands Bytes/Cycles
RL A 1/1
RLC A 1/1
RR A 1/1
RRC A 1/1
SWAP A 1/1
SETB C 1/1
CLR bit
CPL
2/1
INSTRUCTION SET :
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INSTRUCTION SET :
DATA TRANSFERMnemonic Operands Bytes/Cycles
MOV A, Rn 1/1
A, direct 2/1
A, @Ri 1/1
A, #data 2/1
Rn, A 1/1
Rn , direct 2/2
Rn, #data 2/1
direct, A 2/1
direct, Rn 2/2
direct, direct 3/2direct, @Ri 2/2
direct, #data 3/2
INSTRUCTION SET : DATA
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INSTRUCTION SET : DATA
TRANSFER (CONT'D)Mnemonic Operands Bytes/Cycles
MOV @Ri, A 1/1
@Ri, direct 2/2
@Ri, #data 2/1
DPTR, #data16 3/2
C, bit 2/1
bit, C 2/2
MOVX A,@DPTR 1/2
@DPTR,A 1/2
A,@Ri 1/2
@Ri,A 1/2
INSTRUCTION SET: DATA
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INSTRUCTION SET: DATA
TRANSFER (CONT'D)Mnemonic Operands Bytes/Cycles
MOVC A, @A+DPTR 1/2
A, @A+PC 1/2
PUSH direct 2/2
POP direct 2/2
XCH A, Rn 1/1
A, direct 2/1
A, @Ri 1/1
XCHD A, @Ri 1/1
INSTRUCTION SET :
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INSTRUCTION SET :
BRANCHINGMnemonic Operands Bytes/Cycles
LCALL addr16 3/2
ACALL addr11 2/2
RET - 1/2
RETI - 1/2
LJMP addr16 3/2
AJMP addr11 2/2
SJMP rel 2/2
JMP @A+DPTR 1/2
JZ rel 2/2
JNZ rel 2/2
INSTRUCTION SET :
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INSTRUCTION SET :
BRANCHING (CONT'D)Mnemonic Operands Bytes/Cycles
CJNE A, direct, rel 3/2
A, #data, rel 3/2
Rn, #data, rel 3/2
@Ri,#data,rel 3/2
DJNZ Rn, rel 2/2
direct, rel 3/2
NOP - 1/1
JC rel 2/2
JNC rel 2/2
JB bit, rel 3/2
JNB bit, rel 3/2
JBC bit, rel 3/2
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THE I C BUS
(INTER - INTEGRATEDCIRCUIT)
A 2 wire serial data and control bus
Implemented with one serial data (SDA) and one clock(SCL) line.
Unique start and stop conditions.
Slave selection protocol uses a 7-Bit slave address.
Bi-directional data transfer.
Acknowledgement after each byte transferred.
No limit on the number of bytes transferred. Real multimaster capability.
2
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I2C BUS
FEATURES Clock synchronization.
Arbitration procedure.
Transmission speed up to 100Khz
Maximum bus length of 4 meters.
Maximum drive capacity of 400pF.
Allows series resistor for IC protection.
Compatible with most IC technologies (TTL, CMOS,Etc.).
I2C
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I2C
DEFINITIO
NSMASTER:
Initiates a transfer by generatingstart and stop conditions.
Generates the clock.
Transmits the slave address.
Determines data transfer direction.
SLAVE:
Responds only when addressed.
Timing is controlled by the clock line.
I2C
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I2C
HARDWARE
DETAILS Devices connected to the bus must have an open drain oropen collector output for serial clock and data.
The device must also be able to sense the logic level on thesepins.
All devices must have a common reference ground.
The serial clock and data lines are connected to VCC throughpull up resistors.
At any given moment the I2C bus is:
Idle,in Master transmit mode,or in Master receive mode.
THE OPEN DRAIN
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CONFIGURATION
OF I2C CIRCUITS
SCLK1
OUT
SCLK
IN
DATA1
OUT
DATA
IN
SCLK2
OUT
SCLK
IN
DATA2
OUT
DATA
IN
SDA
SCL
DEVICE 2DEVICE 1
I2C devices are wire ANDed together.
+VDD
Rp RpPull-upResistors
Serial clock line
Serial data line
START AND STOP
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START AND STOP
CONDITIONS A transition of the data line, when the clock line is high, is
defined as either a start or a stop condition.
Both start and stop conditions are generated by bus master.
The Bus is busy after a start condition.
SDA
SCL
StartCondition
StopCondition
S P
SDA
SCL
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BIT TRANSFER ON
THE I2C BUS
In normal data transfer, the data line only changesstate when the clock is low.
SDA
SCLData linestable:
Data valid
Change
of dataallowed
I2C
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I2C
ADDRE
SS Each node has a unique 7 bit address.
Peripherals usually have fixed and programmableaddress portions.
Addresses starting with 0000 or 1111 have specialfunctions.
0000000 is a general call address.0 0000001 isa null address. 1111xxxx isreserved for future bus expansion
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FIRST BYTE TRANSMITTED
ON THE I2C BUS
LSB ACK
7-bit slave address
R/W :0 - Slave will be written by master.1 - Slave will be read by master.
R/W
MSB
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ACKNOWLE
DGEMENT
Master/slave receivers pull data line low for one clockpulse after reception of a byte.
Master receiver leaves data line high after receipt ofthe last byte requested.
Slave receiver leaves data line high on the bytefollowing the last byte it can accept.
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DATA TRANSFER ON
THE I2C BUS
1 2 7 8 9
ACK
SCL
SDA
STARTCONDITION
STOPCONDITION
S P3 - 81 2 9
ACK
MSB
POSSIBLE DATA
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POSSIBLE DATA
FORMATS
S SLAVE ADDRESS W A DATA A DATA A P
Master Write:
Master Read:
Acknowledge from slave
Acknowledge from master
No acknowledge from master
S SLAVE ADDRESS R A DATA A DATA NA P
Acknowledge from slave
I2C CLOCK
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C C OC
SYNCHRONIZATIO
N Clock synchronization is used to synchronize arbitrating masters.
It can also be used as a handshake by a slave device to slow datatransfer from a master.
The clock synchronization procedure consists of two algorithms:
1) If the clockline goes low when a master is asserting a high,
the master asserts a low and starts to time out its low clock period.
2) When a master stops asserting a low on the clock line, it waits
until the clockline actually goes high before starting to time thehigh period.
I2C-BUS CLOCK
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I2C BUS CLOCK
SYNCHRONIZATION
PROCEDURE
SCL
CLK 2
CLK 1
Start countinglow period
Wait StateStart counting
high period
MULTIMASTER
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MULTIMASTER
I2C SYSTEMS
Multimaster situations require two additional features of the I2C protocol.
ARBITRATION:
Arbitration is the procedure by which competing masters decide final control of
the bus. I2C arbitration does not corrupt the data transmitted by the prevailing master.
Arbitration is performed bit by bit until it is uniquely resolved.
Arbitration is lost by a master when it attempts to assert a high on the data lineand fails..
ARBITRATION PROCEDURE
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ARBITRATION PROCEDURE
BETWEEN TWO MASTERS
SCL
SDA
DATA1
1 2 3 4 5
DATA2
Transmitter 1 loses arbitration
I2C
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I2C
FAMILY
ICS Microcontrollers
Microprocessors
General Purpose PeripheralsI/O, Memory, Display, DAC, ADC, Clock/Calendar
Peripherals for Specific Target Martkets
Audio, Telephony, Video
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AN OPEN
DESKTOP BUSSTANDARD
BASED ONI2C
ACCESS.B
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US .1
DEC has invented an interconnect method for connecting a PC or Workstation to
low speed I/O devices such as:
Keyboards
Mouses
Trackballs
Tablets
Low speed printers
Modems
This interconnect method, known as ACCESS.bus, is based on the I2C serial protocolinvented by Philips.
ACCESS.B
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US .2ACCESS.bus features:
80 KBps Peak Bandwidth
Hot plugging and unplugging of devices (keyboard, mouse, etc.)
Up to 14 devices
Up to 8 Meters (26.4 feet) in length
Serial, daisy-chained 4-pin cable (2 pins are power and ground). Only ONE device
port needed on computer.
BUS 3
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BUS .3
ACCESS.Bus features:
Layered 3-layer protocol defined by DEC:
Physical layer is I2C.
Base Protocol over I2C defines the structure of I2C messages and definesControl and Status Messages. Also supports auto-addressing and hot plugging.
Applications Protocol defines message semantics for particular device types.
Extremely low cost implementation based on off-the-shelf Microcontrollers with I2Csuch as the Signetics 83/87C751 (used in new DEC workstation ).
ACCESS.BUS 4
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US .4 Device address and type recognition is automatic. No drivers have to be loaded.
Concise protocol. Only 7 standard message types. Fully implemented in the87C751 with 2K of Program memory.
ACCESS.Bus is part of DEC's ARC and ACE platforms.
Fully open and free. No royalties.
DEC and Signetics will provide Developer's Kit with all information required to todevelop applications.
DEC's TRI/ADD developer program will provide technical support, documentationand updates, technical seminars, and newsletters and assist with marketingsupport.
.US 5
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US .5The closest thing to the ACCESS.bus is Apple's ADB (Apple Desktop Bus). The
following is a comparison between ADB and ACCESS.bus:
ADB ACCESS.bus
Hot-Plugging not recommended fully supported
Peak data rate 10 KBits/sec 80 KBits/sec
Daisy-chain limit 3 devices 14 devices
3rd party access Proprietary Open. No royalties
Max. cable length 5 meters 8 meters
DIRECTIONS FROM THE
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CORE PRODUCT
Very SmallPackages
ExtendedI/O
ASIC CellLibrary
I2C SerialBus
EEPROMderivatives
Memory2 to 32 K
EPROM &OTP
Analog-to-Digital
Low PowerLow Voltage
80C51
SpeedUp to 30 MHz
PHILIPS/SIGNETICS 8051FAMILY
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Product Name Process ROM RAM Pins 8-bit Ports Serial I/O Timers Special
8031/51 NMOS 4K 128 40 4 UART 2 Industry Standard
8032/52 NMOS 8K 256 40 4 UART 3 Industry Standard
8XC751 CEPROM 2K 64 24 2+3/8 I2C 1 24 Pin Skinny DIP
8XC752 CEPROM 2K 64 28 2+5/8 I2C 1 8-bit A/D,PWM
8XC31/51 CEPROM 4K 128 40 4 UART 2 20,24, 30MHz
8XCL410 SACMOS 4K 128 40 4 I2C 2 LowVolt/Power (1.8 volts)
80/3C851 EEPROM 4K 128 40 4 UART 2 256 EEPROM
8XC550 CEPROM 4K 128 40 4 UART 2 8-bit A/D, WD
8XC451 CEPROM 4K 128 68 7 UART 2 7 I/O Ports8XC652 CEPROM 8K 256 40 4 UART,I2C 2 8K ROM, I2C Serial Bus
8XC52 CEPROM 8K 256 40 4 UART 3 Industry Standard
8XC053/054 CEPROM 8K/16k 192 42 4 -- 2 TV Display (OSD), D/A
8XC562 CEPROM 8K 256 68 6 UART 4 8-bit A/D, PWM, WD, T2
8XC552 CEPROM 8K 256 68 6 UART,I2C 4 10-bit A/D, PWM, WD, T2
8XC654 CEPROM 16K 256 40 4 UART,I2C 2 16K ROM, I2C Serial Bus
8XC524 CEPROM 16K 512 40 4 UART, I2C 3 16K, 512 bytes, WD
8XC528 CEPROM 32K 512 40 4 UART,I2C 3 32K ROM, 512 RAM, WD
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80C51 CODING:
IDEAS ANDEXAMPLES
READING A TIMER
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"ON THE FLY"
ReadTimer: MOV ValH,TH0 ;Read initial timer high and low values.
MOV ValL,TL0
MOV A,TH0 ;Read timer high byte again.
CJNE A,ValH,ChkHigh ;Has it changed?
SJMP RTEX ;If not, first sample is OK.
ChkHigh: JB ValL.7,RTEX ;Otherwise, check low byte to see if it; changed after the original high byte
; sample.
MOV ValH,A ;If it did change, use second high byte
; sample.
RTEX: RET
COMP
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ARE
The 80C51 has no basic compare instruction. However, the CJNE (compare and jump if not
equal) instruction leaves the carry flag set after execution, allowing further magnitudecomparisons to be made.
This method works for all variations of CJNE:
CJNE A,direct,rel
CJNE A,#data,rel
CJNE Rn,#data,rel
CJNE @Ri,#data,rel
COMP
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AREExamples of four variations of magnitude comparison:
CJNE A,Value,Test ;Branch if A < Value.
Test: JC LT
CJNE A,Value,Test ;Branch if A >= Value.
Test: JNC GTE
CJNE A,Value,Test ;Branch if A > Value.
SJMP Else
Test: JNC GT
Else: -----
CJNE A,Value,Test ;Branch if A
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MODIFY-
WRITEMost instructions that reference 80C51 port data read the value on the port pins ratherthan the value in the port latch. However, some instructions read the port latch instead.
1) Arithmetic or logical operations that may alter port values:
ANL port,src
ORL port,src
XRL port,src
INC port
DEC port
DJNZ port,label
3) Instructions that may alter port bits:
MOV bit,C
JBC bit,label
CPL bit
CLR bitSETB bit
SINGLE STEP UNDER
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PROGRAM CONTROL
The 80C51 does not have any specific built-in facility for allowing a hardware single step
operation. However, when a Return from Interrupt instruction is executed, at least one
instruction from the originally interrupted routine is always executed before another
interrupt may be serviced.
Thus, if execution of RETIs are carefully controlled while an interrupt is pending, a
software single step may be effected.
SINGLE STEP UNDER
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PROGRAM CONTROLThis example uses external interrupt 0 as the means to accomplish the single step. This interrupt is a goodchoice because it is the highest priority interrupt . Note: the user program must not write to the IE or IPregisters or make use of other interrupt related functions.
;Set up for single step of some user routine:
StartSS: SETB PX0 ;Set INT0 as high priority.
SETB IT0 ;Set INT0 to edge triggered mode.
JNB INT0,$ ;Wait for a "single step" interrupt to come,
JB INT0,$ ; and go.
MOV IE,#81h ;Enable INT0 and insure that we are notLJMP UserProg ; interrupted during the following jump.
ExInt0: . . ;Code to dump registers, user program
. . ; address, etc.
JNB INT0,$ ;Wait for a "single step" interrupt to come,
JB INT0,$ ; and go.
RETI ;This RETI will allow one user program instruction to; execute, after which we will return to the INT0 service
; routine.
PULSE WIDTH
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MEASUREMENT
start timer
Problem: measure the width of aninput pulse.
?
stop timer
Assumption: use external interrupt 0 for the
pulse input. Use timer 0 in gated mode.
Note: to measure pulse low time in this
manner, the input must be invertedexternally.
PULSE WIDTH
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MEASUREMENTSetup: MOV TMOD,#09h ;Timer 0 gate on, in mode 1.
MOV TCON,#01h ;Set INT0 to edge triggered mode.
MOV TH0,#0 ;Clear timer 0 for measurement.MOV TL0,#0
SETB TR0 ;Start timer in gated mode.
SETB EX0 ;Enable external interrupt 0.
SETB EA ;Enable global interrupts.
. .
. .
. .
;External interrupt 0 service routine.
ExInt0: CLR TR0 ;Stop timer.
MOV ValH,TH0 ;Save timer value.
MOV ValL,TL0
MOV TH0,#0 ;Clear timer 0 for measurement.
MOV TL0,#0
SETB TR0 ;Restart timer.
RETI
PULSE PERIOD
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MEASUREMENT
start timer
Problem: measure the period ofan input pulse.
?
stop timer
Assumption: use external interrupt 0 for the
pulse input.
Note: this method may entail some loss of
precision due to the possibility ofvariable interrupt latency.
PULSE PERIOD
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MEASUREMENT
Setup: (same as previous example, but leave timer gate function turned off)
MOV TMOD,#01h ;Timer 0 in mode 1.
;External interrupt 0 service routine.
ExInt0: CPL TR0 ;Complement the timer run flag. This starts
; and stops the timer on alternate interrupts.
JB TR0,INT0EX ;Exit if timer is running.MOV ValH,TH0 ;Otherwise sample the timer value.
MOV ValL,TL0
MOV TH0,#0 ;Clear timer so another sample can
MOV TL0,#0 ; be taken.
INT0EX: RETI
CREATING AN
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OUTPUT PULSE
Problem: create a pulse of known
duration on a port pin.
stop pulsestart pulse,timer
timer
Note: the precision of pulses generated usingthis method will vary depending on theinterrupt latency of the timer interrupt.
Assumption: use any spare port bit forthe output.
CREATING AN
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OUTPUT PULSE
Setup: MOV TCON,#0h ;Make sure timer is stopped.
MOV TMOD,#01h ;Set timer to mode 1.
MOV TH0,#HiTime ;Load timer with pulse duration. The value is theMOV TL0,#LoTime ; two's complement of the
number of machine ; cycles to use for the pulsewidth.
SETB TR0 ;Start timer.
SETB P2.0 ;Start pulse (use CLR for a low going pulse).
;Tiimer 0 interrupt routine.
T0INT: CLR P2.0 ;End of pulse (use SETB for a low going pulse).
CLR TR0 ;Stop timer.
RETI
PROGRAMMING A
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PWM OUTPUTProblem: create a PWM output
on a port pin.
set timerhigh time
set timerlow time
repeat
Note: the precision of pulses generated usingthis method will vary depending on theinterrupt latency of the timer interrupt.
PROGRAMMING A
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PWM OUTPUTT0INT: CLR TR0 ;Stop timer.
CPL P2.0 ;Toggle output bit.JB P2.0,SetPWMHigh ;Is current phase high or low?
MOV TH0,PWMLowH ;Set PWM low time.
MOV TL0,PWMLowL
SJMP T0EX
SetPWMHigh: MOV TH0,PWMHighH ;Set PWM high time.
MOV TL0,PWMHighL
T0EX: SETB TR0 ;Restart timer.
RETI
Note: for higher frequency pulses, it may be possible to use thetimer reload feature (mode 2) to obtain more accurate pulsedurations.
BLOCK MEMORY MOVE WITH
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EXTERNAL DATA MEMORY
0000
FFFF
{
{
Problem: move any randomexternal data memory block ofany length to another location.
MEMORY
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MEMORY
MOVEBlockMove: MOV R0,#LOW(FromAddr) ;Initialize 'from' memory pointer.MOV P2,#HIGH(FromAddr)
MOV DPTR,#ToAddr ;Initialize 'to' memory pointer.MOV R1,#LOW(ByteCount) ;Initialize byte count.
MOV R2,#HIGH(ByteCount)
Loop: MOVX A,@R0 ;Read in a source block byte.
MOVX @DPTR,A ;Write byte out to destination block.
INC DPTR ;Increment 'to' memory pointer.
INC R0 ;Increment 'from' memory pointer.MOV A,R0
JNZ L1
INC P2
L1: DJNZ R1,Loop ;Decrement byte count and
DJNZ R2,Loop ; test for end of block.
RET
IMPLEMENTING A SECOND
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UART IN FIRMWAREOften, an application may require a second UART communication function. A simplex (transmit or
receive only at any one time) UART can be programmed with the use of one timer.
The transmit routine will simply start the timer, create a start bit, and then send one bit at every timerinterrupt, until finally sending the stop bit. The transmit bit may be any unused port bit.
Since the receive routine must sample each bit somewhere in the middle of the bit cell, it starts the timerwith a value of a half bit cell when a start is detected. Then, on the first timer interrupt, it verifies thepresence of the start bit and changes the timer count to one full bit cell. On every subsequent timerinterrupt, one data bit is read, until finally the stop bit is verified. The receive bit must be an externalinterrupt pin (usually INT0 or INT1).
UART FLOW:
START TRANSMIT
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START TRANSMIT
Start Transmit
Set up timer for one bit cell time.
Exit
Get byte to be transmittedand set bit count.
Send start bit.
UART FLOW:
START RECEIVE
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START RECEIVE
Exit
Start Receive
(START bit Interrupt)
Set bit count.
Set up timer for one halfbit cell time.
UART FLOW: TIMER
INTERRUPT
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INTERRUPT
Timer Interrupt
Advance bit count.
Receive? Y
Transmit One Bit
Receive One Bit
N
UART FLOW:
TRANSMIT ONE BIT
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TRANSMIT ONE BIT
Transmit One Bit
Exit
Done?
N
YSend STOP bit.
Rotate transmit byte andsend next data bit.
UART FLOW:
RECEIVE ONE BIT
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RECEIVE ONE BIT
Exit
Done?
N
Y
Receive One Bit
Look for START(set error flag and abort if
not found).
Get next data bit androtate into received
byte.
Look for STOP(set error flag and abort if
not found).
First bit?N
Y
Change timer setting to
one full bit cell time.
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SIGNETICS/CEIBO 80C51 FAMILY
DEVELOPMENT BOARD
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DEVELOPMENT BOARD Supports 80C51 derivative microcontrollers that have external program memory access
and serial port. Connects to an MS-DOS compatible PC via serial port (PC runs user interface software).
Line assembler and disassembler.
Register and memory contents may be viewed and altered.
Source, memory, register windows.
32K user program memory on board. Software breakpoints.
80C51 FAMILY
DEVELOPMENT BOARD
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DEVELOPMENT BOARD (CONTINUED)
Help screens.
Symbolic debugger.
Upload and download of object and hex files.
Fully documented. User's manual includes experiments for learning the developmentboard and the 80C51 architecture.
Switches, LEDs, and a potentiometer are included to allow simple experiments to beperformed without additional circuitry.
SUPPORTEDMICROCONTROLLE
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RS
8031/51
8032/52
8xC31/51
8xC32/52
8xC451
8xC550
8xC552
8xC528
8xC652/654
8xC851
Type 1 (full support via RS-232 to PC)
SUPPORTED
MICROCONTROLLERS
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MICROCONTROLLERS(CONTINUED)
The 8xC751 and 8xC752 have no external program memory capability and do notsupport user program loading on the DB-51.
The 8xC410 does not have an on-chip UART and must be communicated with via its I2Cport. The current version of the DB-51 does not support user program loading on the8xC410.
8xC410
8xC751
8xC752
Type 2 (limited support via I2C bus to type 1 device and PC)
DEMO BOARD
BLOCK DIAGRAM
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BLOCK DIAGRAM
Emulation
Memory32K x 8
Monitor
EPROM
Type 1
Microcontrolle
RS-232
Interface
Type 2
Microcontroller
I 2 C
b u s
MS-DOS
Compatible
PC
PC S oftware(user in terface)
USES FOR THE
DEMO BOARD
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DEMO BOARD
Training vehicle for 80C51 product seminars.
Self training and experimentation system for customers, FAEs, sales, factory, etc.
Basis for product demonstrations to customers.
Low cost development support, allows limited hardware and software prototyping.
EMULA
TORS
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TORSBSO/Tasking
128 Technology CenterP.O.Box 9164
Waltham, MA 02254-9164
(617) 894-7800
Signum Systems
171 E. Thousand Oaks Blvd., #202
Thousand Oaks, CA 91360
(805) 371-4608
And others...
Nohau Corp.
51 E. Campbell Ave.Campbell, CA 95008
(408) 866-1820
MetaLink Corp.
325 E. Elliot Road, Suite 23
Chandler, AZ 85225
(602) 926-0797
Ceibo Ltd.
105 Gleason Rd.
Lexington, MA 02173
(617) 863-9927
LIST OF PROGRAMMER
MANUFACTURER CONTACTS
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MANUFACTURER CONTACTSData I/O Corporation
10525 Willows Rd. N.E.
P.O. Box 97046
Redmond, WA 98073-9746
(206) 867-6899
Logical Devices, Inc.
1201 Northwest 65th PlaceFt. Lauderdale, FL 33309
(305) 974-0967
Signetics Co.
(contact nearest sales office)
And many others...
Ceibo Ltd.
105 Gleason Rd.
Lexington, MA 02173
(617) 863-9927
North Valley Designs
1610B Dell AvenueCampbell, CA 95008
(408) 866-4300
Needham's Electronics
4535 Orange Grove Ave.
Sacramento, CA 95841
(916) 924-8037
8051 CROSS
ASSEMBLERS
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ASSEMBLERS
Metalink
macro cross assembler ASM51
Public Domain! Free on the Signetics BBS
2500 AD software
Macro assembler
Cross assembler Simulator / debugger
And a host of others...
8051 C
COMPILERS
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COMPILERSArchimedes Software, Inc.
2159 Union Street
San Francisco, CA 94123-9923(415) 567-4010
Avocet Systems, Inc.
120 Union Street
P.O. Box 490 BP
Rockport, Maine 04856
(800) 448-8500
BSO/Tasking
128 Technology Center
PO Box 9164Waltham, MA 02254-9164
(617) 894-7800
2500 AD Software, Inc.
109 Brookdale Avenue
P.O. Box 480Buena Vista, CO 81211
(800) 843-8144
Franklin Software, Inc.
888 Saratoga Ave., #2
San Jose, CA 95129
(408) 296-8051
And others...
MICROCONTROLLER
SUPPORT BBS
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SUPPORT BBS
Support for Philips/Signetics PLDs and Microcontrollers
Modem 300/1200/2400 baud, 8-N-1
Download software:
- Public Domain 80C51 support tools
- Demonstration code
Send messages to Signetics applications engineers
(800) 451-6644
or
(408) 991-2406