small signal model
DESCRIPTION
small signal modelTRANSCRIPT
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Lecture 5 Review• Current Source• Active Load• Modified Large / Small Signal Models
– Channel Length Modulation
• Text sec 1.2 pp. 28-32; sec 3.2 pp. 128-129
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Current source• Ideal goal• Small signal
model:Open circuit“RD=∞”
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Realizing current source: MOSFET
• Large signal nonideality: Compliance range• “Looks like” current source only for VDS>Veff
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MOSFET ID-VDS characteristic for fixed VGS
• Small-signal nonideality: slope in active region
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Cause: Channel length modulation
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Channel length modulation
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Channel length modulation
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Modify small-signal model: Finite rds current source• Slope = ∆I/∆V
• Ideal:zero slope fi rds = ∞
rds =DVDI
SLOPE =DIDV
=1
rds
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Caution: rDS(on) vs. rds confusion!
rDS(on)
–Triode region–Large signal–True resistance
(V-I through origin)
rds
– Active region– Small signal– Models nonideality
of current source
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Refined MOSFET Small Signal Model
• Add rds in parallel with gmvgs current source at output• SAME FOR N-ch, P-ch• How to relate rds to DC operating point?• Example: gm = 2ID/Veff
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ID- VDS Characteristic for Different VGS
"Family" of curves
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ID- VDS Characteristic for Different VGS
Extrapolate backward: intersect at VDS-axis
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1/slope provides small signal resistance rds
• Intersect at -1/l Slope: 1rds
=ID
1 lfi rds =
1lID
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MOSFET small signal model
rds =1
lIDgm =
2IDVeff
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Increasing Gain• Typical gain (resistive load)
– Lab 4 example: |av | ≈ 2– Class example: |av | ≈ 11.1
• How to increase av?
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Transconductance gm
• Definition
gm =dID
dVGS
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Transconductance gm
• Definition
• ID fromSquare law:
• gm in terms ofW/L, Veff
gm =dID
dVGS
dIDdVGS
=d
dVGS
mnCox2
W2L2
VGS - Vtn( )Veff
1 2 4 3 4 2
È
Î
Í Í
˘
˚
˙ ˙
gm = mnCoxW2L2
Veff
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Summary of gm expressions• All equivalent!
choose whichevergives easier math
• Can’t memorize?rederive fromdefinition of gm
gm = mnCoxW2L2
Veff
gm =2IDVeff
gm = 2mnCoxWL
ID
gm =dID
dVGS
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Common source circuit (Lab 4)
Setting operating point:Adjusted function generator offset for DCoutput at midpoint of signal swing
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Common source circuit (Lab 4)
• DC operating point• Chosen for “halfway”
between rails• ID=1.25mA• Veff ≈ 2.0V (depends
on parameters)
VOUT = VDD - IDRDVOUT = +2.5V
ID =VDD - VOUT
RD
=5V - 2.5V
2kW= 1.25mA
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Common source circuit (Lab 4)
• Small signal gainmagnitude = 2.5
• Not impressive!
gm =2IDVeff
=2(1.25mA)
2.0V
gm =1.25mA / Vav = -gmRD = -(1.25mA/ V)(2 kW)av = -2.5
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How to increase av?
Look at gain expression: av = gmRD
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Increase RD
• New RD = 10kΩ (5X old value)• Problem:
DC operating point• Violates condition for
active region: triode!• DC operating point
stuck at negative rail
VOUT = VDD - IDRDVOUT = 5V - (1.25mA)(10kW)
12.5V1 2 4 4 3 4 4
VOUT = -7.5V ?
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Look at problem symbolically• Use gm=2ID/Veff
• IDRD = DC drop on load• Optimal bias at output:
constrained to VDD / 2
• ID, RD not involved!
• Value of approximate symbolic approachvs. “exact” numerical results from simulation
gm =2IDVeff
av = gmRD =2IDRD
Veff
IDRD =VDD
2
av =VDDVeff
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How to increase gain (resistive load)• increase VDD
– usually fixed byapplication, process
• decrease Veff– does increase gm– but ...
av =VDDVeff
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Problems decreasing Veff
• Veff, W/L gm expression:• 2X increase in gm:
4X increase in size(can’t increase IDRD)
• Increased area:cost penalty
• Increased capacitancespeed penalty
• Veff < ≈ 200 mV: subthreshold region– Not square law: gm expressions invalid
gm = 2mnCoxWL
ID
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Increase av: Different approach• Give up on resistive load ...• What is highest resistance?
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Increasing av: Different approach
• What is highest resistance?• Infinite: open circuit
• Problem: no path for ID
• Any circuit element that:– provides DC current, but– is open circuit in small signal model?
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Current source!• Open in small
signal model• Realizing current
source: MOSFET
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Lab Circuit: MOSFET with active load• Small signal model
for M1• Thevenin equivalent
“looking into”drain of M2(see text sec. 3.1)
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Small signal model
M1 common source M2 Theveninequivalent
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Simplify small signal model
Combine rds1, rds2 in parallel
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Small signal gain
voutvin
= av = -gm1 rds1 rds2( )
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Current source load: Large signal considerations
Output swing limits• Top:
M2 “crash” into triode• Bottom:
M1 crash into triode
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Common Source with Active Load• DC Sweep Schematic
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Active Load Simulation Result (DC Sweep)
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Determining DC Operating Point
Set smallsignal vin = 0
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Determining DC Operating Point
• Active region:Veff determines ID
• Correct VIN:M1, M2 “agree”
• Example:Veff1 = 1.0VID = 100 µA
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If DC bias at input is “wrong”?• Current source
"disagreement"• KCL crisis at output:
2µA, nowhere to go• What happens?
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If DC bias at input is “wrong”?• Capacitance
at output node Vout
• 2µA flows into cap,charges up fi VDS1 increases fi I1 increases
• fi VDS2 decreases fi I1 decreases
• Changes in VDScause changes in ID until “agreement” is reached: ID1 = ID2
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How much change in VDS?• Changes in VDS cause changes in ID until
“agreement” is reached: ID1 = ID2 BUT• Active region: ID is a weak function of VDS• Large change in VDS for small change in ID• Output very sensitive to changes in ID:• Small ∆Veff at input fi Small ∆ID fi
Requires large ∆VDS at output for ID agreementGood: high voltage gain
Bad: tricky to get correct input bias point
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Frequency Domain Considerations
• Ideal op-amp goals:– Infinite gain– Infinite bandwidth
• Active load helps gain• What about bandwidth?
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Frequency Domain Analysis• Start simple:
Assume singleCL at output
• (Ignore MOScapacitancesfor now …)
• Find transferfunction vout/vin
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Small signal model
• Combine rds1||rds2 = rout
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Simpler small signal model
• Combine rout CL into impedance ZL
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Simplified Small Signal Model
• Small signal gain: vout/vin = av = -gmZL
• Frequency dependence of ZL providesfrequency dependence of transfer function
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Closer Look at ZL:• Impedance is parallel
combination of rout, 1/sCL
ZL = rout1
sCL=
11
rout+ sCL
ZL =rout
1 + sroutCL
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Behavior of ZL over frequency:• Let s=jw ZL =
rout1 + jwroutCL
• Low frequency limit:mostly rout
• High frequency limit: mostly CL
w <<1
routCLfi ZL =
rout1 + jwroutCL
ª rout
w >>1
routCLfi ZL =
rout1 + jwroutCL
ªrout
jwroutCLª
1jwCL
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Transfer function• Substitute in ZL
voutvin
= -gmZL =-gmrout
1 + jwroutCL
• Magnitudevoutvin
=gmrout
1 + wroutCL( )2
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Bode Plot of Transfer Function Magnitude
voutvin
=gmrout
1 + wroutCL( )2
Magnitude vs. Frequency (log-log plot)Bandwidth: w3dB
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3-dB Frequency / Bandwidth• Frequency at which magnitude is 3 dB down
(reduced by factor 1/√2)
MAX voutvin
= gmrout AT w = 0
THEN AT w3dB, voutvin
=12
gmrout
12
gmrout =gmrout
1+ w3dBroutCL( )2fi w3dB =
1routCL
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Revisit Bode Plot:• Gain, Bandwidth inversely related!
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Unity Gain Frequency wT / Gain-Bandwidth Product• wT : Frequency at which magnitude is 1
Use approximation wT >> 1/routCL
†
1=gmrout
1+ wT routCL( )2ª
gmrout
wT routCL( )2fi wT =
gm
CL
†
av = gmrout w3dB =1
routCL
fi gmrout
GAIN1 2 3
⋅1
routCL
BANDWIDTH1 2 3
=gm
CL
• Gain x Bandwidth Product
• Independent of rout!– Poorly controlled rout OK
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Summary: Active Load• Active load DC considerations:
– Output swing limited by triode “crash”– To voltage within Veff of rail
• Active load good news / bad news:– Good news: high gain– Bad news: very sensitive to input DC bias
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Massage small signal gain result
• Small signal gain
• Look at parallelcombination
• Substituteexpression for rds
av = gm1 rds1 rds2( )rds1 rds2 =
11
rds1+
1rds2
rds1 rds2 =1
l1ID + l 2ID
rds1 rds2 =1
l1 + l2( )ID
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Massage small signal gain result
• Small signal gain
• Substitute for gm,parallel rds
• ID drops out!
Only l, Veff to work with
av = gm1 rds1 rds2( )av =
2IDVeff1gm1
1l1 + l 2( )ID
rds1 rds2
1 2 4 4 3 4 4
av =2
l1 + l2( )Veff1
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Improve Gain• Reduce Veff
– Minimum ≈ 200 to 300mV (subthreshold)– May not want to go that low (W,L too big)
• Reduce l1, l2
– How? Where does l1 come from?
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Square law model with channel length mod
ID-sat term (at pinchoff) + "extra"
ID =mnCox
2WL
VGS - Vtn( )2
ID -sat1 2 4 4 4 4 3 4 4 4 4
1 + l VDS - Veff( )[ ]
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Square law model with channel length modulation
• Fractional extra part is l(VDS-Veff)• Meaning of l:
Fractional change in current ID pervolt change in VDS
ID =mnCox
2WL
VGS - Vtn( )2
ID -sat1 2 4 4 4 4 3 4 4 4 4
1 + l VDS - Veff( )[ ]
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What causes change? Where does l come from?• Change in effective channel length L• One way to reduce l: longer L• Change ∆L represents smaller fraction
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After some semiconductor physics ...
• KS Silicon dielectric constant 11.8• NSUB Substrate doping units /cm3
Sanity check: 1E+14 to 1E+17• ∆VDS from active-triode edge to “large” VDS• Caution: consistent length units on L, NSUB, e0
l =DID IDDVDS
DIDID
=DLL
l =1L
DLDVDS
DLDVDS
=2KSe0qNSUB
12 VDS - Veff
l =1L
2KSe0qNSUB
12 VDS - Veff
• Definition of l• Fractional
change
• Semiconductorphysics ...(see J&M p. 26)
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Substrate doping NSUB parameter• Needed for SPICE
Extraction procedure:1) Calculate slope from ID-VDS plot2) rds = 1/slope (small signal model)3) Calculate l4) Calculate NSUB
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ExampleVDS-ID data from Lab 5 for P-channel MOSFET:
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1) Calculate slope from ID-VDS plot2) rds = 1/slope (small signal model)
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3) Calculate l
ID = 482 µA
†
l =1
ID ⋅rds=
1482mA( ) 40.2kW( )
=1
19.4V= 0.052V -1
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4) calculate NSUB
• For CD4007, L = 10µm = 1.0E-5m• VDS, Veff for largest VDS data point
†
l =1L
2KSe0qNSUB
12 VDS -Veff
0.052V -1 =1
1E - 5m( )2 11.8( ) 8.85E -12F /m( )
1.6E -19coul( )NSUB
12 4.48V - 0.84V
NSUB = 3.32E + 22 m-3 = 3.32E +16 cm-3
VDS = 4.48 V
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Simulation exercise• Add NSUB to N-channel, P-channel models• DC sweep for CS Amplifier with Active Load
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Common Source with Active Load (DC)• Sweep input over full range 0 to +5V
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DC Sweep Around Operating Point