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SMPTE 2022-5/6 Video over IP Transmitter v4.0

LogiCORE IP Product Guide

Vivado Design Suite

PG032 October 5, 2016

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Table of Contents

IP Facts

Chapter 1: Overview

Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chapter 2: Product Specification

Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Maximum Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chapter 3: Designing with the Core

Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Memory Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Chapter 4: Design Flow Steps

Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Chapter 5: Test Bench

Demonstration Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Appendix A: Verification, Compliance, and Interoperability

Appendix B: Migrating and Upgrading

Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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Appendix C: Debugging

Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Vivado Lab Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Core Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Appendix D: Additional Resources and Legal Notices

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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LogiCORE IP SMPTE 2022-5/6 TX v4.0 www.xilinx.com 4PG032 October 5, 2016 Product Specification

IntroductionThe Xilinx LogiCORE™ IP SMPTE 2022-5/6 Video over IP Transmitter is a module for broadcast applications that requires bridging between SMPTE video connectivity standards (SD/HD/3G-SDI) and 10 Gb/s networks. It is capable of mapping SD/HD/3G-SDI video streams into Ethernet packets and adding systematically generated redundant data. This allows the receiver to detect and correct a limited number of packet errors without the need to ask the transmitter for retransmission of lost packets. The core is for developing Internet protocol-based systems to reduce overall cost in broadcast facility for distribution and routing of audio video data.

Features• Encapsulates SD/HD/3G streams from up to

8 inputs according to SMPTE2022-6.Supports SD-SDI, HD-SDI, 3G-SDI Level-A,3G-SDI Level-B single stream and 3G-SDILevel-B dual stream.

• Per stream basis Forward Error Correction(FEC) packet generation in accordance toSMPTE2022-5

• Supports Level A and Level B FECoperations

• Supports block-aligned and non-blockaligned FEC operations

• Dynamic switching of L and D values in FECmatrix over AXI4-Lite interface

• Supports Virtual Local Area Network(VLAN) tagging

• User configurable Ethernet, IP, UDP and RTPheaders over AXI4-Lite interface

• Support Seamless protection switching inaccordance to SMPTE2022-7

• Statistics Indicator

° Transmitted packet per stream per link

Features (continued)

• Configure inclusion (or exclusion) of FECsupport capability during compile time.

• Configure inclusion (or exclusion) ofseamless protection switching capabilityduring compile time.

• AXI4-Stream data interfaces

• AXI4-Lite control interface

IP Facts

LogiCORE IP Facts Table

Core Specifics

Supported Device Family(1)

Kintex® UltraScale™, Zynq®-7000 AllProgrammable SoC,Virtex®-7, Kintex-7

Supported User Interfaces AXI4-Lite, AXI4-Stream, AXI4

Resources See Table 2-1, Table 2-2, and Table 2-3.

Provided with Core

Design Files Encrypted HDL

Example Design

SMPTE 2022-5/6 High Bit Rate Media TransportOver IP Networks with Forward Error Correction

(XAPP1199) [Ref 1]

Test Bench Verilog and VHDL

Constraints File XDC

Simulation Model

Encrypted RTL,VHDL Behavioral, VHDL or Verilog source HDL

Supported S/W Driver N/A

Tested Design Flows(2)

Design Entry Vivado® Design Suite

Simulation For supported simulators, see theXilinx Design Tools: Release Notes Guide.

Synthesis Vivado Synthesis

Support

Provided by Xilinx @ www.xilinx.com/support

Notes: 1. For a complete list of supported devices, see the Vivado IP

catalog.2. For the supported versions of the tools, see the

Xilinx Design Tools: Release Notes Guide.

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Chapter 1

OverviewAs broadcast and communications markets converge and the use of IP networks for transport of video streams becomes more attractive to broadcasters and telecommunications companies alike, the adoption of 10 Gb/s Ethernet for the transmission of multiple uncompressed Serial Digital Interface (SDI) streams is becoming a major customer requirement. The industry is primarily looking at the SMPTE 2022 set of standards to create an open and interoperable way of connecting video over 10GbE equipment together and ensure that Quality of Service (QoS) is high and packet loss is kept to a minimum or recovered through FEC. As shown in Figure 1-1, high bit rate SMPTE 2022-5/6 is aimed at contribution networks (for example, between broadcast center and regional studio).

The core includes Forward Error Correction (FEC). FEC protects the video stream during transport of high-quality video over IP networks. With FEC, the transmitter adds systematically generated redundant data, along with the video. This carefully designed redundancy allows the receiver to detect and correct a limited number of packet errors occurring anywhere in the video without the need to ask the transmitter for retransmission.

These errors, in the form of lost video packets, can be caused by many reasons, from thermal noise to storage system defects and transmission noise introduced by the environment. FEC gives the receiver the ability to correct these errors without needing a reverse channel to request retransmission of data. In real time systems, the latency is too great to request a retransmission. The ability of Xilinx FPGAs to bridge the broadcast and the communications industries by performing highly integrated real-time video interfaces helps broadcasters reduce costs as well as reduce the overall time it takes to acquire, edit and produce content. Now that video can be reliably delivered over 10 Gb/s Ethernet (10GbE), broadcasters can replace some of the expensive mobile infrastructures supporting

X-Ref Target - Figure 1-1

Figure 1‐1: High Bit Rate SMPTE 2022-5/6 between Broadcast Center and Local Studio

..

..

..

..

X12506

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Chapter 1: Overview

outside live broadcasts, as well as enabling remote production from existing fixed studio set ups, dramatically reducing both capital expenditure and operating expenses.

Feature SummaryThe core maps raw SD/HD/3G-SDI video streams into Ethernet packets as per SMPTE 2022-6. For each media stream with SMPTE 2022-6, the core creates the Forward Error Correction streams in accordance with SMPTE 2022-5 for recovery of IP packets lost to network transmission errors and ensures the highest picture quality of uncompressed, high bandwidth professional video.

The core support of VLAN comes from being able to operate seamlessly when receiving VLAN tagged Ethernet packets. You can configure and instantiate the core from the Vivado® Design Suite. Core functionality can be controlled dynamically through an AXI4-Lite interface.

Applications• Transport uncompressed high bandwidth professional video streams over IP networks.

• Support real-time audio/video applications such as contribution, primary distribution,and digital cinema

Licensing and Ordering Information

License Checkers

If the IP requires a license key, the key must be verified. The Vivado design tools have several license check points for gating licensed IP through the flow. If the SMPTE20222-5/6 TX Core license check succeeds, the IP can continue generation. Otherwise, generation halts with error. License checkpoints are enforced by the following Vivado flow:

Vivado flow: Vivado Synthesis, Vivado Implementation, write_bitstream (Tcl Console command)

IMPORTANT: The IP license level is ignored at checkpoints. The test confirms a valid license exists. It does not check IP license level.

If a Hardware Evaluation License is being used, the core will stop transmitting Ethernet packets after timeout.

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Chapter 1: Overview

License Type

This Xilinx LogiCORE™ IP module is provided under the terms of the Xilinx Core License Agreement. The module is shipped as part of the Vivado Design Suite. For full access to all core functionalities in simulation and in hardware, you must purchase a license for the core. Contact your local Xilinx sales representative for information about pricing and availability.

For more information, visit the SMPTE 2022-5/6 Video Over IP product web page.

Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page. For information on pricing and availability of other Xilinx LogiCORE IP modules and tools, contact your local Xilinx sales representative.

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Chapter 2

Product Specification

StandardsThe core is compliant with the AXI4, AXI4-Stream and AXI4-Lite interconnect standards. See the “Video IP: AXI Feature Adoption” section of the AXI Reference Guide (UG1037) [Ref 2] for additional information. The function of the core is compliant with SMPTE 2022-5/6 standard.

Maximum FrequenciesThe maximum achievable clock frequency can vary. The maximum achievable clock frequency and all resource counts can be affected by other tool options, additional logic in the FPGA, using a different version of Xilinx tools and other factors. See Table 2-1 through Table 2-3 for device family specific information.

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Resource UtilizationResources required for this core have been estimated for Zynq®-7000 All Programmable SoC, Virtex®-7, and Kintex®-7 devices. These values were generated using the Xilinx Vivado® Design Suite. UltraScale™ results are expected to be similar to 7 series results.

Table 2‐1: Resource Utilization for Zynq-7000 Devices (xc7z045, speed -1)

SDICHANNEL

FECINCLUDE FFs LUTs Slices

LUT FF Pairs

36k BLockRAMs

18k BLockRAMs DSP48E1s

1 0 9,494 7,672 2,985 9,760 16 2 0

2 0 12,518 10,154 4,031 12,798 18 2 0

3 0 15,670 11,565 5,079 15,990 20 2 0

4 0 18,833 13,375 6,260 19,135 22 2 0

5 0 21,992 15,775 6,977 22,141 31 2 0

6 0 25,149 17,391 7,605 24,688 33 2 0

7 0 28,047 18,496 8,154 26,849 35 2 0

8 0 31,268 19,506 9,710 31,153 37 2 0

1 1 13,067 9,948 4,203 13,391 52 7 0

2 1 16,567 13,099 5,031 1,6746 54 7 0

3 1 20,105 15,123 6,586 20,566 56 7 0

4 1 23,585 16,755 7,258 23,467 58 7 0

5 1 27,120 19,562 8,009 26,697 67 7 0

6 1 30,630 21,926 9,320 30,408 69 7 0

7 1 33,881 23,339 10,659 34,160 71 7 0

8 1 37,487 24,750 12,115 38,365 73 7 0

Table 2‐2: Resource Utilization for Virtex 7 FPGAs (xc7vx690t, speed -1)

SDICHANNEL


LUT FF Pairs

36k BlockRAMs

18k BlockRAMs DSP48E1s

1 0 9,478 7,657 2,989 9,830 16 2 0

2 0 12,518 10,149 4,050 12,880 18 2 0

3 0 15,654 11,549 4,852 15,764 20 2 0

4 0 18,817 13,362 6,442 19,354 22 2 0

5 0 21,976 15,779 7,187 22,308 31 2 0

6 0 25,149 17,401 8,448 25,555 33 2 0

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7 0 28,047 18,493 8,765 27,738 35 2 0

8 0 31,284 19,368 8,990 29,942 37 2 0

1 1 13,083 9,946 4,179 13,385 52 7 0

2 1 16,551 13,160 5,625 17,184 54 7 0

3 1 20,089 15,087 6,685 20,774 56 7 0

4 1 23,585 16,758 7,883 23,998 58 7 0

5 1 27,136 19,567 9,407 28,077 67 7 0

6 1 30,630 21,916 10,155 31,484 69 7 0

7 1 33,881 23,330 10,406 33,656 71 7 0

8 1 37,471 24,735 11,557 37,416 73 7 0

Table 2‐3: Resource Utilization for Kintex-7 FPGAs (xc7k325t, speed -1)

SDICHANNEL


LUT FF Pairs

36k BLockRAMs

18k BLockRAMs DSP48E1s

1 0 9,494 7,662 3,233 10,087 16 2 0

2 0 12,518 10,148 3,954 12,814 18 2 0

3 0 15,654 11,556 5,132 16,018 20 2 0

4 0 18,833 13,358 5,918 18,799 22 2 0

5 0 21,992 15,788 7,461 22,507 31 2 0

6 0 25,133 17,440 8,566 25,713 33 2 0

7 0 28,047 18,495 8,476 27,065 35 2 0

8 0 31,268 19,500 9,036 30,235 37 2 0

1 1 13,067 9,936 3,870 13,023 52 7 0

2 1 16,567 13,093 5,125 16,773 54 7 0

3 1 20,105 15,091 5,817 19,887 56 7 0

4 1 23,585 16,769 7,563 23,859 58 7 0

5 1 27,120 19,563 8,341 27,131 67 7 0

6 1 30,646 21,979 9,642 30,921 69 7 0

7 1 33,881 23,333 11,242 34,881 71 7 0

8 1 37,487 24,741 11,558 37,333 73 7 0

Table 2‐2: Resource Utilization for Virtex 7 FPGAs (xc7vx690t, speed -1) (Cont’d)

SDICHANNEL


LUT FF Pairs

36k BlockRAMs

18k BlockRAMs DSP48E1s

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Port DescriptionsThe core uses industry standard control and data interfaces to connect to other system components. The following sections describe the various interfaces available with the core. Figure 2-1 shows an I/O diagram of the core. The RX_SDI interface pins depend on the number of channels configured through the Vivado Integrated Design Environment (IDE).

Common Interface

Table 2-4 summarizes the signals which are either shared by, or are not part of the dedicated SDI, AXI4-Stream, AXI4 or AXI4-Lite control interfaces.


Figure 2‐1: Core Top Level Signaling Interface

Table 2‐4: Common Interface Signals

Signal Name Direction Width Description

eth_rst In 1 Ethernet clock domain reset

eth_clk In 1 Ethernet clock

sys_rst In 1 System clock domain reset

sys_clk In 1 System clock

rtp_ts_clk In 1 This port enables the signal for the core logic operating at nominally 27MHz.

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AXI Memory Master Interface

The core uses an AXI4 interface to connect to the AXI4 interconnects. The AXI4 Interconnect provides the access to the external memory through the AXI Double Data Rate (DDR) controller. See the LogiCORE IP AXI Interconnect Product Guide (PG059) [Ref 3] for more information.

interrupt Out 1 Reserved

soft_reset Out 1 Core reset generated from specific control register bit

Table 2‐5: AXI4 Memory Interface Signals


m0_axi_awid Out 1 Write Address Channel Transaction ID

m0_axi_awaddr Out 32 Write Address Channel Address

m0_axi_awlen Out 8 Write Address Channel Burst Length code

m0_axi_awsize Out 3 Write Address Channel Transfer Size code

m0_axi_awburst Out 2 Write Address Channel Burst Type

m0_axi_awlock Out 2 Write Address Channel Atomic Access Type

m0_axi_awcache Out 4 Write Address Channel Cache Characteristics

m0_axi_awport Out 3 Write Address Channel Protection Bits

m0_axi_awqos Out 4 Write Address Channel Quality of Service

m0_axi_awvalid Out 1 Write Address Channel Valid

m0_axi_awready In 1 Write Address Channel Ready

m0_axi_wdata Out 256 Write Data Channel Data

m0_axi_wstrb Out 32 Write Data Channel Data Byte Strobes

m0_axi_wlast Out 1 Write Data Channel Last Data Beat

m0_axi_wvalid Out 1 Write Data Channel Valid

m0_axi_wready In 1 Write Data Channel Ready

m0_axi_bid In 1 Write Response Channel Transaction ID

m0_axi_bresp In 2 Write Response Channel Response Code

m0_axi_bvalid In 1 Write Response Channel Valid

m0_axis_bready Out 1 Write Response Channel Ready

m0_axi_arid Out 1 Read Address Channel Transaction ID

Table 2‐4: Common Interface Signals (Cont’d)


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m0_axi_araddr Out 32 Read Address Channel Address

m0_axi_arlen Out 8 Read Address Channel Burst Length code

m0_axi_arsize Out 3 Read Address Channel Transfer Size code

m0_axi_arburst Out 2 Read Address Channel Burst Type

m0_axi_arlock Out 2 Read Address Channel Atomic Access Type

m0_axi_arcache Out 4 Read Address Channel Cache Characteristics

m0_axi_arprot Out 3 Read Address Channel Protection Bits

m0_axi_arqos Out 4 AXI4 Read Address Channel Quality of Service

m0_axi_arvalid Out 1 Read Address Channel Valid

m0_axi_arready In 1 Read Address Channel Ready

m0_axi_rid In 1 Read Data Channel Transaction ID

m0_axi_rdata In 256 Read Data Channel Data

m0_axi_rresp In 2 Read Data Channel Response Code

m0_axi_rlast In 1 Read Data Channel Last Data Beat

m0_axi_rvalid In 1 Read Data Channel Valid

m0_axi_rready Out 1 Read Data Channel Ready

m1_axi_arid Out 1 Read Address Channel Transaction ID

m1_axi_araddr Out 32 Read Address Channel Address

m1_axi_arlen Out 8 Read Address Channel Burst Length code

m1_axi_arsize Out 3 Read Address Channel Transfer Size code

m1_axi_arburst Out 2 Read Address Channel Burst Type

m1_axi_arlock Out 2 Read Address Channel Atomic Access Type

m1_axi_arcache Out 4 Read Address Channel Cache Characteristics

m1_axi_arprot Out 3 Read Address Channel Protection Bits

m1_axi_arqos Out 4 AXI4 Read Address Channel Quality of Service

m1_axi_arvalid In 1 Read Address Channel Valid

m1_axi_arready In 1 Read Address Channel Ready

m1_axi_rid In 1 Read Data Channel Transaction ID

m1_axi_rdata In 256 Read Data Channel Data

Table 2‐5: AXI4 Memory Interface Signals (Cont’d)


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AXI4-Stream Master Interface: Transmit

See the LogiCORE IP 10-Gigabit Ethernet MAC Product Guide (PG072) [Ref 4] for more information.

Society of Motion Picture and Television Engineers (SMPTE) SD/HD/3G-SDI Interface

See the Society of Motion Picture and Television Engineers (SMPTE) SD/HD/3G-SDI 2.0 Product Guide (PG071) [Ref 5] for more information.

m1_axi_rresp In 2 Read Data Channel Response Code

m1_axi_rlast In 1 Read Data Channel Last Data Beat

m1_axi_rvalid In 1 Read Data Channel Valid

m1_axi_rready Out 1 Read Data Channel Ready

Table 2‐6: AXI4-Stream Interface Signals


pri/sec_m_axis_aresetn Out 1 Active Low reset

pri/sec_m_axis_tdata[63:0] Out 64 AXI4-Stream Data to XGMAC

pri/sec_m_axis_tkeep[7:0] Out 8 AXI4-Stream Data Control to XGMAC

pri/sec_m_axis_tvalid Out 1 AXI4-Stream Data Valid input to XGMAC

pri/sec_m_axis_tlast Out 1 AXI4-Stream last Data input to XGMAC

pri/sec_m_axis_tready In 1 AXI4-Stream acknowledges signals from XGMAC to indicate to start the data transfer

Table 2‐7: SMPTE SD/HD/3G-SDI Interface Signals

Signal Name(1) Direction Width Description

rx[0-7]_rst In 1 Reset

rx[0-7]_clk In 1 Connect to rx[0-7]_usrclk of SMPTE SD/HD/3G-SDI core

rx[0-7]_mode_locked In 1 Connect to rx[0-7]_mode_locked of SMPTE SD/HD/3G-SDI core

rx[0-7]_locked In 1 Connect to rx[0-7]_t_locked of SMPTE SD/HD/3G-SDI core

rx[0-7]_t_family In 4 Connect to rx[0-7]_t_family of SMPTE SD/HD/3G-SDI core

rx[0-7]_t_rate In 4 Connect to rx[0-7]_t_tate of SMPTE SD/HD/3G-SDI core

Table 2‐5: AXI4 Memory Interface Signals (Cont’d)


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1. [0-7] is index that represent up to 8 channels support for SDI streams.

AXI4-Lite Control Interface

The AXI4-Lite interface allows you to dynamically control parameters within the core. Core configuration can be accomplished using an embedded ARM® or soft system processor such as MicroBlaze™.

The core can be controlled through the AXI4-Lite interface using read and write transactions to the SMPTE 2022-5/6 Video over IP Transmitter register space.

The AXI4-Lite slave interface facilitates integrating the core into a processor system, or along with other video or AXI4-Lite compliant IP, connected through the AXI4-Lite interface to an AXI4-Lite master.

rx[0-7]_bit_rate In 1 Connect to rx[0-7]_bit_rate of SMPTE SD/HD/3G-SDI core

rx[0-7]_mode In 2 Connect to rx[0-7]_mode of SMPTE SD/HD/3G-SDI core

rx[0-7]_eav In 1 Connect to rx[0-7]_eav of SMPTE SD/HD/3G-SDI core

rx[0-7]_ce_sd In 1 Connect to rx[0-7]_ce_sd of SMPTE SD/HD/3G-SDI core

rx[0-7]_dout_rdy_3g In 1 Connect to rx[0-7]_dout_rdy_3g of SMPTE SD/HD/3G-SDI core

rx[0-7]_crc_err_a In 1 Connect to rx[0-7]_crc_err_a of SMPTE SD/HD/3G-SDI core

rx[0-7]_a_vpid_valid In 1 Connect to rx[0-7]_a_vpid_valid of SMPTE SD/HD/3G-SDI core

rx[0-7]_a_vpid In 32 Connect to rx[0-7]_a_vpid of SMPTE SD/HD/3G-SDI core

rx[0-7]_line_a In 11 Connect to rx[0-7]_line_a of SMPTE SD/HD/3G-SDI core

rx[0-7]_ds1_a In 10 Connect to rx[0-7]_ds1a of SMPTE SD/HD/3G-SDI core

rx[0-7]_ds2_a In 10 Connect to rx[0-7]_ds2a of SMPTE SD/HD/3G-SDI core

rx[0-7]_ds1_b In 10 Connect to rx[0-7]_ds1b of SMPTE SD/HD/3G-SDI core

rx[0-7]_ds2_b In 10 Connect to rx[0-7]_ds2b of SMPTE SD/HD/3G-SDI core

rx[0-7]_level_b_3g In 1 Connect to rx[0-7]_level_b_3g of SMPTE SD/HD/3G-SDI core

Table 2‐8: AXI4-Lite Interface Signals


s_axi_clk In 1 Clock

s_axi_aresetn In 1 AXI4-Lite Active-Low reset

Table 2‐7: SMPTE SD/HD/3G-SDI Interface Signals (Cont’d)

Signal Name(1) Direction Width Description

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s_axi_awaddr In 9 AXI4-Lite Write Address Bus

s_axi_awvalid In 1 AXI4-Lite Write Address Channel Write Address Valid

s_axi_wdata In 32 AXI4-Lite Write Data Bus

s_axi_wstrb In 4 AXI4-Lite Write Data Channel Data Byte Strobes

s_axi_wvalid In 1 AXI4-Lite Write Data Channel Write Data Valid

s_axi_awready Out 1 AXI4-Lite Write Address Channel Write Address Ready. Indicates DMA ready to accept the write address.

s_axi_wready Out 1AXI4-Lite Write Data Channel Write Data Ready. Indicates DMA is ready to accept the write data.

s_axi_bresp Out 2 AXI4-Lite Write Response Channel. Indicates results of the write transfer.

s_axi_bvalid Out 1 AXI4-Lite Write Response Channel Response Valid. Indicates response is valid.

s_axi_bready In 1 AXI4-Lite Write Response Channel Ready. Indicates target is ready to receive response.

s_axi_arvalid In 1 AXI4-Lite Read Address Channel Read Address Valid

s_axi_arready Out 1 Ready. Indicates DMA is ready to accept the read address.

s_axi_araddr In 9 AXI4-Lite Read Address Bus

s_axi_rready In 1 AXI4-Lite Read Data Channel Read Data Ready. Indicates target is ready to accept the read data.

s_axi_rdata Out 32 AXI4-Lite Read Data Bus

s_axi_rresp Out 2 AXI4-Lite Read Response Channel Response. Indicates results of the read transfer.

s_axi_rvalid Out 1 AXI4-Lite Read Data Channel Read Data Valid

Table 2‐8: AXI4-Lite Interface Signals (Cont’d)


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Register SpaceThe core register space is partitioned to General and Channel specific registers. See the SMPTE 2022-5/6 High Bit Rate Media Transport Over IP Networks with Forward Error Correction (XAPP1199) [Ref 1] reference design for more information on register access.

Table 2‐9: AXI4-Lite Register Map

Address (Hex)

Register NameAccess Type

Default Value(HEX)

Description

Bit Range Value

General

0x0000 control R/W 0x00000000

Control

31:2 Reserved

1 Host processor write done semaphore. 0 – Host processor actively updating registers. 1 – Register update completed by host processor.

0 Reserved

0x0004 reset R/W 0x00000000

Software reset

31:1 Reserved

0 1 – Reset the core

0x000C channel_access R/W 0x00000000

Channel register access

31 0 - primary, 1 - secondary

30:8 Reserved

7:0 The channel number to access the its registers

0x0010 pri_mac_low_addr R/W 0x00000000Primary MAC low address register

31:0 Lower 32-bit of the mac address

0x0014 pri_mac_high_addr R/W 0x00000000

Primary MAC high address register

31:16 Reserved

15:0 Upper 16-bit of the mac address

0x0018 sec_mac_low_addr R/W 0x00000000Secondary MAC low address register

31:0 Lower 32-bit of the mac address

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0x001C sec_mac_high_addr R/W 0x00000000

Secondary MAC high address register

31:16 Reserved

15:0 Upper 16-bit of the mac address

0x0020 sys_conf RBased on

configured generics

System configuration

31 Hitless switching supported

30 FEC recovery supported

29:28 Reserved

27:8 Reserved

7:0 Number of channels supported

0x0024 version R 0x04000000

Hardware version

31:24 Version major

23:16 Version minor

15:12 Version revision

11:8 Patch ID

7:0 Revision number

0x0028 sys_mem_conf R/W 0x00000000

System Memory Configuration

31:3 Reserved

2:0 Most significant bit of allocated memory space

0x0030 hitless_config R/W 0x00000000

Hitless Config

31:1 Reserved

0 0 = enable, 1= disable

Channel

0x0080 ip_header R/W 0x00000000

IP header

31:17 Reserved

16 Reserved

15:8 type of service(TOS)

7:0 time to live(TTL)

0x0084 vlan_tag_info R/W 0x00000000

VLAN tag control

31 0 - without VLAN, 1 - with VLAN

30:16 Reserved

15:0 16-bit VLAN tag info

Table 2‐9: AXI4-Lite Register Map (Cont’d)

Address (Hex)


Default Value(HEX)

Description

Bit Range Value

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0x0088 dest_mac_low_addr R/W 0x00000000Destination MAC low address

31:0 Lower 32-bit destination MAC address

0x008C dest_mac_high_addr R/W 0x00000000

Destination MAC high address

31:16 Reserved

15:0 Upper 16-bit destination MAC address

0x0090 dest_ip_host_low_addr R/W 0x00000000Destination IP host low address

31:0 32-bit destination IPaddress

0x00A0 src_ip_host_low_addr R/W 0x00000000Source IP host low address

31:0 32-bit source IP address

0x00B0 udp_src_port R/W 0x00000000

UDP source port

31:16 Reserved

15:0 16-bit UDP source portaddress

0x00B4 udp_dest_port R/W 0x00000000

UDP destination port

31:16 Reserved

15:0 16-bit UDP dest portaddress

0x00C0 transmit_pkt_cnt R/W 0x00000000Transmitted Packet Count

31:0 number of transmitted packets

0x00CC channel_stat_reset R/W 0x00000000

Channel Statistics Reset

31:1 reserved

0 reset transmitted packet count

0x00D0 transmit_en R/W 0x00000001

Transmit Enable

31:1 Reserved

0 1= transmit enable, 0 = disable

0x00D8 ip_header_fec R/W 0x00000000

IP Header FEC

31:16 Reserved

15:8 type of service(TOS)

7:0 time to live(TTL)


Address (Hex)


Default Value(HEX)

Description

Bit Range Value

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1. You cannot write into a reserved field. All the read out values from the reserved fields are invalid.

Channel (Shared)

0x0100 chan_en R/W 0x00000000

Channel Enable

31:1 Reserved

0 1 - enable channel

0 - disable channel

0x0110 video_para_config R/W 0x00000000

HDR Stream Cfg

31:1 Reserved

0 1 - include video timestamp, 0 - video timesamp not include

0x0114 media_stream_status R 0x00000000

Media Stream Status

31:19 Reserved

18:17 00 - HD01 -SD10-3G11- unknown

16 video lock

15:0 Reserved

0x0118 ssrc R/W 0x00000000SSRC

31:0 32-bit SSRC value

0x011C fec_config R/W 0x00000000

FEC configuration

31:3 Reserved

2 1- Column FEC enable

1 1- Row FEC enable

0 0-block aligned;1-non-block aligned

0x0124 fec_L_value R/W 0x00000000

FEC L value

31:10 Reserved

9:0 10-bit FEC L value

0x0128 fec_D_value R/W 0x00000000

FEC D value

31:10 Reserved

9:0 10-bit FEC D value


Address (Hex)


Default Value(HEX)

Description

Bit Range Value

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CONTROL (0x000) Register

Bit 1 of the CONTROL register is a write-done semaphore for the host processor, which facilitates committing all user register updates in the channel space simultaneously. One set of registers (the processor registers) is directly accessed by the processor interface, while the other set (the active set) is actively used by the core. New values written to the processor registers are copied over to the active set if and only if the register update bit is set. Setting the bit to 0 before updating multiple registers and then setting the bit to 1 when updates are completed ensures all channel space registers are updated simultaneously.

RESET (0x004) Register

Bit 0 is software reset. When asserted High, the configuration registers are held at reset state. At the same time, the soft_reset signal at the core interface is held High. All the register values will be reset to their default values. However, the core will need to be reset by external logic driving all corresponding reset signals through top level ports. This is to leave the flexibility to user in configuring proper reset sequence across multiple subsystems / GTs.

CHANNEL_ACCESS (0x00C) Register

Set the channel to access. All the primary link and secondary link channels share the same set of register addresses in the channel space. To access secondary link channels, set bit 31 to 1. Only 0x084 - 0x0C0 registers are available for secondary link. Bit 7-0 represent the channel number in standard binary count.

PRI_MAC_LOW_ADDR (0x010) Register

This register configures the third, fourth, fifth and sixth bytes of the source Ethernet MAC Address that is inserted into the Ethernet header of the packet of primary link.

PRI_MAC_HIGH_ADDR (0x014) Register

This register configures the first byte and second byte of the source Ethernet MAC Address that is inserted into the Ethernet header of the packet of primary link

SEC_MAC_LOW_ADDR (0x018) Register

This register configures the third, fourth, fifth and sixth bytes of the source Ethernet MAC Address that is inserted into the Ethernet header of the packet of secondary link.

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SEC_MAC_HIGH_ADDR (0x01C) Register

This register configures the first byte and second byte of the source Ethernet MAC Address that is inserted into the Ethernet header of the packet of secondary link

SYS_CONF (0x020) Register

System configuration of the core.

• Bit 31 High indicates seamless switching support.

• Bit 30 High indicates FEC engine is included.

• Bit 7-0 gives the number of channels available to use.

VERSION (0x024) Register

Bit fields of the register facilitate software identification of the exact version of the hardware peripheral incorporated into a system. The core driver can take advantage of this read-only value to verify that the software is matched to the correct version of the hardware.

SYS_MEM_CONF (0x028) Register

This register configures the most significant three bits of the 32-bit AXI memory map address to access the DDR through the AXI interconnect. This also determines the base address of the DDR area to be used by the core.

HITLESS_CONFIG (0x030) Register

This register configures the system to enable/disable hitless protection operation.

IP_HEADER (0x080) Register

This register configures the value of IP header fields such as TOS and TTL for media packets.

VLAN_TAG_INFO (0x084) Register

The VLAN register configures whether the Ethernet packet contains a VLAN tag and the tag control information to insert into each packet. The Tag Protocol Identifier is set to 0x8100.

DEST_MAC_LOW_ADDR (0x088) Register

This register configures the third, fourth, fifth and sixth bytes of the destination Ethernet MAC Address that is inserted into the Ethernet header of the packet.

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DEST_MAC_HIGH_ADDR (0x08C) Register

This register configures the first byte and second byte of the destination Ethernet MAC Address that is inserted into the Ethernet header of the packet.

DEST_IP_HOST_LOW_ADDR (0x090) Register

This register configures the destination IP address that is inserted into the IP header of each packet.

SRC_IP_HOST_LOW_ADDR (0x0A0) Register

This register configures the source IP address that is inserted into the IP header of each packet.

UDP_SRC_PORT (0x0B0) Register

This register configures the UDP source port value that is inserted into the UDP header of each packet.

UDP_DEST_PORT (0x0B4) Register

This register configures the UDP destination port value that is inserted into the UDP header of each packet.

TRANSMIT_PKT_CNT (0x0C0) Register

Statistic register shows how many packets have been sent out.

CHANNEL_STAT_RESET (0x0CC) Register

Resets the value of statistic registers.

TRANSMIT_EN (0x0D0) Register

This register can be used to enable/disable the packet transmission over either primary / secondary link.

IP_HEADER_FEC (0x0D8) Register

This register configures the value of IP header fields such as TOS and TTL for FEC packets

CHAN_EN (0x100) Register

This register enables the channel to work by setting to '1'.

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VIDEO_PARA_CONFIG (0x110) Register

To include video timestamp in SMPTE 2022-6 header, set bit 1 of this register to '1'.

MEDIA_STREAM_STATUS (0x114) Register

Bit 16 is High when the input video from SMPTE SD/HD/3G-SDI is locked to a video format.

Bit 17 and bit 18 indicate the current SDI mode of the channel.

• 0 0= HD-SDI

• 0 1= SD-SDI

• 1 0= 3G-SDI

SSRC (0x118) Register

This register configures the SSRC value that is inserted into the RTP header of each packet.

FEC_CONFIG (0x11C) Register

This register configures the FEC operation mode.

Bit 1 and Bit 2 of this register are for configuring the forward error correction level. For level B FEC sets both bits and for level A FEC sets Bit 2.

Bit 0 is used to configure different scheme of packet interleaving. 0 means block align, 1 means non-block align.

FEC_L_VALUE (0x124) Register

The FEC_L register configures the L value of the FEC matrix.

• Level A FEC 1 <= L<= 1020 and

• Level B FEC 4 <= L <= 1020

FEC_D_VALUE (0x128) Register

The FEC_D register configures the D value of the FEC matrix.

Both level A and level B FEC 4 <= D <= 255.

L x D shall be <= 1500 in SD, <= 3000 for HD (1.485 Gb/s) <= 6000 for 3G HD.

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Chapter 3

Designing with the CoreThis chapter includes guidelines and additional information to facilitate designing with the core.

The core is for broadcast applications that require bridging between SMPTE video connectivity standards SD/HD/3G-SDI and 10 Gb/s Ethernet. The core takes uncompressed SD/HD/3G-SDI streams as input from the SMPTE SD/HD/3G-SDI core, encapsulates the data using prescribed methods into an IP packet with UDP and RTP header together with Forward Error Correction in accordance with SMPTE 2022-5/6, and sends over the AXI4-Stream interface to the 10G Ethernet MAC. The core uses the AXI4 interface to transfer data between the core and buffer in external DDR memory. The register interface is compliant with the AXI4-Lite interface. See the SMPTE 2022-5/6 High Bit Rate Media Transport Over IP Networks with Forward Error Correction (XAPP1199) [Ref 1] reference design for more information.

Note: There is an option to include the Forward Error Correction engine in the SMPTE 2022-5/6 Video over IP Transmitter core. Adding this enables the receiver to recover IP packets lost to the network transmission errors and hence ensure the quality of the uncompressed video. However, it will increase the resource count in the FPGA as well as the usage of external memory. Enabling Seamless Switching adds a redundancy protection link for packets lost to network transmission errors, which also increase device resource count. Resetting an individual channel can be achieved by


Figure 3‐1: SMPTE 2022-5/6 Video over IP Transmitter System Built with other Xilinx IP Cores

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setting Bit 0 Low in the chan_en register (register offset 0x100). To reset the core, all active channels must be reset, followed by setting Bit 0 Low in the reset register (register 0x004).

ClockingSMPTE 2022-5/6/7 transmitter core has five clock domains:

• 27 MHz clock domain

• SDI video clock domain at 74.25 Mhz/148.5 Mhz (and /1.001 rate)

• System clock domain recommended running at 200MHz

• Ethernet clock domain at 156.25 MHz

• AXI4-Lite clock domain recommended running at 100 MHz

ResetsThe SMPTE 2022-5/6 Video over IP Transceiver core has four main resets:

• Ethernet link reset, eth_rst

• System domain reset, sys_rst

• SDI domain reset, rx<port_num>_rst

• AXI4-Lite domain reset, s_axi_aresetn

Reset Requirements

• All the resets must be synchronous to their individual clock domains.

• A minimum of 16 clocks assertion is recommended.

• The ordering of reset deassertion is not important except the SDI domain resets to be the last.

Refer to the SMPTE 2022-5/6 High Bit Rate Media Transport Over IP Networks with Forward Error Correction (XAPP1199) [Ref 1].

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Memory Requirement

AXI Memory Map Bandwidth Requirements

The memory bandwidth is calculated based on maximum transmission of 10 Gbps per link from the SMPTE 2022-5/6 TX including RTP and FEC packet regardless of Channel Number and SDI Format.

The values in Table 3-1 are based on the worst case per port scenario.

For SMPTE 2022-6 packets, the memory required to store one FEC packet is 2048 bytes. The number of FEC packets to buffer for each channel is [FEC_L x 2]. Therefore, the maximum memory utilization for each channel is 4,177,920 bytes.

Table 3‐1: Transmitter AXI-MM Port Bandwidth Consumption

Port Maximum Bandwidth (Gbps)

M0_AXIMM WR 10.5

M0_AXIMM RD 10.5

M1_AXIMM RD 2.00

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Chapter 4

Design Flow StepsThis chapter describes customizing and generating the core, constraining the core, and the simulation, synthesis and implementation steps that are specific to this IP core. More detailed information about the standard Vivado® design flows in the IP Integrator can be found in the following Vivado Design Suite user guides:

• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)[Ref 11]

• Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 6]

• Vivado Design Suite User Guide: Getting Started (UG910) [Ref 7]

• Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 10]

Customizing and Generating the CoreThis chapter includes information about using Xilinx tools to customize and generate the core in the Vivado® Design Suite.

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:

1. Select the IP from the IP catalog.

2. Double-click on the selected IP or select the Customize IP command from the toolbar orpopup menu.

For details, see the sections, “Working with IP” and “Customizing IP for the Design” in the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 6] and the “Working with the Vivado IDE” section in the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 7]

Note: Figures in this chapter are illustrations of the Vivado Integrated Design Environment (IDE). This layout might vary from the current version.

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Vivado Integrated Design Environment

The core is configured to meet the specific needs of the developer before instantiation through the Vivado IDE. This section provides a quick reference to parameters that can be configured at generation time.

The Vivado IDE shows a representation of the IP symbol on the left side, and the parameter assignments on the right side, which are described as follows:

• Component Name: The component name is used as the base name of output files generated for the module. Names must begin with a letter and must be composed from characters: a to z, 0 to 9 and "_". The name v_smpte2022_56_tx cannot be used as a component name.

• Number of SDI Channels: Specifies the number of SDI channels.


Figure 4‐1: Vivado IDE

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• Include Forward Error Correction Engine: When checked, the core is generated with the Forward Error Correction Engine.

• Enable Seamless Switching: When checked, the core is generated with the Secondary AXIS Ethernet Link to support hitless operation.

User Parameters

Table 4-1 shows the relationship between the fields in the Vivado IDE and the User Parameters (which can be viewed in the Tcl console).

Output Generation

The Vivado design tools generate the files necessary to build the core and places those files in the <project>/<project>.srcs/sources_1/ip/<core> directory.

For details, see “Generating IP Output Products” in the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 6].

Constraining the CoreThis section contains information about constraining the core in the Vivado Design Suite.

Required Constraints

Constraints required for the core are clock frequency constraints for the clock domains described in Clocking in Chapter 3. Paths between the clock domains are constrained with a max_delay constraint and use the datapathonly flag, causing setup and hold checks to be ignored for signals that cross clock domains. These constraints are provided in the XDC constraints file included with the core.

Device, Package, and Speed Grade Selections

There are no device, package or speed grade requirements for this core. This core has not been characterized for use in low-power devices.

Table 4‐1: GUI Parameter to User Parameter Relationship

GUI Parameter/Value(1) User Parameter/Value(1) Default Value

Number of SDI channels C_CHANNELS 1

include Forward Error Correction Engine

C_INCLUDE_FEC FALSE

Enable Seamless Switching C_INCLUDE_HITLESS FALSE1. Parameter values are listed in the table where the GUI parameter value differs from the user parameter value. Such

values are shown in this table as indented below the associated parameter.

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Clock Frequencies

See Maximum Frequencies in Chapter 2.

Clock Management

See Clocking in Chapter 3.

Clock Placement

There are no specific clock placement requirements for this core.

Banking

There are no specific banking rules for this core.

Transceiver Placement

There are no transceiver placement requirements for this core.

I/O Standard and Placement

There are no specific I/O standards and placement requirements for this core.

SimulationFor comprehensive information about Vivado simulation components, as well as information about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 10].

Synthesis and ImplementationFor details about synthesis and implementation, see “Synthesizing IP” and “Implementing IP” in the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 6].

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Chapter 5

Test BenchThis chapter contains information about the provided test bench in the Vivado® Design Suite.

Demonstration Test BenchWhen the core is generated using the Vivado IP catalog, a demonstration test bench is optionally created. This is a simple SV test bench that exercises the core. The demonstration test bench source code created from mixed verilog/vhdl and system verilog files under the demo_tb/ directory in the Vivado Design Suite output directory. The test bench top file namely as tb_<component_name>.sv

Using the Demonstration Test Bench

The demonstration test bench instantiates the generated SMPTE2022-56-TX core. Either the behavioral model or the netlist can be simulated within the demonstration test bench. Run the demonstration test bench using the following steps:

1. Generate the core using IP catalog and set it as the top level.

2. Go to Simulation Setting and append prefix “tb_” at the component name stated in theSimulation top module name field. Then click OK.

3. Click Run Simulation to start the behavioral simulation.

The test bench generates data for the 3G-A mode by default and simulation will stop once the data stream checker detected output from SMPTE2022-56-TX receiver side. Any mismatch data occurrence will get displayed by the SDI stream data checker module on the Vivado® IDE console.

Demonstration Test Bench Architecture

Figure 5-1 shows the test bench architecture.

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The test bench for the SMPTE cores (TX and RX) consists of the major test bench components listed in Table 5-1:


Figure 5‐1: Test Bench Architecture

Table 5‐1: Test Bench Components and Descriptions

Testbench Components Description

SDI Video Generator Provides the video inputs to the SMPTE TX core based on the SDI format selection (3G/HD/SD) configured through the SDI Video Generator Configuration Module setup.

Dummy DDR Acts as dummy external storage that is used by the cores and network emulator during the pkt transaction.

XGMAC Bridge Acts as a dummy 10G Ethernet MAC Bridge.

SDI Stream Data Checker Compares the raw data output received by the SMPTE RX core with the originally output data from the SDI Video Generator. Asserts an error if there is any data mismatched.Also detects SOF on the input and output streams to signal successful data transmission and reception by the TX and RX core respectively.

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Configuration Modules Used to configure the TX, RX, SDI generator and network emulator. Consists of the following sub-components: API layer, Driver Layer, HAL layer, AXI4-Lite Master and Slave Decode Logic.

SMPTE RX Simulation model which is an encrypted version of the VOIP Receiver core in a loopback mode in the test bench. You cannot view the encrypted model.

Table 5‐1: Test Bench Components and Descriptions (Cont’d)

Testbench Components Description

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Appendix A

Verification, Compliance, and Interoperability

The SMPTE 2022-5/6 Video over IP Transmitter core has been validated using the Xilinx Kintex®-7 FPGA Connectivity Kit.

See the SMPTE 2022-5/6 High Bit Rate Media Transport Over IP Networks with Forward Error Correction (XAPP1199) [Ref 1] for more information.

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Appendix B

Migrating and UpgradingThis appendix contains information about migrating a design from ISE® to the Vivado® Design Suite, and for upgrading to a more recent version of the IP core. For customers upgrading in the Vivado Design Suite, important details (where applicable) about any port changes and other impact to user logic are included.

Migrating to the Vivado Design SuiteFor information about migrating to the Vivado Design Suite, see the ISE to Vivado Design Suite Migration Guide (UG911) [Ref 8].

Upgrading in the Vivado Design SuiteThis section provides information about any changes to the user logic or port designations that take place when you upgrade to a more current version of this IP core in the Vivado Design Suite.

Parameter Changes

Table B-1 shows the details of changes involved.

Table B‐1: Parameter Changes

VersionNote

v2.0/1 and v3.0 v4.0

Component Name Component Name

unchanged

Number of SDI channels

Number of SDI channels

unchanged

Include FEC Engine Include FEC Engine

unchanged

Enable Seamless Switching

New to version v4.0. Refer to Customizing and Generating the Core for a description.

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Port Changes

Table B-2 shows the details of changes involved.

Functionality Changes

Added Seamless Switching support, which can be enabled thru XGUI option. Refer to Customizing and Generating the Core in Chapter 4 for more information.

Instructions for Minimum Change Migration

SMPTE 2022-5/6 TX Migration from v3.0 to v4.0

Port Changes

In SMPTE 2022-5/6 TX v4.0, a new feature was added which supports SMPTE 2022-7, where the transmitter core transmits two identical AXI-Streams (Primary and Secondary) with different header as configured by the user. The port changes related to the new feature are shown in table Table B-3.

Note: *prefix pri_ is for Primary and sec_ for Secondary

The secondary AXI4-Stream is visible when the Seamless Switching feature is enabled in the core setting. By disabling the Seamless Switching, only the primary AXI4-Stream is visible and is similar to SMPTE 2022-5/6 TX v3.0 core which uses a single Ethernet Link.

Table B‐2: Port Changes

VersionNote

v2.0/1 and v3.0 v4.0

m_axis_aresetn pri_m_axis_aresetn Renamed

m_axis_tdata pri_m_axis_tdata Renamed

m_axis_tkeep pri_m_axis_tkeep Renamed

m_axis_tvalid pri_m_axis_tvalid Renamed

m_axis_tuser pri_m_axis_tuser Renamed

m_axis_tlast pri_m_axis_tlast Renamed

sec_m_axis_tdata newly added for seamless switching purpose

sec_m_axis_tkeep newly added for seamless switching purpose

sec_m_axis_tvalid newly added for seamless switching purpose

sec_m_axis_tuser newly added for seamless switching purpose

sec_m_axis_tlast newly added for seamless switching purpose

s_axi_awaddr s_axi_awaddr port width changed from 8 to 32

s_axi_araddr s_axi_araddr port width changed from 8 to 32

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For minimum change migration, disable the Seamless Switching feature and remap the renamed ports accordingly by referring to Table B-2.

Register Setting

New registers to take note of which were added to support new functionality and features as shown in Table B-4.

Table B‐3: Port Changes as supporting SMPTE2022-7 Feature

SMPTE 2022-5/6 TX v3.0 Ports SMPTE 2022-5/6 TX v4.0 Ports

m_axis_aresetn pri_m_axis_aresetn

sec_m_axis_aresetn

m_axis_tdata[63:0] pri_m_axis_tdata[63:0]

sec_m_axis_tdata[63:0]

m_axis_tkeep[7:0] pri_m_axis_tkeep[7:0]

sec_m_axis_tkeep[7:0]

m_axis_tvalid pri_m_axis_tvalid

sec_m_axis_tvalid

m_axis_tlast pri_m_axis_tlast

sec_m_axis_tlast

m_axis_tready pri_m_axis_tready

sec_m_axis_tready

Table B‐4: Added Register in Register Map

Address (Hex) General/Channel Register Name Register Description

Bit Name

0x0030 General [0] hitless_config Set 1 to disable the secondary link. Only applicable when the seamless switching is enabled during core generation.

0x00C0 Channel * [31:0] transmit_pkt_cnt Statistic counter to count transmitted packet of RTP & FEC from the core

0x00CC Channel * [0] channel_stat_reset Reset of transmit_pkt_cnt register (offset 0x0C0)

0x00D0 Channel* [0] transmit_en Set to 1, to enable packet transmission from the core, default value is 0

0x00D8 Channel* [15: 8] ip_header_fec (TOS) Set the TOS & TTL for FEC packets

[7:0] ip_header_fec (TTL)

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Note: Primary and Secondary registers are configured separately.

For minimum change migration, disable the Seamless Switching and set the primary register accordingly. Refer to Core Debug in Appendix C for crucial register information.

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Appendix C

DebuggingThis appendix includes details about resources available on the Xilinx Support website and debugging tools.

TIP: If the IP generation halts with an error, there might be a license issue. See License Checkers in Chapter 1 for more details.

Finding Help on Xilinx.comTo help in the design and debug process when using the core, the Xilinx Support web page (www.xilinx.com/support) contains key resources such as product documentation, release notes, answer records, information about known issues, and links for obtaining further product support.

Documentation

This product guide is the main document associated with the core. This guide, along with documentation related to all products that aid in the design process, can be found on the Xilinx Support web page (www.xilinx.com/support) or by using the Xilinx Documentation Navigator.

Download the Xilinx Documentation Navigator from the Design Tools tab on the Downloads page (www.xilinx.com/download). For more information about this tool and the features available, open the online help after installation.

Answer Records

Answer Records include information about commonly encountered problems, helpful information on how to resolve these problems, and any known issues with a Xilinx product. Answer Records are created and maintained daily ensuring that users have access to the most accurate information available.

Answer Records can be located by using the Search Support box on the main Xilinx support web page. To maximize your search results, use proper keywords such as

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• Product name

• Tool message(s)

• Summary of the issue encountered

A filter search is available after results are returned to further target the results.

Master Answer Record for the SMPTE 20222-5/6 TX Core

AR 54535

Contacting Technical Support

Xilinx provides technical support at www.xilinx.com/support for this LogiCORE™ IP product when used as described in the product documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that are not defined in the documentation, if customized beyond that allowed in the product documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.

To contact Xilinx Technical Support:

1. Navigate to www.xilinx.com/support.

2. Open a WebCase by selecting the WebCase link located under Additional Resources.

When opening a WebCase, include:

• Target FPGA including package and speed grade.

• All applicable Xilinx Design Tools and simulator software versions.

• Additional files based on the specific issue might also be required. See the relevant sections in this debug guide for guidelines about which files to include with the WebCase.

Note: Access to WebCase is not available in all cases. Please login to the WebCase tool to see your specific support options.

Vivado Lab EditionVivado® Lab Edition inserts logic analyzer and virtual I/O cores directly into your design. Vivado Lab Edition also allows you to set trigger conditions to capture application and integrated block port signals in hardware. Captured signals can then be analyzed. This feature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx.

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The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores, including:

• ILA 2.0 (and later versions)

• VIO 2.0 (and later versions)

See Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 9].

Interface Debug

AXI4-Lite Interfaces

Read from a register that does not have all 0s as a default to verify that the interface is functional. Output s_axi_arready asserts when the read address is valid, and output s_axi_rvalid asserts when the read data/response is valid. If the interface is unresponsive, ensure that the following conditions are met:

• The s_axi_aclk and aclk inputs are connected and toggling.

• The interface is not being held in reset, and s_axi_areset is an active-Low reset.

• The interface is enabled, and s_axi_aclken is active-High (if used).

• The main core clocks are toggling and that the enables are also asserted.

• If the simulation has been run, verify in simulation and/or a Vivado lab tools capturethat the waveform is correct for accessing the AXI4-Lite interface.

AXI4-Stream Interfaces

If data is not being transmitted or received, check the following conditions:

• If transmit <interface_name>_tready is stuck Low following the<interface_name>_tvalid input being asserted, the core cannot send data.

• If the receive <interface_name>_tvalid is stuck Low, the core is not receivingdata.

• Check that the ACLK inputs are connected and toggling.

• Check that the AXI4-Stream waveforms are being followed.

• Check core configuration.

• Add appropriate core specific checks.

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Core Debug1. Ensure SD/HD/3G-SDI Interface of SMPTE 2022-5/6 TX is connected to a video source,

this can be done by steps below

a. Reading media_stream_status (0x114) register, if the Video Lock (bit 16) is High, it indicates that the core has lock to a SDI video.

b. Ensure that the SDI video format (bit 18:17) reflecting the same as SDI source.

2. Ensure that the channel is enabled, by reading bit '0' of chan_en (0x100) register. High means the channel is enabled.

3. Ensure the bit '0' transmit_en (0x0D0) register is High which indicates the transmission is enabled. The transmission can be enabled by writing '1' to bit 0 of transmit_en (0x0D0) register.

If transmit_pkt_cnt (0x0C0) register is incrementing, it indicates the core is transmitting packet out.

media_stream_status (0x114) bit[18:17] Code

00 HD

01 SD

10 3G

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Appendix D

Additional Resources and Legal Notices

Xilinx ResourcesFor support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support.

ReferencesThese documents provide supplemental material useful with this product guide.

1. SMPTE 2022-5/6 High Bit Rate Media Transport Over IP Networks with Forward Error Correction (XAPP1199)

2. AXI Reference Guide (UG1037)

3. LogiCORE IP AXI Interconnect Product Guide (PG059)

4. LogiCORE IP 10-Gigabit Ethernet MAC Product Guide (PG072)

5. Society of Motion Picture and Television Engineers (SMPTE) SD/HD/3G-SDI 2.0 Product Guide (PG071)

6. Vivado Design Suite User Guide: Designing with IP (UG896)

7. Vivado Design Suite User Guide: Getting Started (UG910)

8. ISE to Vivado Design Suite Migration Guide (UG911)

9. Vivado Design Suite User Guide: Programming and Debugging (UG908)

10. Vivado Design Suite User Guide: Logic Simulation (UG900)

11. Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

12. Implementing SMPTE SDI Interfaces with Kintex-7 GTX Transceivers (XAPP592)

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http://www.xilinx.com/support/documentation/ip_documentation/ug1037-vivado-axi-reference.pdf




http://www.xilinx.com/support/documentation/application_notes/xapp592-smpte-sdi-w-k7-gtx-transceivers.pdf

http://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug900-vivado-logic-simulation.pdf

http://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug994-vivado-ip-subsystems.pdf

http://www.xilinx.com/cgi-bin/docs/rdoc?t=vivado+docs

http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_ref_guide;v=latest;d=ug1037-vivado-axi-reference.pdf

http://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug911-vivado-migration.pdf

http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=latest;d=pg059-axi-interconnect.pdf

http://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug896-vivado-ip.pdf

http://www.xilinx.com/cgi-bin/docs/ipdoc?c=v_smpte_sdi;v=latest;d=pg071-v-smpte-sdi.pdf


http://www.xilinx.com/support/documentation/application_notes/xapp1199-smpte2022-56-over-ip.pdf

http://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug908-vivado-programming-debugging.pdf

http://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug910-vivado-getting-started.pdf

http://www.xilinx.com/cgi-bin/docs/ipdoc?c=ten_gig_eth_mac;v=latest;d=pg072-ten-gig-eth-mac.pdf




Revision HistoryThe following table shows the revision history for this document.

Please Read: Important Legal NoticesThe information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support

Date Version Revision

10/05/2016 4.0 • Updated Port Descriptions and Registers.

04/01/2015 4.0 • Updated for Kintex-UltraScale support.

10/01/2014 4.0 • Revision number advanced to 4.0 with design architecture improvement.• Updated the demonstration test bench.• Updated GUI screens.• Updated tables in Chapter 2, Product Specification.• Updated memory requirements for the core.• Updated migrating and upgrading section.

10/02/2013 3.0 • Added XDC and module level constraints to core.• Added demonstration test bench.

03/20/2013 3.0 • Revision number advanced to 3.0 to align with core version number.• Updated to core version 3.0 and Vivado Design Suite.• Removed all material related to Virtex-6 devices, ISE Design Suite, CORE

Generator tools, and UCF.• Updated Vivado IDE screen capture.

12/18/2012 2.1 • Updated to core version 2.1.• Updated to ISE® design tools 14.4 and Vivado Design Suite 2012.4• Updated design to support the latest SMPTE 2022-5/6 draft change.• Added resource numbers for devices using Vivado Design Suite• Updated screen captures in Chapter 4 and Chapter 6.• Updated Debug appendix.

10/16/2012 2.0.1 Updated memory requirement for core.

07/25/2012 2.0 Updated to core version 2.0 and added Vivado Design Suite material Added support for Virtex®-7 devices

04/24/2012 1.0 Initial Xilinx release.

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terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos.© Copyright 2012–2015 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. ARM is a registered trademark of ARM in the EU and other countries. All other trademarks are the property of their respective owners.

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