soc
TRANSCRIPT
1
Agenda
• Introduction• Motivation• Problem statement• Objectives• Block diagram of the Design Implementation• OCP and AXI Protocols• FSM Implementation• Block diagram of the Verification Environment• Conclusion• Future scope• References
2
Introduction
• System on Chip (SoC)• Advancements in the semiconductor technology enables more complex
System-on-Chip (SoC) designs to be implemented in a single IC.• An SoC inturn will have hundreds of intellectual properties (IPs) integrated
into a SoC.• IP’s from different venders have different protocol for communication
• Protocols of the Design • OCP
(Open core protocol).
• AXI
(Advanced extensible Interface).
3
Motivation
• Reuse IP blocks enable the utilization of existing designs for new designs to shorten the time to market
• In IP-based designs, one of the most important issues is integrating different IPs. IPs usually have their own interfaces and they cannot communicate with one another if they use different protocols. Bus bridges are used for conversion and communication among these protocols. Therefore bus bridges are most essential components of any SoC design.
4
Problem Statement
• Designing of OCP to AXI bus bridge with OCP of 8 bit(master) to AXI of 16 bit(slave) transfer using FSM’s in VHDL and verify the Bus Bridge using VHDL test bench and System Verilog Assertions (SVA)
5
Objectives
• Designing of OCP and AXI Bus Functional Models (BFM) in VHDL• Designing of Bus Bridge module in VHDL• Designing of Test wrappers, which contains all the modules like
master, slave, memory.• Creating automated verification environment using scripts.• Writing different test cases.• Integrating OCP and AXI System Verilog Assertion (SVA )
checkers.• Generating coverage report on the DUT• Code is made synthesizable by running on Spyglass lint checks.
6
Block diagram of Design Implementation
OCP
MASTER(BFM)
AXI
SLAVE(BFM)
OCP-AXI
BRIDG
E(DUT)
MEMORY
7
OCP-AXI Bus-Bridge(DUT)
8
Open Core Protocol (OCP)
Features:• Only the master can present commands and is the controlling
entity.
• The slave responds to commands presented to it, either by accepting data from the master, or presenting data to the master.
• OCP has shared bus, it is able to do only read or write operation at a given time.
• To do read or write operation it generates the command followed by it send the address and data information.
9
OCP Simple read and write transfer
10
OCP write non post
11
OCP Bus Function Model
OCP-AXI Bus Bridge
Master Request and DataO
CP
MASTER
MasterBurst info
Slave Responseand Data
MCmd [2:0]
MAddr[31:0]
MData [15 :0]
MBurstLen[3:0]MBurstSeq[2:0]
MReqLast
MRespAccept
SCmdAccept
SData [15 :0]
SRESP[1:0]
OCP port
12
Advanced eXtensible Interface (AXI)Features:• Separate address/control and data phases.• Separate read and write channels, request/response channels.• Two separate bus for read and write.
MASTER SLAVE
Read address
Read data &
response
Write address
Write data
Write response
On each channel:•Information flows from source to destination
•Source uses VALID to indicate information is available
•Destination uses READY to indicate is ready to accept information.
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AMBA AXI Read Channels
Give me some data
Here you go
Independent
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AMBA AXI Write Channels
I’m sending address
Here is the data.
I received that data correctly.
Independent
Independent
15
AMBA AXI Read
Read Address Channel
Read Data Channel
16
AMBA AXI Write
Write Address Channel
Write Response Channel
Write Data Channel
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AXI Bus Function Model
OCP-AXI Bus Bridge
AWADDRAWVALID
AWLEN, AWSIZE, AWBURSTAWREADYWDATA,WLASTWVALIDWREADY
BVALIDBRESPBREADYARADDRARVALID
ARLEN, ARSIZE, ARBURSTARREADY
RDATA, RLAST, RRESPRVALIDRREADY
Write address channel
AXI
SLAVE
Write Datachannel
Write Responsechannel
Read addresschannel
Read datachannel
AXI port
Design of Bus-Bridge
Write address channel
Write Datachannel
Write Responsechannel
Read addresschannel
Read datachannel
Master Request and Data
MasterBurst info
Slave Responseand Data
O
C
P
TO
A
X
I
BUS
BRIDGE
MAddr[31:0]
MData [15 :0]
MBurstLen[3:0]MBurstSeq[2:0]MReqLastMRespAccept
SCmdAccept
SData [15 :0]
SRESP[1:0]
MCmd [2:0]AWADDRAWVALID
AWLEN, AWSIZE, AWBURSTAWREADY
WDATA,WLAST
WVALIDWREADY
BVALID
BRESP
BREADY
ARADDRARVALID
ARLEN, ARSIZE, ARBURSTARREADY
RDATA, RLAST, RRESPRVALIDRREADY
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Equivalent signals in OCP and AXI
OCP Master Bus-bridge AXI Slave
MAddr MAddr AWADDR AWADDR
MAddr MAddr ARADDR ARADDR
MBurstLength MBurstLength AWLEN AWLEN
MBurstLength MBurstLength ARLEN ARLEN
MData MData WDATA WDATA
MDataValid MDataValid WVALID WVALID
MDataLast MDataLast WLAST WLAST
SData SData RDATA RDATA
SRespLast SRespLast RLAST RLAST
SRESP SRESP RRESP RRESP
SRespLast SRespLast BRESP BRESP
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Finite State Machines Implementation
A finite-state machine (FSM) or finite-state automaton , or simply a state machine, is a mathematical abstraction sometimes used to design digital logic or computer programs.
The different FSMs designed for the project are listed below and discussed in detail in the subsequent slides:(a) Finite state machine of OCP Master(b) Finite state machine of OCP Slave(c) Finite state machine of OCP to AXI Master(d) Finite state machine of AXI Master (i) Write process (ii) Read process(e) Finite state machine of AXI Slave (i) Write process (ii) Read process
IDLEMCmd=000
READMCmd=010
req=0001
SCmdAccept & Sresp!
=null
WAIT_RESP
READ_BURS
TMCmd=010
Req=0100
SCmdAccept &
Sresp!
=null
SCmdAccept &
Sresp==null &
count=1
Sresp!=null
WRITEMCmd=010
req=0010
SCmdAccept
WRITE_BURSTMCmd=010
req=0010
~SCmdAccept
~SCmdAccept
& count > 1
~SCmdAccept
Sre
sp!=
null
~SCmdAccept & count > 1
WRITE_NONPOST
MCmd=010
req=
0011
~SCmdAccept
SCmdAccept &
count= 1
SCmdAccept &
Sresp!
=null
(a) Finite state machine of OCP Master
IDLE~SCmdAcceptSresp=NULL
READSCmdAccept
MCmd=read &Mburstlength=0
WAIT_RESPSresp=01
SRespLast=0
READ_BURSTSCmdAcceptSRespLast=1/
count=1
count=1WRITESCmdAccept
Sresp=00
WRITE_BURSTSCmdAccept
Sresp=00
~MDataLast
WRITE_NON POST
SCmdAcceptSresp=01
MData
Last=
1
MCm
d=read
&M
burstlength>0
count>1MCmd=write
&Mburstlength=0
MCmd=writ
e &M
burstlength
>0
MCm
d=w
rite
non
post
&
Mbu
rstle
ngth
=0
(b) Finite state machine of OCP Slave
IDLE~SCmdAcceptSresp=NULL
READSCmdAccept
ARADDR<=MaddrARVALID,BREADy,ARLEN<=Mburstl,WLAST,RREADY
WAIT_RESP
RREADY=0SRESP<BRE
SP
READ_BURST
SCmdAcceptARADDR<=MaddrARVALID,BREADy,ARLEN<=Mburstl,WLAST,RREADY
WRITESCmdAccept
AWADDR<=MaddrAWVALID ,AWLEN
<=MburstWVALID,BREADY
WLAST
WRITE_BURST
SCmdAcceptAWADDR<=MadddrAWLEN<Mburst-1WVALID,BREADYAWSIZE,ARSIZE
WLAST=1
~MDataLast
WRITE_NON POSTSCmdAccept
AWADDR<MaddrAWVALID,WLASTAWLEN<=MburstWVALID,BREADY
Sresp=DVA
MData
Last=
1
MCm
d=read
&M
burstlength>0
RVALID=0 or
MReqLast=0
MCmd=write & Mburstlength=0 &
AWREADY=1
MCm
d=writ
e &M
burstlen
gth>0
& AWREA
DY=1
MCm
d=w
rite
non
post
&
Mbu
rstle
ngth
=0
MCmd=read &Mburstlength=0
RVALID
=1
RVALID=1 &
MReqLast=1
(c) Finite state machine of OCP to AXI Master
IDLEAWLENAWSIZE
AWBURST AWREADY=1 &
Burstlength=0 & w_enb=1
WRITEWDATA
,WVALID=1, BREADY
WRITE_BURST
WDATA,WVALID=1WREADY
AWREADY=0 & w_enb=0
AWREADY=1 &
Burstlength>0 & w_enb=1
WAIT_RESP
BREADY=1WVALID=1
WREA
DY=1
WREADY=0
BRESP=00 & BVALID=1
BRESP!=00 or BVALID=0
WREADY=1 & M
DataLast=1
WRE
ADY=
0 or
MD
ataL
ast=
0
(d) Finite state machine of AXI Master (i) Write process
IDLEARLEN=0ARSIZE=0
ARBURST=0
ARREADY=0 & Burstlength=0 &
r_enb=1
READRDATA
ARVALID, RREADY
READ_BURST
RDATAARVALIDRREADY
ARLEN,ARBURST,ARSIZE
ARREADY=0 & r_enb=0
ARREADY=0 & Burstlength>0
& r_enb=1
RVALID=1
RVALID=0
RVALID=1 & RLAST=1
RVAL
ID=0
or
RLAS
T=0
(d) Finite state machine of AXI Master (ii) Read process
IDLEARLEN=0ARSIZE=0
ARBURST=0
AWVALID=1 & AWLEN=0
WRITEw_enb=1BVALID=1
AWREADY=1Wr_enb=1
WRITE_BURST
W_enb=1,RDATA,ARVALIDRREADY
ARLEN,ARBURST,ARSIZE
AWVALID=0
AWVALID=1 & AWLEN>0
WAIT_RESPBRESP=00
BREADY=1
& W
VALID=1
&
WLA
ST=1
BREADY=0
BREADY=1 & WVALID=1 &
WLAST=1
BREA
DY=0
(e) Finite state machine of AXI slave (i) Write process
IDLEARLEN=0ARSIZE=0
ARBURST=0 ARVALID=1 & ARLEN=0
READRLAST=1
RVALID=1ARREADY=0
READ_BURSTRVALID=1
ARREADY=0RLAST=1/
rd_count=1
ARREADY=0
ARVALID=1 & ARLEN>0
RREADY=1
RREADY=0
RREADY=1 & rd_count=1
RREA
DY=0
and
rd_
coun
t!=0
(e) Finite state machine of AXI Slave (ii) Read process
Various Features Implemented :
• OCP as master supports 16-bit transaction and AXI as slave supports 32 bit transaction.
• Basic read and write between OCP and AXI• Write non post between OCP and AXI• Incrementing precise burst between OCP and AXI
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Verification Environment of Bus-bridge
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Test case format
Command Address Burstlength
The test case format is as shown below:
For example, -- RRR => Reset The DUT -- WRN 00000009 0 => Normal write to address 00000009 -- RDN 00000009 0 => Normal read from address 00000009 -- WNP 00000018 0 => Write non post to address 00000018 -- WRB 00000021 4 => Write burst to address 21 with burstlength of four -- RDB 00000021 4 => Read burst from address 21 with burstlegth
Of four
31
Assertion Based Verification using SVA• An assertion is a description of a property of the design -- If a property that is being checked for in a simulation does not behave the way we expect it to, the assertion fails. -- If a property that is forbidden from happening in a designhappens during simulation, the assertion fails.
• A sample system verilog assertion is as shown below :
32
Coverage Metrics The VCS tool from synopsis is used for coverage metrics. VCS can monitor and evaluate the coverage metrics of Verilog, VHDL and mixed HDL designs during simulation to determine which portions of the design have not been tested.
The various types of coverage dealt in the project are : Line Coverage
Line coverage (or statement coverage) shows you which lines of code are exercised — and which ones are not — by your test bench during a simulation run.
Toggle Coverage Toggle coverage monitors value changes on signal bits in the design. When toggle coverage reaches 100%, it means that every bit of every monitored signal has changed its value from 0 to 1 and from 1 to 0.
FSM Coverage FSM coverage, it identifies a group of statements in the source code to be an FSM and tracks the states and transitions that occur in the FSM during simulation.
Branch Coverage Branch coverage analyses if all the branches in a conditional expression is covered
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Coverage Metrics (Cont….)
The coverage metrics of the bus-bridge is as shown below:
Justification for coverage less than 100 %: Line Coverage & Branch Coverage
Line coverage of AXI master and OCP slave is little less than 100%. this is because of unable to cover the default case statement with “when others”.
34
Spyglass-lint checks The spyglass tool from Atrenta is used for lint check of the bus-bridge. The bus-bridge is lint clean. Lint is based on the commonly accepted set of HDL rules for detecting syntax errors and common connectivity errors such as unused signals and undriven inputs.
Category Error Warnings Information Messages
Black box Resolution 0 0 0
SGDC Checks 0 0 0
Policy lint 0 72 4
Total 0 72 4
Black box resolution indicates if any module is black boxed i.e. module is instantiated but source file is not supplied for spyglass analysis.
SGDC runs very basic rules to check if all the design modules are present and hierarchy of the design.
Lint checks all the rules defined LRM and flag suspicious and non portable usage of language.
Simulation Results :(a) Basic write transaction
Simulation Results :(a) Basic read transaction
Simulation Results :(a) Write non post transaction
Simulation Results :(a) Burst write transaction
Simulation Results :(a) Burst read transaction
Results :
The tabular representation of the clock cycles required for each transaction in a bus-bridge is as shown below:
Sl.no Features No. of clk cycle
1 Simple Write 4
2 Simple Read 4
3 Write Non-post 4
4 Burst Write N+2
5 Burst Read N+2
Where N= the burst length specified
Conclusion
• The OCP to AXI Bus Bridge is designed successfully and the design is verified using test bench and SVA.
• The designed Bus Bridge is able to perform OCP 16 bit to AXI 32 bit operation. The operations includes simple write, simple read, write non post, burst write and burst read.
• The code coverage is achieved by the different test scenarios.
• Integrated Assertions ( both AXI and OCP) to ensure verification.
• Generated the coverage report for the DUT.
• Code is made synthesizable by running the design on Spyglass.
Future Scope
• Developing all the remaining features of the AXI and OCP.
• Verification environment can also be enhanced by using Constrained Random Verification (CRV) or using Incisive Formal Verification (IFV) instead of directed Test cases.
Tools used :
• VCS from SYNOPSYS • SPYGLASS from ATRENTA
References :
• OCP-IP, “Open core protocol Specification v2.1”, http://www.ocpip.org/, 2007.
• ARM, “AMBA Specification v2.0”, http://www.arm.com/, 1999.
• Douglas L.Perry, “VHDL Programming by Example”, Fourth Edition, Tata McGraw-Hill
publishing, ISBN: 0-07-140070-2.
• Kuang-Chien (KC) Chen, “Assertion-Based Verification for SoC Designs”, IEEE Transactions on Electronic Engineering Times, Vol. 22, pp. 584-587, No. 4, Nov 2003.
• Vijay D'silva, S. Ramesh, and Arcot Sowmya, "Synchronous Protocol Automata: A Framework for Modelling and Verification of SoC Communication Architectures," in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'04), Volume 1, February 2004, pp. 390-395.
• Jer-Min Jou, Shiann-Rong Kuang, and Kuang-Ming Wu, "A hierarchical interface design methodology and models for SoC IP integration," in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'2002), Volume 2, May 2002, pp. II-360-II-363.
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