sogang university sogang university. semiconductor device lab. power mosfet (3) 2013. 1. 10. sd lab....
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
Power MOSFET (3)
2013. 1. 10.SD Lab. SOGANG Univ.
BYUNGSOO KIM
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
Contents1. Power U-MOSFET On-Resistance
2. Power U-MOSFET Cell Optimization
3. Device Capacitances
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
1. Power U-MOSFET On-Resis-tance
• The exception of the JFET region resis-tance
- a significant reduction of the overall specific on-resistance - much smaller cell pitch =>reduction of the specific resistance
• The total on resistance:
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
1. Power U-MOSFET On-Resis-tance
1.1 Source Contact Resis-tance
• The contact resistance:
• The specific contact resistance:
• The cell width:
Ex) a trench width(WT): 1μma mesa width (WM): 4μma source contact window width (WC): 3μma source boundary width (WS): 2μmthe width of the contact: 0.5μmthe cell width (WCell): 5 μm
the specific contact resistance: Ω
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
1. Power U-MOSFET On-Resis-tance
1.2 Source Region Resis-tance
• The N+ source region contact:
• The length of the N+ source region:
• The specific resistance of the N+ source region:
- usually negligible in the power U-MOS-FET
- Ex) cell pitch: 5 μm the length of source: 1 μm a typical sheet resistance: 20 Ω the specific resistance: 0.0005 mΩ
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
1. Power U-MOSFET On-Resis-tance
1.3 Channel Resistance• The channel resistance:
• The channel length:
• The specific resistance contributed by the channel:
Ex) a cell pitch: 5 μm The specific on-resistance(Vg=10V): 0.229 mΩ (the channel length: 1 μm, the gate oxide thickness: 500 Å)
• The reduction in the specific on-resistance contributed by the channel in the UMOS-FET
structure is due to the increase in the channel density.
channels formed on both of the verti-cal sidewalls of the trench-gate structure
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
1. Power U-MOSFET On-Resis-tance
1.4 Accumulation Resis-tance
• The accumulation length:
• The resistance of the accumulation layer:
• The specific on-resistance contributed by the accumulation layer:
: 0.6
• smaller than that for the power VD-MOSFET structure
• the accumulation layer path (LA) is only 1 μm in size and the cell pitch is much smaller for the UMOSFET structure.
• In some power U-MOSFET structures, a thicker oxide is used
to reduce the gate–drain capacitance =>the accumulation layer resistance will be increased by the smaller charge within layer
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
• The width of the cross-sectional area for the first por-tion of the current path:
• The resistance of an elemental segment of thickness dy:
• The resistance contributed by the first portion of the drift region:
• The distance over which the cross-sectional area:
• The resistance of this portion of the drift region:
• The specific on-resistance:
• Ex) drift region doping: a blocking voltage capacity: 50V a cell width: 5 μm the specific resistance: 0.209 mΩ
1. Power U-MOSFET On-Resis-tance
1.5 Drift Region Resistance
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
• The specific resistance:
• It is necessary to use a substrate with a thickness of 500μm
• the thin (2–50 μm) epitaxial drift region is grown a substrate with on a thickness of 500 μm to avoid breakage during han-dling of the wafers in the processing equipment.
• The lowest available resistivity: 0.003 Ωcm
The specific resistance: 0.15 mΩ (<50V)
• the wafer thickness reduced to 200 μm after device fabrication =>the specific resistance 0.06 mΩ
• reduce the thickness of the wafer just be-fore application of drain electrode metal
1. Power U-MOSFET On-Resis-tance
1.6 N+ Substrate Resistance
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
1. Power U-MOSFET On-Resis-tance
1.7 Drain Contact Resis-tance
• the current flows through the contact resistance between the drain metal and the N+ substrate.
• Due to the uniform current flow at the drain contact, its resistance is not am-plified.
• a contact resistivity(Ti): Ω
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
1. Power U-MOSFET On-Resis-tance
1.8 Total On-Resistance
• The ideal specific on-resistance: 0.105 mΩ (a device capable of supporting 50 V)
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
1. Power U-MOSFET On-Resis-tance
1.8 Simulation Example
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
2. Power U-MOSFET Cell Opti-mization
2.1 Orthogonal P-Base Contact Structure
• an increase in the channel density by a factor of 2.5 times resulting in a smaller specific on-resistance
• A design with a ratio (ZN+/ZP) of 10 provides an adequate design compromise
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
2. Power U-MOSFET Cell Opti-mization
2.1 Orthogonal P-Base Contact Structure
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
2. Power U-MOSFET Cell Opti-mization
2.2 Impact of Breakdown Voltage
• The breakdown voltage capability - a higher resistivity drift region - larger thickness
• improvements in the performance of the power U-MOSFET structure
- by improving the edge termination design
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
2. Power U-MOSFET Cell Opti-mization
2.3 Ruggedness Improvement
• the enhanced electric field• rounding the bottom of the
trenches
• the enhanced electric field• rounding the bottom of the
trenches• the inclusion of a deep P+ region• larger cell pitch• increase of the on-resistance
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
• In practice the switching speed is limited by the device capacitances.
• the small thickness of the gate oxide - a significant capacitance
• The rate of switching between the on-state and off-state => determined by The rate of being charged or discharged
• A role of the capacitance between the drain and the gate electrodes - the drain current and voltage transitions during the switching event
3. Device Capacitances
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
3. Device Capacitances
6.1 Basic MOS Capacitance
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
3. Device Capacitances
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
3. Device Capacitances
6.2 Power VD-MOSFET Structure Capaci-tances
• The input (or gate) capacitance of the struc-ture
- the overlap of the gate electrode with the N+ source and P-base regions - determined by the oxide capacitance
• It is common design practice in power VD-MOSFET structures to overlap the source elec-trode over the gate electrode.
- a very thick metal layer (4–10 μm) to reduce its resistance =>an additional input capacitance - a thick (typically 6,000 Å) interelectrode di-electric film (tIEOX)
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
• The specific input capacitance:
• The gate–drain (or reverse transfer) capac-itance:
3. Device Capacitances
21.35nF
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3. Device Capacitances
• CSM is decreases with increasing drain bias voltage.
• The applied drain bias:
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3. Device Capacitances
3.0 nF
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3. Device Capacitances
• The output capacitance (CO) is associated with the capacitance of the junction between the P-base region and the N-drift region.
• The specific junction capacitance
• the depletion region thickness at the junction4.3 nF
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
3. Device Capacitances
6.3 Power U-MOSFET Structure Capaci-tances
• The input (or gate) capacitance - the overlap of the gate electrode with the N+ source and P-base regions along the sidewalls of the trench - determined by the oxide capacitance
• The formation of a large source metal area - a very thick metal layer (4–10 μm) to reduce its resistance=>an additional input capacitance - a relatively thick (typically 6,000 Å) interelec-trode dielectric film (tIEOX)
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SOGANG UNIVERSITYSOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB.
• The specific input (or gate) capacitance:
• The input capacitance for the power U-MOS-FET is much larger than that for the power VD-MOSFET.
• the reduction of the specific on-resistance with the power UMOSFET structure is at-tended with an increase in the input gate ca-pacitance.
• The reduction of the specific input capaci-
tance of the power U-MOSFET - increasing the mesa width - accompanied by an increase in the specific on- resistance
3. Device Capacitances
105 nF
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3. Device Capacitances
8.2 nF
much larger than that for the power VD-MOSFET
8.2 nF
4.0 nF
greatly reduced when the mesa width is enlarged an increase in the specific on-resistance
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3. Device Capacitances
5.5 nF
6.0 nF
5.5 nF
the model A - without screening (KS = 0) - a much larger specific output capacitance
the model B - a screening factor KS = 0.75 - the extracted values
Model A:
Model B: