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The Leader in Memory Technology Solid State Drive Verification and Driver Integration Using PCI Express Accelerated VIP (AVIP) CHALLENGES and SOLUTIONS Samsung Team Kannusamy M Sandeep Saha Raghuram Pallapa Presented By Pete Heller (Cadence) Dave Allen (Cadence)

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The Leader in Memory Technology

Solid State Drive Verification and Driver Integration Using PCI Express Accelerated VIP (AVIP)

CHALLENGES and SOLUTIONS

Samsung Team Kannusamy M

Sandeep Saha

Raghuram Pallapa

Presented By Pete Heller (Cadence)

Dave Allen (Cadence)

The Leader in Memory Technology

Agenda

Introduction

Samsung Situation Analysis

Samsung’s Verification Challenges & Cadence Solutions

Validation Environments: Before and After AVIP

Results

Conclusions

2

The Leader in Memory Technology

Introduction

1999

Flash based SSDs 2007 PCIe-SSD

2009 SATA -SSD

PCIe-SSD 2010

SSD

• 18 GB

• 320 GB

• 100 GB to 960 GB • 740 MB/s

• Gen 2.0 • 5.2 TB

• 6 Gbit/s

2012 • Gen 3.0 • 12 TB

Solid State Drives (SSD) are storage devices for persistent data. SSDs are implemented using flash memory versus a spinning hard disk

The PCIe-SSD is a 2nd generation design implementation to speed up data transfer

Previous generations used SATA interfaces even though there was no disk drive

SSD History

SSD provides greater speed and reliability

versus hard disk drives

The Leader in Memory Technology

Situation Analysis: SSDs Challenges for Verification

Verifying a PCIe SSD requires extremely high performance • Must be able to simulate large data transfers (e.g., gigabytes) between

host and device memory • Simulation performance not sufficient for PCIe SSD verification

Must be able to check integration

Must be able to simulate many system level use cases

Must be able do hardware and software integration

Need to develop software prior to silicon availability

Host side must support a large memory for data storage

The Leader in Memory Technology

Design Block Diagram

Solid State Drive (SSD) controller

Replacing SATA with PCI Express 2.0 for external interface

C/C++ Host Driver

(PCIe Root

Complex)

In Simulation

PCI Express (End Point)

PIPE

ARM based CPU subsystem External i/f

C/C++ Memory Model

Transaction Layer

Data Link Layer

Physical Layer (PIPE)

PCI Express Stack

ARM based CPU subsystem

Firmware

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C/C++ Host Driver

(PCIe Root

Complex)

In Simulation

External i/f

System Bus

PIPE

SSD Validation Challenges

ARM based CPU subsystem

Firmware

Simulation too slow to Integrate and Debug host software drivers

PCI Express (End Point)

Simulation too slow for PIPE level PCI Express

verification

Simulation too slow for firmware development and debug

C/C++ Memory Model

Simulation too slow for bulk DMA transfer validation

Lacked ability to translate transaction level packets into

PIPE level traffic

KEY Samsung

RTL

Samsung FW/SW

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Acceleration+AVIP Based Solution (part 1)

PCI Express AVIP C Proxy

Cadence AVIP

KEY

Accelerated on Palladium

External i/f

System Bus

PIPE

PCI Express (End Point)

AVIP generates PIPE level traffic through host transactions to validate PCI Express

at Transaction Layer

Simulation too slow for bulk DMA transfer validation

Samsung RTL

Samsung FW/SW

C/C++ Host Driver

(PCIe Root

Complex)

PCI Express AVIP BFM C/C++

Memory Model

PCI Express Host Driver Modeling, Integration & Debug

Acceleration meets performance needs for PIPE level PCIe verification

Acceleration fast enough to Integrate and Debug host software drivers

ARM based CPU subsystem

Firmware

Simulation too slow for firmware development and debug

The Leader in Memory Technology

C/C++ Host Driver

(PCIe Root

Complex)

Accelerated on Palladium

Acceleration+AVIP Based Solution (part 2)

ARM Tools

PCI Express AVIP C Proxy

Extermal i/f

System Bus

PIPE

PCI Express (End Point)

ARM Devel. Studio w/ RealView

Debugger

VStream Transactor

AVIP+VSTREAM enables fast firmware development and debug

C/C++ Memory Model

PCI Express AVIP BFM

Simulation too slow to validate bulk DMA transfers

ARM based CPU subsystem

Firmware

Firmware Integration & Debug

PCI Express Host Driver Modeling, Integration & Debug

Cadence AVIP

KEY Samsung

RTL

Samsung FW/SW

The Leader in Memory Technology

C/C++ Host Driver

(PCIe Root

Complex)

Accelerated on Palladium

PCI Express AVIP C Proxy

SATA i/f

System Bus

PIPE

ARM based CPU subsystem

PCI Express (End Point)

ARM Devel. Studio w/ RealView

Debugger

VStream Transactor

Acceleration+AVIP Based Solution (part 3)

Firmware Integration & Debug

C/C++ Memory Model

PCI Express AVIP BFM

AVIP enables fast DMA transfers

ARM based CPU subsystem

Firmware

PCI Express Host Driver Modeling, Integration & Debug

ARM Tools

Cadence AVIP

KEY Samsung

RTL

Samsung FW/SW

SATA Controller Validation

The Leader in Memory Technology

Timeline

Month Activity Summary

Jan’12 Samsung using simulation with sim VIP, emulation and

FPGA prototype environments

Feb’12 Samsung realized they needed additional speed for sub

system validation

Mar’12 • Contacted Cadence to identify solution

• Cadence proposed acceleration with AVIP solution for

SoC level validation

Apr’12 Technical team went on-site to construct AVIP based

environment.

May’12 Samsung actively using acceleration/AVIP environment

for validation

Aug’12 Samsung Success story published

10

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Verification Environments (prior to AVIP)

Validation Environment

Simulation In-Circuit Emulation FPGA Prototype

Platform Workstation Palladium ICE+ Speedbridge

Custom built boards

Purpose Subsystem and SoC RTL verification

SoC level HW+FW validation

SoC level validation, application software development

Traffic Source Simulation Target Device

Performance Slow Fast Very Fast

Observability Excellent Good Poor

Controllability Excellent Good Poor

Testbench reuse High n/a n/a

Bring up time Days Weeks Months

The Leader in Memory Technology March 22, 2013 Cadence Confidential: Cadence Internal Use Only

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Verification Environment Options (Including AVIP)

Validation Environment

Simulation Acceleration with AVIP

In-Circuit Emulation

FPGA Prototype

Platform Workstation Palladium XP SA+AVIP

Palladium ICE+S/B Custom built boards

Purpose Subsystem and SoC RTL verification

SoC level HW+FW validation

SoC level HW+FW validation

SoC level validation, application software development

Traffic Source Simulation Host model Target Device

Performance Slow Medium Fast Very Fast

Observability Excellent Excellent Good Poor

Controllability Excellent Excellent Good Poor

Testbench reuse High High n/a n/a

Bring up time Days ~2-5 weeks ~2 weeks 6 months

Acceleration environment adds needed performance and capability

The Leader in Memory Technology

Runs hundreds of times faster than simulation Enables Hardware/Firmware integration and debug Generic plug and play architecture with

straightforward C++ interface Enables easy reuse Flexible host interface Supplements simulation and in-circuit emulation

use models Can be used with partial or complete designs Avoids need for external target hardware

Can leverage external target hardware and virtualized system components

Key Reasons Samsung Selected PCIe AVIP

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Performance Analysis

AVIP saved 7 weeks of verification time and enhanced the Firmware development life cycle relative to simulation

Performance achieved: 410X speedup relative to simulation 1.25 MHz execution speed

Palladium verification environment used on Multi-million gate design

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Cadence PCI Express AVIP Key Features

Compliant with PCI Express 2.0 and 3.0 specifications Functions as Root Complex or End Point Provides simple C++ based user interface Provides high performance on Palladium XP Synthesizable Transaction, Link, and Physical layers all run in

Palladium XP Application Layer runs in simulator Fully configurable model Supports power management Error Injection Supports PIPE and Serial interface

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Conclusion

Overall performance of SSD verification environment is hundreds of times faster than simulation Saved verification time and increased productivity 100% Enabled higher quality product

The PCIe SSD verification environment can be ported to any PCIe based SSDs

with minimal effort. Already being used in follow on projects

The PCIe AVIP provides fast and easy to use C++ based user interface

Users can easily implement the application layer functionality for debugging and

hardware/firmware integration

The Leader in Memory Technology

Thank you

The Leader in Memory Technology

Transaction Based Acceleration(TBA)

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Timeline

Design functionality

Solid State Drive (SSD) for Servers, Laptops/Netbooks and Tablet markets

Adding PCI Express 2.0 to existing SATA based design

Phase 1: Block level verification

Used simulation environment with Cadence PCI Express simulation VIP

Built verification environment and found design bugs

Verification environment shaken out using the simulation VIP (AVIP not used during this phase of the project)

Phase 2: Subsystem validation

3 main validation needs:

PCI Express Host Driver Modeling, Integration & Debug

Firmware Integration & Debug

SATA Controller Validation

First tried to use Cadence simulation VIP together with Palladium/IXCOM

Samsung were familiar with the simulation VIP it seemed to make sense to continue using it.

Unfortunately, the simulation VIP’s performance wasn't sufficiently high to meet their needs

Next decided to employ Accelerated VIP (AVIP) to enable higher performance

AVIP integration was straightforward because DUT was already running on Palladium

Starting with the simulation VIP based environment reduced AVIP bringup time by 2-3 weeks

Samsung embraced Accelerated VIP (AVIP)

AVIP met their subsystem validation performance and functionality requirements

They purchased AVIP licenses and have provided a success story

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