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Contents lists available at ScienceDirect Solid State Electronics journal homepage: www.elsevier.com/locate/sse Size eect of electronic properties in highly arsenic-doped silicon nanowires Tom Mauersberger a,c, , Imad Ibrahim b,c , Matthias Grube a , André Heinzig b,c , Thomas Mikolajick a,b,c , Walter M. Weber a,c,d a NaMLab gGmbH, Noethnitzer Strasse 64a, Dresden 01187, Germany b Chair for Nanoelectronic Materials, TU Dresden, Noethnitzer Strasse 64a, Dresden 01187, Germany c Center for Advancing Electronics Dresden (CfAED), TU Dresden, Dresden 01069, Germany d Institute of Solid State Electronics, TU Wien, Gusshausstrase 25, Wien 1040, Austria ARTICLE INFO The review of this paper was arranged by Joris LacordABSTRACT The unique electrostatic properties of semiconductor nanowires enable the realization of novel transistor types by the possibility to use surround gate architectures resembling ideal gate electrostatic control. Nevertheless one fundamental issue of semiconducting nanowire channels is the reliable control of doping to adjust the charge carrier concentration. Indeed, as dimensions scale down the surrounding media and the interfaces become more important. In this study we experimentally investigate the role of surface depletion and dielectric mismatch on the electronic charge transport of highly arsenic doped and bottom-up grown silicon nanowires. Electrical characterization of silicon nanowires (SiNWs) synthesized by Au catalyzed vapour-liquid-solid (VLS) growth and in-situ arsine (AsH 3 ) doping is reported for the rst time. We demonstrate that high n-type doping is possible by adjusting the dopant precursor ow ratio during growth. Based on electrical measurements of individual na- nowires, reproducible donor concentrations of up to 5.2 × 10 19 cm 3 could be revealed. By measuring the electrical characteristics for individual nanowires in dependence of their radius, we show that the electrically active carrier density drastically reduces for small nanowires at radii much larger than those at which quanti- zation or dopant surface segregation eects are expected to occur. Furthermore, enhancement of the contact transparency for small radii nanowires is demonstrated through dopant segregation upon metal silicidation. Size dependent measurement of electrical characteristics revealed improved contact resistivities as low as 1.4 × 10 11 Ωm 2 . 1. Introduction The superior electrostatic properties of surround gate nanowires are considered to be able to provide the ultimate scaling capability of conventional eld eect transistors (FET) [13]. Their unique elec- tronic properties make them important contenders of beyond com- plementary metal oxide semiconductor (CMOS) electronic switches [3]. The charge transport in those devices relies on the availability of charge carriers in the nanowire and source/drain contact regions usually enabled by impurity doping. In bulk silicon we are somewhat used to the assumption that every dopant atom incorporated is also electrically active. For this to be true several requirements have to be fullled. The dopant atom has to be properly, i.e. substitutionally incorporated in the lattice, which is usually not the case after ion implantation. This makes an additional thermal treatment necessary. Furthermore, the dopant atom has to be ionized. For bulk silicon doped with standard dopants like phosphorous (P), arsenic (As) and boron (B) this is a fair approximation at room temperature with the ionization energies being only a few meV. In nanowires, due to their large surface to volume ratio, the contribution of surfaces and interfaces to surrounding di- electrics and the properties of the dielectric media itself become ex- tremely important as they aect the dopant ionization energies [4]. The reason for the small dopant ionization energies in bulk is the shielding of the dopants Coulomb potential by the surrounding charge carriers in the semi-innite semiconductor. In nanowires, this shielding is reduced due to the limited volume and thus the ionization energy rises. Fur- thermore, it also depends on the dielectric properties of the surrounding dielectric because the dopant potential can penetrate into the nano- wires surrounding and therefore the eld shielding changes. This eect was proposed theoretically [4] and experimentally veried for P-doping in SiNWs [5], indium nitride (InN) nanowires [6] and gallium nitride (GaN) nanowires [7]. Another aspect is the presence of interface states and trapped charges. Active charge carriers along the vicinity of the semiconductor/dielectric interface are expected to be trapped leading https://doi.org/10.1016/j.sse.2019.107724 Corresponding author at: NaMLab gGmbH, Noethnitzer Strasse 64a, Dresden 01187, Germany. E-mail address: [email protected] (T. Mauersberger). Solid State Electronics xxx (xxxx) xxxx 0038-1101/ © 2019 Elsevier Ltd. All rights reserved. Please cite this article as: Tom Mauersberger, et al., Solid State Electronics, https://doi.org/10.1016/j.sse.2019.107724

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  • Contents lists available at ScienceDirect

    Solid State Electronics

    journal homepage: www.elsevier.com/locate/sse

    Size effect of electronic properties in highly arsenic-doped silicon nanowires

    Tom Mauersbergera,c,⁎, Imad Ibrahimb,c, Matthias Grubea, André Heinzigb,c,Thomas Mikolajicka,b,c, Walter M. Webera,c,d

    aNaMLab gGmbH, Noethnitzer Strasse 64a, Dresden 01187, Germanyb Chair for Nanoelectronic Materials, TU Dresden, Noethnitzer Strasse 64a, Dresden 01187, Germanyc Center for Advancing Electronics Dresden (CfAED), TU Dresden, Dresden 01069, Germanyd Institute of Solid State Electronics, TU Wien, Gusshausstrase 25, Wien 1040, Austria

    A R T I C L E I N F O

    The review of this paper was arranged by “JorisLacord”

    A B S T R A C T

    The unique electrostatic properties of semiconductor nanowires enable the realization of novel transistor typesby the possibility to use surround gate architectures resembling ideal gate electrostatic control. Nevertheless onefundamental issue of semiconducting nanowire channels is the reliable control of doping to adjust the chargecarrier concentration. Indeed, as dimensions scale down the surrounding media and the interfaces become moreimportant. In this study we experimentally investigate the role of surface depletion and dielectric mismatch onthe electronic charge transport of highly arsenic doped and bottom-up grown silicon nanowires. Electricalcharacterization of silicon nanowires (SiNWs) synthesized by Au catalyzed vapour-liquid-solid (VLS) growth andin-situ arsine (AsH3) doping is reported for the first time. We demonstrate that high n-type doping is possible byadjusting the dopant precursor flow ratio during growth. Based on electrical measurements of individual na-nowires, reproducible donor concentrations of up to 5.2 × 1019 cm−3 could be revealed. By measuring theelectrical characteristics for individual nanowires in dependence of their radius, we show that the electricallyactive carrier density drastically reduces for small nanowires at radii much larger than those at which quanti-zation or dopant surface segregation effects are expected to occur. Furthermore, enhancement of the contacttransparency for small radii nanowires is demonstrated through dopant segregation upon metal silicidation. Sizedependent measurement of electrical characteristics revealed improved contact resistivities as low as1.4 × 10−11 Ωm2.

    1. Introduction

    The superior electrostatic properties of surround gate nanowires areconsidered to be able to provide the ultimate scaling capability ofconventional field effect transistors (FET) [1–3]. Their unique elec-tronic properties make them important contenders of beyond com-plementary metal oxide semiconductor (CMOS) electronic switches [3].The charge transport in those devices relies on the availability of chargecarriers in the nanowire and source/drain contact regions – usuallyenabled by impurity doping. In bulk silicon we are somewhat used tothe assumption that every dopant atom incorporated is also electricallyactive. For this to be true several requirements have to be fulfilled. Thedopant atom has to be properly, i.e. substitutionally incorporated in thelattice, which is usually not the case after ion implantation. This makesan additional thermal treatment necessary. Furthermore, the dopantatom has to be ionized. For bulk silicon doped with standard dopantslike phosphorous (P), arsenic (As) and boron (B) this is a fair

    approximation at room temperature with the ionization energies beingonly a few meV. In nanowires, due to their large surface to volumeratio, the contribution of surfaces and interfaces to surrounding di-electrics and the properties of the dielectric media itself become ex-tremely important as they affect the dopant ionization energies [4]. Thereason for the small dopant ionization energies in bulk is the shieldingof the dopant’s Coulomb potential by the surrounding charge carriers inthe semi-infinite semiconductor. In nanowires, this shielding is reduceddue to the limited volume and thus the ionization energy rises. Fur-thermore, it also depends on the dielectric properties of the surroundingdielectric because the dopant potential can penetrate into the nano-wire’s surrounding and therefore the field shielding changes. This effectwas proposed theoretically [4] and experimentally verified for P-dopingin SiNWs [5], indium nitride (InN) nanowires [6] and gallium nitride(GaN) nanowires [7]. Another aspect is the presence of interface statesand trapped charges. Active charge carriers along the vicinity of thesemiconductor/dielectric interface are expected to be trapped leading

    https://doi.org/10.1016/j.sse.2019.107724

    ⁎ Corresponding author at: NaMLab gGmbH, Noethnitzer Strasse 64a, Dresden 01187, Germany.E-mail address: [email protected] (T. Mauersberger).

    Solid State Electronics xxx (xxxx) xxxx

    0038-1101/ © 2019 Elsevier Ltd. All rights reserved.

    Please cite this article as: Tom Mauersberger, et al., Solid State Electronics, https://doi.org/10.1016/j.sse.2019.107724

    http://www.sciencedirect.com/science/journal/00381101https://www.elsevier.com/locate/ssehttps://doi.org/10.1016/j.sse.2019.107724https://doi.org/10.1016/j.sse.2019.107724mailto:[email protected]://doi.org/10.1016/j.sse.2019.107724

  • to a depletion or accumulation zone close to the interface [8]. To in-vestigate these effects we used doped VLS-grown nanowires as testvehicles and characterized them individually. Until now, investigationson in-situ doping of bottom-up grown SiNWs were restricted to B [9]and P [10–12]. However, the investigation of in-situ arsenic (As) dopinghas been missing so far despite the relevance of this donor impuritygiven its comparatively large solubility in bulk silicon and its low dif-fusivity principally enabling the capability to create ultra-sharp junc-tions [13]. Here, we report the first electrical characterization of in-situAs-doped VLS-grown SiNWs and study their size dependent electricalproperties.

    2. Experimental

    Doped SiNWs were synthesized by the bottom up particle assistedvapor liquid solid (VLS)-mechanism in an industrial low pressure che-mical vapor deposition (LPCVD) reactor with gold (Au) as catalyst froma nominally 1.2 nm thin sputtered film on oxide-free Si (1 0 0) sub-strates. Process temperature was set from 400 to 450 °C to first allowthe agglomeration of the Au film into nanoparticles and the consecutiveVLS-growth. Monosilane (SiH4) was used as the precursor gas and ar-sine (AsH3) as n-type dopant source. The growth time was adjustedfrom 20 to 30 min to yield SiNWs with lengths up to 40 µm. The dia-meters are homogenous along the nanowirés full length and range from5 to 60 nm as given by the Au cluster thickness. To achieve high n-typedoping, AsH3 to SiH4 gas flow ratios of 9 × 10−2 and 7 × 10−2 wereused, resulting in active donor concentrations of 5.2 × 1019 cm−3 and2.6 × 1019 cm−3, respectively as determined from electrical mea-surements explained below. For electrical characterization, deviceswere fabricated by first detaching and suspending the as-grown wires insolution and posteriorly transferring them to host chips by spray dis-persion. The host chips were composed of a 300 nm thick top insulatingSiO2 layer and predefined contact electrodes made from titanium/nickel (Ti/Ni). Typically, four contact leads were defined by electronbeam lithography and PMMA/-(MA) double resist layer. After exposureand development, a native oxide etch in 100:1 NH4F buffered hydro-fluoric acid in HF was performed. Immediately thereafter, the sampleswere loaded to a sputtering tool to deposit Ti/Ni or pure Ni layers,followed by a lift-off procedure in acetone. For the first electricalcharacterization no annealing was performed, since intrusive silicidecontacts affect the four-point measurement setup. To study dopantsegregation by silicidation, Ni contacted NWs were annealed in forminggas atmosphere at 450 °C for 20 s in a rapid thermal processing furnace.

    3. Results and discussion

    If a nanowire is subject to electrical characterization from twoelectrodes, the total resistance RT of the system can be described as

    = + +R 2 R R RT C M NW (1)

    where RC is the contact resistance at each electrode, RM is the totalresistance of the contact metal and RNW is the nanowire resistance. Ifthe contact resistance is of the same order as the nanowire resistance acorrect determination of RNW is only possible by multiple terminalmethods. For this study, a four-probe technique was chosen allowingthe extraction of the nanowire resistivity assuming a circular nanowirecross section. As we will define later, we will call this the apparentnanowire resistivity ρapp in accordance to Björk et al. [5]:

    =ρπ

    RrLapp NWphys2

    (2)

    with rphys being the physical nanowire radius and L as the probed na-nowire length. Both dimensions were measured by scanning electronmicroscopy (SEM). This was done after electrical characterization as theexcessive electron beam irradiation was found to degrade the char-acteristics. The thickness of the native oxide shell of around 1.8 nm as

    determined by transmission electron microscopy (TEM) was subtractedfrom all measured radii. Nanowires with radii ranging from 7 to 28 nmcould be contacted and measured. Fig. 1 presents the calculated ρappversus the physical nanowire radius for two nominal doping con-centrations. It tends to saturate for large diameters and exhibits a supra-linear increase as the nanowire radius decreases. This behaviour isobserved clearly for both nominal doping concentrations. The nominaldoping concentration ND was obtained from the resistivity values of thethickest measured nanowires to ensure bulk properties and negligiblesize effects. At these diameters, resistivity saturation sets in. For thesewires an empirical bulk mobility model was used to extract the dopingconcentration [14] as common reference works like Sze & Ng [15] orEranna [13] don’t provide values for arsenic doping in silicon. For thetwo corresponding dopant/precursor flow ratios studied, the nominaldoping concentrations ND of 2.6 × 1019 cm−3 and 5.2 × 1019 cm−3

    were extracted. Note that for the lower doping concentration (bluesymbols) even thinner nanowires than the ones provided in the figurecould be measured. For nanowires with radii of 9 and 7 nm resistivitiesof 552 and 1130 mΩcm could be extracted, owing their I-V char-acteristics still being ohmic. The found size effect is similar to the oneobserved in semiconducting P-doped SiNWs [5] and indium nitride(InN) NWs [6] as well as in metallic Cu nano-via interconnects [16],nano-graphitic metallic carbon nanowires [17] and Cu-nanowires [18].To explain the observed effect various phenomena are considered. Sincethe nanowires are single-crystalline and have smooth surfaces, we ex-clude the possibility of mobility degradation by scattering at grainboundaries and rough surfaces as reported in [5,6,19]. Like Björk et al.[5], we also exclude that quantum confinement takes place in the na-nowires, since for silicon this is only expected for radii< 5 nm [4]. Infact, the most plausible explanations are surface depletion by eitherfixed charges (Qf) or charges trapped in interface states (Qit) reducingthe electrically active cross section proposed by Schmidt [8] and donordeactivation by dielectric mismatch proposed initially by Niquet [4] andDiarra [20] and observed experimentally by Björk in P-doped SiNWs[5]. Nanowires grown by the VLS-method dońt have a perfect circularcross section but are typically facetted, e.g. in a hexagonal shape [21].

    Fig. 1. Apparent nanowire resistivity ρapp versus the physical nanowire radiusrphys for two nominal doping concentrations ND of 2.6 × 1019 cm−3 (bluesymbols) and 5.2 × 1019 cm−3 (green symbols). The apparent resistivity tendsto saturate for large radii and supra-linearly increases with decreasing radiusfor the two nominal doping concentrations. The inset shows a scanning electronmicroscopy (SEM) top-view of a nanowire contacted by four titanium/nickel(Ti/Ni) electrodes. No annealing was performed after contact deposition. (Forinterpretation of the references to colour in this figure legend, the reader isreferred to the web version of this article.)

    T. Mauersberger, et al. Solid State Electronics xxx (xxxx) xxxx

    2

  • Thus, nanowires growing in (1 1 0) axis orientation, like the ones stu-died here, were shown to typically have four (1 1 1)- and two (1 1 0)-oriented surfaces (see Fig. 2a). This makes a considerably large part ofthe surface prone to charges trapped in interface states as well as fixedoxide charges as their densities typically are largest for (1 1 1)-orientedsurfaces, followed by (1 1 0) surfaces as compared to ideal (1 0 0)surfaces employed in most modern MOSFETs [22]. Additionally, thenanowires are surrounded by a thin and possibly low quality nativeoxide, which exhibits a rather larger density of fixed oxide charges,oxide trapped charges in the dielectric and a higher level of unsaturatedbonds which lead to interface states that might deplete the nanowiresurface of mobile carriers by charge trapping at interface states. Thismeans that the actual radius carrying the charge could be significantlysmaller than the physical radius measured by SEM. In literature this isusually expressed in terms of a physical nanowire radius rphys that isreduced to a charge carrying electronic radius relec (Fig. 2b). The in-terface states will capture electrons from the surface of a n-doped na-nowire leading to a depletion zone visualized by the white annulus inFig. 2b. By solving Poisson’s equation in polar coordinates and adoptinga full depletion approximation, the electronic nanowire radius can becalculated by [8]:

    = +−

    − ⎛⎝

    + ⎞⎠

    φr r

    2r Q 2r q D

    q(N N ) 1 Dε εelec phys

    2 phys f phys2

    it 0

    D Ar q2 itsphys 2

    0 (3)

    where Qf is the fixed oxide charge density, q is the elementary charge,Dit is the density of interface trapped charges, φ0 is the electrostaticpotential at r = 0, ε0 and εs are the relative dielectric constants ofvacuum and the semiconductor and finally ND,A is the donor or acceptorconcentration. For the following discussions Qf was set to zero, as theeffect of fixed charges on the nanowires electronic properties is as-sumed to be rather weak compared to charges trapped in interfacestates [8]. For a correct determination of the nanowire resistivity theelectronic radius has to be used. A popular method for determination ofinterface state density is C-V characterization. While for top down na-nowire FETs test structures with a large amount of parallel nanowirechannels can be used [23], the estimation for VLS-grown nanowires ismore complex as parallel nanowires would preferably need the samesize and alignment, such that little data is found in literature [24]. Dueto the stochastic size distribution and corresponding preferred crystalorientation [25,26], the density of interface states is an average valueover a broad range of diameters with different Dit levels. For furtheranalysis a rather high Dit of 1 × 1013 eV−1 cm−2 was assumed sincevalues in this range but slightly smaller have been reported by Casséet al. [23] for silicon nanowires with round cross section near the bandedges. The high level assumed here also accounts for the lack of an-nealing in our devices and the presence of only a thin low quality nativeoxide [27]. Fig. 2c) presents the measured resistivity ρapp corrected for

    surface depletion by charges trapped in interface states, yielding thecorrected resistivity ρcorrected. From a comparison to the experimentaldata in Fig. 1, it can be seen that even for a very high density of in-terface traps, the effect of surface depletion for the two doping con-centrations used in this study is very weak. To further circumvent thiseffect and to strongly decrease Dit, one could replace the native oxide bya high quality thermal oxide, followed by an anneal in forming gas-atmosphere to passivate the remaining interface states [28]. The twodashed horizontal lines show the resistivity values of the thickest na-nowires as well as the resistivity if in the measured nanowires onlysurface depletion by charges trapped in interface states would degradethe resistivity. As the resistivity still increases for thinner nanowires,there has to be an additional effect impacting the electrical properties.This effect is most probably dopant deactivation by dielectric mismatchbetween the nanowire and the surrounding SiOx shell and outer air, asthe other possibilities were already excluded. Until now, it was assumedthat all the dopants that are present in the nanowires are also active, i.e.they are ionized generating a free electron that can contribute to acurrent flowing through the nanowire. One important aspect is thescreening of the dopant potential. If we consider a single donor atom insilicon, a certain energy is required to remove the outermost electronfrom the shell. As the extracted dopant concentrations 5.2 × 1019 cm−3

    and 2.6 × 1019 cm−3 are near the Mott transition (Ncrit) of arsenicdoped silicon [29], one can describe this problem as an electron that istrapped in a finite quantum well, where only a certain number of boundstates can exist. The more dopant atoms there are, the stronger thepotential of this impurity can be screened. This means that the quantumwell, where the electron is trapped gets narrower, leading to the energyof bound states to rise. Increasing the concentration of dopants evenfurther eventually leads to a “drop out” of the energy level of theoutermost bound state from the quantum well. That means that theelectron in this state is no longer bound to the donor and is now free tomove inside the silicon. For that to happen these donor atoms have tohave a critical distance, i.e. a critical screening length allowing theinteraction of dopant potentials. As the screening length is an unhandyquantity that we cannot directly influence, it is much more common forsemiconductors to express it in terms of a critical doping concentrationNcrit. From that concentration on, the dopant potentials becomestrongly screened and as an overall effect the ionization energy isdrastically reduced. In literature this phenomena is usually described bya doping concentration dependent ionization energy [29]:

    =+ ( )

    E (N )E

    1cI D

    I,0N

    ND

    crit (4)

    With EI,0 (As) = 54 meV, Ncrit ≈ 3 × 1018 cm−3 and c = 1.5.Arsenic impurities in bulk silicon with a concentration of e.g.ND = 1019 cm−3 would have an ionization energy of only 7.6 meV,

    Fig. 2. a) Schematic of a [1 1 0] oriented siliconnanowires with hexagonal cross section visualizingsurface orientation dependent interface trap densityDit. b) n-doped nanowire with thin native oxide,where a circular shape is assumed. The charged in-terface states with density Dit capture electrons at thenanowire/oxide interface, i.e. at radius rphys andcause a depletion zone at the semiconductor nano-wire surface leaving behind a smaller electricallyactive cross section with radius relec [5]. c) Correctednanowire resistivity ρcorrected versus calculated elec-tronic radius relec.

    T. Mauersberger, et al. Solid State Electronics xxx (xxxx) xxxx

    3

  • being even less than the thermal energy at room temperature. For thisreason, it is safe to assume that in bulk silicon practically all dopants areionized. For nanowires, on the contrary, the situation is different. Theimpurity potentials are not sufficiently screened within the nanowireanymore, but inside the surrounding medium. In practical cases, thismedium is a dielectric and its properties therefore greatly influences theproperties of the nanowire. Diarra et al. studied this problem theoreti-cally and found that with decreasing nanowire radius, the screeningreduces and the dopant ionization energies rise [20]. An expression wasfound that clearly states the importance of the dielectric surrounding ofa nanowire with radius r:

    ⎜ ⎟= + −+

    ⎛⎝

    ⎞⎠rε

    ε εε ε

    F εε

    E (r) E 2s

    s out

    s out

    s

    OUTI I,0

    (5)

    where EI,0 is the bulk ionization energy of the dopant and εs and εout arethe relative dielectric constants of the semiconductor nanowires and itssurrounding dielectric. The function F(x) was given by Niquet et al. [4].The closer the dielectric constants of the semiconductor nanowire andits dielectric surrounding are, the closer is the ionization energy to thebulk case (εs = εout) and the less pronounced is the effect of increased EIfor small nanowires. To understand how this effects the resistivity ofnanowires, the charge neutrality condition was used:

    ⎛⎝

    − ⎞⎠

    =+ −( )

    F E EkT

    N

    g

    2

    1 expC

    F C D

    DE E

    kT

    1/2F D

    (6)

    where NC is the effective density of states in the conduction band, F1/2(x) is the Fermi integral, EF, EC and ED are the Fermi energy, con-duction band energy and donor energy level. gD is the degeneracy levelof the conduction band, k is the Boltzmann constant and T is the tem-perature. The equation says that the concentration of free electrons n isequal to the concentration of ionized donors ND+, which is the case forhighly doped semiconductors. The effect of increased ionization energyis a change of the donor energy level which in turn changes the con-centration of ionized donors. By solving this condition graphically likeproposed in [15], the radius dependent EF, EC and ED were determined(Fig. 3a). For this analysis the bandgap energy was assumed to beconstant with radius, which is a fair assumption for the used size ofnanowires [4]. From the fermi energy the concentration of active car-riers can be determined by inserting EF(r) into the left or right handterm in equation (6) (Fig. 3b). Finally it was possible to calculate theresistivity by using the fundamental relationship:

    =ρnqμ

    1(7)

    where µ is the electron mobility. In nanowires, the mobility is mainlyaffected by surface scattering and the crystal orientation. It has beenfound by simulations, that surface scattering only affects nanowireswith radii smaller than 4 nm [30,31]. For nanowires with radii largerthan 7 nm the electron mobility converges to the universal mobilitycurve for planar silicon MOSFETs. A significant influence of crystalorientation is not expected for radii larger than 6 nm [32]. Further-more, there is no conclusive study about charge carrier mobility in si-licon nanowires which clearly states if its larger or smaller than in bulksilicon [24]. Therefore, it was assumed that the only factor influencingthe mobility is the radius dependent charge carrier concentration givenby the donor deactivation effect. The resulting resistivity according tothe dielectric mismatch effect is plotted in Fig. 3c) together with thedata of Fig. 2 versus the electronic radius to account for surface de-pletion by charges trapped in interface states. The general trend of themodel seems to fit qualitatively well to the experimental data, but thesudden increase of resistivity for small nanowires starts already forthicker nanowires than one would expect by just considering surfacedepletion and dielectric mismatch – an observation which is differentthan the reports on P doped SiNWs by Björk [5]. The found shift couldbe due to several effects: 1) the electron mobility in nanowires could beseriously degraded especially for the thinnest nanowires compared tobulk. 2) As only little is known about the dopant incorporation me-chanism during VLS-growth, especially for As-doping, the number ofincorporated atoms could be radius-dependent. 3) The arsenic dopantatoms could segregate at the interface to the native oxide. This wasalready shown to happen by simulation and experiments for silicon andgermanium nanowires doped with boron and phosphorous [33–36],however it is unknown for arsenic.

    Nanowires contacted by pure Ni leads not necessarily exhibitedohmic characteristics. For radii smaller than 15 nm the characteristicsbecame supralinear, thus it was not possible anymore to correctly de-termine the resistivity. Note that those nanowires were not included inFigs. 1–3. It remains unclear whether the reduced contact area und thusthe contact resistance or a possible lowering in the effective donorconcentration and involved Schottky junctions are responsible for thiseffect. The pure Ni electrodes on Si nanowires open up the possibility touse silicidation for improving the contact properties. Silicides have alow resistivity and can withstand high temperatures [37], which madethem attractive for industrial semiconductor devices. Especially Ti-,

    Fig. 3. a) Calculated Fermi energy EF, conduction band energy EC and donor energy level ED versus nanowire radius r according to the dielectric mismatch model fornanowires with a doping concentration ND = 2.6 × 1019 cm−3. b) Concentration of free electrons n calculated from the radius-dependent fermi energy EF for the twonominal doping concentrations. c) Corrected nanowire resistivity ρcorrected versus electronic radius relec. The solid lines represent the resistivity calculated from thedielectric mismatch model for both nominal doping concentrations and show that additional effects are required to match the observed behaviour.

    T. Mauersberger, et al. Solid State Electronics xxx (xxxx) xxxx

    4

  • Co-, W-, Pt- and currently Ni-silicides are commonly used in MOSFETsfor contacting of source-/drain-regions and the gate electrodes. In theclassical MOSFET technology this is achieved by depositing the corre-sponding metal on top of the contacts. A thermal process will then se-lectively silicidize desired Si-regions. In nanowires, a silicidized contactcan be achieved by thermally activated intruding of metal silicide in thenanowire creating a longitudinal heterostructure [19]. This shifts theactive metal–semiconductor junction inside the nanowire and effec-tively reduces the contact area to the cross section area of the silicon/silicide interface. The created interface was shown to be atomicallysharp in other experiments involving nominally intrinsic SiNWs [38]. Inthis contact geometry the effect of Fermi-level-pinning at the interfaceis reduced and the Schottky barrier should only be given by the nominaldifference of metal work function and semiconductor electron or holeaffinity [39]. As the nanowires are still surrounded by a low qualitynative oxide, they should still be prone to surface depletion by chargestrapped in interface states and donor deactivation by dielectric mis-match. After silicidation, the nanowires were measured again and theresistivity data was analyzed using the same procedure as explainedbefore to determine the corrected resistivity and the dielectric mis-match model. It must be noted, that in this case and different to ourdevice setup described above the contacts are now intrusive throughoutthe full nanowire diameter which means that the forced current fromthe outer electrodes is injected through six consecutive Schottky junc-tions. Nevertheless, the current voltage characteristics of the same de-vice became ohmic upon silicidation. The results are plotted in Fig. 4.The resistivities of thin nanowires improved substantially, e.g. a na-nowire with a physical radius of 15 nm contacted by Ti/Ni had re-sistivities of up to 70 mΩcm whereas the resistivity of nanowires withsilicidized contacts of the same radius decreased to 4 mΩcm. With si-licidized contacts, the dielectric mismatch model captures the majorityof the experimental data quite well. The inset of Fig. 4 shows an SEMtop view of a silicidized nanowire with well distinguishable nickel si-licide phases. The nickel-rich silicide attributed to the section adjacentto the nickel contact lead has a larger lattice constant than silicon,leading to a volume expansion of approximately 30% [19]. The leadingphase towards the pristine Si nanowire is assumed to be cubic NiSi2with CaF2 structure with a comparable lattice constant to that of siliconin accordance with [19,40]. To further investigate the contact proper-ties, the contact resistivity was studied next. It can be calculated fromthe absolute contact resistance RC and the contact area AC:

    =ρ R · AC C C (8)

    The contact resistance can be determined from a measurement ofthe total device resistance using equation (1). Usually, determining thecontact area is not trivial as can be seen in Fig. 1 or Fig. 5 a) for na-nowires contacted by a thin metal lead on top of it. Current transportmight not take place uniformly in this contact, rather it will occur nearthe edges of certain geometries. However, Mohney et al. developed atransmission line model to calculate contact resistivities for nanowirescontacted like that by assuming that 75% of the nanowires surface iscovered by evaporated contact leads [41]. For intruded silicide contactsthe contact area is an ellipsoid or circle spanned by the nanowire radius(see Fig. 5b). This contact geometry eliminates the use of a transmissionline model as the current transport is expected to take place uniformlyacross the Si/NiSi2 interface inside the nanowire. The calculated con-tact resistivity versus nanowire radius is shown in Fig. 6a). With in-creasing radius the contact resistivity exponentially decreases down to(1.4 ± 0.2) × 10−11 Ωm2 for the thickest measured nanowire with aradius of around 26 nm. This is close to the lowest measured contactresisitivity to a silicon nanowire so far of 1.2 × 10−11 Ωm2, obtainedfor P-doped VLS-grown NWs with significantly larger nominal dopingconcentration of ND = 9 × 1019 cm−3 [11]. There, evaporated Ti/Aucontacts were used and ρC was determined by the transmission linemodel by Mohney et al [41]. The reason for the extremely low contactresistivities in our nanowires is most probably dopant segregation. Forplanar silicon it was shown that upon silicidation the dopant atoms tendto accumulate at the intruding interface between silicon and the re-spective silicide due to the fact that theýre not or only hardly soluble inthe silicide [42]. This means that a thin interlayer with a high amountof dopant atoms will form at the interface (see Fig. 5b). The Schottkybarrier becomes thinner, allowing tunneling for electrons with energieslying closer to the fermi energy [43]. It is not expected, that the atomsare substitutionally incorporated within the silicon lattice at the usedsilicidation temperatures. However, it has been shown that dopantsshow an important effect on charge transport at the contact interface.Effectively reducing the Schottky barrier (SB) height, dopant segrega-tion makes the metal semiconductor junction more transparent forcharge carriers [44]. For this reason segregated dopants were originallyproposed to reduce the SB height in SB MOSFETs, where the ON-currentis dominated by the barrier [45]. Dopant segregation in nanowires is aversatile instrument to create sharp interfaces, since other methods likeion implantation or switching gases during VLS-growth are difficult insuch geometries. Hereby a method for determining the effective SBheight of intruded segregated Si/silicide junctions is proposed, whichmakes use of the size effect of active doping concentration discussedbefore. By determining the contact resistivity for individual nanowiresof different radii, one can cover a large range of apparent dopingconcentrations albeit only one single nominal doping concentration ispresent. By plotting the natural logarithm of the contact resistivityversus the inverse of the square root of the apparent doping con-centration ND,app one can clearly distinguish at least two different re-gimes (Fig. 6b). For very high doping concentrations, the transportmechanism across the junction is mainly field emission (FE)/tunneling.In this regime, the contact resistivity is determined by the number offree charge carriers in the semiconductor and a huge sensitivity on thedoping concentration is expected [46]. In this regime the contact re-sistivity can be described in the following form:

    ⎜ ⎟⎛⎝

    ⎞⎠

    ρ ~exp ΦNC,FEBn

    D (9)

    Here, ΦBn denotes the effective Schottky barrier height for electronsand ND is the electrically active doping concentration. This concentra-tion is given by the respective resistivity ρapp of the individual nano-wires and an empirical bulk mobility model was used to determine theapparent doping concentration ND,app [14]. From a linear fit to the plotto the experimental data for the highest doping concentrations, one can

    Fig. 4. Corrected nanowire resistivity ρcorrected of silicidized nanowires. Thesolid line shows the dielectric mismatch model. The right hand image show anSEM top view of a silicidized nanowire with corresponding nickel silicidephases.

    T. Mauersberger, et al. Solid State Electronics xxx (xxxx) xxxx

    5

  • extract the effective Schottky barrier height. For the parameters usedhere, this method yields a SB height of 129 ± 7 meV. This value isclose to already reported values around 100 meV for As segregatedCoSi2/bulk-Si junctions [45]. From a certain apparent doping con-centration on, ρC starts to saturate and will stay constant for the mea-sured range of doping concentrations. This is a hint for a change intransport mechanism, probably from field emission to thermionicemission. In between a mixture of both transport mechanisms will takeplace [46].

    4. Conclusions

    Electrical characterization of bottom-up VLS-grown in-situ As-doped SiNWs was shown for the first time. 4-point measurements ofindividual nanowires of different diameters and different dopant pre-cursor flow ratios revealed doping is possible by changing the gas flowsduring growth. An intricate size effect of nanowire resistivity wasfound, mainly attributed to surface depletion by charges trapped ininterface states and donor deactivation by dielectric mismatch. Ni-contacted NWs were silicidized, leading to substantial improvements of

    resistivity and contact properties owing to the special contact geometryand an effect called dopant segregation. By measuring the contact re-sistivity of individual silicidized nanowires of different diameters, alarge range of active doping concentrations could be covered. Byplotting the contact resistivity versus the electrically active dopingconcentration different transport mechanisms across the metal semi-conductor junction could be revealed. An effective Schottky barrierheight of approximately 130 meV was extracted, which supports theassumption of dopant segregation upon silicidation. The found resultshave important implications for scaled devices. For field effect tran-sistors, regions not covered by the gate need to be doped very highly toaccount for donor deactivation. Similarly, changing the dielectric notonly changes the gate capacitance, but also the number of active chargecarriers in the channel. For nanowires, intruded silicide contacts re-present the optimal metal semiconductor junction due to the uniquecontact geometry and the dopant segregation effect, both contributingto substantially improved conductivity and contact properties.

    Acknowledgements

    This work was supported in part by the German ResearchFoundation (DFG) within the Cluster of Excellence Center forAdvancing Electronics Dresden at Technische Universität Dresden andin part by the project ReproNano under Grant WE 4853/1-3.

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    Size effect of electronic properties in highly arsenic-doped silicon nanowiresIntroductionExperimentalResults and discussionConclusionsAcknowledgementsReferences