IEEE TRANSACTIONS ON COMPUTERS, VOL. c-33, NO. 10, OCTOBER 1984

The VLSI Implementation of a Reed-SolomonEncoder Using Berlekamp's Bit-Seral

Multiplier AlgorthmIN-SHEK HSU, IRVING S. REED, FELLOW, IEEE, T. K. TRUONG, MEMBER, IEEE, KE WANG,

CHIUNN-SHYONG YEH, STUDENT MEMBER, IEEE, AND LESLIE J. DEUTSCH

Abstract Berlekamp has developed for the California Insti-tute of Technology Jet Propulsion Laboratory (JPL) a bit-serialmultiplication algorithm for the encoding of Reed-Solomon (RS)codes, using a dual basis over a Galois field. The conventional RSencoder for long codes often requires lookup tables to performmultiplication of two field elements. Berlekamp's algorithm re-quires only shifting and EXCLUSIVE OR operations. It is shown inthis paper that the new dual-basis (255,223) RS encoder can berealized readily on a single VLSI chip with NMOS technology.

Index Terms Bertekamp's bit-serial multiplier, dual basis,Reed-Solomon code, trace, VLSI.

I. INTRODUCTION

A REED-SOLOMON (RS) code is a cyclic symbol error-correcting code. The decoding algorithm for an RS

code can be used to obtain the correct codeword for a varietyof burst types of binary errors that occur during the trans-mission of the codeword through a channel. This error-tolerant property of the RS code makes it useful in manycommunication and computer systems. In particular, a con-catenated Reed-Solomon/Viterbi channel encoding systemhas been adopted both by the European Space Agency (ESA)[1] and JPL [2], [3] for the deep-space downlink.An RS code is a block sequence of Galois field symbols.

Each symbol is a field element in GF(2') where GF(2m)denotes the finite field of 21 binary symbols. This sequenceof symbols can be considered to be the coefficients of apolynomial. The code polynomial C(x) of such a code isC(x) = c0 + clx + + cn_lx'-l where ci E GF(2m).The parameters of an RS code are summarized as follows:m = number of bits per symbol;n-= 2m - 1 = the length of a codeword in symbols;t = maximum number of error symbols that can be

corrected;d = 2t + 1 = design distance;2t = number of check symbols;k = n - 2t = number of information symbols.

Manuscript received December 22, 1982; revised March 8, 1984. This workwas supported in part by the U.S. Air Force Office of Scientific Research underGrant AFOSR-80-015 1, in part by the Department of the Navy Naval Electron-ics Systems Command under Contract N00039-80-C-0641, and in part byNASA under Contract NAS.7-100.

I. -S. Hsu, I. S. Reed, K. Wang, and C. -S. Yeh are with the Department ofElectrical Engineering, University of Southern California, Los Angeles, CA90089.

T. K. Truong and L. J. Deutsch are with the Jet Propulsion Laboratory,California Institute of Technology, Pasadena, CA 91109.

In the JPL design, m = 8, n = 255, t = 16, d - 33,2t = 32, and k = 223. This is the (255, 223) RS code. Thisparticular code is capable of correcting a maximum of16 errors or 32 erasures.The generator polynomial of an RS code is defined by

b+ 2t-1 2t

g(X) = E (x - y) = Egixij=b i=O

(1)

where b is a nonnegative integer, often chosen to be 1, andy is a primitive element in GF(2m). In order to reducethe complexity of the encoder it is desirable to make thecoefficients of g(x) symmetric so that g(x) = x-d- g(1/x).To accomplish this b must be chosen to satisfy 2b + d-2 = 2' - 1. Thus, for the (255,223) RS code, b = 112.

Let I(x) = c2tx2t + c2t,+x2'2t+1 + c,-1x"-1 andP(x) = c0 + clx + + c2t,Ix2' be the informationpolynomial and the check polynomial, respectively. Thenthe encoded RS code polynomial is represented by

C(x) = I(x) + P(x). (2)To be an RS code C(x) must be also a multiple of g(x). Thatis, C(x) = q(x)g(x). The encoding process is to find P(x)from I(x) and g(x). This is achieved by the division algo-rithm. Dividing I(x) by g(x) yields

I(x) = q(x)g(x) + r(x). (3)

If one lets P(x) =-y(x), then q(x)g(x) = I(x) - y(x) =1(x) + P(x) = C(x). Hence, C(x) is given by (2) whereP(x) = -r(x).The RS encoder performs the above division process to

obtain the check polynomial P(x). Fig. 1 shows the structureof a t-error correcting RS encoder over GF(2m). In Fig. 1 Rifor 0 < i c 2t - 2 and Q are m-bit registers. Initially, allregisters are set to zero, and both switches (controlled by acontrol signal SL) are set to position A.The information symbols c.,.. ,C2 are fed into the

division circuit of the encoder and also transmitted from theencoder one-by-one. The quotient coefficients are generatedand loaded into Q register sequentially. The remainder coef-ficients are computed successively. Immediately after C2, isfed to the circuit, both switches are set to position B. Atthe very same moment C2,1. is computed and transmitted.Simultaneously, ci is computed and loaded into registerRi for0 c i 2t - 2. Next C2,.2. , c0 are transmitted from the

0018-9340/84/1000-0906$01 .00 X 1984 IEEE

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HSU et al.: VLSI IMPLEMENTATION OF REED-SOLOMON ENCODER

JSLFig. 1. A structure of a t-error correcting RS encoder.

encoder one-by-one. C2J-2,* ' *, c0 retain their values becausethe content of Q is set to zero when the upper switch is atposition B.The complexity of the design of an RS encoder results from

the computation of the products zgi for 0 < i c 2t - 1.These computations can be performed in several ways [4].Unfortunately, none of them is suited to the pipeline process-ing structures usually seen in VLSI design. Recently,Berlekamp [5] developed a bit-serial multiplier algorithmthat has the features needed to solve this problem. In thispaper Berlekamp's method is applied to the design of a(255, 223) RS encoder, which can be implemented on a singleVLSI chip.

II. MATHEMATICAL PRELIMINARIES

In order to understand Berlekamp's multiplier algorithmsome mathematical preliminaries are needed. Toward thisend the mathematical concepts of the trace and a com-plementary (or dual) basis are introduced. For more detailsand proofs see [4], [5].

Definition 1: The trace of an element /3 belonging toGF(pm), the Galois field of pm elements, is defined asfollows:

mn-l

Tr(/3)= E pk. (4)k=O

In particular, for p = 2,rn-i

Tr(,B)= , (03)2kk=O

The trace has the following properties:1) [Tr(,/)]P = /3 + lP + * + pPm-l = Tr(O8) where /3

GF(pm). This implies that Tr(,3) e GF(p), i.e., the trace is inthe ground field GF(p);

2) Tr(,B + r) = Tr(/3) + Tr(r) where /3, r E GF(pm);3) Tr(c,3) = cTr(,3) where c E GF(p);4) Tr(l) m(mod p).Definition 2: A basis {,mj} in GF(pm) is a set of m linearly

independent elements in GF(pm).Definition 3: Two bases {,uj} and {Ak} are said to be com-

plementary or the dual of one another if

Tr(jAk) = {0ifj = k

j k.

The basis {,ij} is called the original basis, and the basis {Ak}is called the dual basis.

Lemma: If a is a root of an irreducible polynomial ofdegree m in GF(pm), then {ak} for 0 ' k . m - 1 is a basisof GF(pm). The basis {ak} for 0 ' k ' m - 1 is called thenormal or natural basis of GF(pm).Theorem 1 (Theorem 19 in [4]): Every basis of a Galois

field over GF(2) has a complementary basis.Corollary 1: Suppose the bases {,j} and {Ak} are com-

plementary. Then a field element z can be expressed in thedual basis {Ak} by the expansion

m-l m-1

Z = E ZkAk = E Tr(z, k)Akk=O k=O

(6)

where Zk = Tr(Zplk) is the kth coefficient of the dual basis.Proof: Let z = zoAo + zjAk + + z, 1A ,-. Multi-

ply both sides by ak and take the trace. Then by Definition 3and the properties of the trace

m-( (Tr(zak) = Tr I zi (Aillk) = Zk -

i=OQ.E.D.

This corollary provides a theoretical basis for the new RSencoder algorithm.

III. BERLEKAMP'S BIT-SERIAL MULTIPLIER ALGORITHMOVER GF(2m)

A simple example is used to illustrate Berlekamp's newbit-serial multiplier algorithm. Consider a (15, 11) RS codeover GF(24). For this code, m = 4, n = 15, t = 2,d = 2t + 1 = 5, and n - 2t = 11 information symbols.Let a be a root of the primitive irreducible polynomialf(x) = x4 + x + 1 over GF(2). a satisfies a'15 = 1. Anelement z in GF(24) is representable by 0 or a1 for somej, 0 ' j ' 14. z can be represented also by a polynomial ina over GF(2). This is the representation of GF(24) in thestandard basis {ak} for 0 ' k ' 3. That is, z = uo + u,a +U2a2 + U3a3 where Uk E GF(2) for 0 ' k ' 3.

In Table I, the first column is the index or logarithm of anelement in base a. The logarithm of the zero element isdenoted by an asterisk. Columns 2-5 show the 4-tuples of thecoefficients of the elements expressed as polynomials.The trace of an element z in GF(24) is found by

Definition 1 and the properties of the trace to be

Tr(z) = uoTr(l) + u,Tr(a) + u2Tr(a2) + U3Tr(a3)

where Tr(l) 4 (mod 2) = 0, Tr(a) = Tr(a2) a +a2 + a(4 + a8 = 0, and Tr(a3) = a3 + a6 + a9 + a2= 1.Thus, Tr(z) = U3. The trace element ak in GF(24) is listed incolumn 3 of Table I.By Definition 2 any set of four linearly independent

elements can be used as a basis for the field GF(24). To findthe dual basis of the standard basis {fa} in GF(24) let afield element z be expressed in dual basis {A0, Al, A2,A3}.From Corollary 1 the coefficients of z are Zk = Tr(zak) for0. k ' 3.

Let z = a" for some i,0 i c 14. Then Zk = Tr (a'+k),for 0 ' k . 3. The coefficient Zk of an element z in the dualspace can be obtained by cyclically shifting the trace column

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IEEE TRANSACTIONS ON COMPUTERS, VOL. c-33, NO. 10, OCTOBER 1984

TABLE IREPRESENTATIONS OF ELEMENTS OVER GF(24) GENERATED BY a4 = a +

Power Elements in Elements inj Normal Base TR(a3) Dual Base

a3a2ala0 ZoZ1Z2Z3* 0000 0 00000 0001 0 01 A3I 0010 0 0010 A22 0100 0 0100 A3 1000 1 10014 0011 0 00115 0110 0 01106 1100 1 11017 1011 1 10108 0101 0 01019 1010 1 101110 0111 0 011111 1110 1 111112 1111 1 111013 1101 1 110014 1001 1 1000 AO

in Table I upward by k positions where the first row is ex-cluded. These appropriately shifted columns of coefficientsare shown in the last four columns of Table I. In Table Ithe elements of the dual basis AO, A1, A2, A3 are underlined.Evidently, A0 = a'14, A1 = a2, A2 = a, and A3 = 1 are thefour elements of the dual basis.

In order to make the generator polynomial g(x) symmetricb must satisfy the equality 2b + d - 2 = 2' - 1. Thus,b = 6 for this code. The y in (1) can be any primitiveelement in GF(24). In this example let y = a. Thus, thegenerator polynomial is given by

g(x) = Hl (x - ac) = E glxj=6 i=o

where go = =4 1, gl = g3 = aC3, and g2 = a.

In Berlekamp's multiplier algorithm the fixed multipliergi, for 0 ' i < 3, are expressed as powers of primitiveelement a or in standard basis. The multiplicand z, a fieldelement, is assumed to be represented in the dual basis {Ak}.That is, z = ZoAO + zIAI + z2A2 + z3A3 where Zk = Tr(zak)for 0 < k c 3. The final product zgi is also represented inthe dual basis {Ak}, for 0 < i < 3. That is, zgi has the form

3

zgi Ti (z)Ak (8)k=0

where Jjk)(z) = Tr(zgiak) is to be computed. Since g3 = g1,only zg0, zgl, and Zg2 are computed.

In Berlekamp's algorithm the computation of T(k)(Z) is per-

formed recursively on k for 0 k 3. Initially, for k = 0,

-T°(z)- Tr (Zgo) ~. T z° ZO-T(l°(z)

=

Tr (zgl)=

Tr (za3)= z3 (9)

TT')(z) [Tr (zg2) [Tr (za) J Zil,where Tr(zac) = Tr((zoA0 + z1Aj + z2A2 + z3A3)ai) = zj for

0 < j c 3. Equation (9) can be expressed in a matrix formas follows:

[T°)(z)- [1 0 0 01[zolT(°)(z) = 0 0 0 1 z,

T2)(z)J [0 1 0 0J Z2

L3J

(10)

The above matrix is the 3 x 4 binary mapping matrix of themultiplication.To compute T(k)(z) for k > 0, observe that T(k)(Z) =

Tr((az)giakl) = T(k-)(az). Hence, T(k)(z) is obtained fromTIk-i)(z) by replacing z by y = az. Let az = y = yoAo +YIAI + Y2A2 + y3A3 where Ym = Tr(yam) = Tr(za'm+l) for0 cm- < 3. Then T(k) is obtained from TVk-) by replacing zoby yo = Tr(za) = zl, z1 by Yi = Tr(za2) = Z2, Z2 by Y2 =Tr(za3) = z3 and Z3 by y3 = Tr(za 4) = Tr(z(a + 1)) =zo + z1-To recapitulate zgi = TVo)Ao + TP)2A, + T2)A2 + T13)A3

where 0 < i < 3 and z = ZOAO + zIAI +. z2A2 + z3A3 canbe computed by Berlekamp's bit-serial multiplier algorithmas follows.

1) Initially fork = 0, compute TO()(z), T(°)(z), and T(°)(z) by(10). Also, TT3)(z) = T()(z).

2) For k = 1, 2, 3, compute T(k)(z) by

T(k) (z) T(k- 1)(y)

where 0 < i < 3 and y = az = yOAO + yIAI + y2A2 + y3A3with yo = zi, y1 = Z2, Y2 = Z3, andy3 = Z0 + ZI = Tf whereTf = z0 + z, is the feedback term of the algorithm.The above example illustrates Berlekamp's bit-serial

multiplier algorithm. This algorithm requires shifting andXOR operations only. The same procedure extends similarlyto the design of a (255, 223) RS encoder over GF(28).

(7)IV. A VLSI ARCHITECTURE OF A (255, 223) RS ENCODER

In this section an architecture is designed to implement a(255, 223) RS encoder using Berlekamp's multiplier algo-rithm. This architecture can be realized quite readily on asingle NMOS VLSI chip.

Let GF(28) be generated by a where a is a root of aprimitive irreducible polynomial f(x) = x8 + X7 + X2 +x + 1 over GF(2). The representations of this field in boththe standard basis and its dual basis can be found in [6]. Thedual basis {Ao, A,,kl * , A7} of the standard basis is the orderedset la99 ,

197 ,a203 C 202 a201 c 200, a199 ,a100}Two binary matrices, one for the primitive element

A = all and the other for y = a, were computed. It wasfound that the binary mapping matrix for y = all had asmaller number of l's. Hence, this binary mapping matrixwas used in the design. By (1) the generator polynomial g(x)of the (255, 223) RS code with b' = 112 is g0 + glx +

+ g32x32 where g0 = g32 = 1, g1 = g31 =a24 , g2 =

30= 59, g3 = 929 a, 4 =g28 = a4, g5 = = a43,126 251 97

g6 =g26 =a ,g7 = g25 = a ,g8g 24 a 923= a30, g0 = 22 = aC3, g11 = 21= a213, gl2 = 20=

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HSU et al.: VLSI IMPLEMENTATION OF REED-SOLOMON ENCODER

ag50913 = gl9 = a66, g14 = 918 = a170, 915 = g17 a 5, and= a24.The binary mapping matrix is computed from gi and is

shown in the Appendix. The feedback term Tf in Berlekamp'salgorithm is computed to be

Tf = Tr(a8z) = Tr((a7 + ca2 + a + l)z)

ZO + ZI + Z2 + Z7. ( 1)In the following an architecture is designed to realize a

(255,223) RS encoder using the above parameters andBerlekamp's algorithms. An overall block diagram of thisencoder is shown in Fig. 2. In Fig. 2 VDD and GND arepower pins. CLK is a clock signal, which in general is aperiodic square wave. The information symbols are fed intothe chip from the data-in pin DIN bit-by-bit. Similarly, theencoded codeword is transmitted out of the chip from thedata-out pin DOUT sequentially. The control signal LM(load mode) is set to 1 (logic 1) when the information sym-bols are loaded into the chip. Otherwise, LM is set to 0.

Fig. 3 shows the block diagram of a (255, 223) RS encoderover GF(28) using Berlekamp's bit-serial multiplier algo-rithm. The input data andLM signals are synchronized by theCLK signal, while the operations of the circuit and outputdata signal are synchronized by two nonoverlapping clocksignals 01 and 02 generated in the circuit. To save spacedynamic registers [7] are used in this design. The timingdiagram of CLK, 41, 02, LM, DIN, and DOUT signals areshown in Fig. 4. The delay of DOUT with respect to DIN isdue to the input and output flip-flops.The circuit in Fig. 3 is divided into five units. The circuits

in each unit are discussed in the following.1) Product Unit: The product unit is used to compute

Tf, T31, * *, To. This circuit is realized by a programmablelogic array (PLA) circuit [7]. Since To = T31, T1 = T30, * ,

T15 = T17, only Tf, T31,* * *, T17, and T16 are actually imple-mented in a standard PLA circuit. To, * *, T15 are connecteddirectly to T31, * , T17, respectively. A standard PLA circuithas the advantage over other circuits of being easy toreconfigure.

2) Remainder Unit: The remainder unit is used to storethe coefficients of the remainder during the division process.In Fig. 3 Si for 0 < i c 30 are 8 bit shift registers withreset. Addition in the circuit is a modulo 2 addition or theEXCLUSIVE OR operation. While c32 is being fed to the circuitc31 is being computed and trangmitted sequentially from thecircuit. Simultaneously, ci is computed and then loaded intoSi for 0 < i ' 30. Then c30,.*. , c0 are transmitted out ofthe encoder bit-by-bit.

3) Quotient Unit: In Fig. 3 Q is a 7 bit shift register withreset. R represents an 8 bit shift register with reset andparallel load. The parallel load operation of R is controlledby the LD signal. R and Q store the currently operatingcoefficient and the next coefficient of the quotient poly-nomial, respectively. zi for 0 < i c 7 are loaded into Revery eight clock cycles. Immediately after all 223 informa-tion symbols are fed into the circuit, the control signal SLchanges to logic 0. Thenceforth the contents of Q and R arezero so that the check symbols in the remainder unit sustaintheir values.

VDD

CLKDIN ENCODER _ DOUT

LM _ CHIP

tGND

Fig. 2. The symbolic diagram of an RS encoder chip.

'~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Idi d

I0

0 UNITs

REMAINDER UNIT

Fig. 3. The block diagram of an RS encoder.

DIN 1iE\i\/IT'JiT N. BTTT%

CLK JL1-F

12 1..

START

B~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~i BIlTDOUT j..NUAs

Fig. 4. The signals of DIN, LM, CLK, 41, 02, START, and DOUT.

4) I1O Unit: This unit handles the input/output opera-tions. In Fig. 3 both Fo and F1 are flip-flops. A pass transistorcontrolled by 01 is inserted before F1 for the purpose ofsynchronization. Control signal SL selects whether a bit of aninformation symbol or a check symbol is to be transmitted.

5) Control Unit: The control unit in Fig. 3 generates thenecessary control signals. This unit is further divided intothree parts. The first part of the control unit is used to gener-ate two nonoverlapping clock signals 4, and 42 from CLK.The two-phase clock generator circuit in [7] is used in thisdesign. The second part is a used to generate control signalsSTART and SL. The logic diagram of this part of the controlunit is shown in Fig. 5. The third part is a divide-by-8 binarycounter. This counter generates theLD signal to load zi 's intoR. The START signal resets all registers and the binary coun-ter before the encoding process begins.The circuit accepts one bit of an information symbol, trans-

mits one bit of the encoded code, and performs one step ofBerlekamp's algorithm in one time unit. Immediately after allof the information symbols are received by the encoder, thecheck symbols are available in the remainder unit. After

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IEEE TRANSACTIONS ON COMPUTERS, VOL. C-33, NO. 10, OCTOBER 1984

LMt START

r T SL

01 02 01

Fig. 5. A logic diagram of the circuit for generating controlsignals START and SL.

Fig. 6. Layout of the (255, 223) RS encoder chip.

TABLE 11THE PRIMARY MODIFICATIONS OF THE ENCODER CIRCUIT IN FIG. 2 NEEDED TO CHANGE A PARAMETER

The value usedParameter for the circuit New

to be changed in Fig. 2 value The circuits of Fig. 2 that require modification

I) Generator Polynomial (8) g(x) The connections of the PLA in the product unit needto be changed.

2) The Finite Field Used GF(2') GF(2') All registers are m-bit resistors, except Q is an (m - 1)-bit register. A divide-by-m counter is used.

3) Error-Correcting Capability 16 t 2t - 2 shift registers are required in the remainderunit. (The generator polynomial is also changed.)

4) Number of Information Symbols 223 k None is changed since k is implicitly contained in thecontrol signal LM.

transmitting the check symbols, the encoder is ready toprocess the next codeword.

Since a codeword contains 255 symbols, the computationof a complete encoded codeword requires 255 "symbolcycles." A symbol cycle is the timeinterval needed to executea complete cycle of Berlekamp's algorithm. Since a symbolhas 8 bits, a symbol cycle contains 8 bit cycles. Here a bitcycle is defined to be the time interval needed to execute onestep of Berlekamp's algorithm. In this design a bit cyclerequires one period of the clock cycle.The layout of this (255, 223) RS encoder is shown

in Fig. 6. The entire circuit was simulated on a general-purpose computer by using ESIM (a logic-level circuit simu-

lation program) and SPICE (a transistor-level circuitsimulation program) [8]. The completed circuit requiresabout 3000 transistors, while a similar JPL design requires 30CMOS IC chips [5]. This RS encoder design will be fabri-cated and tested in the near future. It is estimated that aclock cycle could be as small as 0.2 ks using 5 gm NMOStechnology. In conclusion it should be noted that layout usedCaeser program [9].

V. CONCLUDING REMARKS

A VLSI structure is developed for a Reed-Solomon en-coder using Berlekamp's bit-serial multiplier algorithm. Thisstructure is both regular and simple.

HSU et al.: VLSI IMPLEMENTATION OF REED-SoLOMoN ENCODER 9

The circuit in Fig. 2 can be modified easily to encode anRS code with parameters other than those used in Section IV.Table II shows the primary modifications needed in thecircuit to change a given parameter.

APPENDIX

[7] C. Mead and L. Conway, Introduction To VLSI Systems. Reading, MA:Addison-Wesley, 1980.

[8] L. W. Negal and D. 0. Pederson, "SPICE-Simulation program withintegrated circuit emphasis," Electron. Res. Lab., Univ. California,Berkeley, CA, Memo. ERL-M382, Apr. 12, 1973.

[9] J. Ousterhout, "Editing VLSI circuits with Caeser," Univ. California,Berkeley, CA, Apr. 21, 1982.

The binary mapping matrix for v =RS encoder is given by

a" of

1 0 0 0 0 0 0 01 1 0 1 1 0 1 01 1 1 1 1 1 1 0

0 1 1 0 1 0 1 00 0 O 0 1 0 0 00 1 1 1 1 0 0 01 0 1 1 0 0 0 01 1 0 1 0 1 1 11 0 0 0 0 1 1 01 0 1 0 0 1 0 10 O 0 1 0 0 0 00 1 0 1 0 1 0 00 1 1 0 1 1 O000o1 1 0 1 0 1 01 1 0 1 0 1 0 10 0 0 0 0 1 0 01 0 0 0 1 1 1 0

f the (255, 223)

zo

Z2Z3Z4Z5Z6

REFERENCES

[1] H. F. A. Reefs and A. R. Best, "Concatenated coding on a spacecraft-to-ground telemetry channel performance," in Proc. ICC 81, Denver, CO,1981.

[2] J. Odenwader et al., "Hybrid coding system study final report," LinkabitCorp., NASA CR114, 486, Sept. 1972.

[3] M. Perlman and J. J. Lee, "Reed-Solomon encoder-Conventionalversus Berlekamp's architecture," Jet Propulsion Lab., Pasadena, CA,Memo. 3610-81-119, July 10, 1981.

[4] P. J. MacWilliams and N. J. A. Sloane, The Theory Of Error-CorrectingCodes. Amsterdam: North-Holland, 1978.

[5] E. R. Berlekamp, "Bit-serial Reed-Solomon encoders," IEEE Trans.Inform. Theory, vol. IT-28, no. 6, pp. 869-874, Nov. 1982.

[6] T. K. Truong, L. J. Deutsch, 1. S. Reed, 1. -S. Hsu, K. Wang, and C. -S.Yeh, "The VLSI design of a Reed-Solomon encoder using Berlekamp'sbit-serial multiplier algorithm," Jet Propulsion Lab., Pasadena, CA, TDARep. 42-77, pp. 72-86, Aug. 15, 1982.

In-Shek Hsu was born in Hsin-Chu, Taiwan, China,on April 5, 1956. He received the B.S.E.E.and M.S.E.E. degrees from the National TaiwanUniversity in 1978 and 1980, respectively, and isnow working toward the Ph.D. degree in theDepartment of Electrical Engineering, Universityof Southern California, Los Angeles, CA.From 1980 to 1981, he was an Associate Engineer

in the Electronic Research and Service Organiiation,Hsin-Chu, Taiwan. He was responsible for inte-grated circuit design. His research interests include

the areas of VLSI, communication, integrated circuit design, process, signalprocessing, and electromagnetic theory.

Irving S. Reed (SM'69-F'73), for a photograph and biography, see p. 360 ofthe April 1984 issue of this TRANsAcrboNs.

T. K. Truong (M'82), for a photograph and biography, see p. 360 of theApril 1984 issue of this TRANSAcTIONS.

Ke Wang was born in Beijing, China, in 1938. He received the B.S. degreein electrical engineering from Chao Tung University, China, in 1952.From 1980 to 1982 he was a Visiting Scholar in the Department of Electrical

Engineering, University of Southern California, Los Angeles, CA. He is nowworking at the Institute of Space Technology, Beijing. His areas of interestinclude VLSI, coding theory, and communication systems.

Chiunn-Shyong Yeh (S'79), for a photograph and biography, see p. 360 of theApril 1984 issue of this TRANSACTIONS.

Leslie J. Deutsch was born in Inglewood, CA, on

April 15, 1955. He received the B.S. degreein mathematics from the California Institute ofTechnology (Caltech), Pasadena, CA, in 1976,and the M.S. and Ph.D. degrees in theoreticalmathematics from Caltech in 1979 and 1980,respectively, specializing in harmonic analysis.From 1980 to the present, he has been employed

by the Jet Propulsion Laboratory, Califormia Instituteof Technology. There, he has worked on problemsrelated to coding, communications systems, and

signal processing. He is currently the Supervisor of the Digital Signal Process-ing Research Group at the Jet Propulsion Laboratory. In this capacity, he leadsresearch efforts in communications, radar processing, and algorithms forvery large scale integrated circuits (VLSI). He is also employed by DeutschResearch Laboratories where he participates in the design of digital audiotone synthesizers.

ToT,T2T3T4T5T6T7T8

TioT,,T12T13T,4T15T16

,911