spad sensor characterization and production testing · results in a large output voltage swing...
TRANSCRIPT
SPAD Sensor Characterization and
Production Testing
Dr. Daniel Van Blerkom
Forza Silicon
April 9, 2019
2
Forza offers a complete end-to-end suite of services to transition a custom
design from prototype engineering samples to volume production.
Custom IC Design and Production Services
3
Forza Design Services – Image Sensors
• Automotive Imaging
• Broadcast & Digital Cinematography
• High Speed Analysis
• Industrial & Machine Vision
• Medical Imaging
• Military Imaging
• Security & Surveillance
• High Speed Data Communication
4
Forza Design Services – Image Sensors
• Automotive Imaging
• Broadcast & Digital Cinematography
• High Speed Analysis
• Industrial & Machine Vision
• Medical Imaging
• Military Imaging
• Security & Surveillance
• High Speed Data Communication
High Dynamic Range Sensors
140 dB Linear Dynamic Range
5
1. Availability of foundry processes with qualified SPAD devices
2. Continued improvement and size reduction of SPADs
3. New time-of-flight applications in consumer and automotive markets
Interest in SPAD based time-of-flight sensors
Lee et al, IEEE JSTQE 2018
6
1. Availability of foundry processes with qualified SPAD devices
2. Continued improvement and size reduction of SPADs
3. New time-of-flight applications in consumer and automotive markets
Interest in SPAD based time-of-flight sensors
Lee et al, IEEE JSTQE 2018
7
1. Availability of foundry processes with qualified SPAD devices
2. Continued improvement and size reduction of SPADs
3. New time-of-flight applications in consumer and automotive markets
Interest in SPAD based time-of-flight sensors
Lee et al, IEEE JSTQE 2018
8
• SPAD (Single photon avalanche diode) Biased above breakdown voltage
Single photon creates cascade of electrons
Results in a large output voltage swing
• Non-idealities Quenching & recharge required after firing – leads
to “dead time”
Dark count rate (DCR)
• SPAD readout SPAD pulse arrival time converted by a Time-to-
Digital Converter (TDC)
• SPAD sensors targeted for direct TOF
SPADs and SPAD readouts
9
• Several foundries offer SPAD and AFE as a device/circuit combination
• Often the SPAD and AFE are combined into one layout cell
• Dense arrays of SPADs need custom layout, arrangement of AFEs
SPAD diode & the Analog Front End
SPAD pixel quenching
• Passive quenching with disabling
• Bias is beyond breakdown
• Tunable quench resistance
• Individual SPADs can be disabled
• The output is a true digital pulse
containing timing information
20
SPAD_Out
VSPADOFFVHV
Anode
En En
En
VDDPIX
En
VQUENCH
ST industrial 130nm CMOS SPAD - 2013
• Pixel only containing passive
quenching circuit
9
Metric IMG175SPAD Value (@ 60°C)
[SPIE Photon Counting
Conference]
VHV0 13.8V
DCR Median ~1k cps
PDP 3.1% (850nm)
Fill Factor 6% 21.6%
Pulse Width 25ns
Max Count Rate 37Mcps
Jitter 120ps FWHM, 870ps FW1%M
Current per Pulse 0.08pA
After-Pulsing <0.1%
Cross-Talk <0.01% (isolated SPAD)
Pelligrini, ISSW 2018
10
Photo-generated electron triggers avalanche current pulse
Circuit quenches avalanche, then re-establishes bias across SPAD
Output pulse is squared-up and buffered
SPAD operation
time
time
Vspad
Vout
Avalanche
Quench / Recharge
11
Basic SPAD / TDC operation
START
SPAD 4
SPAD 3
SPAD 2
SPAD 1
CLK
TDC COUNT 0 1 2 3 4 5 6
1
2
1. START pulse initiates laser pulse & TDC counter
2. Returning photon causes SPAD to avalanche
3. SPAD pulse output stops and latches TDC counter
12
Histogram of photon arrivals
ttof
Multiple pulses are sent, and a histogram of arrivals is
created; the peak return indicates distance to object.
13
SPAD performance improvements
Figure 1. Sensor block diagram
Figure 2. Sensor photomicrograph Figure 3. Dual clock DNL and
calibration for RO to clock transition
Figure 4. Dual clock INL and calibration for
RO to clock transition
Table 1. State-of-the-art comparison table
Figure 5. 252 × 128 Flash 3D image using PH
with intensity superimposed. Image captured in 8
exposures due to limited illumination angle.
Figure 6. Non-linearity of physical
target measurement up to 50 m using
6 × 128 subset of main array.
252 × 144SPAD ARRAY
10.
2 m
m
21.6 mm
144 × 6ADDRESS
LATCH& TDCS
72 PHR BLOCKS
PVT PLL
CLOCK PLL
144 × 6ADDRESS
LATCH& TDCS
DN
L (
LS
B)
Parameter This work [1] [2] [3]
Technology 180 nm 180 nm 130nm CIS 150 nm
Sensor
resolution252 × 144 32 × 1(1) 512 × 1(1) 64 × 64(1)
Pixel pitch (µm) 28.5 25 23.78 60
Fill factor (%) 28 70 49.31 26.5
DCR @(VEB)
(cps/µm2)0.62 (5V) 6 (3.3V) N/A 57 (3V)
Integrated
histogrammingPer-pixel None Per-pixel None
No. of TDCs 1728 32 512 4096
TDC area (µm2) 4200 31000 (2) 5400(2)N/A
Distance range
(m)2-50 128 N/A 367-5862
(4)
Accuracy (Non-
linearity) (m)0.08 0.37
(3) N/A 1.5-35(4)
(1)Macro pixel resolution.
(2) Estimated from paper.
(3)Measured at 100m.
(4) Emulated results.
2018 Symposium on VLSI Circuits Digest of Technical Papers 70
Figure 1. Sensor block diagram
Figure 2. Sensor photomicrograph Figure 3. Dual clock DNL and
calibration for RO to clock transition
Figure 4. Dual clock INL and calibration for
RO to clock transition
Table 1. State-of-the-art comparison table
Figure 5. 252 × 128 Flash 3D image using PH
with intensity superimposed. Image captured in 8
exposures due to limited illumination angle.
Figure 6. Non-linearity of physical
target measurement up to 50 m using
6 × 128 subset of main array.
252 × 144SPAD ARRAY
10.2
mm
21.6 mm
144 × 6ADDRESS
LATCH& TDCS
72 PHR BLOCKS
PVT PLL
CLOCK PLL
144 × 6ADDRESS
LATCH& TDCS
DN
L (
LS
B)
Parameter This work [1] [2] [3]
Technology 180 nm 180 nm 130nm CIS 150 nm
Sensor
resolution252 × 144 32 × 1(1) 512 × 1(1) 64 × 64(1)
Pixel pitch (µm) 28.5 25 23.78 60
Fill factor (%) 28 70 49.31 26.5
DCR @(VEB)
(cps/µm2)0.62 (5V) 6 (3.3V) N/A 57 (3V)
Integrated
histogrammingPer-pixel None Per-pixel None
No. of TDCs 1728 32 512 4096
TDC area (µm2) 4200 31000
(2)5400
(2)N/A
Distance range
(m)2-50 128 N/A 367-5862(4)
Accuracy (Non-
linearity) (m)0.08 0.37
(3) N/A 1.5-35(4)
(1) Macro pixel resolution. (2) Estimated from paper.(3)Measured at 100m. (4) Emulated results.
2018 Symposium on VLSI Circuits Digest of Technical Papers 70
Henderson
et al 2019 Lindner et al 2018
Perenzoni et al 2017
Process 40nm/90nm 0.18 um 0.15 um Array Size 256 x 256 252 x 144 64 x 64 Pixel Pitch 9.2 um 28.5 um 60 um
Fill Factor 51% 28% 26.5% DCR @ RT 20 Hz 195 Hz 6.8 kHz
14
SPAD Sensor Clock Management
PLLFB CLK
TDC
TDC
TDC
TDC
REF CLK
• Clock skew and jitter management is critical to
accurate time measurements. SPAD to SPAD variations
Channel to channel variations
• Build symmetrical clock trees to equalize skew on all
branches.
15
• SPAD analog and digital supplies have large
current spikes, due to low on-chip clock skew.
• Aggressive clock gating to control power
dissipation causes large supply current shifts.
Characterization challenge – Power supply management
PLLFB CLK
TDC
TDC
TDC
TDC
REF CLK
16
• The SPAD high voltage bias is critical to performance Too low: PDP degradation, some SPADs won’t avalanche
Too high: DCR increase, reliability?
• Leakage on high-voltage supply can cause large on-chip power dissipation
• ESD protection of high-voltage supply needs care
• Power-on sequence of high-voltage & low-voltage supplies is critical to avoid
high voltage leakage onto low-voltage gates & forward biasing junctions.
Characterization challenge – High voltage bias
17
Testing under DC illumination can reveal a lot about SPAD performance
Characterization - CMOS imager vs. SPAD sensor
CMOS Image Sensor SPAD Sensor
Dark Image Dark Current DSNU FPN
Read Noise
DCR DCR non-uniformity VHV bias sensitivity
Illuminated image QE
PRNU Conversion Gain
PDP
PDP non-uniformity After-pulsing
Saturated Image Full-well Dead Time
Spatial / Temporal Modulated Light
MTF
TDC Linearity
18
• Enable only one SPAD at a time to look at distribution of parameters.
Characterize individual SPADs in array
19
• DCR histogram can be captured
on each SPAD in array.
• DCR distribution often shows a
long “tail”.
• Temperature and high voltage
excess bias makes tail worse.
Dark count rate (DCR)
65C 95C
20
0
50
100
150
200
250
2 4 6 8 10 12 14 16 18 20 22 24
Co
un
ts
Interarrival Time (nsec)
Histogram
• Under saturated conditions, we plot inter-arrival times of SPAD pulses
• Minimum inter-arrival time indicates dead time
• Ideal Poisson statistics shown as reference
Dead time
0
1
1 51 101 151 201 251 301 351 401 451 501
Time
Saturated SPAD firing sequence
Poisson statistics
Saturated measurement
Dead
time
21
• After-pulsing can be estimated from deviation from Poisson statistics
• Can also be seen in pulse response histogram
After-pulsing
Lee et al, IEEE JSTQE 2018
22
• Plotting response of SPAD to high voltage supply shows on-set of
avalanche at Vbd.
• Distribution of Vbd is also critical to setting proper level, to make sure all
SPADs respond.
High-voltage dependence
14.8 15 15.2 15.4 15.6 15.8 16 16.2 16.4 16.6
Series1
SP
AD
firin
g r
ate
Vbd
23
• Photon Detection Probability Requires calibrated light source & monochrometer
Non-uniformity of PDP can also be measured
• Cross-talk Possible if neighboring SPADs can be enabled and read out separately
Cross-talk will appear as correlation between pulses
Measuring other key parameters
time
time
SPAD
firing
SPAD
firing
24
To test the time-stamping functionality,
a triggered pulsed laser can be used.
By sweeping the delay between the
start edge and the laser pulse, the
timing accuracy of the sensor can be
measured.
Significant jitter can be accumulated in
the test system, which can corrupt the
measurements.
Dynamic Measurement
25
• Very thorough testing on initial lots Dark, Illuminated, and Saturated frames
High voltage sweep
Temperature sweep
Sweep pulse delay to test TOF response
• Test each SPAD to determine DCR
distribution, yield.
• Remove tests for later lots as yield stabilizes,
to optimize test cost & throughput. Sample wafers for complete test to track process
Production Testing – how much to test?
Defect
spec
26
• Collect data in multiple modes Illumination conditions, high voltage bias
• Save all the data
• Package different grades to build statistics
• Correlate to final package test results Use same test system for wafer & final test
Wafer Testing – Optical test for SPADs
12” Fully Automated Wafer Probe w/
Flexible Optical Fixture Configuration
27
• Defining the pixel defect criteria is critical to yield
• For traditional imaging applications Human perception of image quality drives defect criteria
Process yield may not be sufficient to meet cost goals
• TOF applications are unlike traditional imaging More like machine vision – can potentially tolerate defects
Algorithms can be designed to be tolerant to defects
• Requires modeling of system with defects & non-idealities
Alignment on Specifications
Thank You!
Questions?