Spartan II Features

Plentiful logic and memory resources– 15K to 200K system gates (up to 5,292 logic cells)

– Up to 57 Kb block RAM storage Flexible Input/Output (I/O) interfaces

– From 86 to 284 I/Os

– 16 signal standards Advanced 0.25/0.22um 6-Layer Metal Process High performance

– System frequency as high as 200 MHz Advanced Clock Control with 4 Dedicated Delay Lock Loops

(DLLs) Unlimited Re-programmability Fully Peripheral Component Interface (PCI) Compliant

Spartan-II Top-level Architecture

• Configurable logic blocks– Implement logic here!

• I/O Blocks (IOBs)– Communicate with other

chips

– Choose from 16 signal standards

• Block Random Access Memory (RAM)– On-chip memory for higher

performance

Spartan-II Top-level Architecture

• Clocks and delay locked loops– Synchronize to clock on and

off chip

• Rich interconnect resources – Three-state internal buses

• Power down mode– Lower quiescent power

CLB Slice (Simplified)• 1 Configurable Logic Block

(CLB) holds 2 slices• Each slice contains two sets

of the following:– Four-input Look-Up Table

(LUT)• Any 4-input logic function• Or 16-bit x 1 RAM• Or 16-bit shift register

CLB Slice (cont’d)

• Each slice contains two sets of the following:– Carry & control

• Fast arithmetic logic• Multiplier logic• Multiplexer logic

– Storage element• Latch or flip-flop• Set and reset• True or inverted inputs• Sync. or async. control

CLB

MUXF6

Slice

LUT

LUTMUXF5

Slice

LUT

LUTMUXF5

Dedicated Expansion Multiplexers• MUXF5 combines 2 LUTs to

form– 4x1 multiplexer

– Or any 5-input function

• MUXF6 combines 2 slices to form– 8x1 multiplexer

– Or any 6-input function

I/O Block (Simplified)• Registered input, output, 3-state control• Programmable slew rate, pull-up, pull-down, keeper

and input delay

I/O Interface Standards• I/O can be programmed for 16 different signal

standards– VCCO controls maximum output swing– VREF sets input, output, three-state control

• Different banks can support different standards at the same time– Logic level translation– Boards with mixed standards

IOBs Organized As Independent Banks

• As many as eight banks on a device– Package dependent

• Each bank can be assigned any of the 16 signal standards

2ns

2ns

2ns2ns

CLB Array

High Performance Routing• Hierarchical routing

– Singles, hexes, longs

• Sparse connections on longer interconnects for high speed

• Routing delay depends primarily on distance– Direction independent

– Device-size independent

• Predictable for early design analysis

Power-down Mode

• Controlled by single power down pin• All inputs blocked, appear low internally• All outputs disabled• All register states preserved• Power-down status pin• Synchronous wake up• 100 uA typical

Mode

Config.Data

Format

Direction ofSynchronizing

Clock UseSlaveSerial

Serial FPGA receivesCCLK

Processor or CPLD or another FPGA ( in Mastermode) controls configuration of slave FPGA

Also for configuring multiple slave FPGAs in adaisy chain (2ND, 3RD FPGA, etc.).

MasterSerial

Serial FPGA generatesCCLK

FPGA in Master mode configures itself from aserial PROM.

Also, 1st FPGA (master) in daisy chain controlsconfiguration of slave FPGA(s) in a daisy chain.

SlaveParallel

Byte FPGA receivesCCLK

Processor or CPLD controls the fast configuration ofslave FPGA.

JTAG Serial FPGA receivesTCK

Make use of existing boundary scan port

There are four ways to program a Spartan-II FPGA

Configuration Modes

Device XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200

Logic Cells 432 972 1728 2700 3888 5292

Block RAM Bits 16,384 24,576 32,768 40,960 49,152 57,344

Block RAM Qty. 4 6 8 10 12 14

Max. User I/Os 86 132 176 196 260 284

Package VQ100 VQ100

CS144 CS144

TQ144 TQ144 TQ144 TQ144

PQ208 PQ208 PQ208 PQ208 PQ208

FG256 FG256 FG256 FG256

FG456 FG456 FG456

Spartan-II Family Overview

Spartan-II Architecture Summary Delivers all the key requirements for ASIC replacement

– 200,000 gates

– 200 MHz

– Flexible I/O interfaces

– On-chip distributed and block RAM

– Clock management

– Low power

– Complete development system support