Sonia Luengo - October 2003

SPD Very Front End Board

Sonia Luengo - October 2003

Very Front End Board- Test Functionality (I)

Sonia Luengo - October 2003

Very Front End Board- Test Functionality (II)

Sonia Luengo - October 2003

Very Front End Board- Status

Design has been splitted into two different boards:

• PMT + ASICs + FPGA + Transceivers +DACs • Level Shifter + Serializer + Cable Compensation + Output Connectors + Input Connector + Power Supply Connector

Size of both boards: 12cm x 8cm

Sonia Luengo - October 2003

Very Front End Board- First Board (I)

Sonia Luengo - October 2003

Very Front End Board- First Board (II)

Sonia Luengo - October 2003

Very Front End Board- Second Board

Sonia Luengo - October 2003

Very Front End Board- Mapping (I)

PMT ( Top View in VFE Board):

8 16 24 32 40 48 56 64

7 15 23 31 39 47 55 63

6 14 22 30 38 46 54 62

5 13 21 29 37 45 53 61

4 12 20 28 36 44 52 60

3 11 19 27 35 43 51 59

2 10 18 26 34 42 50 58

1 9 17 25 33 41 49 57

Note: Gnd at Bottom

Sonia Luengo - October 2003

Very Front End Board- Mapping (II)

ASICs Mapping:

Note: Odd ASICs are in top layer. Even ASICs are in bottom layer.

124

113

102

91

ASIC1:

2820

2719

2618

2517

ASIC2:

4436

4335

4234

4133

ASIC4:

6052

5951

5850

5749

ASIC3:

168

7

14156

135

ASIC5:

3224

3123

3022

2921

ASIC6:

4840

4739

4638

4537

ASIC8:

6456

6355

6254

6153

ASIC7:

Sonia Luengo - October 2003

Very Front End Board- Mapping (III)Serializers Mapping:

Inputs Outputs

ASIC1(1-4/ 9-12) CO1

ASIC2(17-20/ 25-28)

ASIC5(5-8)

Test0(MSB)

S1: Inputs Outputs

ASIC3(49-52/57-60) CO3

ASIC4(33-36/ 41-44)

ASIC7(61-64)

Test2(MSB)

S3:

Inputs Outputs

ASIC5(13-16) CO2

ASIC6(21-24/ 29-33)

Subchannel

Test1(MSB)

S2: Inputs Outputs

ASIC7(53-56) CO4

ASIC8(37-40/ 45-49)

Test3

Test4(MSB)

S4: