spec_565

June 1999 Version 6.4 Page i of ii

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A565 Specifications

A565 Specifications

A565 System Specification

Advanced Analog Pin Unit

Advanced Time Measurement Subsystem

Breakdown Voltage Current Source

DC Reference Source

DC Subsystem

Handler/Prober Control Interface

High Current Current Source

High Current Unit

High Current Voltage Source

High Frequency Digitizer

High Power Matrix

High Power V/I Source

High Speed Digital Instrumentation

High Speed Sampler

High Voltage Ammeter

High Voltage Digital Card (HVDC)

IF Modulated Source

LA302 System Frequency Reference

Low Current Ammeter

Low Frequency AC 100 Digitizer

Low Frequency AC 100 Source

Microwave Source

Octal V/I Source

Power AL Disconnect Card

Power V/I Source

June 1999 Version 6.4 Page ii of ii

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Precision Low Frequency Digitizer

Precision Low Frequency Source

Precision Multimeter

Pulse Driver

Quad Opamp Channel Card

Serial Bus Channel Card

Stored Data Performance Bits

Superclock

Synchronized Power Subsystem Base

THADS24 Channel Card

Universal Backplane V/I Source

Universal Backplane 100 V V/I Source

VHF Arbitrary Waveform Generator

VHF Arbitrary Waveform Generator, 1 Meg

VHF Arbitrary Waveform Generator 400

VHF Arbitrary Waveform Generator 400 Differential

VHF Continuous Wave Source

VHF Measure Module

Version Date 9449 1–1

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Specs 1 A565 System Specification

Notes:

1. This specification is the MASTER reference specification for the A565Analog VLSI Test system. It contains the specifications that definethe proper conditions for the system instrumentation specifications.

The information in this document supersedes any similar information inearlier dated individual instrument ESSD's, or other Teradynedocumentation.

2. Specifications assume no unusual environmental conditions, e.g.:rapid rate of temperature change, thermal gradients, drafts.

3. Specifications are checked by Teradyne supplied procedures. Othermethods may yield different results.

4. All specifications subject to change without notice.

5. NOMINAL values refer to calculated values for specifiedquantities without incorporating variations due to tolerances.Nominal values are supplied as guidelines and are not guaranteed.

6. TYPICAL values refer to measured values for specified quantitieswhich have been determined based upon a limited sample of systems.Typical values are supplied as guidelines and are not guaranteed.

7. This is the period of time that System power must be continuouslyapplied before Instrumentation Auto-Calibration is performed inorder for Instrumentation to be guaranteed to meet specification.

System power must be continuously applied during this period, and allsystem covers must be properly in place and closed.

8. Inrush current value applies for one half line cycle, decreasingin amplitude to Steady State Line Current Value within 10 cycles.

9. Power Supply should be set for the 'Nominal Voltage', but is allowedto be within the indicated 'Limits'."Ripple & Noise" (PARD) is the combination of AC ripple & power supplyswitching noise. See the applicable note to determine where thisparameter should be measured."Current" indicates the maximum available current for the particularsupply, and is used as reference only. No measurements are done."Power Supply Reference" refers to location and/or power supplyreference number.



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10. Voltage measurements for this supply are made at the Sense pins onthe Power Supply molex connector. Pin 1 is +, pin 4 is -.Ripple & Noise measurements are made at the Force pins (studs).Use a differential scope w/ two X10 probes. Scope should bebandwidth limited to 20MHz. CONSULT THE A565 SERVICE MANUAL FORA DETAILED EXPLANATION ON HOW TO MEASURE NOISE & RIPPLE.

11. This supply should be measured at the PACS backplane terminals.(+) at J14, and (-) at Power Ground Stud.

12. These voltages and noise measurements are made at the Analog DCDistribution Bus located on the right side(Operator) of the cabinet.

13. Power Supply should be set for the "Nominal Voltage", but is allowedto be within the indicated "Limits"."Ripple & Noise" (PARD) is the combination of AC ripple & power supplyswitching noise.These parameters are measured at the Analog backplane in the test head,at Slot 22 on the indicated pin numbers. First number is the groundreference. (Note these measurements can be made at ANY Analog Channelcard slot for those configurations that have a Channel Card locatedin Slot 22)"Current" indicates the maximum available current for the particularsupply, and is used as reference only. No measurements are done."Power Supply Reference" refers to location and/or power supplyreference number.

14. SWPS2; Mainframe Base Switcher Power Supply output: +5v, is sharedbetween BOTH the Mainfame Bus and BOTH PATH II Analog sections.This voltage is adjusted inside the mainframe at that listed setting.

PS4,7-9; Mainframe Base Linear +/-30, +/-75v, are shared between theMainframe Analog DC Distribution Bus and BOTH PATHII Analog sections.These voltages are adjusted inside the mainframe at those listedsettings.

15. This power supply output is programmed by the SFO board. Themanual adjustment is complex, refer to the service documentationfor complete details. The voltages shown here reflect the supplyoutput when the SFO board is in the cleared state.

16. Test head User power is shared from the Analog Power Supplies locatedon the Base Linear Power Tray. The outputs to the test head are fused andrelay switched by software control. The specifications listed in thistable refer to the nominal voltage available at the DIB and the MAXIMUMcurrent allowed in order to maintain a +/-5% voltage tolerance.Voltages are measured at the DIB, ground ref is 'User Power Ground'.

17. Digital Test head power supplies: SWPS3 refers to TH#1, SWPS4 to TH #2.

18. SWPS5-7; Mainframe HSD25 Power Supply outputs: -2, +5v and -5.2v,are shared between BOTH the Mainfame Digital Busbar and BOTH PATH IIHSD25 sections.These voltages are adjusted inside the mainframe at those listedsettings.



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SWPS5; +15v,is shared between the Mainfame and PATHII HSD25 slots.This voltage is adjusted inside the mainframe at those listedsettings.

SWPS6: +6v output is shared between BOTH PATHII DTH Sections. Thisoutput is kelvined at the supply and is adjusted to those settingslisted in the Mainframe HSD25 section.

19. This output remains unused at this time, with future use committed tothe DSIO cage.

20. THADS is an acronym for the Test Head Analog Distribution System,a coaxial connection network which is local to the test head. ThisSpecification gives typical characterization data for the INTERNALdistribution network only, from one Channel Card slot to another.It does NOT include the effects of Channel Cards, or Config Board,Isopin, or DIB wiring.

21. Instrument specifications for the A565 system, with a PATH IItest head apply at the end of cable assemblies, either Teradyneor customer supplied.MAXIMUM LENGTH OF THESE CABLES ARE 1 meter (39 inches) long,except for the Handler/Prober communications interface.

The Handler/Prober interface specifications apply at the end ofup to 12 feet (3.6 meters) of cable.

These cable assemblies must be fabricated using wire types listedbelow:

· DC Subsystem:- Matrix pins: 50 ohm miniature coax (30 AWG) [Sense (shld), Force (cntr)]

Coax dielectric must NOT be PVC. Teflon or similar material is requiredfor proper leakage performance.

- DUT Source: 100 ohm Shielded Twisted Pair (STP) (30 AWG) [F & S(center conductors), Guard (shield)]

· Analog Pin Unit: Same as Matrix pins

· High Current Unit: Same as DUT Source

· Power V/I:- Force lines: #14 awg w/600v insulation (UL 1015)- Sense lines: #20 awg w/600v insulation (UL 1015)

· HSD25:- 50 ohm precision coax cable. Gore p/n DXSN 1456 or equivalent:

26 AWG center conductor w/ expanded teflon dielectric50 ohm +/1 ohm characteristic impedanceTime delay 1.23 ns/ft nominalCapacitance 27 pf/ft max

· Advanced Time Measurement Subsystem:- 50 ohm miniature coax (30 AWG) [Shield (shld), Signal (cntr)]



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· High Frequency Digitizer: 50 Ohm coax, RD316 or equivalent (Doubleshielded)

· Precision Low Frequency Source / Low Frequency AC Source:- PLFS / LFAC S HI: 100 ohm Shielded Twisted Pair (30 AWG) [AC DGS & HI

(center conductors), Shield (shld)]- PLFS / LFAC S LO: 100 ohm Shielded Twisted Pair (30 AWG) [AC DGS & LO

(center conductors), Shield (shld)]- KELVIN LO: 50 ohm miniature coax (30 AWG) [Shield (shld), Signal (cntr)]


· Precision Low Frequency Digitizer / Low Frequency AC Digitizer:- PLFD / LFAC D HI: 100 ohm Shielded Twisted Pair (30 AWG) [AC DGS & HI

(center conductors), Shield (shld)]- PLFD / LFAC D LO: 100 ohm Shielded Twisted Pair (30 AWG) [AC DGS & LO



· Precision Multimeter:- 50 ohm miniature coax (30 AWG) [Shield (shld), Signal (cntr)]


· Reference Source:- REFSRC HI: 100 ohm Shielded Twisted Pair (30 AWG) [AC DGS & HI

(center conductors), Shield (shld)]- REFSRC LO: 100 ohm Shielded Twisted Pair (30 AWG) [AC DGS & LO



· High Frequency Sampler:- 50 ohm miniature coax (30 AWG) [Shield (shld), Signal (cntr)]

· Stored Data Performance Bits: #24 gauge wire

· Ultra High Frequency Source: TBD

· Very High Frequency Arbitrary Waveform Generator:- 50 ohm coax, RG223 or equivalent (Double shielded)

· Very High Frequency Continuous Wave Source:- 50 ohm coax, RG223 or equivalent (Double shielded)

· Serial Bus Channel Card:- 100 ohm miniature coax cable.33 AWG center/drain conductors100 ohm +/- 10 ohm characteristic impedanceNominal capacitance: 12 pf/ftPropagation delay: 1.20 ns/ft +/- 0.03 ns/ftVp (nominal) 85%



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· Test Head User Power: #24 gauge wire

· Miscellaneous Signals:- 50 ohm miniature coax (30 AWG) [Shield (shld), Signal (cntr)]Coax dielectric must NOT be PVC. Teflon or similar material is requiredfor proper leakage performance. Used on the following signals:

User ClockDGS

- #24 AWG wire used on the following signals:TIP Config ID D0 User Alarm Config ID +5VSafety* Config ID3 CE Config ID SK Config ID4 CEConfig ID DI



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1 OPERATING ENVIROMENT

1.1 Ambient Temperature: 20 deg C to 30 deg C [Note 2](68 deg F to 86 deg F)

1.2 Relative Humidity: 40% to 60% non-condensing [Note 2]

1.3 System Warm-Up Period: Thirty minutes Minimum [Note 7]

1.4 Air Conditioning Requirement: 47,782 BTU/hourm maximumat system's maximum Configuredpower consumption of 20 kVA.

59,728 BTU/hour maximumat system's maximum ratedpower consumption of 25 kVA.

2 AC POWER

2.1 Input Power Configuration 3 phase/4 wire Delta

2.2 System Power Consumption2.2.1 Maximum System Consumption 25 kVA Maximum2.2.2 Maximum System Configuration 20 kVA Maximum2.2.3 Typical System Configuration 16 - 20 kVA

2.3 Line Voltage2.3.1 Line Voltage Ranges 190,200,208,240,380,400,416,480 VAC2.3.2 Line Voltage Variation +/-5% Maximum

2.4 Line Frequency 50 or 60 Hz2.4.1 Line Frequency Variation +/-2 Hz

2.5 Inrush Line Current 10X steady state line current [Note 8]

3 A565 DC POWER SUPPLY SPECIFICATIONS

3.1 Base System Power (supplies located on Linear Power Tray, EXCEPT SWPS2)

[Note 9]Nominal Voltage Ripple/ Power Supply

& Limits Noise NOTE Current Reference--------------- -------- ---- ------- -------------

- 2.10 V +/-50 mV 200 mV p-p 10 150 A SWPS2- 5.25 V +/-50 mV 200 mV p-p 10 60 A+ 5.15 V +/-50 mv 200 mV p-p 10 150 A

+12.00 V +/-100 mV 150 mV p-p 12 10 A PS5

+12.00 V +/-100 mV 150 mv p-p 12 10 A PS6

+15.00 V +/-50mV 150 mV p-p 12 14.7 A PS10

-15.00 V +/-50 mV 150 mV p-p 12 14.7 A PS11



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+30.00 V +/-25 mV 200 mV p-p 12 3.3 A PS4

-30.00 V +/-25 mV 200 mV p-p 12 3.3 A PS9

+40.00 V +/-50 mv 150 mV p-p 12 6 A PS1

-40.00 V +/-50 mv 150 mV p-p 12 6 A PS2

+75.10 V +/-75 mV 150 mV p-p 12 1.2 A PS7

-75.10 V +/-75 mV 150 mV p-p 12 1.2 A PS8

3.2 HSD-25 Power *Optional (Supplies located below Digital Option Card Cage)



+5.05 V +/-50 mV 200 mV p-p 10 150 A SWPS5+15.05 V +/-50 mV 200 mV p-p 10 52 A-15.05 V +/-50 mV 200 mV p-p 10 16 A

-5.25 V +/-50 mV 200 mV p-p 10,19 150 A SWPS6-2.05 V +/-50 mV 200 mV p-p 10 150 A+6.05 V +/-50 mV 200 mV p-p 10 60 A

- 5.25 V +/-50 mV 200 mV p-p 10 400 A SWPS7

3.3 PACS Power *Optional(SWPS1 located in PS Column Switcher Side,PS3 located in Base Linear Power Tray.)



-5.25 V +/-50 mV 200 mV p-p 10 250 A SWPS1+5.05 V +/-50 mv 200 mV p-p 10 150 A

+6.05 V +/-50 mV 150 mV p-p 11 5 A PS3

3.4 Test Head Power

3.4.1 Analog Channel Cards (Supplies located on Test head Power Tray)(*Shared Supplies located on Base Power Tray,*SEE NOTE 14)

[Note 13]Nominal Voltage Ripple/ Slot 22/ Power Supply

& Limits Noise Pin No. Current Reference--------------- -------- ------ ------- --------------5.25 V +0mv/-25mv 150mV p-p 50C/49C 20A PS4

+5.15 V +50mV/-80mv 200mV p-p 48C/47C n/a *SWPS2

+6.00 V +50mv/-0mv 100mV p-p 48C/47C 7.5A PS1

+15.00 V +50mv/-0mv 100mV p-p 44C/43C 4.5A PS2



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-15.00V +0mv/-50mv 100mV p-p 44C/42C 4.5A PS3

+30.10V +25mv/-55mv 200mV p-p 48C/46C *PS4

-30.10V +55mv/-25mv 200mV p-p 48C/45C *PS9

+75.10V +75mv/-100mv 150mV p-p 44C/40C *PS7

-75.10V +100mv/-75mv 150mV p-p 44C/39C *PS8

3.4.2 Digital Channel Cards (Supplies located in Switcher Power SupplyColumn, *Shared Supplies are located belowDigital Option Card Cage


& Limits Noise NOTE Current Reference--------------- -------- ---- ------- -------------+10.10V +/- 50mV 200mV p-p 15,17 60A SWPS3/4- 5.30V +/- 50mV 200mV p-p 15,17 60A-10.05V +/- 50mV 200mV p-p 10 15A

+ 6.05V +50mV/-80mV 200mV p-p 18 *SWPS6

- 2.05V +80mV/-50mV 200mV p-p 18 *SWPS6

- 5.25V +80mV/-50mV 200mV p-p 18 *SWPS7

+ 5.05V +50mV/-80mV 200mV p-p 18 *SWPS5

+15.15V +50mV/-80mV 200mV p-p 18 *SWPS5

3.5 Test Head User Power [Note 16]

Nominal Voltage Maximum Current--------------- ---------------

+ 5.15 V 1 A- 5.25 V 1 A+12.00 V 1 A+15.05 V 1 A-15.05 V 1 A+30.05 V 0.5 A-30.05 V 0.5 A

3.6 Handler/Prober Interface Power (Parallel I/F Connectors J11-J14)

Nominal Voltage Maximum Current (per connector)--------------- ---------------+ 5.15 V 100 mA+12.00 V 50 mA

4.0 THADS Internal Bus Specifications [Note 20]These specifications apply for connection of any Analog ChannelCard slot to any other Analog Channel Card slot.

THESE SPECIFICATIONS INCLUDE ONLY THE EFFECTS OF THE THADS SYSTEM.



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THEY ARE MEASURED FROM ONE CHANNEL CARD SLOT TO ANOTHER, AND DO NOTINCLUDE THE EFFECTS OF CHANNEL CARDS, CONFIG BOARDS, OR DIB WIRING.

These specifications are typical only.

Insertion loss and cross talk are specified for a 50 ohmenvironment.

CAPACITANCE <200 pF (typical)For THAD-A or THAD-B

INSERTION LOSSLOSS FREQUENCY (Minimum)1 dB 10 MHz (typical)2 dB 15 MHz (typical)3 dB 20 MHz (typical)

10 dB 40 MHz (typical)For THAD-A or THAD-B

CROSSTALK TO QUIET CHANNELFREQUENCY CROSSTALK1 kHz -110 dB (typical)10 kHz -90 dB (typical)100 kHz -70 dB (typical)1 MHz -50 dB (typical)10 MHz -30 dB (typical)For THAD-A (driven) to THAD-B; or from THAD-B (driven) to THAD-A

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Specs 2 Advanced Analog Pin Unit

NOTES:

NOTE1 All of accuracy is defined by software calibration.

NOTE2 All specs apply with the measurement filter on and average10 times. All of accuracy is defined by software calibration.Resolution and Accuracy are defined by 14-bits Standard Voltmeter.

0. AAPU FEATURES

0.1 CUSTOMER FEATURES

0.1.1 4 Quadrant operation at full square (+/-30 V, +/-30 mA)

0.1.2 3 Modes availableV-FORCE/I-MEASURE modeI-FORCE/V-MEASURE modeVoltage Measure mode (High-Z mode)

0.1.3 Programmable ClampVoltage-Clamp (I-FORCE/V-MEASURE mode)Current-Clamp (V-FORCE/I-MEASURE mode)

0.1.4 4 AAPU V/I Source and Measurement per board

0.1.5 Device Ground Sense (DGS) compensation for accuracy

0.1.6 Two alarm types:Overload AlarmGuard Alarm

0.1.7 Independent control Force/Sense and Guard output relays

0.1.8 Solid-state Ranging for V and I ranges

0.1.9 Force and Sense connection via two Diodes(1.2 V Clamp)

0.1.10 Gate control by Trigger bus

0.1.11 Independent Clear for each AAPU

0.1.12 Automatic calibration every 4 hours

0.1.13 Gate on/off control



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1. AAPU Specifications

1.1 Voltage Forcing (Note1)1.1.1 Range Resolution Accuracy

(14 bits)2V 0.25 mV +/-(0.1% + 1.5 mV)5V 0.625 mV +/-(0.1% + 3.0 mV)

10V 1.25 mV +/-(0.1% + 6.0 mV)30V 3.75 mV +/-(0.1% + 18 mV)

1.1.2 Maximum Forcing Voltage +/-30 V1.1.3 Maximum Allowable Voltage +/-60 V

1.2 Voltage Measuring (Note2)1.2.1 Range Resolution Accuracy

(14 bits)2V 0.25 mV +/-(0.1% + 1.5 mV)5V 0.625 mV +/-(0.1% + 3.0 mV)

10V 1.25 mV +/-(0.1% + 6.0 mV)30V 3.75 mV +/-(0.1% + 18 mV)

1.2.2 Maximum measurable voltage +/-30 V

1.3 Current Forcing (NOTE1)1.3.1 Range Resolution Accuracy

(14 bits)200uA 25 nA +/-(0.1% + 0.25 uA + 1 nA/V)

1mA 0.125 nA +/-(0.1% + 0.8 uA)5mA 0.625 nA +/-(0.1% + 4.0 uA)

30mA 3.75 nA +/-(0.1% + 24 uA)Matrix leakage included

1.3.2 Maximum Forcing Current +/-30 mA

1.4 Current Measuring (NOTE2)1.4.1 Range Resolution Accuracy

(14 bits)

2uA 0.25 nA +/-(0.5% + 110 nA + 1 nA/V)10uA 1.25 nA +/-(0.2% + 120 nA + 1 nA/V)50uA 6.25 nA +/-(0.2% + 200 nA + 1 nA/V)

200uA 25 nA +/-(0.1% + 0.3 uA + 1 nA/V)1mA 125 nA +/-(0.1% + 1.0 uA)5mA 625 nA +/-(0.1% + 5.0 uA)

30mA 3.75 uA +/-(0.1% + 30 uA)Matrix leakage included

1.4.2 Maximum measurable current +/-30 mA

1.5 Voltage Measure mode (High-Z mode) (NOTE2)1.5.1 Range Resolution Accuracy

(14 bits)2V 0.25 mV +/-(0.1% + 1.5 mV)5V 0.625 mV +/-(0.1% + 3.0 mV)

10V 1.25 mV +/-(0.1% + 6.0 mV)30V 3.75 mV +/-(0.1% + 18 mV)



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1.5.2 Maximum measurable voltage +/-30 V1.5.3 Output impedance >10 MOHM

1.6 Programmable Clamp1.6.1 Voltage Clamp

Range Resolution Accuracy(8 bits)

2V 8 mV +7%,-0% of Range full scale (Nominal)5V 20 mV +7%,-0% of Range full scale (Nominal)

10V 40 mV +7%,-0% of Range full scale (Nominal)30V 120 mV +7%,-0% of Range full scale (Nominal)

1.6.2 Current ClampRange Resolution Accuracy

(8 bits)2uA --- Not supported

10uA 40 nA +7%,-0% of Range full scale (Nominal)50uA 0.2 uA +7%,-0% of Range full scale (Nominal)

200uA 0.8 uA +7%,-0% of Range full scale (Nominal)1 mA 4 uA +7%,-0% of Range full scale (Nominal)5 mA 20 uA +7%,-0% of Range full scale (Nominal)

30 mA 120 uA +7%,-0% of Range full scale (Nominal)

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Specs 3 Advanced Time Measurement Subsystem

Notes:

Note A Specification supported after TMS autocalibration.

Note 1 The accuracy of a time measurement is a function of many sourcesof error. These errors are characteristics of the TMS timer, inputchannel selected, and input signal. They are listed (see referencedspecifications for individual parameter values):

TMS Base Timer Specifications:RESL = Resolution = quantization error (1.1.2)TBE = Time Base Error = Gain error (1.1.3)TJTTR = Timer Jitter = Random error (1.1.4)

Front End Specifications:PLE = Time meas. offset (skew) = PLE (start) + PLE (stop)FJTTR = Front End Jitter = Random errorTLE = Trigger level error at selected input

= Gain errorEn = Analog noise voltage at the front end

= Random error

Absolute uncertainty calculations need to combine each source ofgain, offset, random, and quantization error for the measurement.In many cases, some error terms cancel or are negligible.For example: the 10 ps resolution spec is always negligible; the1 ppm Time Base Error does not add significant error to short timemeasurements; and trigger level errors will cancel in a periodtype measurement.

Please see the TMS section and appendix of the user's manual fora complete discussion of determining time measurement accuracy.

Note 2 Precounter must be counting events on the start channel to maintainprecounter accuracy. Similarly, the postcounter must be countingevents on the stop channel for its accuracy specification to hold.See the TMS section of the user's manual for TMS applicationswhich will reduce counter uncertainty to zero.

Note 5 This is a worst case specification which applies to free-running,asynchronous input signals. Counter will perform to +/-0 countsfor gated or synchronized signals.



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I - ADVANCED TMS BASE SPECIFICATIONS

0. TMS Base Features

0.1 TMS Input Selection -Advanced Test Head0.1.1 2 TMS (TFE) Channels -standard0.1.2 2 additional TFE Channels -optional0.1.3 Analog Channels with THADS access -optional0.1.4 Trigger Bus Access -optional0.1.5 HSDS Channels (vol or voh receivers) -optional0.1.6 HSD Channels (vol or voh receivers) -optional

0.2 Independent Start, Stop, Enable Event/Slope Selection0.2.1 Start-Stop on same channel0.2.2 Start-Stop on different channels0.2.3 Independent Start, Stop, Enable Slope Selection

0.3 Start Enable (Start holdoff) control0.3.1 Precount Events on START, STOP, or ENABLE channel0.3.2 Precount Time (after TMS ARM'ing)0.3.3 Precount Time after an Event on START, STOP, or ENABLE channel0.3.4 Direct Start Enable computer control0.3.5 Start Enable Gate (ENABLE channel)0.3.6 Independent Start Enable Event Slope Selection

0.4 Stop Enable (Stop holdoff) control0.4.1 Stop-After-Start interlock0.4.2 Postcount Events on START, STOP, or ENABLE (after Start)0.4.3 Postcount Time (after Start)0.4.4 Direct Stop Enable computer control0.4.5 Stop Enable Gate (ENABLE channel)

0.5 TMS Timer/Counter Modes0.5.1 Period Mode0.5.2 Frequency Mode0.5.3 Duty Cycle Mode0.5.4 Risetime Mode0.5.5 Pulsewidth Mode0.5.6 Propagation Delay Mode0.5.7 Event Count Mode0.5.8 Ratio Count Mode0.5.9 Time Interval Mode (a general purpose timer/counter mode)

0.6 Time Measurement RAM -available in all modes

0.7 Timer Operation Control (Available in all modes except Duty Cycle)0.7.1 High Resolution (20 us interpolation - Not in Duty Cycle mode)0.7.2 High Speed (real time measurement)

1. TMS Base Timer/Counter Functions

1.1 Timer - Time Measurement1.1.1 Range1.1.1.1 Direct TMS Measurement +/-250 ms1.1.1.2 Computer Extension +/-no limit



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1.1.2 Resolution1.1.2.1 High Resolution timer 8 ps, Nominal1.1.2.2 High Speed timer 8 ns, Nominal1.1.3 Time Base Error (Note A) see LA302 specifications1.1.4 Timer Jitter (Note A)1.1.4.1 Jitter (pk-pk) <500 ps1.1.4.2 Jitter (rms) <100 ps1.1.5 Accuracy Relationship +/-[Resolution + TBE*Time + Jitter]

(Total measurement uncertainty also includes time channelerrors. See also time channel specifications and Note 1.)

1.2 Counter - Event Count1.2.1 Range1.2.1.1 Direct TMS count 0 to 167772151.2.1.2 Computer Extension 0 to no limit1.2.2 Resolution 1 count1.2.3 Accuracy (Note 5) +/-1 count1.2.4 Maximum Count Rate 100 MHz

1.3 Start Enable1.3.1 Precounter (Note 2)1.3.1.1 Range 0 to 16777215 counts1.3.1.2 Resolution 1 count1.3.1.3 Accuracy +/-1 count1.3.1.4 Window of Uncertainty +/-8 ns1.3.1.5 Maximum Count Rate 100 MHz1.3.2 Pre Timer1.3.2.1 Range 0 to 134 ms1.3.2.2 Resolution 8 ns1.3.2.3 Accuracy +/-10 ns

1.4 Stop Enable1.4.1 Postcounter (Note 2)1.4.1.1 Range 0 to 16777215 counts1.4.1.2 Resolution 1 count1.4.1.3 Accuracy +/-0 counts1.4.1.4 Maximum Count Rate 100 MHz1.4.2 Post Timer1.4.2.1 Range 0 to 134 ms1.4.2.2 Resolution 8 ns1.4.2.3 Accuracy +/-10 ns

1.5 Multiple Measurement Memory1.5.1 Range1.5.1.1 All modes except duty cycle 2 to 1024 measurements1.5.1.2 Duty cycle mode 2 to 512 measurements1.5.2 Resolution Integer1.5.3 Minimum Cycle Time1.5.3.1 High resolution mode <20 us1.5.3.2 High speed mode <400 ns



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2. Time Front End (TFE) Channel Input

2.0 TFE Features2.0.1 Time Channel Accuracy Relationship (Note 1)

+/-[PLE + SQRT[Jitter^2 + (En/Slew)^2] + TLE/Slew]2.0.2 THADS Bus Access - see analog instrument specifications2.0.3 Selectable Hysteresis levels Low Hyst High Hyst2.0.3.1 Standard Linear Stations, Advanced Linear Stations, and Advanced

Mixed-Signal Stations have selectable hysteresis levelsLow Hyst. High Hyst.

2.0.3.1.1 +/-6 V range 6 mV 100 mV2.0.3.1.2 +/-30 V range 30 mV 500 mV2.0.3.1.3 +/-200 V range 300 mV 5 V2.0.3.2 Catalyst Stations have selectable hysteresis levels

(specified levels are typical)Low Hyst. High Hyst.

2.0.3.2.1 +/-6 V range 6 mV 10 mV2.0.3.2.2 +/-30 V range 30 mV 50 mV2.0.3.2.3 +/-200 V range 300 mV 500 mV2.0.4 Selectable Input Impedance 50 Ohm and 1 Mohm

2.1 TFE Path Length Error (Note A) +/-250 ps2.1.1 Prior to autocal release (V5.0) +/-5.0 ns, Typical2.1.2 Catalyst test head using +/-500 ps

A5 DIB Adapter

2.2 Front End Jitter negligible

2.3 Input Capacitance2.3.1 Advanced Linear Stations <150 pF2.3.2 Advanced Mixed Signal Stations <150 pF2.3.3 Production Analog Test Head <300 pF

using LA683-00 Configuration Board2.3.4 Catalyst Test Head <200 pF2.3.5 Catalyst Test Head using <250 pF

A5 DIB Adapter

2.4 Analog Errors (Note A)2.4.1 6 V Range (50 Ohm/1 MOhm): Standard Linear, Advanced Linear,

and Advanced Mixed-Signal Stations2.4.1.1 Maximum Operating Range +/-6.4 V2.4.1.2 Maximum Allowable Voltage2.4.1.2.1 50 Ohm input +/-6.4 V, Nominal2.4.1.2.2 1 MOhm input +/-15 V, Nominal2.4.1.3 Threshold Range +/-6.0 V2.4.1.4 Threshold Resolution 0.76 mV, Nominal2.4.1.5 Trigger Level Error (TLE) +/-(1.0% + 15 mV)2.4.1.6 Input Amplifier Noise (En)2.4.1.6.1 TFE Channel Noise (pk-pk)<20.0 mV2.4.1.6.2 TFE Channel Noise (rms) <4.0 mV2.4.1.7 Input R Accuracy +/-1%2.4.1.8 Hysteresis Accuracy +/-(20% + 3 mV)2.4.2 30 V Range: Standard Linear, Advanced Linear, and

Advanced Mixed-Signal Stations2.4.2.1 Maximum Operating Range +/-32 V2.4.2.2 Maximum Allowable Voltage +/-60 V, Nominal



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2.4.2.3 Thresh. Range +/-30 V2.4.2.4 Threshold Resolution 3.8 mV, Nominal2.4.2.5 Trigger Level Error (TLE) +/-(1.5% + 75 mV)2.4.2.7 Input R Accuracy +/-1%2.4.2.8 Hysteresis Accuracy +/-(20% + 15 mV)2.4.3 200 V Range: Standard Linear, Advanced Linear, and

Advanced Mixed-Signal Stations2.4.3.1 Maximum Operating Range +/-220 V2.4.3.2 Maximum Allowable Voltage +/-220 V, Nominal2.4.3.3 Thresh. Range +/-200 V2.4.3.4 Threshold Resolution 38 mV, Nominal2.4.3.5 Trigger Level Error (TLE) +/-(2.0% + 750 mV)2.4.3.7 Input R Accuracy +/-1%2.4.3.8 Hysteresis Accuracy +/-(20% + 150 mV)2.4.4 6 V Range (50 Ohm/1 MOhm): Catalyst Station2.4.4.1 Maximum Operating Range +/-6.0 V2.4.4.2 Maximum Allowable Voltage2.4.4.2.1 50 Ohm input +/-6.0 V, Nominal2.4.4.2.2 1 MOhm input +/-12.5 V, Nominal2.4.4.3 Threshold Range +/-6.0 V2.4.4.4 Threshold Resolution 0.76 mV, Nominal2.4.4.5 Trigger Level Error (TLE) +/-(1.0% + 15 mV)2.4.4.6 Input Amplifier Noise (En)2.4.4.6.1 TFE Channel Noise (pk-pk)<20.0 mV2.4.4.6.2 TFE Channel Noise (rms) <4.0 mV2.4.4.7 Input R Accuracy +/-1%2.4.5 30 V Range: Catalyst Station2.4.5.1 Maximum Operating Range +/-30 V2.4.5.2 Maximum Allowable Voltage +/-60 V, Nominal2.4.5.3 Thresh. Range +/-30 V2.4.5.4 Threshold Resolution 3.8 mV, Nominal2.4.5.5 Trigger Level Error (TLE) +/-(1.5% + 75 mV)2.4.5.7 Input R Accuracy +/-1%2.4.6 200 V Range: Catalyst Station2.4.6.1 Maximum Operating Range +/-220 V2.4.6.2 Maximum Allowable Voltage +/-220 V, Nominal2.4.6.3 Thresh. Range +/-200 V2.4.6.4 Threshold Resolution 38 mV, Nominal2.4.6.5 Trigger Level Error (TLE) +/-(2.0% + 750 mV)2.4.6.7 Input R Accuracy +/-1%

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Specs 4 Breakdown Voltage Current Source

Note:

1 Measurement resolution is determined by the system resource usedfor analog-to-digital conversion of the measurement bus signal.The standard system VM is the default converter used to capture ameasurement. Its specifications can be found in the standard DCsubsystem ESSD. In general, measurement accuracy is limited bygain and offset errors. Meter resolution is not a significantportion of the measurement uncertainty.



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I. BVCS SPECIFICATION LIST

0. BVCS Features

0.1 Forcing Current Source0.1.1 Measure Voltage0.1.2 Low Z off-state to discharge DUT and delivery capacitance0.1.3 Two Compensation Settings

0.2 Forcing Voltage Source0.2.1 Measure Current

0.3 General Features0.3.1 Instrument Safety Interlock0.3.2 IMAGE Programming Language

0.6 Synchronization Capabilities0.6.1 Trigger Bus

0.7 Output Delivery System0.7.1 8 output pins in AL test head or in PATH head

0.8 Internal Protection0.8.1 Heat Sink Thermal Protection0.8.2 Excess Current in Off-state Shutdown

0.9 Measurement Alarms0.9.1 Heat Sink Thermal Protection0.9.2 Excess Current in Off-state Shutdown0.9.3 Open Loop Indicator

1. BVCS Forcing Current Source Specifications

1.1 Resolution and Accuracy

Range Resolution Accuracy----- ---------- --------

1.1.1 10 uA 305 pA (nominal) +/-(0.5% + 50 nA)1.1.2 100 uA 3.05 nA (nominal) +/-(0.5% + 500 nA)1.1.3 1 mA 30.5 nA (nominal) +/-(0.5% + 5 uA)1.1.4 10 mA 305 nA (nominal) +/-(0.5% + 50 uA)

1.2 Maximum Programmable Output Current1.2.1 BVCS as current source 10 mA

1.3 Maximum Programmable Output Voltage1.3.1 High Power V/I as voltage supply 750 V



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1.4 Settling Time into a short circuit (50 ohms)

Range Settling time into 50 ohms----- -------------------------

1.4.1 10 uA <1.5 ms typical1.4.2 100 uA <5.5 ms typical1.4.3 1 mA <750 us typical1.4.4 10 mA <400 us typical

1.4 Settling time into device is a combination of settling timeof the current source and characteristics of output deliverysystem such as capacitance.

1.5 Periodic and Random Deviations (PARD)

Range PARD----- --------------------

1.5.1 10 uA <50 nA typical1.5.2 100 uA <100 nA typical1.5.3 1 mA <500 nA typical1.5.4 10 mA <5 uA typical

1.6 Stability The BVCS will settle into any realor first order reactive load withinthe specifications.Settling time is limited by thedelivery path and device characteristics.

1.7 Maximum Allowable Voltage

Any voltages applied to BVCS output should neverexceed voltage programmed on the HPVI.

2. BVCS Voltage Measurement Specifications

2.1 Accuracy

Resolution see DC subsystem specifications (NOTE 1)

Range Accuracy_____ ________

2.1.1 1000 V +/-(0.5% + 1.25 V)2.1.2 200 V +/-(0.5% + 1.00 V)2.1.3 50 V +/-(0.5% + 0.50 V)

2.1.4 Additional correction applied to voltage forcing mode

Vreal = vmeas - iout * Rout

whereiout is current measured with BVCS ammeterRout is output resistance specified in 3.2 of this

document



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2.2 Voltmeter Noise <200 mV p-p typical

2.3 Voltmeter Settling Time <20 us typical

2.4 Maximum Allowable Voltagenot to exceed voltage programmed on the HPVI

3. Voltage Forcing Accuracy

3.1 Accuracy

Determined by high voltage source instrument and Rout

3.2 Output Resistance (Rout)

249.7 for irange = 10 mA453.5 for irange = 1 mA493.8 for irange = 100 uA498.3 for irange = 10 uA498.8 for irange = 1 uA

3.3 Maximum Programmable Output Voltage3.3.1 High Power V/I as voltage supply 750 V

3.4 Maximum Programmable Output Current 10 mA

3.5 Settling Time Limited by high voltage source

3.6 Periodic and Random Deviations (PARD) Limited by high voltage source3.7 Stability Limited by high voltage source

4. BVCS Current Measurement Specifications

4.1 Accuracy

Resolution see DC subsystem specifications (NOTE 1)

Range Accuracy (% of reading + offset)----- --------------------------------

4.1.1 1 uA +/-(0.5% + 10 nA)4.1.2 10 uA +/-(0.5% + 50 nA)4.1.3 100 uA +/-(0.5% + 500 nA)4.1.4 1 mA +/-(0.5% + 5 uA)4.1.5 10 mA +/-(0.5% + 50 uA)



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4.2 Ammeter Noise

Range-----

4.2.1 10 uA <30 nA typical4.3.2 100 uA <50 nA typical4.4.3 1 mA <300 nA typical4.5.4 10 mA <3 uA typical

4.3 Ammeter Settling time <100 us typical

4.4 Maximum Allowable Current 10 mA

5. BVCS Output Delivery System Specifications

5.1 Capacitance

5.1.1 For Advanced Linear (AL) Test Headunguarded <180 pF typicalguarded <60 pF typical

5.1.2 For Production Analog Test Head (PATH)unguarded <120 pF typicalguarded <60 pF typical

5.2 Leakage and Dielectric Absorption

5.2.1 For Advanced Linear (AL) Test Head

After 1 ms < 130 nA + 0.1 nA/V typicalAfter 2 ms < 50 nA + 0.1 nA/V typicalAfter 10 ms < 5 nA + 0.1 nA/V typical

5.2.2 For Production Analog Test Head (PATH)

After 1 ms <130 nA + 0.1nA/V typicalAfter 2 ms <50 nA + 0.1 nA/V typicalAfter 10 ms <5 nA + 0.1 nA/V typical

7. BVCS Miscellaneous Specifications

7.2 Maximum Output Voltage (applied to any disconnected output)Limited to programmed voltage of high voltage source

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Specs 5 DC Reference Source

NOTES:

1) Notation Notes:+ = arithmetic sum** = raised to the powerVbl = programmed dc baseline

2) All specifications are guaranteed unless noted as TYPICAL or NOMINAL.

3) TYPICAL specifications are sample tested, NOT 100% tested and areNOT guaranteed.

4) NOMINAL specifications are generally calculated values, are NOT 100% testedand are NOT guaranteed.


DC Reference Source

Main Menu

1. REFERENCE SOURCE SPECIFICATIONS

1.1 Maximum Output Voltage +/-11.0 V max.

1.2 Voltage Resolution 17 bits, 168 uV

1.3 Accuracy +/-(Vbl*6 + 2.5) mV

1.4 Long Term DNL 14 bits

1.5 DC Baseline Drift <(10 uV + (0.2 + 0.0011(Vbl**3.5))(time)) uV

1.6 Output Current1.6.1 Compliance Limit >20 mA1.6.2 Maximum Short Circuit <65 mA

1.7 Output Impedance (DC - 500 kHz)1.7.1 25 Ohms1.7.1.1 Accuracy +/-1 Ohm1.7.1.2 Max. Capacitive Load >1 nF1.7.2 Low Z1.7.2.1 Zout <1 Ohm1.7.2.2 Max. Capacitive Load >100 pF1.7.3 Remote Kelvin (C pin only)1.7.3.1 Zout <0.1 Ohm1.7.3.2 Max. Capacitive Load >100 pF

1.8 Settling Time <2 ms to 1 PPM offinal value

1.9 Total Noise (BW)1.9.1 0.1 Hz - 10 Hz <18 uVrms1.9.2 50 Hz - 20 kHz <20 uVrms1.9.3 50 Hz - 100 kHz <22 uVrms1.9.4 50 Hz - 1 MHz <40 uVrms

1.10 Slew Rate >8 V/us nominal

1.11 Overcurrent Alarm Detection Threshold <45 mA

1.12 Time Measurement Access1.12.1 Path Length Error (after autocalibration) +/-5 ns1.12.2 Input Capacitance <500 pF

2 DC REFERENCE SOURCE FEATURES

2.1 Output protected against sustained short circuit to ground.

2.2 Kelvin Operation on C pin output via D pin connection

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Specs 6 DC Subsystem

NOTES:

1. All measurement specifications apply with the filter on. Filtersettling time may be reduced by leaving the filter off until justbefore making a measurement. This is called "precharging". Timeto settle is typically <1 ms after precharging. Settling time isdependent on noise and signal variations and must be determined foreach application individually.

2. All specifications for voltage accuracy apply at the point theKelvin connection is made. In cases where the Kelvin connectionis made on the channel card rather than at the Device Under Test(DUT), there will be an additional voltage error term which isproportional to the current flowing. The resistance is specifiedfor the path between the channel card internal Kelvin point andthe Iso-Pin(TM).

3. Linear stations on the A520 are specified and checked as an A510.

4. The 100 V Voltmeter is only available when the UBVI100 is alsopresent in the configuration.


DC Subsystem

Main Menu

I DC SUBSYSTEM SPECIFICATION LIST (See Note 3)

1 V-I SOURCE PERFORMANCE SPECIFICATIONS

1.1 Voltage Forcing (See Note 2)1.1.1 Range Resolution Accuracy

(16 BITS)(Nominal)

0.5V 15.63 uV +/-1 mV1V 31.25 uV +/-1 mV2V 62.50 uV +/-(0.05% OR 1 mV) (WHICHEVER IS5V 156.25 uV +/-(0.05% OR 1 mV) GREATER)10V 312.50 uV +/-(0.05% OR 2.5 mV) "20V 625.0 uV +/-(0.05% OR 5 mV) "50V 1.563 mV +/-(0.05% OR 25 mV) "100V 3.125 mV +/-(0.1% OR 50 mV) "200V 6.250 mV +/-(0.1% OR 100 mV) "

1.1.2 Max Voltage Output +/-60 V1.1.3 Max Current Output +/-200 mA1.1.4 Max Allowable Voltage +/-65 V Nominal1.1.5 Maximum Path Resistance 500 milliohms Typical (see note 2)

(channel card to Iso-Pin)

1.2 Voltage Measuring (See note 2)1.2.1 Range Resolution Accuracy

(14 BITS)(Nominal)

0.5V 62.50 uV +/-1 mV1V 125.0 uV +/-1 mV2V 250.0 uV +/-(0.05% OR 1 mV) (WHICHEVER IS5V 625.0 uV +/-(0.05% OR 1 mV) GREATER)10V 1.25 mV +/-(0.05% OR 2.5 mV) "20V 2.50 mV +/-(0.05% OR 5 mV) "50V 6.250 mV +/-(0.05% OR 25 mV) "100V 12.50 mV +/-(0.1% OR 50 mV) "200V 25.00 mV +/-(0.1% OR 100 mV) "(All specs apply with the measurement filter on. See note 1.)

1.2.2 Maximum Operating Voltage +/-60 V min.1.2.3 Maximum Allowable Voltage +/-65 V Nominal1.2.4 Maximum Path Resistance 500 milliohms Typical (see note 2)

(channel card to Iso-Pin)

1.3 Current Forcing1.3.1 Range Resolution Accuracy

(12 BITS)(Nominal) +/- % of Value + Offset + Volt Effect

200mA 100 uA +/-(0.1% + 200 uA)20mA 10 uA +/-(0.1% + 20 uA)2mA 1 uA +/-(0.1% + 2 uA)200uA 100 nA +/-(0.1% + 300 nA + 1 nA/V)20uA 10 nA +/-(0.1% + 120 nA + 1 nA/V)(Matrix, multiplexer, and standard cabling leakage included.)


DC Subsystem

Main Menu

1.4 Current Measuring1.4.1 Range Resolution Accuracy

(14 BITS)(Nominal) +/- % of Reading + Offset + Volt Effect

200mA 25 uA +/-(0.1% + 100 uA)100mA 12.5 uA +/-(0.1% + 50 uA)50mA 6.25 uA +/-(0.1% + 25 uA)20mA 2.5 uA +/-(0.1% + 10 uA)10mA 1.25 uA +/-(0.1% + 5 uA)5mA 625 nA +/-(0.1% + 2.5 uA)2mA 250 nA +/-(0.1% + 1 uA)1mA 125 nA +/-(0.1% + 600 nA + 1 nA/V)500uA 62.5 nA +/-(0.1% + 350 nA + 1 nA/V)200uA 25 nA +/-(0.1% + 200 nA + 1 nA/V)100uA 12.5 nA +/-(0.1% + 150 nA + 1 nA/V)50uA 6.25 nA +/-(0.1% + 125 nA + 1 nA/V)20uA 2.5 nA +/-(0.1% + 110 nA + 1 nA/V)10uA 1.25 nA +/-(0.1% + 105 nA + 1 nA/V)5uA 625 pA +/-(0.1% + 103 nA + 1 nA/V)

1.4.2 Maximum Operating Current 200 mA min.(Matrix, multiplexer, and standard cabling leakage included.)(All specs apply with the measurement filter on. See note 1.)

A. V/I SOURCE SUPPLEMENTAL CHARACTERISTICS

A.1 Four Quadrant Ground Referenced Operation

A.2 Parallel operation of sources for increased current output (up to4 sources in parallel)

A.3 Active Driven Guard System with protection alarm

A.4 Diodes Clamps between Force and Sense lines for protection againstopen Kelvin Operation

A.5 Individual Source Gating, Clearing, and Reset Functions

A.6 Source Diagnostic Modes

A.7 Source Alarms. - Open Loop, Guard, Overload

A.8 Common Device Ground Sense for all sources

A.9 Individual Source Disconnect Function

A.10 Performance of Correction DACs - Offset, Gain, Linearity


DC Subsystem

Main Menu

2 VOLTMETER

2.1 Voltage Measuring:2.1.1 Range Resolution Accuracy

(14 BITS)(Nominal)

0.5V 62.50 uV +/-1 mV1V 125.0 uV +/-1 mV2V 250.0 uV +/-(0.05% OR 1 mV) (WHICHEVER IS5V 625.0 uV +/-(0.05% OR 1 mV) GREATER)10V 1.25 mV +/-(0.05% OR 2.5 mV) "20V 2.50 mV +/-(0.05% OR 5 mV) "50V 6.250 mV +/-(0.05% OR 25 mV) "100V 12.50 mV +/-(0.1% OR 50 mV) "200V 25.00 mV +/-(0.1% OR 100 mV) "(All specs apply with the measurement filter on. See note 1.)

2.1.2 Maximum Measurable Voltage2.1.2.1 60 V Voltmeter Single-ended +/-60 V (Either Input)2.1.2.2 60 V Voltmeter Differential +/-120 V2.1.2.3 100 V Voltmeter Single-ended +/-100 V (Either Input)2.1.2.4 100 V Voltmeter Differential +/-200 V2.1.3 CMRR 80 dB at dc2.1.4 Maximum Allowable Voltage2.1.4.1 60 V Voltmeter +/-65 V w/ respect to Gnd, Nominal2.1.4.2 100 V Voltmeter +/-105 V w/ respect to Gnd, Nominal2.1.5 Input Leakage 10 nA + 1 nA/V max., Typical

(includes matrix, mux and cabling effects)2.1.6 Filter2.1.6.1 0.5,5,50 V ranges 150 Hz (-3 dB) Nominal2.1.6.2 1,10,100 V ranges 270 Hz (-3 dB) Nominal2.1.6.3 2,20,200 V ranges 410 Hz (-3 dB) Nominal

2.2 SAMPLE AND DIFFERENCE2.2.1 Gains Resolution (Nominal) Gain Accuracy + Offset

X1 Same as Measure Range +/-(0.5% + 0.1% F.S.)X10 Measure Range x10 +/-(0.5% + 0.1% F.S.)X100 Measure range x100 +/-(1% + 1% F.S.)

2.2.2 SAD Decay X1 0.1% of FS/10 sX10 0.1% of FS/1 sX100 0.1% of FS/0.1 s

2.3 COMPARATORS2.3.1 Resolution 0.05% of Full Scale Nominal2.3.2 Accuracy +/-0.25% of Full Scale + accuracy of

selected metering function. Typical

B. VOLTMETER SUPPLEMENTAL CHARACTERISTICS

B.1 Two Input Channels - VM1, VM2

B.2 Driven Guard System with output alarm

B.3 Device Ground Sense for meter reference


DC Subsystem

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B.4 Selectable Low Input Impedance - 20K

B.5 Diagnostic Modes - Power supplies, Delta Bus, Internal Temperature

B.6 Alarms - DGS, Guard, Overload

3 MATRIX

3.1 Switching Time 3.5 ms MAX

4 DELTA SOURCE/BUS

4.1 Delta Source V/I Modulation Ranges 2, 20, 200 V

4.2 Delta Source Resolution 0.05% of Full Scale

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Specs 7 Handler/Prober Control Interface

0.1 Handler/Prober Interface Features

0.1.1 True Hardware Readback (DEFAULT = Low True Logic)

0.1.2 FIVE (5) Input Hardware Control Signals:[AutoSS, Reject, Retest, Alarm, and Start]

0.1.3 FOURTEEN (14) Output HARDWARE Control Signals:[BIN0 - BIN11, EOS, and Retest (Input Echoed)]

0.1.4 ALL I/O Signals’ Phase, Logic Levels, and Timing are programmable.ALL I/O Phase (LOW or HIGH True Logic) programmable.(Default=Low)

True)ALL I/O Logic Levels (+5 V or +12 V) programmable.BIN and EOS Timing are Independently programmable for outputsequences up to 1 second duration in 1 ms steps.INPUT group of Signals’ Phase and Logic Levels areindependently programmable from OUTPUT Group of Signals.

0.1.5 ALL inputs from Remote Handler/Prober are debounced through RC filtersconsisting of an Input series Resistor (47 Kohm) shunted toground via a 0.01 uF Capacitor.

0.1.6 ALL Input thresholds between -0.6 V and +5.6 V, are protected viaclamping diodes after the filter.

0.1.7 ALL inputs are "pulled up" to 5 V via 12 Kohm resistors.

0.1.8 Output Signals are gated via SAFETY* signal.


Handler/Prober Control Interface

Main Menu

1. REMOTE HANDLER/PROBER INTERFACE SPECIFICATIONS

1.1 INPUT SPECIFICATIONS1.1.1 Input "HIGH" Level Range = 3 V to 30 V.1.1.2 Signal duration = 1 ms minimum.1.1.3 Input Current requirements(nominal) for various "HIGH" Input Voltage

Levels. (Currents into the Tester are considered positive.)Input Voltage Current

0 V -400 uA typical5 V +/-20 uA typical

12 V +700 uA typical24 V +2.0 mA typical30 V +2.6 mA typical

1.1.4 Logic State Voltage0 <1.2 V1 >1.9 V

1.1.5 Maximum Input Voltage = +30 V1.1.6 Minimum Input Voltage = -0.6 V

1.2 OUTPUT SPECIFICATIONS1.2.1 LOW Output: Vout-Lo(VoL), bit set to 1-Low True Logic.

VoL < 0.3 V @ Isink = 8 mAVoL < 1.0 V @ Isink = 50 mA

1.2.1.1 Maximum Short Circuit Current when Vout-Lo shorted to Vcc.Nominal Sinking current @ +5 V or +12 V Rail = 60 mA.Maximum short circuit duration = 1 second.

(RETEST OUTPUT = 20 mA nominal Sinking @ either +5 V/+12 V Rail)1.2.2 HIGH Output: VoH (Vout-Hi, +5 V Rail, bit set to 1-High True Logic)

VoH > 4.6 V @ Isource = 0 uAVoH > 3.9 V @ Isource = 500 uAVoH = 4.4 V typical

1.2.2.1 IosH (Short Circuit Current @ Vout-Hi)4.0 mA nominal Sourcing @ +5 V Rail

1.2.3 HIGH Output: VoH (Vout-Hi, +12 V Rail, bit set to 1-High True Logic)VoH > 10.9 V @ Isource = 0 uAVoH > 10.2 V @ Isource = 500 uAVoH = 10.8 V typical

1.2.3.1 IosH (Short Circuit Current @ Vout-Hi)9.5 mA nominal Sourcing @ +12 V Rail

1.3 OUTPUT TIMING SPECIFICATIONS1.3.1 EOS and BIN Signals are Independently programmable up to a period of

1 second in 1 ms steps.[Up to 1000 events (each event = 1 ms) with 1 ms resolution]

1.3.2 Timing Accuracy = +/-20%

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Specs 8 High Current Current Source

NOTES:

NOTE 1 Pulsed specifications are guaranteed for duty cycles less than 10%.Exceeding specifications may result in an instrument shutdownduring power pulse.

NOTE 2 Specification is guaranteed for an output current between 30%of full-scale and full scale.

NOTE 3 Sinking power quadrant programming conditions must not exceedeither the maximum current or the maximum power specification.Exceeding either parameter may result in permanent instrument damage.

NOTE 4 Measured over a 10 Hz to 1 MHz bandwidth.

NOTE 5 Measurement resolution is determined by the system resource usedfor analog-to-digital conversion of the measurement bus signal.The standard system VM is the default converter used to capturea measurement. Its specifications can be found in the standardDC subsystem ESSD. In general, measurement accuracy is limitedby gain and offset errors. Meter resolution is not a significantportion of the measurement uncertainty.

NOTE 6 Voltage clamp settling time depends on current programmingconditions. Typical numbers apply for a 20% overcurrent.

NOTE 7 The voltage/current compliance specification is defined asfollows. The current is the maximum current that may be programmedfor the specified duration without damaging the instrument.The voltage is supplied as a typical number for the maximumvoltage that can be sustained across the load with the maximumcurrent flowing.



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I. HIGH CURRENT CURRENT SOURCE INSTRUMENTATION SPECIFICATIONS

0. HCCS Features

0.1 Forcing Current Source0.1.1 Measure Voltage0.1.2 Voltage Clamp with automatic crossover0.1.3 Sink Power (Load Mode)0.1.4 Programmable ON and OFF States0.1.5 Modulation Capability/Modulation Bus Access

0.2 General Features0.2.1 Instrument Safety Interlock0.2.2 Safety Fault Shutdown Sequencer0.2.3 Floating 4 Wire Kelvin Output0.2.4 Image(tm) Programming Language


0.4 Output Delivery Systems0.4.1 Two Station Multiplexer0.4.2 High Power Matrix (HPM) Access0.4.3 AL Test Head Access

0.5 Internal Protection0.5.1 Heat Sink Thermal Shutdown0.5.2 Junction Thermal Protection0.5.3 Sense Overload Shutdown0.5.4 Over Voltage Shutdown0.5.5 Over Current Relay Protection0.5.6 Open loop indicator0.5.7 SPS Shutdown

0.6 Measurement Alarms0.6.1 Heat Sink Thermal Shutdown0.6.2 Junction Thermal Protection0.6.3 Sense Overload Shutdown0.6.4 Over Voltage Shutdown0.5.5 Over Current Relay Protection0.6.6 Open loop indicator0.6.7 SPS Shutdown

1. HCCS Forcing Current Source Specifications


Range Resolution Accuracy----- ---------------- -----------------

1.1.1 1 A 30.5 uA (nominal) +/-(0.5% + 5 mA)1.1.2 5 A 152.5 uA (nominal) +/-(0.5% + 12.5 ma)1.1.3 10 A 305 uA (nominal) +/-(0.5% + 25 mA)1.1.4 100 A 3.05 mA (nominal) +/-(0.5% + 250 mA)



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1.2 Maximum Programmable Output Voltage1.2.1 Load Mode -30 V -> 100 V1.2.2 Source Mode 0 V -> 30 V

1.3 Maximum Programmable Output Current 100 A

1.5 Compliance Points (Notes 1 and 7)

Sourcing Power QuadrantRange/Mode Voltage(typical)/ Current(nominal)(nominal) DC 100 ms 1 ms

--------- -------- -------- -------1.5.1 30 V source 25 V/15 A 17 V/50 A 14 V/100 A1.5.2 -30 V load -25 V/15 A -17 V/50 A -14 V/100 A

Sinking Power Quadrant (Load Mode) (Note 3)Power Limit (nominal)

DC 100 ms 10 ms 1 ms----- ----- ----- -----

1.5.4 0 V compliance 400 W 1.8 kW 2.9 kW 3.2 kWMax. Current 25 A 50 A 50 A 100 A

1.6 Settling Time (Note 2)1.6.1 to specification <500 us (resistive)1.6.2 at 100 us +/-3% of final value (resistive)

1.7 Voltage Clamp Response Time 50 us for a 20% over voltage typical

1.8 Periodic and Random Deviations (PARD) (Note 4, typical)1.8.1 Current <0.025% FS rms <0.15% FS p-p1.8.2 Voltage <50 mV rms <300 mV p-p

1.9 StabilityThe HCCS will settle into any realor first order inductive load withinthe compliance specifications.Settling time may be limited by slewrate or overshoot. Voltage settlinginto a capacitor not recommended.

2. HCCS Current Measurement Specifications

2.1 Accuracy

Resolution see DC subsystem specifications (Note 5)


2.1.1 1 A +/-(0.5% + 5 mA)2.1.1 5 A +/-(0.5% + 12.5 mA)2.1.2 10 A +/-(0.5% + 25 ma)2.1.3 100 A +/-(0.5% + 250 mA)

2.2 Ammeter noise <0.1% of range p-p typical



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2.3 Maximum allowable Current FS value limited by current clamp

3. HCCS Voltage Clamp Specifications


Vrange Resolution Accuracy (typical)------ ------------- ---------------

3.1.1 100 V 12.5 mV (nominal) +/-[1.5% + 1 V + 1.5 V*(Iactual/Irange)]

3.5 Settling Time (Note 6)3.5.1 to specification <100 us typical3.5.2 at 50 us +/-3% of final value typical

3.7 Periodic and Random Deviations (PARD) (note 4)<1 mA rms <6 mA p-p typical

3.8 StabilityThe HCCS will settle into any realor first order inductive load withinthe compliance specifications.Settling time may be limited by slewrate or overshoot. Voltage settlinginto a pure capacitance is unspecified.

4.0 HCCS Voltage Measurement Specifications

4.1 Accuracy

Resolution see DC subsystem specifications (Note 5)


4.1.1 2 V +/-(0.5% + 5 mV)4.1.2 10 V +/-(0.5% + 10 mv)4.1.3 20 V +/-(0.5% + 20 mV)4.1.4 100 V +/-(0.5% + 100 mV)

4.2 Voltmeter noise <0.1% FS p-p typical

4.3 Maximum Allowable Voltage4.3.1 100 V range 1000 V, nominal4.3.2 20 V range 200 V, nominal4.3.3 10 V range 100 V, nominal4.3.4 2 V range 20 V, nominal

7. HCCS Miscellaneous Specifications7.1 Output Connect time <50 ms nominal7.2 Output Disconnect time <50 ms nominal7.3 Trigger Delay 30 us +/- 20 us



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7.4 Maximum Output Voltage (not to exceed)7.4.1 Disconnected7.4.1.1 Any output to chassis 1000 V Common Mode nominal7.4.1.2 Between any input 1000 V Differential nominal7.4.2 Connected7.4.2.1 (any output to chassis) 1000 V Common Mode nominal7.4.2.2 Between any output - source mode 0 V < Vout <30 V nominal7.4.2.3 Between any output - load mode -30 V < Vout < 100 V nominal

7.5 Kelvin Performance Allowable F-S Separation at user area7.5.1 Direct output 2.0 V nominal7.5.2 Matrixed Output 1.5 V nominal

7.6 Modulation Accuracy +/-1.0% nominal

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Main Menu

Specs 9 High Current Unit

I HCU SPECIFICATION LIST

1 V-I SOURCE PERFORMANCE SPECIFICATIONS1.1 Voltage Forcing:1.1.1 Range Resolution Accuracy

(14 bits)(Nominal)

2 V 250 uV +/-(0.1% + 1.5 mV)30 V 3.75 mV +/-(0.1% + 15 mV)

1.1.2 Max Voltage Output +/-30 V (see A.1)1.1.3 Max Current Output +/-2 A (Note 1,see A.1)

1.2 Voltage Measuring1.2.1 Range Resolution Accuracy

(14 bits)(Nominal)

2V 250uV +/-(0.1% + 1.5mV)30V 3.75mV +/-(0.1% + 15mV)

1.2.2 Maximum Operating Voltage +/-30 V (see A.1)

1.3 Current Forcing1.3.1 Range Resolution Accuracy

(12 bits)(Nominal)

20 mA 5 uA +/-(0.1% + 20 uA)200 mA 50 uA +/-(0.1% + 200 uA)

2 A 500 uA +/-(0.2% + 2 mA)

1.3.2 Maximum Output Current +/-2 A (Note 1,see A.1)

1.4 Current Measuring1.4.1 Range Resolution Accuracy

(14 bits)(Nominal)

20 mA 5 uA +/-(0.1% + 20 uA)200 mA 50 uA +/-(0.1% + 200 uA)2 A 500 uA +/-(0.2% + 2 mA)

(All specs apply with the measurement filter on.)


High Current Unit

Main Menu

1.4.2 Maximum Operating Current +/-2 A (Note 1,see A.1)Note 1: LIMITATIONS:

HCU used through system MATRIX: 1 A MAXThis includes:

A520 Test Head at the DIBA510AL Test Head at the DIBA510 Systems at the J1-J4 Bulkhead connectors

HCU as a DUTSRC (DUTSRC 2,3,4, ONLY): 1 A MAXWhen used in the:

A520 Test Head at the DIBA510 System at the J1-J4 Bulkhead connectors

HCU as a DUTSRC (DUTSRC 2,3,4 ONLY): 2 A MAXWhen used in the:

A510AL Test Head with DUTHCU cable installedA510 System at the HCU Bulkhead connectors


High Current Unit

Main Menu

A. HCU SUPPLEMENTAL CHARACTERISTICS

A.1 Four Quadrant Ground Reference Operation, however 2nd and4th Quadrants have the limitation as below.

| +I|| +2 A ----------

/| |/ | |

/ | |/ | |

/ | |/ | |

/ | |/ | |

/ | |/ | |

/ | |/ | |

/ | |/ | |

/ | |/ | |

-V ----------------------------------------- +V-30 V | | / +30 V

| | /| | /| | /| | /| | /| | /| | /| | /| | /| | /| | /| | /| | /| |/----------------| -2 A

|-I

A.2 Active Driven Guard System with protection alarm

A.3 Diode Clamps between Force and Sense lines for protection againstopen Kelvin Operation

A.4 Individual Source Gating, Clearing, and Reset Functions

A.5 Alarm -- Over load, Guard

A.6 Common Device Ground sense for all sources

A.7 Individual Source Disconnect Function


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Specs 10 High Current Voltage Source

NOTES:

1 Pulsed specifications are guaranteed for duty cycles less than 10%.Exceeding specifications may result in an instrument shutdownduring power pulse.

2 Optimum range means that the specification is guaranteed for aspecified portion of the voltage range.

3 Full range means that the specification is guaranteed for anyoutput voltage within the compliance range. The compliance range isnot the nominal range but a range between 0 and the specifiedcompliance.

4 The V/I compliance of forcing voltage source in the power sinkquadrant is limited by a load line of specified resistance.

5 Measured over a 10 Hz to 1 MHz Bandwidth.

6 Measurement resolution is determined by the system resource usedfor Analog-to-Digital conversion of the measurement bus signal.The standard system VM is the default converter used to capture ameasurement. Its specifications can be found in the standard DCsubsystem ESSD. In general, measurement accuracy is limited by gainand offset errors. Meter resolution is not a significant portionof the measurement uncertainty.



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I - HCVS SPECIFICATION LIST

0. HCVS Features

0.1 Forcing Voltage Source0.1.1 Measure Current0.1.2 Current Clamp with automatic crossover0.1.3 Sink Power (discharge C)0.1.4 Programmable ON and OFF States0.1.5 Modulation Capability / Modulation Bus Access0.1.6 Two Compensation settings

0.2 General Features0.2.1 Instrument Safety Interlock0.2.2 Safety Fault Shutdown Sequencer0.2.3 Floating 4 Wire Kelvin Output0.2.4 IMAGE Programming Language



0.5 Internal Protection0.5.1 Heat Sink Thermal Shutdown0.5.2 Junction Thermal Shutdown0.5.3 Open Kelvin/Sense Overload Shutdown0.5.4 Over Current Relay Protection0.5.5 Open loop indicator0.5.6 SPS Shutdown

0.6 Measurement Alarms0.6.1 Heat Sink Thermal Shutdown0.6.2 Junction Thermal Shutdown0.6.3 Open Kelvin/Sense Overload Shutdown0.6.4 Over Current Relay Protection0.6.5 Open loop indicator0.6.6 SPS Shutdown

1. HCVS Forcing Voltage Source Specifications


Range Resolution Accuracy----- ----------------- ------------------

1.1.1 30 V 1.83 mV (nominal) +/-(0.5% + 150 mV)1.1.2 60 V 1.83 mV (nominal) +/-(0.5% + 150 mV)1.1.3 90 V 1.83 mV (nominal) +/-(0.5% + 150 mV)1.1.4 120 V 1.83 mV (nominal) +/-(0.5% + 150 mV)

1.2 Maximum Programmable Output Voltage 120 V



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1.4 Optimum Range Compliance Points (Notes 1, and 2)

Sourcing Power QuadrantRange Compliance Range / Compliance Current

(nominal) dc 100 ms 1 ms--------- ------------- ----------- ------------

1.4.1 30 V 8-25V / 15A 0-10V / 50A1.4.2 60 V 15-50V / 8A 0-30V / 40A 10-40V / 85A1.4.3 90 V 20-80V / 5A 0-40V / 30A 20-70V / 60A1.4.4 120 V 45-110V / 4A 5-65V / 20A 30-100V / 35A

1.5 Full Range Compliance Points (Notes 1, 3, and 4)

Sourcing Power QuadrantRange Full Scale Range / Full Range Compliance

(nominal) dc 100 ms 10 ms 1 ms--------- --------- --------- --------- ----------

1.5.1 30 V 25V / 12A 15V / 40A 15V / 50A 12V / 100A1.5.2 60 V 50V / 6A 35V / 30A 40V / 40A 45V / 65A1.5.3 90 V 80V / 3A 60V / 15A 70V / 20A 75V / 40A1.5.4 120 V 110V / 2A 95V / 8A 100V / 12A 110V / 25A

1.5.5 Sinking Power Compliance 10 ohm / 300 W average

1.6 Settling Time1.6.1 to specification <500 us (non-reactive)1.6.2 at 100 us +/-3% of final value (non-reactive)

1.7 Current Clamp Response Time 200 us for a 20% overcurrent

1.8 Periodic and Random Deviations (PARD) (note 5)1.8.1 <50 mV rms1.8.2 <300 mV p-p

1.9 Stability The HCVS will settle into any realor first order reactive load withinthe compliance specifications.Settling time may be limited by slewrate or overshoot.

2. HCVS Current Measurement Specifications

2.1 Accuracy

Resolution see DC subsystem specifications (note 6)


2.1.1 100 A +/-(1.0% + 250 mA)2.1.1 10 A +/-(1.0% + 25 mA)2.1.2 1 A +/-(1.0% + 5 mA)



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2.2 Ammeter noise <1% of range p-p

2.3 Ammeter settling time2.3.1 to specification <500 us2.3.2 at 100 us +/-5% of final value

2.4 Maximum allowable Current FS value limited by current clamp

3. HCVS Current Clamp Specifications


Irange Resolution Accuracy------ --------------- ------------------

3.1.1 100 A 25 mA (nominal) +/-(1.5% + 250 mA)

3.5 Settling Time3.5.1 to specification <1 ms3.5.2 at 100 us +/-3% of final value

3.7 Periodic and Random Deviations (PARD) (note 5)3.7.1 < 1 mA rms3.7.2 < 6 mA p-p

3.8 Stability The HCVS current clamp will settleinto any reasonable real or firstorder reactive load within thecompliance specifications.Settling time may be limited by slewrate or overshoot.

4. HCVS Voltage Measurement Specifications

4.1 Accuracy



4.1.1 150 V +/-(0.5% + 150 mV)

4.2 Voltmeter noise <60 mVp-p<10 mVrms

4.3 Voltmeter settling time <100 us

4.4 Maximum Allowable Voltage 1200 V Nominal

7. HCVS Miscellaneous Specifications7.1 Output Connect time <50 ms7.2 Output Disconnect time <50 ms7.3 Trigger Delay 30 us +/- 10 us



Main Menu

7.4 Maximum Output Voltage(any output to chassis) 1000 V

7.5 Kelvin Performance(Allowable F-S Separation)

7.5.1 Direct output 2.0 V7.5.2 Matrixed Output 1.5 V7.5.3 AL Test head Output 1.0 V

7.6 Modulation Accuracy +/-1.0%

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Main Menu

Specs 11 High Frequency Digitizer

1. HIGH FREQUENCY AC DIGITIZER SPECIFICATIONS

A. Customer Level Specifications

1.1 General Specifications (Apply to all Frequency Ranges)(NOTE: All specifications including those that are Frequency Rangespecific assume that the signal being digitized is between fullscale and half scale of the selected range.)

1.1.1 Peak Input Voltage (AC + DC) +/-20.0 V max.1.1.2 AC p-p Input Voltage 16.384 V max.1.1.3 AC Waveform Amplitude Ranges 8.192 V peak

4.096 V peak2.048 V peak1.024 V peak512 mV peak256 mV peak128 mV peak64 mV peak32 mV peak16 mV peak8 mV peak

1.1.4 Input Capacitance <80 pF typ.1.1.5 Input Resistance Accuracy @ DC

50 ohm +/-2%10k ohm +/-5%

1.1.6 DC Offset Without Autocal

Amplitude Range DC Offset--------------- ---------8.192 V peak +/-160 mV RTI4.096 V peak +/-80 mV RTI2.048 V peak +/-40 mV RTI8.0 mV - 1.024 V peak +/-20 mV RTI

1.1.7 DC Offset With Autocal (NOTE: Requires "dccal: on "to be selected)

Amplitude Range DC Offset--------------- ---------8.192 V peak +/-16 mV RTI4.096 V peak +/-8 mV RTI2.048 V peak +/-4 mV RTI8.0 mV - 1.024 V peak +/-2 mV RTI



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1.1.8 DC Offset Drift 500 uV/C nominal1.1.9 Programmable DC Baseline Removal

Range +/-12.288 VResolution 6 mV(12 bits)Accuracy +/-(.1% FSR + 10 mV)Settling Time for 24 V Change 5 ms to 0.1% of

final value nominal1.1.10 Settling Time for 4.0 V Step to 1% of Step 100 ns typ.

(NOTE: The above specification for settling time assumes no anti-aliasing filter is selected.)

1.1.11 Overvoltage Recovery Time 300 ns nominal(Need to spec conditions.)

1.1.12 Sample Rate Range 600 kHz min.- 20 MHz max.1.1.13 Dynamic AC Gain 20 dB +/- 0.5 dB

to 1.0 MHz1.1.14 High Pass Filter

Stop Band End 128 kHz min.Pass Band Start 256 kHz min.Pass Band Gain 20 dB +/- 0.5 dBStop Band Attenuation 20 dB min.

1.1.15 Waveform Digitizing Resolution 12 bits1.1.16 Overvoltage Alarm Detection Threshold +/-1.024 V peak nom.1.1.17 Time Measurement Access1.1.17.1 Path Length Error (after autocalibration) +/-5 ns1.1.17.2 Input Capacitance <500 pF

1.2 FREQUENCY RANGE I 100 Hz - 1 MHz1.2.1 Sine Wave Amplitude Accuracy

Amplitude INPUT Z MODE ACCURACY--------- ------------ ---------4.097 V peak - 8.192 V peak 10 kohm +/-0.5 dB

50 ohm +/-0.5 dB2.049 V peak - 4.096 V peak 10 kohm +/-0.4 dB

50 ohm +/-0.4 dB8.0 mV peak - 2.048V peak 10 kohms +/-(0.30 dB +1.0 mV rms)

50 ohm

1.2.2 Sine Wave Harmonics(2nd & 3rd)

Amplitude Harmonic Level--------- --------------4.097 V peak - 8.192 V peak -50 dB2.049 V peak - 4.096 V peak -55 dB129 mV peak - 2.048 V peak -60 dB8.0 mV peak - 128 mV peak 91 uV rms max.

1.2.3 Sine Wave Spurious Responses (BW = 100 Hz - 5 MHz)

Amplitude Spurious Level--------- --------------2.049 V peak - 8.192 V peak -50 dB257 mV peak - 2.048 V peak -60 dB8.0 mV peak - 256 mV peak 181 uV rms max.



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1.2.4 Noise Density (BW = 30 kHz)(NOTE: Applicable over a BW = 100 Hz - 5 MHz)

AMPLITUDE RANGE S/N RATIO--------------- ---------8.192 V peak >77 dB4.096 V peak >77 dB2.048 V peak >75 dB1.024 V peak >73 dB512 mV peak >69 dB256 mV peak >63 dB128 mV peak >57 dB64 mV peak >51 dB32 mV peak >45 dB16 mV peak >39 dB8 mV peak >33 dB

1.2.5 Anti-Aliasing Filter Characteristics

Filter Stop Band Start Frequency Stop Band Attenuation------ ------------------------- ---------------------400 kHz 600 kHz max. -50 dB min. to 30 MHz2.0 MHz 3.0 MHz max. -50 dB min. to 30 MHz

(NOTE: The frequencies under the filter column represent thefrequencies where the above guaranteed level accuracies end. THEY ARENOT THE -3 dB FREQUENCIES.)

1.3 FREQUENCY RANGE II 1 MHz - 5 MHz1.3.1 Sine Wave Amplitude Accuracy

Amplitude Input Z Mode Accuracy--------- ------------ --------8.0 mV peak - 8.192 V peak 10 kohm +/-(0.5 dB + 1 mV rms)

50 ohm

1.3.2 Sine Wave Amplitude Accuracy - Production Analog Test Head (PATH)

Amplitude Input Z Mode Accuracy--------- ------------ --------8.0 mV peak - 8.192 V peak 10 kohm +/-(0.75 dB + 1 mV rms)

50 ohm


Amplitude Harmonic Level--------- --------------4.097 V peak - 8.192 V peak -40 dB2.049 V peak - 4.096 V peak -45 dB129 mV peak - 2.048 V peak -50 dB8.0 mV peak - 128 mV peak 288 uV rms max.



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Amplitude Spurious Level--------- --------------4.097 V peak - 8.192 V peak -40 dB2.049 V peak - 4.096 V peak -45 dB129 mV peak - 2.048 V peak -50 dB8.0 mV peak - 128 mV peak 288 uV rms max.




Filter Stop Band Start Frequency Stop Band Attenuation------ ------------------------- ---------------------2.0 MHz 3.0 MHz max. -50 dB min. to 30 MHz3.6 MHz 5.4 MHz max. -50 dB min. to 30 MHz6.1 MHz (see 2.3.6) 9.15 MHz max. -50 dB min. to 30 MHz10.0 MHz 15.0 MHz max. -50 dB min. to 30 MHz

(NOTE: The frequencies under the filter column represent thefrequencies where the above guaranteed level accuracies end. THEY ARENOT THE -3 dB FREQUENCIES.)

1.3.7 Group Delay of 6.1 MHz Filter <10 ns up to 4.4 MHz typ.1.3.8 NTSC Video Waveform Specifications

Differential Gain +/-0.5% max.Differential Phase +/-0.5 degrees max.

1.4 FREQUENCY RANGE III 5 MHz - 9.5 MHz

1.4.1 Sine Wave Amplitude Accuracy

1.4.1.1 Advanced Linear & Advanced Mixed-Signal Test Heads1.4.1.1.1 Frequency = 5 MHz - 7.5 MHz

Amplitude Input Z mode Accuracy--------- ------------ ----------8.0 mV peak - 8.192 V peak 10 kohm +/-(1.0 dB +1 mV rms)

50 ohm



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1.4.1.1.2 Frequency = 7.5 MHz - 9.5 MHz


50 ohm +/-(1.0 dB +1 mV rms)

1.4.1.2 Production Analog Test Head(PATH)1.4.1.2.1 Frequency = 5 MHz - 7.0 MHz


50 ohm

1.4.1.2.2 Frequency = 7.0 MHz - 9.5 MHz

Amplitude Input Z mode Accuracy--------- ------------ ----------2.049 V peak - 8.192 V peak 10 kohm +/-(1.75 dB +1 mV rms)

50 ohm +/-(1.5 dB +1 mV rms)8.0 mV peak - 2.048 V peak 10 kohm +/-(2.0 dB +1 mV rms)

50 ohm +/-(1.0 dB +1 mV rms)


Amplitude Harmonic Level---------- --------------2.049 V peak - 4.096 V peak -40 dB129 mV peak - 2.048 V peak -45 dB8.0 mV peak - 128 mV peak 512 uV rms max.


Amplitude Spurious Level--------- --------------2.049 V peak - 4.096 V peak -40 dB129 mV peak - 2.048 V peak -45 dB8.0 mV peak - 128 mV peak 512 uV rms max.





Main Menu


Filter Stop Band Start Frequency Stop Band Attenuation------ ------------------------- ---------------------6.1 MHz (see 2.3.6) 9.15 MHz max. -50 dB min. to 30 MHz10.0 MHz 15.0 MHz max. -50 dB min. to 30 MHz(NOTE: The frequencies under the filter column represent thefrequencies where the above guaranteed level accuracies end. THEY ARENOT THE -3dB FREQUENCIES.)

1.5 HIGH FREQUENCY AC DIGITIZER FEATURES

1.5.1 Unbalanced Differential Test Head to Mainframe Transmission

1.5.2 Input protected against sustained +/-60 V overvoltage.

1.5.3 Monitoring port before the A/D (after the anti-aliasing filters)section of signal path in the mainframe.

1.5.4 Parity generation for the data going to the CMEM.

1.5.5 Overvoltage input alarm sent to the CMEM with the waveform samples asmeasured at the A/D input.

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Main Menu

Specs 12 High Power Matrix

NOTES:

NOTE 1 Measurement resolution is determined by the system resource usedfor analog-to-digital conversion of the measurement bus signal.The standard system VM is the default converter used to capturea measurement. Its specifications can be found in the standardDC subsystem ESSD. In general, measurement accuracy is limitedby gain and offset errors. Meter resolution is not a significantportion of the measurement uncertainty.

NOTE 2 High Power Matrix pins must be programmed in parallel and connectedin parallel at the device area for currents greater than per-pinspecifications (up to the maximum spec listed).

NOTE 3 Pulsed specifications are guaranteed for duty cycles less than 10%with a period of less than 10 ms. Exceeding specifications may resultin permanent damage to relay contacts.

NOTE 4 Specifications apply from the input of the HPM to the end of thestandard linear delivery system or to the beginning of the AdvancedLinear/Advanced Mixed-Signal delivery system, whichever is appropriate.The test head delivery system begins at the SPS AL Disconnect Card.

NOTE 5 OVP may be disabled at user's discretion for reduced leakage, butthis is not currently implemented due to safety considerations.

OVP Over Voltage Protection (SCR crowbar - both polarities).


High Power Matrix

Main Menu

I. HIGH POWER MATRIX INSTRUMENTATION SPECIFICATIONS

0. HPM Features

0.1 Two Station Multiplexer

0.2 Four lines by 12 pins per HPM Module0.2.1 All lines withstand maximum voltage0.2.2 Lines 1 and 2 are designated high current lines (10 A per pin)0.2.3 Lines 3 and 4 are designated medium current lines (5 A per pin)

0.3 Expandable to 24 pins per SPS/UB card cage (two HPM modules)

0.4 The High Voltage Ammeter (HVA) can be parallel connected or serialconnected to certain hp_lines via a system connection from theHVA to the HPM

0.5 Connection to Standard DC Matrix0.5.1 Non-Universal Backplane based systems:0.5.1.1 Force/Sense/Guard connections made on a pin per pin basis.

(DC XPT 1 connects only to hp_xpt 1, etc.)0.5.1.2 Maximum number of connections equal to whichever is less: the

number of hp_xpts or dc_xpts present in the system.0.5.2 Universal Backplane based systems:0.5.2.1 Force/Sense/Guard connections can be between any hp_xpt

and the standard DC lines 1-8.0.5.2.2 Maximum number of connections is equal to the number of hp_xpts

present in the system.

0.6 Safety Features0.6.1 Safety signal must be grounded to make any connections in HPM0.6.2 Triggering of SPS_Shutdown signal in the event of an attempted

unsafe connection.0.6.3 Non-Universal Backplane based systems:0.6.3.1 All connections to standard DC matrix

(force/sense/guard for all hp_xpts) fused at maximum current0.6.3.2 OVP on all pins0.6.4 Universal Backplane based systems:0.6.4.1 All connections to standard DC matrix

(force/sense/guard for all hp_xpts) fused at maximum current0.6.4.2 OVP on all pins0.6.4.3 Triggering of SPS_Shutdown in the event of a crowbar alarm.

1. HPM Current Specifications (Notes 2, 3, 4)

1.1 High Current Lines 1 and 21.1.1 Maximum Current per Pin 10 A, continuous1.1.2 Maximum Current per Pin (Note 3) 20 A, pulsed1.1.3 Maximum Operating Current (Note 2) 40 A, continuous1.1.4 Maximum Operating Current (Notes 2, 3) 80 A, pulsed

1.2 Medium Current Lines 3 and 4 (Notes 2, 3, 4)1.2.1 Maximum Current per Pin 5 A, continuous1.2.2 Maximum Current per Pin (Note 3) 10 A, pulsed1.2.3 Maximum Operating Current (Note 2) 20 A, continuous


High Power Matrix

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1.2.4 Maximum Operating Current (Notes 2, 3) 40 A, pulsed

2. HPM Voltage Specifications (all Lines and Pins)

2.1 Maximum Voltage2.1.1 Line or Pin to ground, non-switching +/-1000 V, nominal2.1.2 Force to guard, non-switching +/-200 V, nominal

3. HPM Switching Specifications (all Lines and Pins)

3.1 Maximum Switching Speed 2.0 ms, nominal3.2 Switching voltage/current cannot exceed:3.2.1 Max switching current 1 A, nominal3.2.2 Max switching voltage 50 V, nominal3.2.3 Max switching power 10 VA, nominal

4. HPM DC Matrix Interface Specifications

4.1 Non-Universal Backplane based Systems4.1.1 Maximum Current per xpt, non-switching 1 A, nominal4.1.2 Max Allowable Voltage +/-60 V, nominal4.1.3 Max Leakage at 60 V < +/-10 uA4.1.4 Max Allowable Voltage, OVP off +/-200 V, nominal4.1.5 Max Leakage at 60 V, OVP off < +/-1 uA, typical

4.2 Universal Backplane based Systems4.2.1 Current Specifications4.2.1.1 Maximum Current, non-switching 2 A, nominal4.2.1.2 Force Fuse rating 2 A, nominal4.2.1.3 Sense/Guard Fuse rating 1 A, nominal4.2.2 Voltage Specifications4.2.2.1 Max Allowable Voltage +/-60 V, nominal4.2.2.2 Max Allowable Voltage, OVP off +/-200 V, nominal4.2.3 Switching Specifications4.2.3.1 Switching speed 2 ms, nominal4.2.3.2 Switching voltage/current cannot exceed:4.2.3.3 Max switching current 10ma, nominal4.2.3.4 Max switching voltage 30V, nominal4.2.3.5 Max switching power 300mW, nominal4.2.4 Leakage Specifications

(DC Matrix, HPM, and standard cabling errors included)4.2.4.1 Max Leakage at 60 V < +/-15 uA4.2.4.2 Max Leakage at 60 V, OVP off < +/-2 uA4.2.5 OVP Specifications4.2.5.1 OVP activation point 67 V, nominal4.2.5.2 Activation time, Current > 40 mA 1 us, nominal4.2.5.3 Voltage Clamp Value, Current < 40 mA 67 V, nominal

5. HPM Leakage Specifications

5.1 Max Leakage at +/- 1000V, with active guard < +/-10 uA, typical(HPM, and standard cabling errors included)


High Power Matrix

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6. HPM Path Resistance Specifications

6.1 HPM Instrument to SPS bulkhead 300 mohms, max, nominal(round trip - HPM, standard cabling errors included)

6.2 Standard DC Matrix to SPS bulkhead6.2.1 Non-Universal Backplane based Systems 300 mohms, max, nominal

(AD819, HPM, standard cabling errors included)6.2.2 Universal Backplane based Systems 500 mohms, max, nominal

(AD751, HPM, standard cabling errors included)

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Main Menu

Specs 13 High Power V/I Source

NOTES:

1 Pulsed specifications are guaranteed for duty cycles less than 10%.Exceeding specifications may result in an instrument shutdownduring power pulse.

2 Optimum range means that the specification is guaranteed for anoutput voltage between 40% of full-scale and full scale.

3 Full range means that the specification is guaranteed for anyoutput voltage within the range. The forcing voltage range isdefined between 2V and full scale.

4 The forcing voltage compliance V/I region is specified by a loadline resistance in the power sinking quadrant. The current will beless than the voltage on the source output divided by the statedresistance.

5 Measured over a 10 Hz to 1 MHz Bandwidth.

6 Measurement resolution is determined by the system resource usedfor Analog-to-Digital conversion of the measurement bus signal.The standard system VM is the default converter used to capture ameasurement. Its specifications can be found in the standard DCsubsystem ESSD. In general, measurement accuracy is limited by gainand offset errors. Meter resolution is not a significant portionof the measurement uncertainty.

7 Settling time is specified for output values between 5% and 100% ofrange.



Main Menu

I - HPVI SPECIFICATION LIST

0. HPVI Features

0.1 Forcing Voltage Source0.1.1 Measure Current0.1.2 Current Clamp with automatic crossover0.1.3 Sink Power (discharge C)0.1.4 Programmable ON and OFF States0.1.5 Modulation Capability / Modulation Bus Access0.1.6 Current Measurement Range is Independent of Current

Limit0.1.7 Two Compensation settings

0.2 Forcing Current Source0.2.1 Measure Voltage0.2.2 Voltage Clamp with automatic crossover0.2.3 Programmable ON and OFF States0.2.4 Two Compensation settings

0.5 General Features0.5.1 Instrument Safety Interlock0.5.2 Safety Fault Shutdown Sequencer0.5.3 Floating 4 Wire Kelvin Output0.5.4 IMAGE Programming Language



0.8 Internal Protection0.8.1 Heat Sink Thermal Shutdown0.8.2 Junction Thermal Shutdown0.8.3 Open Kelvin Shutdown0.8.4 Over Current Relay Protection0.8.5 Open loop indicator0.8.6 SPS Shutdown

0.9 Measurement Alarms0.9.1 Heat Sink Thermal Shutdown0.9.2 Junction Thermal Shutdown0.9.3 Open Kelvin Shutdown0.9.4 Over Current Relay Protection0.9.5 Open loop indicator0.9.6 SPS Shutdown



Main Menu

1. HPVI Forcing Voltage Source Specifications


Range Resolution Accuracy----- ---------------- -----------------

1.1.1 85 V 6.25 mV (nominal) +/-(0.5% + 250 mV)1.1.2 170 V 6.25 mV (nominal) +/-(0.5% + 250 mV)1.1.3 255 V 12.5 mV (nominal) +/-(0.5% + 500 mV)1.1.4 340 V 12.5 mV (nominal) +/-(0.5% + 500 mV)1.1.5 510 V 12.5 mV (nominal) +/-(1.0% + 1.0 V)1.1.6 750 V 12.5 mV (nominal) +/-(1.0% + 1.0 V)



1.4 Optimum Range Compliance Points (Notes 1, and 2)

Sourcing Power QuadrantRange dc 100 ms 10 ms 1 ms----- ----- ----- ----- -----

1.4.1 85 V 4.0 A 8.0 A 10.0 A 10.0 A1.4.2 170 V 2.0 A 5.0 A 7.0 A 10.0 A1.4.3 255 V 1.4 A 4.0 A 4.5 A 8.5 A1.4.4 340 V 1.0 A 3.5 A 4.0 A 7.0 A1.4.5 510 V 700 mA 2.0 A 2.2 A 4.2 A1.4.6 750 V 500 mA 1.9 A 2.0 A 3.5 A

1.5 Full Range Compliance Points (Notes 1, 3, and 4)Sinking Power

Sourcing Power Quadrant QuadrantRange dc 100 ms 10 ms 1 ms (nominal)----- ----- ----- ----- ----- ---------

1.5.1 85 V 3.0 A 8.0 A 10.0 A 10.0 A 58 ohm1.5.2 170 V 1.5 A 5.0 A 7.0 A 10.0 A 58 ohm1.5.3 255 V 1.0 A 3.5 A 4.0 A 6.5 A 58 ohm1.5.4 340 V 700 mA 2.6 A 3.5 A 5.0 A 58 ohm1.5.5 510 V 500 mA 1.7 A 2.0 A 3.2 A 233 ohm1.5.6 750 V 350 mA 1.3 A 1.7 A 2.5 A 233 ohm

1.6 Settling Time (Note 7)1.6.1 to specification <500 us (non-reactive)1.6.2 at 100 us +/-3% of final value (non-reactive)

1.7 Current Clamp Response Time 200 us for a 20% over current

1.8 Periodic and Random Deviations (PARD) (note 5)1.8.1 85-340 V ranges < 50 mV rms < 300 mV p-p1.8.2 510, 750 V ranges < 100 mV rms < 600 mV p-p

1.9 Stability The HPVI will settle into any realor first order reactive load withinthe compliance specifications.



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Settling time may be limited by slewrate or overshoot.

2. HPVI Current Measurement Specifications

2.1 Accuracy



2.1.1 10 A +/- (1.0% + 12.5 mA)2.1.2 1 A +/- (1.0% + 8.5 mA)2.1.3 100 mA +/- (1.0% + 125 uA)2.1.4 10 mA +/- (1.0% + 85 uA)2.1.5 1 mA +/- (1.5% + 2 uA)2.1.6 100 uA +/- (1.5% + 2 uA)

2.2 Ammeter noise <1% of range p-p typical

2.3 Ammeter settling time2.3.1 to specification <500 us typical2.3.2 at 100 us +/-5% of final value typical

2.4 Maximum allowable Current 10 A independent of ammeter range.

3. HPVI Forcing Current Source Specifications


Irange Vrange Resolution Accuracy------ ------ ------------- ---------------

3.1.1 100 mA 510, 750 V 25 uA (nominal) +/-(1.5% + 1 mA)3.1.2 100 mA 85-340 V 50 uA (nominal) +/-(1.5% + 2 mA)3.1.3 10 A 510, 750 V 2.5 mA (nominal) +/-(1.5% + 25 mA)3.1.4 10 A 85-340 V 5 mA (nominal) +/-(3.0% + 50 mA)



3.4 Compliance PointsSourcing Quadrant

Irange Vrange dc 100 ms 10 ms 1 ms------ --------- ------ ------ ------ ------

3.4.1 100 mA 510, 750 V Vrange Vrange Vrange Vrange3.4.2 100 mA 85 - 340 V Vrange Vrange Vrange Vrange3.4.3 10 A 510, 750 V same as FV compliance points (1.4 & 1.5).3.4.4 10 A 85 - 340 V same as FV compliance points (1.4 & 1.5).

3.5 Settling Time (note 7)3.5.1 to specification <1 ms typical3.5.2 at 100 us +/-3% of final value typical



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3.6 Voltage Clamp Response Time <100 us for 10% over voltage typical

3.7 Periodic and Random Deviations (PARD) (note 5)3.7.1 100 mA range <20 uA rms < 100 uA p-p typical3.7.2 10 A range <1 mA rms < 6 mA p-p typical

3.8 Stability The HPVI will settle into any realor first order reactive load withinthe compliance specifications.Settling time may be limited by slewrate or overshoot.

4. HPVI Voltage Measurement Specifications

4.1 Accuracy



4.1.1 800 V +/-(0.5% + 1.0 V)

4.2 Voltmeter noise <6 Vp-p typical<1 Vrms typical

4.3 Voltmeter settling time <100 us typical

4.4 Maximum Allowable Voltage 1200 V

7. HPVI Miscellaneous Specifications7.1 Output Connect time <50 ms typical7.2 Output Disconnect time <50 ms typical7.3 Trigger Delay 30 us +/- 20 us7.4 Maximum Output Voltage

(any output to chassis) 1000 V7.5 Kelvin Performance Allowable F-S Separation7.5.1 Direct output 2.0 V typical7.5.2 Matrixed Output 1.5 V typical7.5.3 AL Test head Output 1.0 V typical

7.6 Modulation Accuracy +/-1.0% typical

�


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Specs 14 High Speed Digital Instrumentation

Note:Recalibration is required after Temperature change of > +/-3 Cor a 1% power supply change in the test head programmable supplyfrom the values the system was calibrated at.

I. HIGH SPEED DIGITAL SPECIFICATIONS

1. CHANNEL COUNT

1.1 Maximum Channel Count 64 channels1.2 Channel increment by which system is expandable 8 channels

The channel mainframe backplane supports 64 channels. Eachbackplane slot supports 8 channels. Channel numbers areassigned based on backplane slot number. Within a backplane,channels can be populated in any order.

Up to two PATH II test heads are supported.

2. VECTOR RATE

2.1 Vector Rate 25 MHz2.2 Single Cycle IO Rate 25 MHz2.3 Dual Drive 50 MHz

The base vector rate for the system allows full functionalityon all channels. A special "dual drive" mode provides driveonly vector rates of twice the nonmultiplexed rate using asingle channel.

3. DRIVER SPECIFICATIONS

3.1 VIH/VIL DC Voltage Levels (No load)3.1.1 Voltage ranges -2 to +7 V3.1.2 Voltage resolution 1 mV3.1.3 Voltage Accuracy for 0.5 V to 9 V swings (with no load)3.1.3.1 Accuracy +/-(0.25% + 30 mV)

True when: VIH/VIL > 1 V above their negative railVIH > 1 V below its positive railVIL > 1.4 V below its positive rail

3.1.3.2 Accuracy at/near voltage rails +/-(0.25% + 60 mV)



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3.1.3.3 VIH/VIL after focused calibration +/-(0.05% + 14 mV)

3.2 VIH/VIL DC Output Current3.2.1 DC Output Current Hi Source 30 mA < I < 100 mA3.2.2 DC Output Current Low Sink 30 mA < I < 100 mA

3.3 Output Impedance3.3.1 Resistance, DC

VIH/VIL > 1 V from either voltage rail 50 ohms, +/-2.5 ohmsVIH/VIL < 1 V from either voltage rail 50 ohms, +/-5 ohms typ.Measured at current 30 mA.

3.3.2 Impedance 50 ohms, nominal

3.4 Waveform Fidelity3.4.1 Overshoot or undershoot up to 25 ns <(20% delta V)

after transition.3.4.2 Overshoot or undershoot 25 ns to 5 us <(1% delta V + 40 mV)

after transition.3.4.2 Preshoot up to 2 ns before transition <(10% delta V)

Transition is defined as the 80% point on the drive waveform.Valid when levels are more than 1 V from either rail.

3.5 Rise/Fall Time3.5.1 3 V swing (20%-80%) <5 ns3.5.2 9 V swing (20%-80%) <10 ns

Valid when levels are more than 1 V from either rail.When swinging within 1 V of a rail the edge transitiontime increases by 500 ps typically.

3.6 Minimum Pulse Width (with full level and edge placement accuracy)3.6.1 3 V swing 10 ns

4. COMPARATOR SPECIFICATIONS

4.1 VOH/VOL DC Voltage Levels4.1.1 Voltage ranges -2 to +7 V4.1.2 Voltage resolution 1 mV4.1.3 Voltage Accuracy for 0.5 V to 9 V swings4.1.3.1 VOH/VOL +/-(1.0% + 60 mV)4.1.3.2 VOH/VOL after focused calibration +/-(0.1% + 20 mV)4.1.4 Inputs are protected by a silicon diodes.

This provides current protection of: 200 mA nominalThis current is the total for all the channelscards in the test head. It is assumed that only afew boards will be in a overload state at atime.

The diodes are clamped to voltages 0.2 Vabove and below the driver, comparator and loadvoltage rails. See spec 4.1.1 for the rail values.



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4.2 Input Impedance4.2.1 DC resistance 4 Megohms nominal4.2.2.1 Leakage <50 uA4.2.2.2 Leakage, -2 V to +3 V <25 uA

Assuming the IOH/IOL current loads are programmed to zero current.

4.3 Device LoadingThe device loading is most accurately modeled as atransmission line from the device under test to thechannel card's pin electronics.

4.3.1 50 ohm transmission line from 7 ns typicalIso-pin (TM) to channel card through1 M cable.

4.3.2 Lumped capacitance on the path <2 pF typical(As measured by a 1 ns TDR waveform)

4.3.3 Distributed capacitance of a precision 27 pF/ft Maximum50 ohm coaxial cable (+/-1 ohm)

4.4 Waveform Fidelity4.4.1 Overshoot or undershoot up to 25 ns <(20% delta V)

after transition.4.4.2 Overshoot or undershoot 25 ns to 5 us <(1% delta V + 40 mV)

after transition. typical4.4.3 Preshoot up to 2 ns before transition <(10% delta V)

Transition is defined as the 80% point on the input waveform.Valid when levels are more than 1 V from either rail.(Driven by a backmatched source, channel's driver in HIZ)

4.5 Input Minimum Pulse Width 5 ns Minimum

4.6.1 Minimum pulse detectable 12 ns @ 500 mV overdrivewith comparators.

4.7 Receiver Hysteresis 2 mV typical

5. DYNAMIC LOAD SPECIFICATIONS

5.1 IOH/IOL DC Current Levels5.1.1 Current range 50 mA5.1.2 Current resolution 5 uA5.1.3 Current Accuracy5.1.3.1 IOH/IOL 0 ua to 32 mA +/-(1.0% + 250 uA)5.1.3.2 IOH/IOL 300 ua to 10 mA +/-(0.5% + 100 uA) typ.

Where |IOH| + |IOL| <= 10 mAFor the entire test program

5.2 VCP DC Voltage Levels5.2.1 Voltage range -2 to +7 V5.2.2 Voltage resolution 1 mV5.2.3 Voltage Accuracy (with no external load)

For |Vcp - Vdut| > 1 V and:5.2.3.1 IOH = IOL = 2 mA +/-(0.1% + 115 mV)

Some headroom between the VDUT and the channel voltage railsis required to meet the accuracies stated above.



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5.3 Input Resistance, DC 50 ohms, +/-10 ohmsThe active load can be used to terminate thechannel's transmission line if IOH and IOL areprogrammed to an appropriately large value and VCPis programmed to the desired termination voltage.

5.4 Settling TimeIOH/IOL settles to within +/- 10% of <10 ns typicallyprogrammed value after transition through VCP.

6. PER PIN PARAMETRIC MEASUREMENT UNIT (PPMU)A four quadrant Force Voltage and Measure Current or ForceCurrent and Measure Voltage parametric measurement circuit.

6.1 Voltage Forcing/Measuring (No load)6.1.1 Voltage range -2 to +7 V6.1.2 Voltage force resolution 275 uV6.1.3 Voltage force accuracy +/-(0.16% + 14 mV)6.1.4 Voltage measure resolution 3.66 mV6.1.5 Voltage measure accuracy +/-(0.43% + 18 mV)

6.2 Current Forcing Ranges

Range Resolution Accuracy-------- ---------- ----------------+/-2 mA 220 nA +/-(0.25% + 17 uA)+/-200 uA 22 nA +/-(0.2% + 1.7 uA)

6.3 Current Measuring RangesAcquire

Range Resolution Accuracy Time--------- ---------- ----------------- ---------+/-2 mA 2.93 uA +/-(0.58% + 16 uA) 1 us+/-200 uA 293 nA +/-(0.52% + 2.1 uA) 1 us

* +/-20 uA 29.3 nA +/-(0.51% + 0.16 uA) 1 ms* +/-2 uA 2.93 nA +/-(1.0% + 21 nA) 10 ms* +/-200 nA 293 pA +/-(1.4% + 2.1 nA) 100 ms* Integrating current measurement ranges

6.5 VSYS Level6.5.1 Range -2 to +7 V6.5.2 Resolution 59.6 mV6.5.3 Accuracy +/-(0.15% + 60 mV)

7. TIMING GENERATION

7.1 Clock Generation7.1.1 Master Clock (MCLK)

The HSD25 subsystem timing is derived from a master clock source.Master clock originates from a 10 MHz reference in the system.

7.1.1.1 Frequency Range 160 MHz to 200 MHzPeriod Range 6.25 ns to 5 ns

7.1.1.2 Frequency Resolution 4 Hz7.1.1.3 Frequency Accuracy 1 ppm + 1 ppm/year



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7.1.2 C0 Digital Subsystem ClockC0 is generated by dividing down from master clock.

7.1.2.1 Frequency Range ~5 kHz to 25 Mhz7.1.2.2 Frequency Resolution <=1 Hz7.1.2.3 Frequency Accuracy 1 ppm + 1 ppm/year7.1.2.4 Divider Range 8 to 327717.1.2.5 Number of timing sets 10237.1.3 T0 Digital Subsystem Clock

T0 is generated by dividing down from the C0 clock.7.1.3.1 Frequency Range ~5 kHz to C0 rate7.1.3.2 Frequency Resolution <=1 Hz7.1.3.3 Frequency Accuracy 1 ppm + 1 ppm/year7.1.3.4 Divider Range 1 to 2557.1.3.5 Number of timing sets 10237.1.4 Clock Selection

Each channel can select either T0 or C0 as its cycle clock.This allows clock channels to operate at a higher rate thandata channels. Channels running on the C0 clock must be driveonly.

7.2 Edge Generation7.2.1 Timing Generators per Channel

Up to six edges can be active per cycle per channel. Severalof the edges have multiple functions depending on the modeselected for the channel.

D0 - go active and if format is complement surround alsogo to complement of the data.

D1 - go to the data value.D2 - if the format is a return format go to complement of the data.D3 - Go to HIZ or if the channel is in dual drive mode

go to the complement of the 2nd cycle's data.R1 - Open compare window edge or if the channel is in dual drive

mode, go to the 2nd cycle's data value.R2 - Close compare window or if the channel is in dual drive

mode and the format is a return format, go to the complementof the 2nd cycle's data value.

7.2.2 Timing Sets7.2.2.1 Number of timing sets 1023

There are 1023 global timing sets, TSETs. Each TSETnumber selects one of 32 sets of timing per channel, anedge set. Each edge set has unique timing information foreach channel's six edges. TSETs can be changed on the flyon each vector.

7.2.2.2 Selectable masking of any edge7.2.2.3 Repeat of the previous timing set within a pattern7.2.3 Formatting Capabilities

Each channel can be independently programmed for one of threeformatting modes: Normal I/O, Single Cycle I/O, and dual drive.

7.2.3.1 Normal mode I/O FormatsEach cycle is either a drive cycle or a comparecycle. Several drive and compare formats aresupported both statically and dynamically.

Drive Formatsnrz, nrzc Non Return To Zero and its complementrz, rzc Return To Zero and its complement



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ro, roc Return To One and its complementcs, csc Complement Surround and its complementclkhi Clock High independent of pattern dataclklo Clock Low independent of pattern datafhi Static drive high independent of pattern dataflo Static drive low independent of pattern dataoff Static HIZ independent of pattern data

The following drive formats operate similarly to those aboveexpect they operate only during drive cycles:

drvclkhi, drvclklo, drvhi and drvlo.

Compare Formatscmplo Compare to Lowcmphi Compare to Highcmplog Compare to Logic (also known as Valid)cmpmid Compare to Midbandcmppat Compare to Data Patterncmpmask Mask Comparator, Inhibits Pass/fail Comparisonscmpoff Mask r1/r2 edges, turns off comparisons

The following compare formats operate similarly to those aboveexpect they operate only during compare cycles:

rcvlo, rcvhi, rcvlog, rcvmid, rcvmask.

Pattern Data Bit Assignments (3 bits per channel)Pattern Bits Driver Comparator PeditC B A State Expect Symbol----- ------ ---------- ------0 0 0 Low Mask 00 0 1 Mask Mask X0 1 0 Repeat Mask -0 1 1 High Mask 11 0 0 HIZ Low L1 0 1 HIZ Midband M1 1 0 HIZ Valid V1 1 1 HIZ High H

7.2.3.2 Single Cycle IO Mode Formats "io_midband and io_valid"

Each cycle contains both drive and compare edges.There is no required sequence to the order of the driveportion of the cycle to the compare portion of the cycle.In IO mode return to HIZ is the default format.

The edge assignments are the same as the I/O Mode.

All of the formats listed for the I/O mode can be usedin IO mode.

Due to a limit in the number of pattern data bits there aretwo sets of formats. One supports testing logic outputs andthe other digital signal outputs. To test a logic pin theio_midband format is selected. In this mode all expect patterncodes are supported with the exception of the valid expectcode. To test a digital signal pin the io_valid format is



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selected. For this mode midband is not supported.

Pattern Data Bit Assignments for the io_midband FormatPattern Bits Driver Comparator PeditC B A State Expect Symbols----- ------ ---------- -------0 0 0 Low Low 0 L0 0 1 Low Midband 0 M0 1 0 Low Mask 0 X0 1 1 Low High 0 H1 0 0 High Low 1 L1 0 1 High Midband 1 M1 1 0 High Mask 1 X1 1 1 High High 1 H

Pattern Data Bit Assignments for the io_valid Format

Pattern Bits Driver Comparator PeditC B A State Expect Symbols----- ------ ---------- -------0 0 0 Low Low 0 L0 0 1 Low Mask 0 X0 1 0 Low Valid 0 V0 1 1 Low High 0 H1 0 0 High Low 1 L1 0 1 High Mask 1 X1 1 0 High Valid 1 V1 1 1 High High 1 H

7.2.3.3 Dual Drive Mode FormatsThis mode uses the comparison edges to generate two drivestates per cycle. It is a drive only mode of operation.Either drive state can be generated first.

All of the same drive formats as normal mode are supportedwith the exception of the complement surround formats.

Dual Drive Mode Pattern Data Bit AssignmentsPattern Bits 1st Drive 2nd Drive PeditC B A State State Symbols----- ---------- ---------- -------X 0 0 Low Low 0 0X 0 1 High Low 1 0X 1 0 Low High 0 1X 1 1 High High 1 1

7.2.4 Channel Output InitializationPrior to a pattern burst each channel can be initialized toa user specified condition: Driver LOW, HIGH or HIZ.At the start of a pattern burst the system will initializedall channels to: high, low or HIZ depending on what thefirst vector's pattern data is.



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7.2.5 Edge RangeMinimum 0 nsMaximum, the smaller of either: 4*(Tester Cycles) -

8*(MCLK period)or: 8188*(MCLK Period)

7.2.6 Edge Resolution (MCLK Period)/647.2.7 Edge Placement Accuracy

Edge accuracy applies at the device socket. However,the device interface board must be in place at the timecalibration is run and the HSD traces on the board musthave a 50 ohm impedance.

7.2.7.1 D1, D2 Edges +/-1 ns7.2.7.2 R1, R2 Edges +/-1 ns

Window Strobe +/-1 nsNarrow Strobe (typical) +/-1 nsDual Drive +/-1 ns

Window type Break point----------- -----------Window Strobe (R2-R1) > 5 nsNarrow Strobe 2.5 ns < (R2-R1) < 5 ns

7.2.7.3 D0, D3 EdgesUsed as Complement or HIZ Edges +/-2 ns typical

7.2.7.4 Maximum electrical length of trace 2 ns typicaldeskewable from end of interface cablesto device socket.

7.2.7.5 Reduction in edge placement accuracy when +/-150 pscalibration set has been interpolated

7.2.8 Edge Restrictions7.2.8.1 Edge Regeneration time 4 MCLK periods

This is the time required between thegeneration of any edge and the nextoccurrence of the same edge on the samechannel. (i.e. D1 to the next D1)

7.2.8.2 Minimum Drive pulse width 10 ns MinimumThis defines the minimum spacing betweendrive edges; D0, D1, D2, D3 as well asR1, R2 when operating in dual drive mode.(Level and edge placement accuracy may be degraded)

7.2.8.3 Minimum HIZ or Active pulse width 10 ns MinimumThis defines the minimum spacing betweenHIZ control edges; D0 to D3 and D3 to D0.

7.2.8.4 Minimum R2 to R1 edge separation 8.5 ns MinimumThis is the time required from the closing ofa comparison window to the opening of the nextcomparison window on the same channel.

7.3 Pass/Fail GenerationPass/Fail status will be generated for each compare cycle thathas a R2 edge. In cases where the R2 edge is masked the pass/fail result is not determined until a cycle that closes thecomparison window with a R2 edge occurs. All other cyclesgenerate a default "Pass" status. A compare cycle will



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generate a pass if the input to the digital channel is in astable state for the entire comparison window and the state ofthe input matches the vector's expected state.

HIGH = Above the high comparator (VOH) andabove the low comparator (VOL).

LOW = Below VOH and below VOL.MIDBAND = Below VOH and above VOL.LOGIC = Above VOH or below VOL.

7.4 Logic Signal GenerationThe logic level detected at the comparator is generatedfor every channel for every comparison cycle. The logic signalwill be a logic 1 if the input to the channel's comparator isnot below the low comparator, VOL, at any time during the comparisonwindow.

If the channel's input was below the low comparator forthe entire comparison window, a logic 0 value is returned.

The ambiguity of whether the channel was high during the entirecomparison window or a whether transition occurred canbe eliminated by using an expect valid pattern formatfor the vector of interest. If a transition occurs thepattern will fail.

8. Digital Vector I/O

8.1 Pattern Source8.1.1 Number Of Digital Vectors8.1.1.1 Random access memory PRAM 16 k vectors8.1.1.2 Sequential Access Memory (SAM) 64 k vectors8.1.1.3 Optional Large Sequential Access Memory (SAM) 1 M vectors

The memory architecture consists of a mixture of random accessmemory and sequential access memory. Patterns are automaticallysplit up between the two memories by the system software.Pattern writing and debugging are both performed on a virtualvector pattern space.

8.1.2 Pattern Memory LoadingPatterns can be loaded from the Tester computer using DMA.

8.1.3 Scan TestingScan patterns can be coded into the vector memories.

9. SEQUENCE CONTROL

9.1 Microcode Memory Depth

9.1.1 Random access memory PRAM 16 k vectors9.1.2 Sequential Access Memory (SAM) 64 k vectors9.1.3 Optional Large Sequential Access Memory (SAM) 1 M vectors



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9.2 Pattern Execution Control9.2.1 Basic Opcodes

<blank> Continue to next vector unless the fail flag isset. If fail is set, halt.

HALT Stop pattern execution unconditionally. It isnot allowed on the very first vector executed.

9.2.2 Opcode ModifiersNO_HALT Do not stop the pattern if there is a failure.

By default a failing vector halts the patternimmediately.

ICYC Inhibit counting by the cycle counter and thefail counter for this vector.

MASK Masks the comparisons on all channels. Pass/Failgeneration is inhibited but logic capture isstill active.

CLR_FAIL Clear formatter accumulated fail information thatwill be read back by the test program. The cleartakes effect immediately; fails up to andincluding the current vector are cleared.

QUAL Controls the capture of vectors into thehistory RAM in some of the history RAM modes.

CLR_COND Clear the condition bits used to make conditionalbranches in the pattern. This modifier onlyworks on conditional branch opcodes. Only theconditions being tested will be cleared.

9.2.3 Repeat opcodeREPEAT <n> Execute this vector n times. 1 <= n <= 32768.

9.2.4 Looping OpcodesSET_LOOP <n> Push n onto loop stack, 1 <= n <= 65536.

SET_LOOP 1 will execute vectors in loop once.There is a loop stack for this counter whichallows a loop nesting level of 5.

SET_LOOP1 <n> Set loop counter 1 to n, 1 <= n <= 65536.There is no loop stack for loop counter 1.

SET_LOOP2 <n> Set loop counter 2 to n, 1 <= n <= 65536.There is no loop stack for loop counter 2.

LOOP <n> Similar to SET_LOOP, but pushes n onto the stackthe first time only, not each time the loopexecutes.

LOOP1 <n> Similar to SET_LOOP1, but sets loop counter 1 thefirst time only, not each time the loop executes.

LOOP2 <n> Similar to SET_LOOP2, but sets loop counter 2 thefirst time only, not each time the loop executes.

EXIT_LOOP <label> Pop loop stack and jump to label. Used for earlyescape from a loop. Can only be used with LOOP andSET_LOOP.

END_LOOP <label>Decrement the loop counter. If not zero, gotolabel. If zero, pop loop stack and continue.Can only be used with SET_LOOP and LOOP.

END_LOOP1 <label>Decrement loop counter 1. If not zero, goto label.If zero, continue. Can only be used with SET_LOOP1and LOOP1.

END_LOOP2 <label>Decrement loop counter 2. If not zero, goto label.



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If zero, continue. Can only be used with SET_LOOP2and LOOP2.

POP_LOOP Pop the loop counter stack.MATCH <label> Terminate a match-mode loop. Decrement loop

counter. If non-zero and failure detected,goto label. Else continue.

9.2.5 BranchingJUMP <label> Go to vector specified unconditionally.SET_GLO <label> Loads the global address register with the

address of the vector with the specified label.This register may also be loaded from theIMAGE program using the "set hsd50 global_address"statement.

JMP_GLO Jump to the address in the global address register.

9.2.6 Subroutine CallsSubroutine stack depth 8 levels

CALL <label> Call vector specified as a subroutine.EXE_GLO Call the address in the global address register as

a subroutine.RETURN Return from CALL or EXE_GLO.EXE_ARG Called from within a subroutine: execute the

vectors following the CALL until an END_ARG isencountered.

END_ARG Terminate subroutine argument vectors; transfercontrol back to subroutine.

PUSH <label> Push address of label onto subroutine stack.POP Pop subroutine stack.

9.2.7 Conditional operationsIF (FLAG), JUMP, ENABLE <FLAG>

The commands JUMP, CALL, RETURN, EXIT_LOOP, EXE_ARG, END_ARG,EXE_GLO, and JMP_GLO may be made conditional on any of fourconditions using the ENABLE and IF statements.The conditions are:

FAIL A failing vector was detected.PASS No failing vector has been detected.CPU The pattern has been signaled by the test program

statement "resume hsd50".EXT Vector bus cage or formatter cage condition was

detected.SCF Other SCM executed the SET_SCF opcode.

To invert the sense of a test, '!' may precede the condition. Allconditions are latched until a CLR_COND or CLR_FLAG command isexecuted.

ENABLE <flag list> Enables the testing of multiple condition flagsThe flags can be ANDed or ORed together.

ENABLE must occur on a vector previous to the one containing the IF.CLR_FLAG <flag list>Clears the specified condition flags.

in the pattern. The condition bitsare FAIL, CPU, EXT, and SCF.



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9.2.8 SynchronizationREADCODE <n> Return a readback code to the test program.CLR_CODE Erase a previous READCODE. A code persists until

this command is issued, even across differentpattern runs.

SET_SCF Set SCF condition on the other SCM.

9.3 Cycle Counter 32 bits wideThis counter keeps track of how many tester cycles havebeen executed. Since vectors can be repeated the number ofvectors in a pattern will often not equal the number of cyclesexecuted. Counting may be inhibited under microcode control.

9.4 Fail Counter 16 bits wideThis counter keeps track of how many cycles the fail flagas been asserted. In general it will equal the number offailing cycles in a pattern. Counting may be inhibitedunder microcode control.

9.5 Debug Features

9.5.1 History RAM 4 k vectorsTester cycles can be captured in a RAM. There are severalmodes of operating this RAM to aid in debugging.

Capture all cycles.Capture only cycles qualified by the QUAL opcode modifier.Start capture on the first vector with a QUAL.Capture the first 63 failures.Start capture after Nth Cycle.

There are two modifiers to the HRAM's operation:Capture until full or wrap.Compress repeat cycles.

For each channel either Pass/Fail or logic data can be selectedfor storage. For the SCM, cycle count, vector and flag statusare stored.

9.5.2 Sequencer Debug FeaturesGlobal Mask Of Comparators For N Cycles.Halt After N Cycles.Halt On Fails.Inhibit Halt On Fail.Inhibit Halt On Fail For N Cycles.

9.6 Keep Alive Operation 1 to 16 vectorsThis mode always the HSD subsystem to continue to provide asimple pattern to the device under test while various memorieswithin the subsystem are reloaded.

Entry into Keep Alive occurs on the vector programmed and starts atthe first keep alive vector. Exit from Keep Alive occurs at theend of the keep alive pattern and starts sourcing the first vectorof the pattern indicated. All failures can be masked during keepalive so accumulated fail can be valid across keep alive



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boundaries.

Memories that can be reloaded:All vector memories, 16 K and 1 Meg.All channel timing values, ie. edge_sets.The channel's TSET to edge_set mappings.

Memories that cannot be reloaded:The divider timing sets for T0 and C0.

Channel setup that cannot be modified:Drive and receive formats.Channel card DC level values.Channel card relay setupsT0 and C0 clock divider values.

9.7 System Pipelines (number of cycles)

9.7.1 SCM Vector To Dpin Output 39From the SCM executing a vector to the data forthat vector arriving at the DUT.

9.7.2 Dpin Input To SCM Formatter Fail Or Condition Flag 21From the cycle on which a vector's data arrivesat the DUT and the DUT is tested to the cycleon which a branch can be conditional on theDUT's response, FAIL or EXT.

9.7.3 SCM Vector To Branchable Result 60From the SCM executing a vector to the cycleon which a branch can be conditional on theDUT's response, FAIL or EXT.

10. DC MATRIX FRONT END10.1 DC Path Series Resistance From Kelvin Point <=0.65 ohms typical10.2 Number of connections 1 matrix/8 channels

11. TIME MEASUREMENT INTERFACE TO DIGITAL CHANNELS

11.1 Time Measurement (TMS) access on each HSD channel11.1.1 Start, Stop, and/or Enable on either HSD Comparator (vol, voh)11.1.2 Enable channel access to either HSD Comparator

11.2 Time Measurement Interface AccuracyTMS path length error correction through the HSD comparators.

11.2.1 Path Length Error (rising edge to rising edge)11.2.1.1Relative to HSD channel +/-300 ps11.2.1.2Relative to non-HSD channel +/-5.0 ns

HSD to non-HSD performance is only specifiedfor systems with a TDR test head board of -01or greater version. Part number 879-943-01.

11.2.2 Analog Parameters(Cin, Trigger Level Error, etc.) See section 4.

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Specs 15 High Speed Sampler

Notes:

1) Thermal tail compensation utilized.

2) AD928-03 unit driven from a source with output resistance <=50 ohms.

3) Applies after a minimum of 30 minute warm-up of the sampler control card inthe test head, and after a minimum 5 minute warm-up of the AD928 sampler frontend. Ambient temperature changes occurring after calibration may degrade DCoffset further. See DC offset drift specs (1.14.X).

4) dT refers to the change in ambient temperature between the timewhen DC offset calibration was performed and the time when the actualmeasurement was made on the DUT (in degrees centigrade).

5) Rsource is the parallel combination of the source resistance of thecircuitry driving the sampler front end and the input resistance ofthe sampler front end (typically 13 kohm). For example, assume theAD928-03 were driven from a DUT (or DIB circuit) having a 300 ohm outputresistance, and a 2 degree C temperature change was anticipated betweenthe time DC calibration was performed and the time the measured resultwas taken. This might be the case if the DC offset were not calibratedevery time the job was run. The worst case DC offset drift would be:

+/-(0.1 mV + ((0.3 mV *2) + (300*0.4e-6)*2)) = +/-0.94 mV

6) Aperture jitter is uncertainty in the timing position of where the inputsignal is sampled. Timing reference for the sampling event is thesystem 10 MHz reference (the reference supplied to the aux clock unit).The specification thus includes jitter of the aux clock unit. The DUT,DUT clock, and DIB-derived sampler clock (if used) can add to the totaljitter in a given application. These jitter components can be added tothe sampler jitter using a square-root-of-the-sum-of-the-squares type ofcalculation to determine total jitter

SDR means the user programmed strobe delay range, in nanoseconds.SWR means the user programmed sweep window range, in nanoseconds.CSR means the sampler clock slew rate, in volts per nanosecond.

7) Actual full scale ranges may be read back within the test program using thefunction tl_hfsc_get_sweep_window() or tl_hfsc_get_strobe_range().

8) Specification applies after autocalibration. Includes effects ofsweep linearity and sweep range accuracy. SWR means the user programmedsweep window range. For example, if the 300 ns sweep window range was


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chosen, the accuracy would be:+/-(0.5 ns + (300 ns * 0.0025) + (300 ns/600 us) * 300 ns) = +/-1.4 ns

Now, if a sweep resolution of 256 were used, the effective sampling ratewould be 256/300 ns, or 853 MHz. The time interval between samples wouldbe 1/853 MHz, or 1.17 ns. The accuracy of this time interval would be:

+/-((1.4 ns/300 ns) * 1.17 ns) = +/-5.4 ps

So the nominal size of each of the 255 time intervals would be 1.17 ns +/- 5.4 ps(that is, all intervals have the same nominal error). Note that timing jitter mayforce averaging techniques to be used to achieve the above accuracy.

9) Aperture delay is the time delay from the occurrence of a clock input tothe sampler to the actual point on the analog input waveform that issampled. The aperture delay variation is the unit-to-unit variationof the aperture delay (for the sampler front end unit). When severalsampler front end units are included on a DIB for a particular application,the aperture delay variation is sometimes referred to as the “skew”between the sampler front end units. The aperture delay variation canbe reduced to almost zero with a DIB-type deskew. This process generallyrequires that jumpers be manually placed into the DUT socket during thedeskew procedure. Limitations on the accuracy of this deskew are imposedby timing jitter, noise, and equal path length wiring techniques on theDIB. Deskew to a level of +/-75 ps has been demonstrated.

10) The strobe signal from the master controller is distributed to each samplerfront end using a buffer located on the DIB. Relative skew of this bufferis not included in this specification.

11) The strobe signal for each sampler front end comes directly from the samplercontrol card. Only one front end is connected to each sampler control card.

12) The actual effective sampling rate in sweep mode depends on the userprogrammed sweep window and sweep increment resolution:

eff. samp. rate = (sweep inc. res./sweep window)

In step mode, the effective sample rate depends on the user programmedsample clock frequency and the DUT clock frequency, and therefore isonly limited by the sampler ref clock divider range. See the User Manualfor methodology used to compute the effective sample rate.

13) For sweep increment resolution programmed to 4, the sweep window is limitedto less than 1.5 us. For sweep increment resolution programmed to 2, thesweep window is limited to less than 640 ns.

14) The strobe repetition period must always be at least 2.25 times longerthan the sweep_window or the strobe_range to achieve specified linearity.In sweep mode, if sweep_resolution is smaller than 4096, the stroberepetition period must be further increased by a factor of

(sweep_res)/(sweep_res-1)

15) When using the system aux clock at frequencies in the range of 200 MHz to250 MHz to provide the clock for the sampler, the aux clock amplitude


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must be programmed in the range of 0 dB to -7 dB. Cable losses prohibitthe use of the -8 dB and -9 dB settings.

16) The risetime specification of 350 ps corresponds to a 10% to 90% risetime.Verification of this specification is performed at the 20% to 80% pointswith a 221 ps test limit.

17) The range beyond 1.0 V is still usable with reduced linearity specifications.

18) The DC accuracy of the AD706-00 can be calibrated to the accuracy of the AD928-XXusing a simple gain correction.

19) Spec only guaranteed when used with Teradyne AD706-00 compatible configurationboards.

20) Spec valid for a 50 ohm source impedance. Lower source impedances will yield a moreextreme DC offset.


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I. HIGH FREQUENCY SAMPLER INSTRUMENTATION SPECIFICATIONS

1.0 GENERAL SPECIFICATIONS

1.1 Voltage Resolution 2 - 16 bits (adjustable)

1.2 Bandwidth1.2.1 AD928-XX DC to > 1 GHz1.2.2 AD706-00 DC to > 520 MHz

1.3 Risetime (NOTE 16)1.3.1 AD928-XX <350 ps1.3.2 AD706-00 <675 ps

1.4 Input Voltage Range1.4.1 AD928-XX +/-2.048 V1.4.2 AD706-00 +/-1.0 V

1.5 Maximum Safe Input Voltage +/-3 V nominal

1.6 Input Resistance1.6.1 AD928-03 >10 kohm, <16 kohm1.6.2 AD928-02 75 ohm +/-1% nominal1.6.3 AD928-01 50 ohm +/-1% nominal1.6.4 AD928-00 37.5 ohm +/-1% nominal1.6.5 AD706-00 50 ohm +2/-1% nominal

1.7 Input Capacitance - AD928-XX units only <5 pF nominal

1.8 Settling Time (NOTE 1)1.8.1 AD928-00 unit1.8.1.1 to +/-1500 uV of final value <4 ns1.8.1.2 to +/-750 uV of final value <6 ns1.8.1.3 to +/-400 uV of final value <15 ns1.8.2 AD928-01 unit1.8.2.1 to +/-1500 uV of final value <4 ns1.8.2.2 to +/-750 uV of final value <6 ns1.8.2.3 to +/-400 uV of final value <15 ns1.8.3 AD928-02 unit1.8.3.1 to +/-1600 uV of final value <4 ns1.8.3.2 to +/-800 uV of final value <6 ns1.8.3.3 to +/-425 uV of final value <15 ns1.8.4 AD928-03 unit1.8.4.1 to +/-1500 uV of final value <6 ns1.8.4.2 to +/-800 uV of final value <8 ns1.8.4.3 to +/-500 uV of final value <15 ns1.8.5 AD706-00 unit1.8.5.1 to +/-1100 uV of final value <40 ns1.8.5.2 to +/-600 uV of final value <80 ns1.8.5.3 to +/-400 uV of final value <100 ns

1.9 Noise (BW = 1 GHz)1.9.1 AD928-XX (NOTE 2) <100 uV RMS1.9.2 AD706-00 <175 uV RMS

1.10 DC Linearity +/-0.01% of Input Voltage Range


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1.11 DC Accuracy1.11.1 AD928-XX +/-0.1% of reading +/- DC offset1.11.2 AD706-00 (NOTE 18) +/-0.1%, -1.1% of reading +/- DC offset

1.12 DC Offset (uncalibrated)1.12.1 AD928-00, -01, -02 +/-7.0 mV1.12.2 AD928-03 +/-440 mV1.12.3 AD706-00 (NOTES 19, 20) +/-10 mV

1.13 DC Offset (calibrated) (NOTE 3)1.13.1 ref clk freq DC to < 20 MHz +/-0.5 mV1.13.2 ref clk freq 20 MHz to < 130 MHz +/-1.5 mV1.13.3 ref clk freq 130 MHz to 250 MHz +/-2.5 mV

1.14 DC Offset Drift (NOTE 4)1.14.1 AD928-00, -01, -02, AD706-00 +/-0.3 mV/dT nominal1.14.2 AD928-03 (NOTE 5) +/-((0.3 mV/dT) + (Rsource*0.4 uA)/dT) nominal

1.15 Total Harmonic Distortion1.15.1 Fin < 15 MHz -52 dB typical1.15.2 Fin < 40 MHz -47 dB typical1.15.3 Fin < 100 MHz -45 dB typical

1.16 DIB Clock Frequency Range (NOTE 15) <250 MHz

1.17 DIB Clock dV/dt >5 V/us

2.0 TIMEBASE SPECIFICATIONS

2.1 Effective Sampling Rate (NOTE 12) <10 ps nominal

2.2 Aperture Jitter (NOTE 6)2.2.1 Sweep Mode < +/-(1 ps+(3.5 V/CSR)+(SWR/10E3)) RMS2.2.2 Fixed, Step Modes < +/-(1 ps+(3.5 V/CSR)+(SWR/10E3)) RMS

2.3 Aperture Delay Variation (NOTE 9)

2.4 Strobe Delay Range (SDR) (NOTE 7) 40 ns to 4 us, in >12288 ranges

2.5 Strobe Delay Resolution 1/4096 (12 bits) of SDR

2.6 Strobe Delay Linearity +/-0.25% of SDR

2.7 Sweep Window Range (SWR) (NOTE 7) 40 ns to 4 us, in >12288 ranges

2.8 Sweep Increment Resolution (NOTE 13) 1/(2**n) of SWR, for integern = 1 to 12

2.9 Sweep Increment Linearity +/-0.25% of SWR

2.10 Sweep Increment Absolute Accuracy (NOTE 8)+/-(0.5 ns + (0.25% + (SWR/600 us) * 100% of SWR))

2.11 Strobe Repetition Rate (NOTE 14) >=1.3 us


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Specs 16 High Voltage Ammeter

NOTES:

NOTE 1 Specifications supported after HVA autocalibration.

NOTE 2 Specification applies to ammeter current over-range to 1/2 A.Ammeter is fused at 1 A.

NOTE 3 Specification applies at the end of the standard lineardelivery system.

NOTE 4 Applies to DC leakage currents at +/-750 VDC from ground.

NOTE 5 Feature applies to HVA+ only.

NOTE 6 Applies when 2 KV delivery system is used. Limited to 1 KV whenconnected to the HPM or a bulkhead configured for use at 1 KV.



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I. HIGH VOLTAGE AMMETER INSTRUMENTATION SPECIFICATIONS

0. HIGH VOLTAGE AMMETER FEATURES

0.1 On board matrix capability.0.1.1 2 high lines in per each of 2 stations0.1.2 6 low lines out per each of 2 stations.0.1.3 Series connection to HPM0.1.4 Parallel connection to HPM0.1.5 Direct input line from HVS (Note 5)

0.2 Programmable guards0.2.1 Guards on 2 direct input lines0.2.2 Guards on 6 direct output lines

0.3 Input floatability0.3.1 1400 V minimum pin-to-pin isolation capability.0.3.2 1000 V minimum pin-to-ground isolation capability.0.3.3 2040 V minimum pin-to-pin isolation capability. (Notes 5,6)0.3.4 2040 V minimum pin-to-ground isolation capability. (Notes 5,6)

0.4 Alarms provide flagging for:0.4.1 Ammeter over-range/blown fuse0.4.2 Guard current alarm

0.5 Instrument Protection0.5.1 Overcurrent protection- protected for 500 mA overrange.0.5.2 Fused at 1 A0.5.3 Generates system shutdown for fuse blown or overrange. (Note 5)

0.6 Self-test capability using only the System Calibration Standard.

0.7 Access to System Measure Bus for Ammeter calibration.

1.0 AMMETER ACCURACY (note 1)

RANGE ACCURACY---------------- ---------------

1.1 100 mA +/-0.2% +/- 120 uA1.2 10 mA +/-0.2% +/- 12 uA1.3 1 mA +/-0.2% +/- 1.2 uA1.4 100 uA +/-0.2% +/- 120 nA1.5 10 uA +/-0.2% +/- 30 nA1.6 1 uA +/-0.5% +/- 20 nA

2.0 AMMETER VOLTAGE DROP

2.1 Current under-range > +/-[(Iprog. * 5 ohms) +/- 10 mV] typical

2.2 Current over-range > +/- [(Iprog. * 5 ohms) +/- 800 mV] typical

3.0 GUARD ALARM > 1.5 mA source or sink typical



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4.0 AMMETER SETTLING TIME TO 1% OF RANGE (Note 3)

RANGE SETTLING TIME (nominal)---------------- ---------------

4.1 100 mA <1 ms4.2 10 mA <1 ms4.3 1 mA <1 ms4.4 100 uA <5 ms4.5 10 uA <10 ms4.6 1 uA <50 ms

5.0 MAXIMUM FLOATABILITY, nominal5.1 1000 V any input/output to ground5.2 1400 V pin-to-pin5.3 2040 V any input/output to ground (Notes 5,6)5.4 2040 V pin-to-pin (Notes 5,6)

6.0 LEAKAGE CURRENT (Notes 3 and 4)6.1 Any input/output to ground, guard on <50 nA typical6.2 Any input/output to ground, guard off <10 uA typical6.3 Ammeter guards to ground <10 uA typical

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Specs 17 High Voltage Digital Card (HVDC)

The HVDC is high voltage digital version of the A5 HSD digital. It is compati-ble with the existing A5 HSD channel cards but contains a rider board whichallows a high voltage digital mode. For the HSD equivalent specifications, con-sult the HSD-50. The specifications listed below cover the additional specifica-tions of the HV Digital Card in used through the high voltage rider board.

0.1 High Voltage DigitalCard Key Features

• High Voltage Digital channel card is equivalent to the A5 HSD channelcards but contains a HV digital rider which can provide up to eight chan-nels of 27 V digital drive and 48 V digital compare capability.– Each HV Digital Card pin can be used as either a HV pin or a standard

HSD pin.– Each HV Digital Card pin is provides high voltage I/O.

• No change in DIB Pogo pin assignments for HSD digital pins in normal orextended mode

• No extra relays on the DIB - all switching is done on the HV Digital Cardrider card.

• Up to 64 HV Digital Card pins on the A565 or A567• Simple, familiar programming in the IMAGE environment.• The HV digital card has three high voltage modes of operation:

– HV voltage drive only mode (hv_drv)– HV drive-receive mode (hv_drv_rcv) mode for I/O– HV receive only mode (hv_rcv) – note below that this mode has higher

bandwidth and short circuit protection.


High Voltage Digital Card (HVDC) High Voltage Digital Card Key Features

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1 General Specifications

1.1 Max number of HV channels by system type:

1.1.1 A565 system64 channels x 2 heads

1.1.2 A567 system64 channels x 2 heads

1.2 Number of HV channels/board: 8 channels (8 drive + 8 receive)

2 Driver Specifications

2.1 Max data rate at 27 V drive: 10 MHz NRZ (Clock rate 5 MHz)

2.2 Driver edge placement accuracy with autocalibration: < ±10 ns

2.3 Drive voltage resolution: 5 mV

2.4 Drive level accuracy: < ±(1.25% +150 mV)

2.5 Driver output impedance: 50 ohms ± 10%

2.6 Minimum drive pulse width: 100 ns at 50% points

2.7 Driver rise time: < 30 ns 20%-80% at 27 V swing

2.8 Driver fall time: < 30 ns 20%-80% at 27 V swing

2.9 VIH, VIL range: -0.5 to 27 V

2.10 Max driver current at 27 V: 15 mA

2.11 Short circuit protection range in drive or drive-receive mode: -3 to +30 V(maximum HVDC input voltage beyond which damage may occur)

2.12 Maximum driver settling time: 75ns after 80% point to ±5% of spec

3 HV Comparator Specifications

3.1 Max Compare Rate: 10 MHz

3.2 Comparator voltage resolution: 8 mV

3.3 Worst case compare timing accuracy after autocalibration: ±5 ns

3.4 Maximum compare Input Impedance: 1Mohm ± 5%

3.5 Compare input capacitance: 30 pF lumped capacitance - typical

3.6 Minimum pulse detection: 50 ns at 50% points

3.7 Compare voltage accuracy: < ±(1.25%+100 mV)

3.8 Maximum compare voltage settling time: 25 ns from 80% point to ±5% of spec

3.9 Compare Levels Range for VOH VOL for each high voltage digital mode:

3.9.1 Mode: hv_drv_rcv: 0 to 27 V

3.9.2 Mode: hv_drv: Not applicable

3.9.3 Mode: hv_rcv: 0 to 48 V

3.10 Short circuit protection in Receive mode: -24 to +64 V(maximum voltage at HVDC input beyond which damage may occur)

3.11 Maximum comparator receive bandwidth in high voltage receive mode:25 MHz typical

3.12 Maximum compare receive bandwidth in high voltage drive receive mode:10 MHz typical

4 I/O specifications


High Voltage Digital Card (HVDC) High Voltage Digital Card Key Features

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4.1 Worst case D0, D3 timing accuracy with autocalibration: ±30 ns

4.2 Minimum tristate settling time: 20 ns typical,

4.3 Voltage during settling time is programmable using VHiz

4.4 Minimum tristate input resistance: 100 kohms

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Specs 18 IF Modulated Source

NOTES:

1) All Specifications apply at the DIB "blind mate" RF connector.

2) All specifications assume a 50 ohm load. The software leveling calibrationallows the user to specify any load and will compensate the output levelto achieve the programmed level at the programmed load. Spectral purityspecifications may vary as the load varies from 50 ohms.

3) Level Accuracy specifications assume that software calibration is NOTdisabled (level:none is NOT selected).

4) Level Accuracy < 10 dBm = Absolute Accuracy @ 10 dBm + Step AttenuatorRelative Accuracy + Fine Attenuator RelativeAccuracy + Mismatch Errors @ DUT.

- Only count error sources that are used, @ 10 dBm do not counteither Step or Fine Attenuator errors, at 1 dB Step incrementsdo not count Fine Attenuator, and so on.

Level Accuracy > 10 dBm = Absolute Accuracy @ 10 dBm + >10 dBm RelativeAccuracy + Mismatch Errors @ DUT.




8) Section 3 applies when the optional IF Modulated Source capability ispresent. This requires the use of the VHFAWG as the fundamental modulatedsignal source. See the VHFAWG ESSD for detailed specifications coveringthe conditions applicable to the IF Modulated Source as noted in this ESSD.

9) Items 3.6-3.9 are measured at output carrier frequencies of 5 MHz, 45 MHz,90 MHz, 110 MHz, 150 MHz, and 180 MHz.

10) Items 3.6.3, 3.7.1, and 3.7.2 above have no limitations otherthan waveform resolution (12 bits) and sampling criteria outlined insections 2.0, 3.0, 4.0, and 5.0 of the VHFAWG ESSD.

11) Digital modulation types measured for 5 MHz output frequency. Resultsare calculated from 256 symbols.


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1.0 FEATURES

1.1 Frequency Ranges (CW Mode) Resolution1.1.1 4.5 - 500 MHz 1 Hz steps1.1.2 500 - 1000 MHz 2 Hz steps1.1.3 1000 - 2000 MHz 4 Hz steps1.1.4 2000 - 4000 MHz 8 Hz steps

1.2 Level Range1.2.1 4.5 - 3500 MHz +13 dBm to -50 dBm1.2.2 3500 MHz - 4000 MHz +10 dBm to -50 dBm

1.3 Level Resolution <0.1 dB

1.4 Test Head Level Control1.4.1 Step Attenuators 1, 2, 4, 8, 16, 32 dB

1.5 Level Compensation for Load Impedance

1.6 Modulation Modes1.6.1 Analog Modes CW, AM, FM, Phase, Pulse, Arbitrary1.6.2 Digital Modes 0.3 GMSK, 0.5 GMSK, DECT, CT2,Arbitrary

1.7 Modulation Mode Frequency Ranges Resolution1.7.1 5 - 68 MHz 1 Hz steps1.7.2 68 - 180 MHz 2 Hz steps

2.0 CW SPECIFICATIONS

2.1 Frequency Accuracy Directly derived from the LA302 systemFrequency Reference Module.

2.2 Level Accuracy2.2.1 Absolute Accuracy @ 10 dBm2.2.1.1 4.5 MHz - 50MHz +/-0.35 dB2.2.1.2 50 MHz - 1300 MHz +/-0.25 dB2.2.1.3 1300 - 3000 MHz +/-0.35 dB2.2.1.4 3000 - 4000 MHz +/-0.45 dB2.2.2 Step Attenuator Relative Accuracy <10 dBm2.2.2.1 4.5 - 2000 MHz (These limits are typical from 4.5 MHz-50 MHz)2.2.2.1.1 (1,2,4 dB Att. selected) +/-0.25 dB2.2.2.1.2 (8,16,32 dB Att. selected) +/-0.30 dB2.2.2.1.3 Additional error if 2 Att. sel. +/-0.15 dB2.2.2.1.4 Additional error if 3-6 Att. sel.+/-0.25 dB2.2.2.2 2000 - 2999 MHz2.2.2.2.1 (1,2,4 dB Att. selected) +/-0.25 dB2.2.2.2.2 (8,16,32 dB Att. selected) +/-0.35 dB2.2.2.2.3 Additional error if 2 Att. sel. +/-0.10 dB2.2.2.2.4 Additional error if 3 Att. sel. +/-0.20 dB2.2.2.2.5 Additional error if 4-6 Att. sel.+/-0.30 dB2.2.2.3 3000 - 4000 MHz2.2.2.3.1 (1,2,4 dB Att. selected) +/-0.25 dB2.2.2.3.2 (8,16,32 dB Att. selected) +/-0.45 dB2.2.2.3.3 Additional error if 2 Att. sel. +/-0.25 dB


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2.2.2.3.4 Additional error if 3 Att. sel. +/-0.60 dB2.2.2.3.5 Additional error if 4-6 Att. sel.+/-0.95 dB2.2.3 Fine Attenuator Relative Accuracy < 10 dBm2.2.3.1 4.5 to 300 MHz +/-0.15 dB2.2.3.2 300 to 3000 MHz +/-0.10 dB2.2.3.3 3000 to 4000 MHz +/-0.15 dB2.2.4 Relative Accuracy > 10 dBm2.2.4.1 4.5 to 3000 MHz2.2.4.1.1 10 - 11 dBm +/-0.3 dB2.2.4.1.2 11 - 12 dBm +/-0.4 dB2.2.4.1.3 12 - 13 dBm +/-0.5 dB2.2.4.2 3000 to 4000 MHz2.2.4.2.1 10 - 11 dBm +/-0.5 dB2.2.4.2.2 11 - 12 dBm +/-0.6 dB2.2.4.2.3 12 - 13 dBm +/-0.7 dB

2.3 Settling Time (includes software overhead)2.3.1 Frequency Settling Time <500 us to 0.1 rad.2.3.2 Level Settling Time2.3.2.1 0.06 dB/Attenuator Bit up to 0.12 dB of final value in <2 ms2.3.2.2 0.03 dB/Attenuator Bit up to 0.06 dB of final value in <10 ms

(NOTE: The 32 dB Attenuator Bit is actually two 16 dB pads, sothe limit is 0.12 dB @ 2 ms and 0.06 dB @ 10 ms)

(NOTE: When crossing either 1000 MHz and 2000 MHz, thelevel settling time is 10 ms to 0.1 dB)

2.4 Spectral Purity2.4.1 SSB Phase noise (+13 to -10 dBm and -22 to -40 dBm output levels)

Frequency Offset from carrier1 kHz 10 kHz 10 MHz

---------------------------------------------------------------4.5 - 500 MHz -110 dBc -118 dBc -122 dBc500 - 1000 MHz -104 dBc -114 dBc -118 dBc1000 - 2000 MHz -98 dBc -108 dBc -113 dBc2000 - 4000 MHz -92 dBc -102 dBc -108 dBc

2.4.2 SSB Phase noise (-10 to -21 dBm and -40 to -50 dBm output levels)Frequency Offset from carrier

1 kHz 10 kHz 10 MHz---------------------------------------------------------------4.5 - 500 MHz -108 dBc -112 dBc -113 dBc500 - 1000 MHz -104 dBc -110 dBc -112 dBc1000 - 2000 MHz -98 dBc -106 dBc -110 dBc2000 - 4000 MHz -92 dBc -101 dBc -106 dBc

2.4.3 Harmonic Spurious vs. Output Power LevelFreq Range 12 - 13dBm 11 - 12dBm 10 - 11dBm---------------------------------------------------------------4.5- 50 MHz (Typ.) -25 dBc -25 dBc -25 dBc50 - 1000 MHz -25 dBc -25 dBc -25 dBc1000 - 1100 MHz -25 dBc -25 dBc -24 dBc1100 - 2000 MHz -25 dBc -27 dBc -28 dBc2000 - 2500 MHz -26 dBc -26 dBc -27 dBc2500 - 4000 MHz -30 dBc -31 dBc -32 dBc


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Freq Range 5 - 10dBm 0 - 5dBm <0 dBm----------- ----------------------------------------------------4.5 - 50 MHz (Typ.) -25 dBc -29 dBc -30 dBc50 - 1000 MHz -25 dBc -29 dBc -30 dBc1000 - 1100 MHz -25 dBc -28 dBc -30 dBc1100 - 2000 MHz -29 dBc -32 dBc -35 dBc2000 - 2500 MHz -28 dBc -32 dBc -33 dBc2500 - 4000 MHz -33 dBc -35 dBc -35 dBc

2.4.4 Non-Harmonic Spurious4.5 - 500 MHz -58 dBc500 - 1000 MHz -54 dBc1000 - 2000 MHz -50 dBc2000 - 4000 MHz -46 dBc

2.4.5 1/2 & 3/2 FO4.5 - 250 MHz -66 dBc250 - 3000 MHz -55 dBc3000 - 4000 MHz -50 dBc

2.4.6 Residual FM (in 300 Hz - 15 kHz BW)4.5 - 500 MHz <3 Hz500 - 1000 MHz <7 Hz1000 - 2000 MHz <13 Hz2000 - 4000 MHz <25 Hz

2.5 Output Impedance2.5.1 Impedance 50 Ohm nominal2.5.2 VSWR2.5.2.1 4.5 - 1000 MHz <1.5:1 output typ.2.5.2.2 1000 - 2000 MHz <1.7:1 output typ.2.5.2.3 2000 - 3000 MHz <2.0:1 output typ.2.5.2.4 3000 - 4000 MHz <2.2:1 output typ.

3.0 MODULATION SPECIFICATION

3.1 Sample Rate Restrictions for VHFAWG

Mod. Input Freq (Fo) VHFAWG Filter Min. Sample Rate--------------------- ------------- ----------------

3.1.1 1.9 MHz - 2.1 MHz 4 MHz 4.5 MHz + Fo3.1.2 1.9 MHz - 2.1 MHz 5.5 MHz 4.5 MHz + Fo3.1.3 11.5 MHz - 12.5 MHz Bypass 32 MHz + Fo3.1.4 29.5 MHz - 34.5 MHz Bypass 16 MHz + 3xFo

3.2 Frequency3.2.1 Range 5.0 MHz to 180.0 MHz3.2.2 Resolution 1 Hz for 5.0 - 68.0 MHz,

2 Hz for 68.0 - 180.0 MHz3.2.3 Settling Time 500 us max. to 0.1 radian

3.3 RF Output (same as CW mode)

3.4 Spectral Purity3.4.1 Non-Harmonic Spurious -58 dBc max.3.4.2 Harmonic Spurious (same as CW Mode)


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3.5 Modulation Frequency Response +/-0.5 dB BW (min.) +/-1 dB Bandwidth (min.)---------------- ---------------

3.5.1 2 MHz Mod. Input Freq. 300 kHz 1.0 MHz3.5.2 12 MHz Mod. Input Freq. 1.0 MHz 1.5 MHz3.5.3 32 MHz Mod. Input Freq. 5.0 MHz 8.0 MHz3.5.4 Group Delay 50 ns max. 50 ns max.

3.6 Amplitude Modulation (see note 9)3.6.1 Output Level <=0 dBm (carrier power level)3.6.2 Range 0 - 100%3.6.3 Accuracy (see note 10)3.6.4 Distortion + Noise 1.0% for 90% AM, 1 kHz mod.,

300 Hz to 15 kHz bandwidth.

3.7 Frequency Modulation (see note 9)3.7.1 Deviation Range (see note 10)3.7.2 Deviation Accuracy (see note 10)3.7.3 Distortion + Noise 0.1% max. for 1 kHz mod., 12 kHz and

25 kHz dev. measured in300 Hz - 15 kHz BW, 75 us deemph.

3.8 Phase Modulation (see note 9)3.8.1 Deviation Error 2 deg. (0.035 rad.) max. for

0.5 rad. peak dev.(10 kHz peak dev. at 20 kHz rate.).

3.9 Wideband Frequency/Phase Modulation (see note 9)3.9.1 Deviation Error 2 deg. (0.035 rad.) max. for

0.5 rad. peak dev.(288 kHz peak. dev. at 576 kHz rate)

3.10 Digital Modulation (see note 11)3.10.1 PI/4-DQPSK (Pi/4-shifted Differential Phase Shift Keying)3.10.1.1 Modulation Input Freq. 2 MHz, 12 MHz, 32 MHz (+/-0.5 dB BW)3.10.1.2 Error Vector Magnitude 2% rms, 4% peak3.10.1.3 Magnitude Error 1% rms, 2% peak3.10.1.4 Phase Error 1 deg. rms, 2 deg. peak3.10.2 0.3GMSK/GSM (0.3-Gaussian Minimum Shift Keying, GSM Standard)3.10.2.1 Modulation Input Freq. 2 MHz, 12 MHz, 32 MHz (+/-0.5 dB BW)3.10.2.2 Magnitude error 1% rms, 2% peak3.10.2.3 Phase error 1 deg. rms, 2 deg. peak3.10.3 0.5GMSK/CT-2 (0.5-Gaussian Minimum Shift Keying, CT-2 Standard)3.10.3.1 Modulation Input Freq. 2 MHz, 12 MHz, 32 MHz (+/-0.5 dB BW)3.10.3.2 Magnitude error 1% rms, 2% peak3.10.3.3 Phase error 1 deg. rms, 2 deg. peak3.10.4 0.5GMSK/DECT (0.5-Gaussian Minimum Shift Keying, DECT Standard)3.10.4.1 Modulation Input Freq. 12 MHz, 32 MHz (+/-0.5 dB BW)3.10.4.2 Magnitude error 2% rms, 4% peak3.10.4.3 Phase error 2 deg. rms, 4 deg. peak

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Specs 19 LA302 System Frequency Reference

NOTES:

1) ACCURACY VS. CALIBRATION INTERVAL

The following are some examples of the worst case accuracy based on fourdifferent calibration intervals. These examples assume adjustment to+/-1 x 10e-8 with a calibration standard accurate to +/-3 x 10e-8.

Calibration Interval Accuracy-------------------- --------

30 Days +/- 8 x 10e-890 Days +/- 1.4 x 10e-7

180 Days +/- 2.3 x 10e-71 Yr. +/- 3.5 x 10e-7

Accuracy = +/-(Settability + Temp. Stab. + cal std. + Aging)

I SYSTEM 10 MHz FREQUENCY REFERENCE SPECIFICATIONS

1 Frequency Accuracy1.1 Initial Accuracy +/-1 x 10e-7

1.2 Adjustability +/-1 x 10e-8

1.3 Temperature Stability (0 - 50 deg. C) +/-1 x 10e-8

1.4 Aging Rate1.4.1 Per Day +/-1 x 10e-91.4.2 Per Year +/-3 x 10e-7

1.5 Warm-up <2 hours

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Specs 20 Low Current Ammeter

Notes:

1. Instrument specifications are valid at the system isopins on A5systems with AL or AMS test heads. For systems with PATH test heads,the specifications are valid at the configuration board.

2. Certain tests require the connection of external equipment orthe use of wired paths between the instrument I/O and the DUT site.

3. The use of Teflon isolated isopads (Teradyne p/n 464-533-00 orequivalent), low noise triaxial cable (Coaxco p/n 33-1009 Yellowor equivalent) and low current/low noise wiring techniques ismandatory on all fixturing external to the board on A5 systems.In general, the signal node must be surrounded by driven shieldand guarded where necessary to prevent leakage and noise.

4. The term “PLC” refers to one power line cycle of 1/60 Hz (16.67 ms)or 1/50 Hz (20.00 ms) duration depending on line frequency.

5. Low current measurements are significantly influenced by fixturingand measurement methodology. Fixturing must employ low current/low noise wiring techniques to limit the influence of externalelectrical and mechanical perturbations on the signal. Certainmeasurement techniques make possible the removal of offsets andsystematic fixturing effects. Consult the appropriate Teradyneapplications note for a discussion of low current fixturing andmeasurement techniques.

6. When used as an extension, insertion accuracy (IA) of the LCA mustbe combined with the accuracy of the instrument serving as thesource or measurement device.

7. The Low Current Ammeter is usable in the following versions ofIMAGE and Solaris operating systems on A5 systems:

IMAGE V5.0 to IMAGE V6.2.ir1 - SunOS 4.4.1 and earlierIMAGE V6.3 and IMAGE V6.3.y2k - SunOS 4.4.1 and earlier and Solaris 2.5.1IMAGE V6.4 - SunOS 4.4.1 and Solaris 2.5.1


Low Current Ammeter

Main Menu

VARIANCES

The following variances have been applied against the specifications:

3.1.3 Ranges and Measurement Accuracy for A5 systemsLevel nPLC Type Accuracy (%rdg + offset)----- ---- --- ------------------------

3.1.3.6 100 pA 8 INT +/-3.5% +/- 5 pA + f.e.*3.1.3.7 10 pA 15 INT +/-3.5% +/- 5 pA + f.e.*


Low Current Ammeter

Main Menu

I. Low Current Ammeter Instrumentation Specifications

1. LCA Channels

1.1 ExpandabilityMinimum of 8 channels, expandable in 8 channel increments.

2. LCA Basic Functions

2.1 Connectivity2.1.1 Matrix, THADS, User Clock, Grounds

- Two internal channel card (“cc”) busses, eachLCA channel connects to either internal bus.

- Two matrix pins per card, each to one cc bus- Two THADS connections per card, each to one cc bus- One user clock per card, connects to both cc busses

2.1.2 Pogo Block I/O2.1.2.1 A5 systems

- DUT signal- Triax connection to instrument input with dual shields

2.1.3 Trigger Bus- Accepts trig bus 1-6 to drive commutation selector

2.1.4 Measure Bus- Driven differentially, channel selectable either

statically or via commutation selector2.1.5 Calibration Bus

- Used to transfer system reference to on-boardcalibration standard

2.2 Force and Measure Functions2.2.1 Current Measurement Via Resistive I/V Mode 10 uA to 100 nA full scale2.2.2 Current Measurement Via Integrate I/V Mode2.1.2.1 A5 systems 10 nA to 10 pA full scale2.2.3 Current Measurement Via Resistive Extension Mode 10 uA to 100 nA full scale

2.3 Commutation Selector- 256 possible timeslots- Selects one of 8 channels for presentation to measure bus- Modulo-n operation (repeats)- Driven by trigger lines 1-6- May be driven by CPU

3. LCA Electrical Specifications (within operating environment)

3.1 Electrical Specifications, Measurement in ITOV Mode3.1.1 Common Mode Voltage Range +/-60 V3.1.2 Voltage Offset +/-1.05 mV


Low Current Ammeter

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3.1.3 Ranges and Measurement Accuracy for A5 systems(at 0 V common mode & for specified measurement interval)

Level nPLC Type Accuracy (%rdg + offset)----- ---- --- ------------------------

3.1.3.1 10 uA n/a RES +/-1.5% +/- 50 nA3.1.3.2 1 uA n/a RES +/-1.5% +/- 5 nA3.1.3.3 100 nA n/a RES +/-2.0% +/- 500 pA3.1.3.4 10 nA 1 INT +/-2.0% +/- 50 pA3.1.3.5 1 nA 4 INT +/-2.5% +/- 5 pA + f.e.*3.1.3.6 100 pA 8 INT +/-3.5% +/- 2 pA + f.e.*3.1.3.7 10 pA 15 INT +/-3.5% +/- 2 pA + f.e.*

* = Fixture Error, see Notes 3 & 5.

3.2 Electrical Specifications, Force in Extension Mode(all given specifications are typical)

3.2.1 Common Mode Voltage Range +/-60 V (typ.)3.2.2 Voltage Offset +/-1.05 mV (typ.)3.2.3 Ranges and Forcing Accuracy for A5 systems (at 0 V common mode)

Range Type Insertion Accuracy(1PLC) (% rdg + offset)----- ---- ----------------

3.2.3.1 10 uA RES +/-2.0% +/- 50 nA + s.m.a.*3.2.3.2 1 uA RES +/-2.0% +/- 5 nA + s.m.a.*3.2.3.3 100 nA RES +/-2.5% +/- 500 pA + s.m.a.*

* = Source/Measurement Accuracy, see Note 6.

4. Absolute Maximum Ratings (exceeding these ratings may damage the channel)

4.1 Maximum Input Drive Voltage +/-65 V

4.2 Maximum Drive Voltage With Shorted Output +/-40 V

4.3 Maximum Short Circuit Output Current +/-10 mA

4.4 Maximum Sustained Current +/-1 mA

4.5 Maximum Output With Input Drive Removed +/-73 V

Users should take precautions against shortingthe LCA output and against leaving the inputdrive open.

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Specs 21 Low Frequency AC 100 Digitizer

Notes:

1) Notation Notes:+ = arithmetic sumor = greater value of++ = rms sumVin = peak input voltage appliedVrng = voltage range of digitizerVbl = programmed dc baseline


3) TYPICAL specifications are sample tested, are NOT 100% tested, and areNOT guaranteed.

4) NOMINAL specifications are generally calculated values, are NOT 100% tested,and are NOT guaranteed.

5) Total Noise Specifications exclude THD.

6) DC Offset and Absolute Accuracy specifications do not include errorsdue to DC Baseline Accuracy, which is specified separately.

7) Low Frequency Noise and Drift are guaranteed after system warmup,at least 20 minutes after power is applied to the test head containingthe channel card.



Main Menu

1 GENERAL SPECIFICATIONS (frequency range independent)

1.1 Input Voltage Range1.1.1 Signal +/-11.0 V peak1.1.2 Blocked DC (AC coupling on: 949-658-00 Dual Channel card Only)

+/-150 Vdc, nominal

1.2 Differential Signal Input Voltage +/-11.0 V peak

1.3 Waveform Range and Resolution1.3.1 Resolution 16 bits/range1.3.2 Ranges 14.48 V peak

(max Vin 11.0 V peak)10.24 V peak7.24 V peak5.12 V peak3.62 V peak2.56 V peak1.81 V peak1.28 V peak0.905 V peak0.640 V peak0.452 V peak0.320 V peak0.226 V peak0.160 V peak0.113 V peak

1.4 DC Baseline Removal1.4.1 Range +/-11.0 V peak1.4.2 Resolution (17 bits) 168 uV1.4.3 Accuracy +/-(Vbl*6 + 0.5) mV1.4.4 Long Term DNL 14 bits

1.5 Input Impedance >9.8 MOhm nominal

1.6 Input Capacitance <200 pF nominal

1.7 Common Mode Rejection1.7.1 DC - 100 Hz, Amplitude Range:1.7.1.1 14.48 V - 7.24 V >80 dB1.7.1.2 5.12 V - 3.62 V >85 dB1.7.1.3 2.56 V - 226 mV >90 dB1.7.1.4 160 mV - 113 mV >105 dB1.7.2 100 Hz - 1 kHz, Amplitude range:1.7.2.1 14.48 V - 7.24 V >65 dB1.7.2.2 5.12 V - 3.62 V >70 dB1.7.2.3 2.56 V - 905 mV >70 dB1.7.2.4 640 mV - 226 mV >75 dB1.7.2.5 160 mV - 113 mV >85 dB1.7.3 1 kHz - 20 kHz, Amplitude range:1.7.3.1 14.48 V - 7.24 V >35 dB1.7.3.2 5.12 V - 3.62 V >40 dB1.7.3.3 2.56 V - 905 mV >45 dB1.7.3.4 640 mV - 226 mV >50 dB1.7.3.5 160 mV - 113 mV >60 dB



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1.7.4 20 kHz - 100 kHz, Amplitude range:1.7.4.1 14.48 V - 7.24 V >25 dB1.7.4.2 5.12 V - 3.62 V >30 dB1.7.4.3 2.56 V - 905 mV >30 dB1.7.4.4 640 mV - 226 mV >35 dB1.7.4.5 160 mV - 113 mV >50 dB

1.8 Settling Time (after change in -)1.8.1 DC Baseline <2 ms1.8.2 Voltage Range <5 ms1.8.3 "bandwidth"1.8.3.1 2,5 kHz <10 ms1.8.3.2 20, 100 kHz <4.5 ms1.8.4 "connect" <4.5 ms

1.9 DC Offset <(Vrng*1.5 + 1.0) mV

1.10 Time Measurement Access1.10.1 Path Length Error (after autocalibration) +/-5 ns nominal1.10.2 Input Capacitance <500 pF nominal

1.11 Capture Memory Depth 256k samples

1.12 AC coupling (949-658-00 Dual Chan Card Only)1.12.1 LF cutoff, precharge off 3.5 Hz nominal1.12.2 LF cutoff, precharge on 17 kHz nominal

2 FREQUENCY RANGE 1: 0.1 Hz - 100 Hz (static linearity parameters)

2.0 Operating Conditions:2.0.1 Anti-aliasing Filter (bandwidth) 2 kHz2.0.2 Sample Rate Range2.0.2.1 Minimum 8 kHz2.0.2.2 Maximum 125 kHz

2.1 Waveform Linearity Error +/-30 ppm

2.2 Input Linearity Error +/-5 ppm

2.3 Absolute Accuracy +/-(Vin*5 + 5) mV

2.4 Low Frequency Noise (<10 Hz) and Drift2.4.1 Baseline off <(10 + (Vrng*seconds)) uV peak typical2.4.2 Baseline on <(38 + (Vrng*seconds) + (Vbl*1.25*seconds)) uV peak

2.5 Spectral Impurities (85 dB) <(Vrng*40 or 5) uVrms

2.6 Total noise (50 Hz - 2 kHz) (85 dB) <(Vrng*40 ++ 5) uVrms

3 FREQUENCY RANGE 2: 50 Hz - 2 kHz

3.0 Operating Conditions:3.0.1 Anti-aliasing Filter (bandwidth) 2 kHz



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3.0.2 Sample Rate Range3.0.2.1 Minimum 8 kHz3.0.2.2 Maximum 125 kHz

3.1 Sine Wave Amplitude Accuracy (0.05 dB) +/-(Vin*6.9 + 1) mV

3.2 Total Harmonic Distortion (85 dB) <(Vin*40 or 5) uVrms

3.3 Non-harmonic Spurious (85 dB) <(Vrng*40 or 5) uVrms

3.4 Total Noise (50 Hz - 2 kHz) (85 dB) <(Vrng*40 ++ 5) uVrms



4.1 Sine Wave Amplitude Accuracy (0.06 dB +/-(Vin*6.9 + 1) mV typical+/-(Vin*38 + 1) mV worst case






5.1 Sine Wave Amplitude Accuracy (0.06 dB) +/-(Vin*6.9 + 1) mV typical+/-(Vin*38 + 1) mV worst case



5.4 Total Noise (50 Hz - 20 kHz) (85dB) <(Vrng*40 ++ 10) uVrms


6.0 Operating Conditions:6.0.1 Anti-aliasing Filter (bandwidth) 100 kHz6.0.2 Sample Rate Range6.0.2.1 Minimum 320 kHz6.0.2.2 Maximum 781.25 kHz



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6.1 Sine Wave Amplitude Accuracy (0.6 dB) +/-(Vin*72 + 1) mV typical+/-(Vin*778 + 1) mV worst case




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Specs 22 Low Frequency AC 100 Source

Notes:

1) Spectral impurities include only non-harmonically related spectralcomponents.

2) Notation Notes:+ = arithmetic sumor = greater value of++ = rms sumVpk = programmed amplitudeVbl = programmed dc baseline





7) DC Offset and Absolute Accuracy specifications do not include errorsdue to DC Baseline Accuracy, which is specified separately.

8) Low Frequency Noise and Drift are guaranteed after system warmup,at least 20 minutes after power is applied to the test head containingthe channel card.



Main Menu

I. LFAC-100 SOURCE INSTRUMENTATION SPECIFICATIONS

1 General Specifications (frequency range independent)

1.1 Peak Output Voltage (AC + DC) +/-11.0 Vpk

1.2 Waveform Resolution 16 bits

1.3 DC Baseline1.3.1 Range +/-11.0 V1.3.2 Resolution (17 bits) 168 uV1.3.3 Accuracy +/-(Vbl*6 + 0.5) mV1.3.4 Long Term DNL 14 Bits

1.4 Waveform Amplitude Range & Resolution1.4.1 DC to 100 kHz <10.24 Vpk1.4.2 Resolution <1 mdB

1.5 Output Current Compliance Limit >20 mA

1.6 Maximum Short Circuit Current <65 mA

1.7 Overcurrent Alarm Detection Threshold1.7.1 (879-858-45 CC only) <45 mA1.7.2 (949-658-00 Dual CC) <65 mA

1.8 Output Impedance (DC - 100 kHz)1.8.1 25 Ohms (879-858-45 CC only)1.8.1.1 Accuracy +/-1 Ohm1.8.1.2 Max. Capacitive Load >1 nF nominal1.8.2 Low Z1.8.2.1 Zout1.8.2.1.1 (879-858-45 CC) <1 Ohm1.8.2.1.2 (949-658-00 Dual CC) <2 Ohm1.8.2.2 Max. Capacitive Load1.8.2.2.1 (879-858-45 CC) >100 pF nominal1.8.2.2.2 (949-658-00 Dual CC) >1 nF nominal1.8.3 Remote Kelvin (C pin, 879-858-45 CC only)1.8.3.1 Zout <0.1 Ohm1.8.3.2 Max. Capacitive Load >100 pF nominal

1.9 Slew Rate >8 V/us nominal

1.10 Settling Time (after change in -)1.10.1 DC Baseline <2 ms1.10.2 Waveform Amplitude (attenuator change) <5 ms1.10.3 Waveform Amplitude (same attenuator) <1 ms1.10.4 "lpfilt"1.10.4.1 2 kHz <10 ms1.10.4.2 20, 100 kHz <4.5 ms1.10.5 "connect" <4 ms

1.11 DC Offset <(Vpk*2 + 2) mV

1.12 Time Measurement Access1.12.1 Path Length Error (after autocalibration) +/-5 ns nominal



Main Menu

1.12.2 Input Capacitance <500 pF nominal

2 Frequency Range 1: 0.1 Hz - 100 Hz (static linearity parameters)

2.0 Operating Conditions2.0.1 Smoothing Filter (lpfilt) 2 kHz


2.2 Output Linearity Error +/-5 ppm

2.3 Absolute Accuracy +/-(Vpk*5 + 5) mV

2.4 Low Frequency Noise (<10 Hz) and Drift2.4.1 Baseline off <(10 + (Vpk * seconds)) uVpeak typical2.4.2 Baseline on <(25 + (Vpk*seconds) + (Vbl*1.25*seconds)) uVpeak

2.5 Spectral Impurities2.5.1 50 Hz - 1 MHz (85 dB) <(Vpk*40 or 40) uVrms

2.6 Total Noise (BW)2.6.2 50 Hz - 1 MHz (85 dB) <(Vpk*40 ++ 40) uVrms

3 Frequency Range 2: 50 Hz - 2 kHz


3.1 Sine Wave Amplitude Accuracy3.1.1 (+0.1 dB, -0.5 dB) +(Vpk*12 + 1) mV

-(Vpk*59 + 1) mV

3.2 Total Harmonic Distortion (85 dB) <(Vpk*40 or 40) uVrms





4.1 Sine Wave Amplitude Accuracy4.1.1 (+0.1 dB, -0.5 dB) +(Vpk*12 + 1) mV

-(Vpk*59 + 1) mV





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5.1 Sine Wave Amplitude Accuracy5.1.1 (+0.5 dB, - 1.0 dB) +(Vpk*59 + 1) mV

-(Vpk*120 + 1) mV

5.2 Total Harmonic Distortion5.2.1 50 kHz - 100 kHz (75 dB) <(Vpk*130 or 40) uVrms

5.3 Spectral Impurities5.3.1 100 kHz - 1 MHz (75 dB) <(Vpk*130 or 40) uVrms

5.4 Total Noise (BW)5.4.1 50 Hz - 100 kHz (75 dB) <(Vpk*130 ++ 40) uVrms5.4.2 50 Hz - 1 MHz (65 dB) <(Vpk*400 ++ 40) uVrms

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Main Menu

Specs 23 Microwave Source

NOTES:

1) All Specifications apply at the DIB "blind mate" RF connector.



4) Level Accuracy < 10 dBm = Absolute Accuracy @ 10 dBm + Step AttenuatorRelative Accuracy + Fine Attenuator RelativeAccuracy + Mismatch Errors @ DUT.

- Only count error sources that are used, @ 10 dBm do not counteither Step or Fine Attenuator errors, at 1 dB Step incrementsdo not count Fine Attenuator, and so on.

Level Accuracy > 10 dBm = Absolute Accuracy @ 10 dBm + >10 dBm RelativeAccuracy + Mismatch Errors @ DUT.




8) Section 3 applies when the optional IF Modulated Source capability ispresent. This requires the use of the VHFAWG as the fundamental modulatedsignal source. See the VHFAWG ESSD for detailed specifications coveringthe conditions applicable to the IF Modulated Source as noted in this ESSD.

9) Items 3.6-3.9 are measured at output carrier frequencies of 5 MHz, 45 MHz,90 MHz, 110 MHz, 150 MHz and 180 MHz.

10) Items 3.6.3, 3.7.1, and 3.7.2 above have no limitations otherthan waveform resolution (12 bits) and sampling criteria outlined insections 2.0, 3.0, 4.0, and 5.0 of the VHFAWG ESSD.

11) Digital modulation types measured for 5 MHz output frequency. Resultsare calculated from 256 symbols.


Microwave Source

Main Menu

1.0 FEATURES

1.1 Frequency Ranges Resolution1.1.1 4.5-500 MHz 1 Hz steps1.1.2 500-1000 MHz 2 Hz steps1.1.3 1000-2000 MHz 4 Hz steps1.1.4 2000-4000 MHz 8 Hz steps

1.2 Level RangeCW mode without IF Modulated Source

1.2.1 4.5 - 4000 MHz +13 dBm to -50 dBmCW mode with IF Modulated Source

1.2.2 4.5 - 3500 MHz +13 dBm to -50 dBm1.2.3 3500 MHz - 4000 MHz +10 dBm to -50 dBm

1.3 Level Resolution <0.1 dB

1.4 Test Head Level Control1.4.1 Step Attenuators 1, 2, 4, 8, 16, 32 dB

1.5 Level Compensation for Load Impedance

1.6 Modulation Modes (with optional IF Modulated Source capability)1.6.1 Analog Modes CW, AM, FM, Phase, Pulse, Arbitrary1.6.2 Digital Modes 0.3GMSK, 0.5GMSK, DECT, CT2, Arbitrary,

Pi/4-DQPSK

1.7 Modulation Mode Frequency Ranges(with optional IF Modulated Source capability)

Resolution1.7.1 5 - 68 MHz 1 Hz Steps1.7.2 68 - 180 MHz 2 Hz Steps

2.0 SPECIFICATIONS

2.1 Frequency Accuracy Directly derived from the LA302 systemFrequency Reference Module

2.2 Level Accuracy2.2.1 Absolute Accuracy @ 10 dBm2.2.1.1 4.5 MHz - 50MHz +/-0.35 dB2.2.1.2 50 MHz - 1300 MHz +/-0.25 dB2.2.1.3 1300 - 3000 MHz +/-0.35 dB2.2.1.4 3000 - 4000 MHz +/-0.45 dB2.2.2 Step Attenuator Relative Accuracy < 10 dBm2.2.2.1 4.5 - 2000 MHz (These limits are typical from 4.5 MHz-50 MHz)2.2.2.1.1 (1,2,4 dB Att. selected) +/-0.25 dB2.2.2.1.2 (8,16,32 dB Att. selected) +/-0.30 dB2.2.2.1.3 Additional error if 2 Att. sel. +/-0.15 dB2.2.2.1.4 Additional error if 3-6 Att. sel.+/-0.25 dB2.2.2.2 2000 - 2999 MHz2.2.2.2.1 (1,2,4 dB Att. selected) +/-0.25 dB2.2.2.2.2 (8,16,32 dB Att. selected) +/-0.35 dB2.2.2.2.3 Additional error if 2 Att. sel. +/-0.10 dB2.2.2.2.4 Additional error if 3 Att. sel. +/-0.20 dB


Microwave Source

Main Menu

2.2.2.2.5 Additional error if 4-6 Att. sel.+/-0.30 dB2.2.2.3 3000 - 4000 MHz2.2.2.3.1 (1,2,4 dB Att. selected) +/-0.25 dB2.2.2.3.2 (8,16,32 dB Att. selected) +/-0.45 dB2.2.2.3.3 Additional error if 2 Att. sel. +/-0.25 dB2.2.2.3.4 Additional error if 3 Att. sel. +/-0.60 dB2.2.2.3.5 Additional error if 4-6 Att. sel.+/-0.95 dB2.2.3 Fine Attenuator Relative Accuracy < 10 dBm2.2.3.1 4.5 to 300 MHz +/-0.15 dB2.2.3.2 300 to 3000 MHz +/-0.10 dB2.2.3.3 3000 to 4000 MHz +/-0.15 dB2.2.4 Relative Accuracy > 10 dBm2.2.4.1 4.5 to 3000 MHz2.2.4.1.1 10 - 11 dBm +/-0.3 dB2.2.4.1.2 11 - 12 dBm +/-0.4 dB2.2.4.1.3 12 - 13 dBm +/-0.5 dB2.2.4.2 3000 to 4000 MHz2.2.4.2.1 10 - 11 dBm +/-0.5 dB2.2.4.2.2 11 - 12 dBm +/-0.6 dB2.2.4.2.3 12 - 13 dBm +/-0.7 dB

2.3 Settling Time (includes software overhead)2.3.1 Frequency Settling Time <500 us to 0.1 rad.2.3.2 Level Settling Time2.3.2.1 0.06 dB/Attenuator Bit up to 0.12 dB of final value in <2 ms2.3.2.2 0.03 dB/Attenuator Bit up to 0.06 dB of final value in <10 ms

(NOTE: The 32 dB/Attenuator Bit is actually two 16 dB pads, sothe limit is 0.12 dB @ 2 ms and 0.06 dB @ 10 ms.)

(NOTE: When crossing either 1000 MHz and 2000 MHz, thelevel settling time is 10 ms to 0.1 dB.)

2.4 Spectral Purity2.4.1 SSB Phase noise (+13 to -10 dBm and -22 to -40 dBm output levels)

Frequency Offset from carrier1 kHz 10 kHz 10 MHz

---------------------------------------------------------------4.5 - 500 MHz -110 dBc -118 dBc -122 dBc500 - 100 MHz -104 dBc -114 dBc -118 dBc1000 - 2000 MHz -98 dBc -108 dBc -113 dBc2000 - 4000 MHz -92 dBc -102 dBc -108 dBc

2.4.2 SSB Phase noise (-10 to -21 dBm and -40 to -50 dBm output levels)Frequency Offset from carrier

1 kHz 10 kHz 10 MHz---------------------------------------------------------------4.5 - 500 MHz -108 dBc -112 dBc -113 dBc500 - 1000 MHz -104 dBc -110 dBc -112 dBc1000 - 2000 MHz -98 dBc -106 dBc -110 dBc2000 - 4000 MHz -92 dBc -101 dBc -106 dBc


Microwave Source

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2.4.3 Harmonic Spurious vs. Output Power LevelFreq Range 12 - 13 dBm 11 - 12 dBm 10 - 11 dBm---------------------------------------------------------------4.5 - 50 MHz (Typ.) -25 dBc -25 dBc -25 dBc50 - 1000 MHz -25 dBc -25 dBc -25 dBc1000-1100 MHz -25 dBc -25 dBc -24 dBc1100-2000 MHz -25 dBc -27 dBc -28 dBc2000-2500 MHz -26 dBc -26 dBc -27 dBc2500-4000 MHz -30 dBc -31 dBc -32 dBc

Freq Range 5 - 10 dBm 0 - 5 dBm <0 dBm---------------------------------------------------------------4.5- 50 MHz (Typ.) -25 dBc -29 dBc -30 dBc50 - 1000 MHz -25 dBc -29 dBc -30 dBc1000-1100 MHz -25 dBc -28 dBc -30 dBc1100-2000 MHz -29 dBc -32 dBc -35 dBc2000-2500 MHz -28 dBc -32 dBc -33 dBc2500-4000 MHz -33 dBc -35 dBc -35 dBc

2.4.4 Non-Harmonic Spurious4.5 - 500 MHz -58 dBc500 - 1000 MHz -54 dBc1000 - 2000 MHz -50 dBc2000 - 4000 MHz -46 dBc

2.4.5 1/2 & 3/2 FO4.5 - 250 MHz -66 dBc250 - 3000 MHz -55 dBc3000 - 4000 MHz -50 dBc

2.4.6 Residual FM (in 300 Hz - 15 kHz BW)4.5 - 500 MHz <3 Hz500 - 1000 MHz <7 Hz1000 - 2000 MHz <13 Hz2000 - 4000 MHz <25 Hz

2.5 Output Impedance2.5.1 Impedance 50 ohm nominal2.5.2 VSWR2.5.2.1 4.5 - 1000 MHz <1.5:1 output typ.2.5.2.2 1000 - 2000 MHz <1.7:1 output typ.2.5.2.3 2000 - 3000 MHz <2.0:1 output typ.2.5.2.4 3000 - 4000 MHz <2.2:1 output typ.

3.0 MODULATION SPECIFICATIONS (with optional IF Modulated Source capability)(see note 8)

3.1 Sample Rate Restrictions for VHFAWG

Mod. Input Freq (Fo) VHFAWG Filter Min. Sample Rate--------------------- ------------- ----------------

3.1.1 1.9 MHz - 2.1 MHz 4 MHz 4.5 MHz + Fo3.1.2 1.9 MHz - 2.1 MHz 5.5 MHz 4.5 MHz + Fo3.1.3 11.5 MHz - 12.5 MHz Bypass 32 MHz + Fo3.1.4 29.5 MHz - 34.5 MHz Bypass 16 MHz + 3xFo


Microwave Source

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3.2 Frequency3.2.1 Range 5.0 MHz to 180.0 MHz3.2.2 Resolution 1 Hz for 5.0 - 68.0 MHz,

2 Hz for 68.0 - 180.0 MHz3.2.3 Settling Time 500 us max. to 0.1 radian.

3.3 RF Output (same as CW mode)

3.4 Spectral Purity3.4.1 Non-Harmonic Spurious -58 dBc max.3.4.2 Harmonic Spurious (same as CW Mode)

3.5 Modulation Frequency Response+/-0.5 dB BW (min.) +/-1 dB Bandwidth (min.)---------------- ---------------

3.5.1 2 MHz Mod. Input Freq. 300 kHz 1.0 MHz3.5.2 12 MHz Mod. Input Freq. 1.0 MHz 1.5 MHz3.5.3 32 MHz Mod. Input Freq. 5.0 MHz 8.0 MHz3.5.4 Group Delay 50 ns max. 50 ns max.

3.6 Amplitude Modulation (see note 9)3.6.1 Output Level <=0 dBm (carrier power level)3.6.2 Range 0 - 100%3.6.3 Accuracy (see note 10)3.6.4 Distortion + Noise 1.0% for 90% AM, 1 kHz mod.,

300 Hz to 15 kHz bandwidth

3.7 Frequency Modulation (see note 9)3.7.1 Deviation Range (see note 10)3.7.2 Deviation Accuracy (see note 10)3.7.3 Distortion + Noise 0.1% max. for 1 kHz mod., 12 kHz and

25 kHz dev. measured in300 Hz-15 kHz BW, 75 us deemph.

3.8 Phase Modulation (see note 9)3.8.1 Deviation Error 2 deg. (0.035 rad.) max. for

0.5 rad. peak dev.(10 kHz peak dev. at 20 kHz rate)

3.9 Wideband Frequency/Phase Modulation (see note 9)3.9.1 Deviation Error 3 deg. (0.052 rad.) max. for

0.5 rad. peak dev.(288 kHz peak. dev. at 576 kHz rate)

3.10 Digital Modulation (see note 11)3.10.1 PI/4-DQPSK (Pi/4-shifted Differential Phase Shift Keying)3.10.1.1 Modulation Input Freq. 2 MHz, 12 MHz, 32 MHz (+/-0.5 dB BW)3.10.1.2 Error Vector Magnitude 2% rms, 4% peak3.10.1.3 Magnitude Error 1% rms, 2% peak3.10.1.4 Phase Error 1 deg. rms., 2 deg. peak3.10.2 0.3 GMSK/GSM (0.3-Gaussian Minimum Shift Keying, GSM Standard)3.10.2.1 Modulation Input Freq. 2 MHz, 12 MHz, 32 MHz (+/-0.5 dB BW)3.10.2.2 Magnitude error 1% rms, 2% peak3.10.2.3 Phase error 1 deg. rms., 2 deg. peak3.10.3 0.5 GMSK/CT-2 (0.5-Gaussian Minimum Shift Keying, CT-2 Standard)3.10.3.1 Modulation Input Freq. 2 MHz, 12 MHz, 32 MHz (+/-0.5 dB BW)


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3.10.3.2 Magnitude error 1% rms, 2% peak3.10.3.3 Phase error 1 deg. rms, 2 deg. peak3.10.4 0.5 GMSK/DECT (0.5-Gaussian Minimum Shift Keying, DECT Standard)3.10.4.1 Modulation Input Freq. 12 MHz, 32 MHz (+/-0.5 dB BW)3.10.4.2 Magnitude error 2% rms, 4% peak3.10.4.3 Phase error 2 deg. rms, 4 deg. peak

�


Main Menu

Specs 24 Octal V/I Source

NOTES:

1 All system metering specifications apply with the system meter filter on.

2 All specifications for voltage accuracy apply at the point the Kelvin (forceto sense) connections are made. Voltage accuracy only applies when there isonly one point of connection for each OVI channel High and Low Sense. Allspecifications for current accuracy apply to the current flow from the OVIHigh Force signal.

3 V/I = Voltage Forcing / Current ForcingVprog = Programmed Voltage of SourceVrange = Voltage Range of SourceIprog = Programmed Current Clamp of SourceIrange = Current Range of SourceVCM = Common-mode voltage, absolute voltage between Low Sense and Analog

Ground, measured in voltsVhigh = absolute maximum of either VCM or (the High Force voltage with respect

to either the Low Force voltage OR the Analog Ground voltage), measuredin volts

Rload = Resistance of the Load, measured from High Sense to Low Sense

4 Modulation accuracy does not include errors due to modulation source. The netDC accuracy while modulating is found by summing the modulation accuracy of theOVI and the appropriate forcing accuracy specification of the source ofmodulation.

5 Area of specified performance is defined by:*Range* = extent of programmability for forced or metered parameter*Maximum Output* = boundary condition for specified operation of instrument*Maximum Allowable* = absolute maximum rating to which instrument can be

subjected; specifications are not applicable at this operating point.

6 Scaled output slew rate is the output of the THADS buffer divided bythe attenuation.

7 Instrument shutdown is a hardware protection feature. Repeatedly driving theinstrument into shutdown will reduce reliability.

8 Current forcing accuracy specifications apply when the actual instrumentcurrent flow is the same sign as the programmed current.When sourcing currents from the instrument, Iprog >= 0.0When sinking currents into the instrument, Iprog < 0.0

9 Maximum allowable resistance includes the interface to the device up to


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the Kelvin point.


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I. OCTAL V/I SOURCE INSTRUMENTATION SPECIFICATIONS

0. OCTAL V/I FEATURES

0.1 GENERAL0.1.1 Ability to force voltage or current with automatic crossover0.1.2 Full four quadrant operation (source or sink, positive or negative)0.1.3 Selectable slew/settling for the following combinations of current

ranges and slew settings:10A range - any slew setting5A range - any slew setting1A range - any slew setting

200uA range - any slew setting other than fast0.1.4 Force and Sense outputs for Hi and Lo leads of each channel0.1.5 Configurable in either 4 or 8 channels0.1.6 All channels independently floating0.1.7 Sources can be paralleled for higher current capability0.1.8 4 selectable voltage ranges0.1.9 4 selectable current ranges0.1.10 Ability to modulate either Voltage or Current from the Wave Bus,

whichever parameter is being forced0.1.11 Current or Voltage Metering through the DC System Meter0.1.12 Current or Voltage Metering through Local Meters0.1.13 Ability to control sampling of Local Meters from Trigger Bus0.1.14 Ability to gate individual channels from Trigger Bus

0.2 CONNECTIONS0.2.1 Voltmeter and ammeter connected to backplane measure busses0.2.2 Trigger bus connection for source gate (any 1 of 8 trigger lines)0.2.3 Trigger bus connection for Local Meter sampling

(any 1 of 8 trigger lines)0.2.4 Wave bus connection for modulation (voltage or current)0.2.5 Relay disconnection in the test head to the device under test0.2.6 Each channel has independent relay 2 to 1 MUX for High or Low

DUT pins0.2.7 Connections to THADS busses in the test head0.2.8 Connections to DC xpts through the channel card

0.3 SAFETY/ALARMS0.3.1 Shutdown signal listener and driver0.3.2 Shutdown for Power Supply Module fan failure0.3.3 Shutdown for Heatsink Module fan failure0.3.4 Shutdown for Power Supply Module transformer overtemperature

condition0.3.5 Shutdown for thermal junction (output stage)0.3.6 Alarm for mode error (in constant I mode when force:v programmed,

or in constant V mode when force:i programmed)0.3.7 Alarm for sense overcurrent detection0.3.8 Alarm for open kelvin0.3.9 Alarm for open loop condition0.3.10 Alarm for overrange condition on Local Meters0.3.11 Channel alarms are captured for each Local Meter strobe and reported

as run-time errors0.3.12 Run-time error for overwriting Local Meter data0.3.13 Run-time error for reading back data from Local Meters prior to

generating a strobe


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0.3.14 Run-time error to report a missed Local Meter strobe0.3.15 System safety signal required for external connections0.3.16 Interlock of cables for mapping and instrument protection0.3.17 Software runtime error generated for disconnecting relays with

more than specified current flowing

1. VOLTAGE FORCING

1.1 Range, Note 5 0 to +/-100 V

1.2 Ranges 2 V, 10 V, 50 V, 100 V Full Scale

1.3 DC Accuracy, Calibrated1.3.1 Vrange = 2 V 0.25% + 3 mV + VCM*(0.01 mV/V)1.3.2 Vrange = 10 V 0.25% + 7.5 mV + VCM*(0.05 mV/V)1.3.3 Vrange = 50 V 0.25% + 37 mV + VCM*(0.25 mV/V)1.3.4 Vrange = 100 V 0.25% + 75 mV + VCM*(0.5 mV/V)

1.4 Maximum Output Current, Note 51.4.1 DC

minimum of (applicable compliance current limit) or (100 W/Vprog)1.4.2 Pulsed, <=5 ms, 10% duty cycle

minimum of (applicable compliance current limit) or (150 W/Vprog)

1.5 Maximum Allowable Voltage, Note 51.5.1 Differential Hi to Lo +/-100 V, nominal1.5.2 Single Channel Hi or Lo to Gnd +/-200 V, nominal


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Table 1: 1.6 Voltage Forcing Settling Time

ProgrammedSlew Rate

0-100 V transition,Full Scale Current programmed on 1 A, 5 A, 10 A range,

Resistive Load > 500 ohms

3% of Final Value To Specification

1.6.1.1 Slow 9.0 ms6.5 ms, typical

23 ms8 ms, typical

1.6.1.2 Norm 900 us625 us, typical

2.3 ms800 us, typical

1.6.1.3 Fast 200 us130 us, typical

500 us160 us, typical

ProgrammedSlew Rate

0-40 V transition,Full Scale Current programmed on 1 A, 5 A, 10 A range,

Resistive Load = 25 ohms


1.6.2.1 Slow 13 ms 32 ms

1.6.2.2 Norm 1.3 ms 3.2 ms

1.6.2.3 Fast 290 us 710 us

ProgrammedSlew Rate

0-140 mV transition,Full Scale Current programmed on 1 A, 5 A, 10 A range,

Resistive Load = 0.15 ohms


1.6.3.1 Slow 18 ms, typical 45 ms, typical

1.6.3.2 Norm 6.0 ms 8.0 ms

1.6.3.3 Fast 1.3 ms 3.2 ms

ProgrammedSlew Rate

0-100 V transition,20% of Full Scale Current programmed

on 1 A, 5 A, 10 A range, Resistive Load > 500 ohms



1.6.4.2 Norm 3.5 ms, typical 4.0 ms, typical

1.6.4.3 Fast 750 us, typical 1.5 ms, typical


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1.7 Voltage Forcing Slew Rate, Resistive Load > 500 ohms1.7.1 Full Scale current programmed on 1A, 10A range1.7.1.1 Slew slow 35 V/ms, typical1.7.1.2 Slew norm 350 V/ms, typical1.7.1.3 Slew fast 1600 V/ms, typical1.7.2 Full Scale current programmed on 5A range1.7.2.1 Slew slow 17.5 V/ms, typical1.7.2.2 Slew norm 175 V/ms, typical1.7.2.3 Slew fast 800 V/ms, typical1.7.3 Variable current programmed on 1A, 10A range1.7.3.1 Slew slow (35 * Iprog / Irange) V/ms, typical1.7.3.2 Slew norm (350 * Iprog / Irange) V/ms, typical1.7.3.3 Slew fast (1600 * Iprog / Irange) V/ms, typical1.7.4 Variable current programmed on 5A range1.7.4.1 Slew slow (17.5 * Iprog / Irange) V/ms, typical1.7.4.2 Slew norm (175 * Iprog / Irange) V/ms, typical1.7.4.3 Slew fast (800 * Iprog / Irange) V/ms, typical

2. SYSTEM VOLTAGE METERING

2.1 Range, Note 5 0 to +/-100 V

2.2 Ranges 2 V, 1 0V, 50 V, 100 V Full Scale

2.3 Accuracy, Calibrated, Note 12.3.1 Vrange = 2 V 0.25% + 3 mV + VCM *(0.01 mV/V)2.3.2 Vrange = 10 V 0.25% + 7.5 mV + VCM *(0.05 mV/V)2.3.3 Vrange = 50 V 0.25% + 37 mV + VCM *(0.25 mV/V)2.3.4 Vrange = 100 V 0.25% + 75 mV + VCM *(0.5 mV/V)

2.4 Maximum Allowable Voltage, Note 52.4.1 Differential Hi to Lo +/-100 V, nominal2.4.2 Single Channel Hi or Lo to Gnd +/-200 V, nominal

3. LOCAL VOLTAGE METERING

3.1 Range, Note 5 0 to +/-100 V

3.2 Ranges 2 V, 10 V, 50 V, 100 V Full Scale

3.3 Accuracy, Calibrated3.3.1 Voltmeter Filter Low (vm_filt:low)3.3.1.1 Vrange = 2 V, vm_filt:low 0.25% + 3 mV + VCM *(0.01 mV/V)3.3.1.2 Vrange = 10 V, vm_filt:low 0.25% + 7.5 mV + VCM *(0.05 mV/V)3.3.1.3 Vrange = 50 V, vm_filt:low 0.25% + 37 mV + VCM *(0.25 mV/V)3.3.1.4 Vrange = 100 V, vm_filt:low 0.25% + 75 mV + VCM *(0.5 mV/V)3.3.2 Voltmeter Filter Medium or Bypass (vm_filt: medium or bypass)3.3.2.1 Vrange = 2 V, vm_filt:medium or bypass 0.25% + 8 mV + VCM *(0.01mV/V)3.3.2.2 Vrange = 10 V, vm_filt:medium or bypass 0.25% + 25 mV + VCM *(0.05mV/V)3.3.2.3 Vrange = 50 V, vm_filt:medium or bypass 0.25% + 125 mV + VCM *(0.25 mV/V)3.3.2.4 Vrange = 100 V, vm_filt:medium or bypass 0.25% + 250 mV + VCM *(0.5 mV/V)

3.4 Maximum Allowable Voltage, Note 5


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3.4.1 Differential Hi to Lo +/-100 V, nominal3.4.2 Single Channel Hi or Lo to Gnd +/-200 V, nominal

3.5 Local Voltage Metering Bandwidth3.5.1 2V range3.5.1.1 vm_filt: low 510 Hz, typical3.5.1.2 vm_filt: medium 29 kHz, typical3.5.1.3 vm_filt: bypass 72 kHz, typical3.5.2 10V, 50V, 100V ranges3.5.2.1 vm_filt: low 510 Hz, typical3.5.2.2 vm_filt: medium 28 kHz, typical3.5.2.3 vm_filt: bypass 58 kHz, typical

3.6 Local Voltage Metering Settling Time to within 3% of Final Value3.6.1 vm_filt: low 1.2 ms, typical3.6.2 vm_filt: medium 21 us, typical3.6.3 vm_filt: bypass 11 us, typical

4. CURRENT FORCING

4.1 Range, Note 54.1.1 DC 0 to +/-4 A4.1.2 Pulsed (<=5ms, 10% duty cycle) 0 to +/-10 A

4.2 Ranges 200 uA, 1 A, 5 A, 10 A Full Scale

4.3 Accuracy, Calibrated4.3.1 Irange = 200uA 0.4% + 1.5 uA + 10 nA/Vhigh

where Vhigh = maximum of the High Force voltage with respect toeither the Low Force voltage OR the System Ground voltage

4.3.2 Irange = 1 A 0.4% + 2.5 mA4.3.3 Irange = 5 A 0.5% + 6 mA4.3.4 Irange = 10 A 0.5% + 12.5 mA

4.4 Maximum Allowable Voltage, Note 54.4.1 DC minimum of (applicable compliance voltage limit) or (100 W/Iprog)4.4.2 Pulsed, <=5 ms, 10% duty cycle

minimum of (applicable compliance voltage limit) or (150 W/Iprog)

4.5 Maximum Output Voltage, Note 5 +/-100 V


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Table 2: 4.6 Current Forcing Settling Time

ProgrammedSlew Rate

0-Fullscale transition on the 1 A range,|Vprog - Iprog*Rload| > 12 V,Resistive Load <= 2.0 ohms


4.6.1.1 Slow 9.0 ms750 us, typical

23 ms1.7 ms, typical





ProgrammedSlew Rate

0-Fullscale transition on the 5 A, 10 A range,|Vprog - Iprog*Rload| > 12 V,Resistive Load <= 2.0 ohms



23 ms7.5 ms, typical





ProgrammedSlew Rate

0-1 A transition on the 1 A, 5 A, 10 A range,|Vprog - Iprog*Rload| > 12 V,




75.0 ms60.0 ms, typical

4.6.3.2 Norm 3.5 ms2.9 ms, typical

7.5 ms6 ms, typical


2.25 ms1 ms, typical

ProgrammedSlew Rate

0-400 mA transition on the 1 A, 5 A, 10 A range,|Vprog - Iprog*Rload| > 12 V,




4.6.4.2 Norm 48 ms, typical 120 ms, typical

4.6.4.3 Fast 10 ms, typical 23 ms, typical

ProgrammedSlew Rate

0-Fullscale transition on the 1 A, 5 A, 10 A range,|Vprog - Iprog*Rload| = 2 V,Resistive Load = 0.15 ohms


4.6.5.1 Slow 2.3 ms, typical 4.5 ms, typical

4.6.5.2 Norm 230 us, typical 450 us, typical

4.6.5.3 Fast 100 us, typical 120 us, typical


Octal V/I Source

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5. SYSTEM CURRENT METERING

5.1 Range, Note 5 0 to +/-10 A

5.2 Ranging5.2.1 Ranges (Irange) 200 uA, 1 A, 5 A, 10 A5.2.2 Ammeter Gains (amm_gain) 1, 10

5.3 DC Accuracy, Calibrated, Notes 1, 35.3.1 Irange = 200 uA amm_gain=1 0.4% + 0.5 uA + Vhigh*(10 nA/V)5.3.2 Irange = 200 uA amm_gain=10 0.4% + 750 nA + Vhigh*(10 nA/V)5.3.3 Irange = 1 A amm_gain=1 0.4% + 2.5 mA + VCM *(5 uA/V)5.3.4 Irange = 1 A amm_gain=10 0.4% + 1.25 mA + VCM *(5 uA/V)5.3.5 Irange = 5 A amm_gain=1,10 0.5% + 6 mA + VCM *(25 uA/V)5.3.6 Irange = 10 A amm_gain=1,10 0.5% + 12.5 mA + VCM *(50 uA/V)


5.5 Maximum Allowable Voltage, Note 55.5.1 Single Channel Hi or Lo to Gnd +/-200 V, nominal

6. LOCAL CURRENT METERING

6.1 Range, Note 5 0 to +/-10 A

6.2 Ranging6.2.1 Ranges (Irange) 200 uA, 1 A, 5 A, 10 A6.2.2 Ammeter Gains (amm_gain) 1, 10

6.3 DC Accuracy, Calibrated, Notes 3,86.3.1 Ammeter Filter Low (amm_filt:low)6.3.1.1 Irange = 200 uA amm_gain=1, amm_filt:low 0.4% + 1.5 uA + Vhigh*(10 nA/V)6.3.1.2 Irange = 200 uA amm_gain=10,amm_filt:low 0.4% + 750 nA + Vhigh*(10 nA/V)6.3.1.3 Irange = 1 A amm_gain=1, amm_filt:low 0.4% + 2.5 mA + VCM*(5 uA/V)6.3.1.4 Irange = 1 A amm_gain=10,amm_filt:low 0.4% + 1.25 mA + VCM*(5 uA/V)6.3.1.5 Irange = 5 A amm_gain=1,10 amm_filt:low 0.5% + 6 mA + VCM*(25 uA/V)6.3.1.6 Irange = 10 A amm_gain=1,10 amm_filt:low 0.5% + 12.5 mA + VCM*(50 uA/V)

6.3.2 Ammeter Filter Medium or Bypass (amm_filt:medium or bypass)6.3.2.1 Irange = 200 uA amm_gain=1,10

amm_filt:medium or bypass 0.4% + 2.5 uA + Vhigh*(10 nA/V)6.3.2.2 Irange = 1 A amm_gain=1,10

amm_filt:medium or bypass 0.4% + 5 mA + VCM*(5 uA/V)6.3.2.3 Irange = 5 A amm_gain=1,10

amm_filt:medium or bypass 0.5% + 12.5 mA + VCM*(25 uA/V)6.3.2.4 Irange = 10 A amm_gain=1,10

amm_filt:medium or bypass 0.5% + 25mA + VCM*(50 uA/V)


6.5 Maximum Allowable Voltage, Note 56.5.1 Single Channel Hi or Lo to Gnd +/-200 V, nominal

6.6 Local Current Metering Bandwidth6.6.1 amm_filt: low 500 Hz, typical


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6.6.2 amm_filt: medium, amm_gain=1 28 kHz, typical6.6.3 amm_filt: medium, amm_gain=10 26 kHz, typical6.6.4 amm_filt: bypass, amm_gain=1 65 kHz, typical6.6.4 amm_filt: bypass, amm_gain=10 50 kHz, typical

6.7 Local Current Metering Settling Time to within 3% of Final Value6.7.1 amm_filt: low 1.1 ms, typical6.7.2 amm_filt: medium 21 us, typical6.7.3 amm_filt: bypass 8.5 us, typical

7. COMPLIANCE RANGES

7.1 DC Range Maximum V/Maximum I/Maximum Power7.1.1 25 V Compliance 25 V/4 A/100 W7.1.2 50 V Compliance 50 V/2 A/100 W7.1.3 100 V Compliance 100 V/1 A/100 W

7.2 Pulsed Range, <=5ms, 10% duty cycle7.2.1 25 V Compliance 25 V/10 A/150 W7.2.2 50 V Compliance 50 V/5 A/150 W7.2.3 100 V Compliance 100 V/2 A/150 W

7.3 Maximum Allowable Power, Note 57.3.1 Single Channel7.3.1.1 DC 100 W7.3.1.2 Pulsed, <=5 ms, 10% duty cycle 150 W7.3.2 Octal V/I7.3.2.1 DC 800 W7.3.2.2 Pulsed, <=5 ms, 10% duty cycle 1200 W

7.4 Switching Time between Compliance Range changesCompliance ranges may not be switched under load

7.4.1 To 25 V Compliance range 5 ms, typical7.4.2 To 50 V Compliance range 16 ms, typical7.4.3 To 100 V Compliance range 16 ms, typical


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8. MODULATION

8.1 Voltage Modulation

8.1.1 Ranging8.1.1.1 Full Scale Range with wave_gain = 0.1 400 mV8.1.1.2 Full Scale Range with wave_gain = 1.0 4 V8.1.1.3 Full Scale Range with wave_gain = 10.0 40 V

8.1.2 Resolution depends on modulation source; reference modulation source ESSD

8.1.3 DC Accuracy, Note 48.1.3.1 wave_gain = 0.1 0.5% + 4 mV, typical8.1.3.2 wave_gain = 1.0 0.5% + 7 mV, typical8.1.3.3 wave_gain = 10.0 0.5% + 35 mV, typical

8.1.4 Bandwidth 20 kHz, typical1 V volt pp, 2 V range, 4 A programmed on 5 A rangefast slew50 kohm loadrelative to measurement made at 1 kHz

8.2 Current Modulation

8.2.1 Ranging8.2.1.1 Full Scale Range with wave_gain = 0.1, Irange = 1A, 5A, 10A 40 mA

7. Graphical Summary of Octal V/I Single Channel Power Curves


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8.2.1.2 Full Scale Range with wave_gain = 1.0, Irange = 1A, 5A,10A 400 mA8.2.1.3 Full Scale Range with wave_gain = 10.0, Irange = 1A, 5A,10A 4.0 A

8.2.2 Resolution depends on modulation source; reference modulation source ESSD

8.2.3 DC Accuracy, Note 48.2.3.1 wave_gain = 0.1, Irange = 1 A 0.5% + 0.2 mA, typical8.2.3.2 wave_gain = 0.1, Irange = 5 A, 10 A 1.0% + 1 mA, typical8.2.3.3 wave_gain = 1.0, Irange = 1 A 0.5% + 1 mA, typical8.2.3.4 wave_gain = 1.0, Irange = 5 A, 10 A 0.5% + 2 mA, typical8.2.3.5 wave_gain = 10.0, Irange = 1 A, 5 A, 10 A 0.5% + 10 mA, typical

8.2.4 Bandwidth 20 kHz, typical100 mA pp, 15 V programmed, 1 A programmed on 5 A rangefast slew1.0 ohm loadrelative to measurement made at 1 kHz

9. CONNECTIONS

9.1 Total Connect Time, High and Low, including 9.1.1 5.1 ms, typical9.1.1 Settling Time required by the user after

a connect statement to close relays 2.6 ms, typical9.2 Total Disconnect Time, High and Low, including 9.2.1 4.3 ms, typical9.2.1 Settling Time required by the user after

a disconnect statement to open relays 2.2 ms, typical

10. THADS BUFFERS

10.1 Ranges 25 V, 100 V, 200 V, AC10.2 Attenuation10.2.1 25 V Range 0.240, nominal10.2.2 100 V Range 0.060, nominal10.2.3 200 V Range 0.030, nominal10.2.4 AC Range, midband 0.97, typical

10.3 Absolute maximum input voltage, AC range 200 V

10.4 Output DC Accuracy 5% of Signal + 100 mV, typical

10.5 Dynamics10.5.1 25 V Range10.5.1.1 Output Rise Time, 10 V input transition, 10% to 90% <55 ns, typical10.5.1.2 Bandwidth 1 MHz, typical10.5.1.3 Scaled Output Slew Rate, 10 V input, Note 6 >270 V/us, typical10.5.2 100V Range10.5.2.1 Output Rise Time, 10 V input transition, 10% to 90% <55 ns, typical10.5.2.2 Bandwidth 1 MHz, typical10.5.2.3 Scaled Output Slew Rate, 10 V input, Note 6 >320 V/us, typical10.5.3 200 V Range10.5.3.1 Output Rise Time, 10V input transition, 10% to 90% <55 ns, typical10.5.3.2 Bandwidth 1MHz, typical10.5.3.3 Scaled Output Slew Rate, 10V input, Note 6 >500 V/us, typical10.5.4 AC Range


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10.5.4.1 Output Rise Time, 10 V input transition, 10% to 90% <400 ns, typical10.5.4.2 Low Frequency Cutoff, -3 dB from midband 5 Hz, typical10.5.4.3 High Frequency Bandwidth, -3 dB from midband 1 MHz, typical10.5.4.4 Output Slew Rate, 10 V input >35 V/us, typical

10.6 Attenuator Input Resistance to system ground10.6.1 25 V Range 12 Mohms, typical10.6.2 100 V Range 9.7 Mohms, typical10.6.3 200 V Range 9.4 Mohms, typical10.6.4 AC Range >500 Mohms, typical

11. MISCELLANEOUS

11.1 Floating Performance11.1.1 Average Low Side Leakage Current to Ground, 0 V 10 uA, typical11.1.2 Low Side Resistance to Ground 40 kohm, typical

11.2 Maximum Allowable Series Resistance inForce lead for maximum voltage and currentsimultaneously, Note 9 0.10 ohm, nominal

11.3 Shutdown/Alarm Conditions, Note 711.3.1 Sense Current threshold 200 uA, typical11.3.2 Overtemperature Shutdown11.3.2.1 Junction temperature prediction threshold 110 deg C, nominal


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11.3.2.2 Pulse Current threshold timefor |Output Current|>5 A

-0.014*ln((Output Current - 5 A)/Output Current), nominal

11.3.2.3 Heatsink temperature threshold 60 deg C, nominal11.3.3 Relay Overcurrent Detect absolute threshold 200 mA +/- 40 mA, typical

�

Typical Octal V/I Pulse Current Shutdown Time, Note 7

(sec

onds

)

(Amps)


Main Menu

Specs 25 Power AL Disconnect Card

NOTES:

NOTE 1This specification covers the PALDCC itself, the cable to the system,the connector from that cable to the PALDCC and the Pogo pinconnections between the PALDCC and the Configuration board.

NOTE 2Resistance numbers apply from the bulkhead connector (but not includingthe contact resistance itself) to the Pogo pad on the configurationboard.

NOTE 3Holdoff voltage applied with force, sense, and guard for a pin connectedtogether. If multiple force connections are present, they are allconnected together. All other pins are tied to ground.

NOTE 4Throughout this document PALDCC is an acronym for Power Advanced LinearDisconnect Card.

NOTE 5The term “non-switching” is used in this document to refer to a state inwhich the relays are closed and no instantaneous power is dissipatedin the relay; “hot-switching” the relays is damaging and reduces thelifetime of the instrument.

NOTE 6This specification or feature does not apply to the PVIDCC.



Main Menu

I. POWER ADVANCED LINEAR DISCONNECT CARD SPECIFICATIONS

0. PALDCC Features

0.1 Disconnect Pins0.1.1 Quantity 60.1.2 Disconnect pin current 9 A Max, non-switching, nominal0.1.3 Disconnect pin voltage 1000 V, non-switching, nominal

0.2 TMS buffers (Note 6)0.2.1 Quantity 20.2.2 Input ranges 800 V FS

100 V FS20 V FS

0.2.3 Input Connections0.2.3.1 Any one of 6 pins, multiplexed0.2.3.2 Cal strobe signal, multiplexed0.2.4 Output Connections0.2.4.1 Output, buffer A THADS A0.2.4.2 Output, buffer B THADS B

0.3 The PALDCC passes the following signals from the system to theconfiguration board (Note 6):

System safety (SAFETY*)SPS safetyShutdown (shutdown*)

1. Disconnect Pins (Note 5)

1.1 Disconnect pin current 9 A Max DC, non-switching, nominal1.2 Disconnect pin current 12 Amps Max pulsed, non-switching, nominal1.3 Disconnect pin voltage 1000 V holdoff, non-switching, nominal

(Note 3)1.4 Maximum pulse width 1 ms for 12 A rating, nominal1.5 Maximum pulse duty cycle 50% for 12 A rating, nominal1.6 Holdoff voltage between any 125 V Max, nominal

two of force/sense/guard

1.7 Maximum switched voltage/current cannot exceed any of the following:1.7.1 50 V, nominal1.7.2 10 mA, nominal1.7.3 500 mW, nominal

(open circuit voltage multiplied by closed circuit current)

1.8 (Note 6) Path resistance, for any pin force connection, between connectoron Bulkhead and Config. Measured with all force connections for eachpin in parallel.

Path R, per pin 0.12 ohms nominal

2. THADS Buffers/Attenuators (Note 6)

2.1 Gain ranges +/-800 V FS+/-100 V FS+/-20 V FS



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2.2 Output of attenuator +/-6 V full scale, nominal

2.3 Gain accuracy, measured at DCRange Gain Gain Offset

(Nom.) Error (referred to input)------ ------- -------- --------------

2.3.1 800 V x0.0075 +/-5% +/-1.3 V nominal2.3.2 100 V x0.06 +/-5% +/-160 mV nominal2.3.3 20 V x0.30 +/-5% +/-33 mV nominal

2.4 Maximum input voltage: 1000 V on any range, nominal

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Main Menu

Specs 26 Power V/I Source

Notes

Note 1. DC Subsystem voltmeter resolution.

Note 2. Vo = Power V/I actual output voltage expressed in volts.Io = Power V/I actual output current expressed in amperes.Ps = Source power dissipation expressed in Watts.Duty Cycle ranges from 0-100%.

Note 3. F.S. signifies full scale on the programmed range.

Note 4. Operating characteristics of quadrant I are equivalent to those ofquadrant III. Operating characteristics of quadrant II are equivalentto those of quadrant IV. All four quadrants are shown for clarity.

Note 5. Voltage forcing accuracy term Ci is related to the current rangesetting as follows:

Ci = 12.5 mV/A on 40 mA rangeCi = 10.0 mV/A on 200 mA rangeCi = 0.7 mV/A on 1 A rangeCi = 0.3 mV/A on 5 A rangeCi = 0.2 mV/A on 30 A range

Note 6. DC Subsystem Delta Source resolution.


Power V/I Source

Main Menu

0. Power V/I Features

0.1 The Power V/I can be multiplexed up to 4 stations.

0.2 The A510 Mainframe can support up to two POWER V/I's consistingof two power V/I card sets, associated support cards, and power supplymodules.

0.3 The Power V/I can be connected to the AC Sub-System and the DeltaBus and modulated for ripple rejection tests on high-power devices.

0.4 The Power V/I is completely electrically isolated from the A510 testsystem. All voltages and currents are generated with respect to thePOWER V/I chassis and signal ground, and are floated from the A510system ground. (Power V/I signal ground is connected to common floatingpower return).

0.5 The Power V/I is a "pseudo" four-quadrant supply operating in quadrantsI and IV. Operation in quadrants II and III is achieved by outputpolarity switching using relays.

0.6 The Power V/I incorporates four alarms per POWER V/I source. All alarmsare monitored by the A510 system software.

0.6.1 Clamp Alarm - real time output monitor alarm0.6.2 Thermal Alarm - latched0.6.3 Setup Alarm - latched relay hot-switching prevention alarm0.6.4 Rail Fail Alarm - real time raw DC supply failure alarm

0.7 The Power V/I has three user-selectable loop speeds; fast, normal, andslow.

0.8 The Power V/I's can be parallel connected or serial connected.

0.9 The Power V/I has two modes of operation; high compliance mode and lowcompliance mode. Low compliance mode is used for high current at lowvoltages and high compliance mode is used for low current at highvoltages.

0.10 The Power V/I has user-selectable output impedance when the pwrsrc isgated off. The user can specify either ZOUT = high to force zeroamps, or ZOUT = low to force zero volts.


Power V/I Source

Main Menu

I. Power V/I Specification List

1. Voltage Forcing

1.1 Ranges 2 V, 10 V, 50 V

1.2 Resolution 11 bits plus sign

1.3 Maximum Operating Voltage +/-51.2 V

1.4 Accuracy (Notes 2, 3, 5) +/-(0.5% + 0.2% F.S. + (Ci*Io)), Max

2. Voltage Metering

2.1 Ranges 2 V, 10 V, 50 V

2.2 Resolution (1) 13 bits plus sign

2.3 Accuracy (Notes 2, 3, 5) +/-(1.6% + 0.3% F.S. + (Ci*Io)), Max

3. Current Forcing

3.1 Ranges 40 mA, 200 mA, 1 A, 5 A, 30 A

3.2 Resolution 11 bits plus sign

3.3 Maximum Operating Current See Section 7 below

3.4 Accuracy (Note 3) +/-(1.1% + 0.3% F.S.), Maximum

4. Current Metering

4.1 Ranges 40 mA, 200 mA, 1 A, 5 A, 30 A

4.2 Resolution (Note 1) 13 bits plus sign

4.3 Accuracy (Note 3) +/-(1.6% + 0.4% F.S.), Maximum

5. Isolation

5.1 Max Voltage to Ground +/-300 V, Nominal

5.2 Max Leakage to Ground +/-50 uA

6. Delta Bus Connections

6.1 Ranges 2 V, 20 V, 200 V

6.2 Resolution (Note 6) 11 bits plus sign


Power V/I Source

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6.3 Gain (Delta Bus to Power V/I output)6.3.1 Delta Source 2 V range: x0.2 Nominal6.3.2 Delta Source 20 V range: x2 Nominal6.3.3 Delta Source 200 V range: x20 Nominal

7. Operating RegionAllowable regions of operation: (Note 4)

The attached graphs depict the allowable areas of operation of the source.Note that in some regions the Power V/I's output must be pulsed to limitpower dissipation of the source. (See Figures 1 thru 18.)

7.1 Duty cycle and pulse width limitationsThe duty cycle and pulse width limits indicated are typical maximums.Exceeding these limits may cause the thermal protection circuitry toshut down the source.

7.2 DC operationDC operation is guaranteed for -1 A < Io < 1 A and -50 V < Vo < 50 V.This particular operating region is not shown on the plots.

7.3 Nominal power dissipation limits (Note 2)The attached graphs (Figures 1 thru 18) apply for operation of asingle Power V/I source. In cases where two Power V/I sources areactive, the power dissipation of both sources together must not exceed265 Watts. In mathematical terms:

[Ps (pwrsrc 1) + Ps (pwrsrc 2)] <= 375 W

7.3.1 Case 1 For operation in quadrant I, high compliance modePs = [84.5 - (0.4)(Io) - Vo](Io)(duty cycle in %)(1/100%)

7.3.2 Case 2 For operation in quadrant III, high compliance modePs = [84.5 + (0.4)(Io) + Vo](-Io)(duty cycle in %)(1/100%)

7.3.3 Case 3 For operation in quadrant IV, either compliance modePs = [19.0 + (0.4)(Io) + Vo](-Io)(duty cycle in %)(1/100%)

7.3.4 Case 4 For operation in quadrant II, either compliance modePs = [19.0 - (0.4)(Io) - Vo](Io)(duty cycle in %)(1/100%)

7.3.5 Case 5 For operation in quadrant I, low compliance modePs = [42.7 - (0.4)(Io) - Vo](Io)(duty cycle in %)(1/100%)

7.3.6 Case 6 For operation in quadrant III, low compliance modePs = [42.7 + (0.4)(Io) + Vo](-Io)(duty cycle in %)(1/100%)

Note: Ps = [Volts + (Ohms)(Amps) + Volts](Amps)(D.C. in %)(1/100%)

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Main Menu

Specs 27 Precision Low Frequency Digitizer

Notes:

1) The keyword "lpfilt" selects both the analog anti-aliasing filter and theDDF bank. In the case of the 2 kHz range, the analog anti-aliasing filteris the same as for the 5 kHz range.

2) Notation Notes:+ = arithmetic sumor = greater value of++ = rms sumVpk = programmed amplitudeVbl = programmed dc baselineDDF = digital decimation filter




6) There are two complete sets of Digital Decimation Filters that may beselected. One set is optimized for Frequency Domain Performance and one forTime Domain Performance. All specifications in frequency ranges 2 ->500 kHz that refer to DDF apply when using the Frequency Domain DDF's.

7) Total Harmonic Distortion Specifications for all frequency ranges exceptthe 500 kHz range apply only when operating in DDF mode, NOT DDF bypassmode.


For help interpreting some of the specifications in this document, see “AmplitudeError”, “Total Harmonic Distortion”, and “Total Noise” in the “InterpretingSpecifications” document.



Main Menu

I. PRECISION LOW FREQUENCY DIGITIZER


1.1 Input Voltage Range +/-11.0 Vpk

1.2 Differential Input Voltage +/-11.0 Vpk

1.3 Waveform Range & Resolution1.3.1 Resolution >20 bits/range1.3.2 Ranges 14.48 V peak

10.24 V peak7.24 V peak5.12 V peak3.62 V peak2.56 V peak1.81 V peak1.28 V peak0.905 V peak0.640 V peak0.452 V peak0.320 V peak0.226 V peak0.160 V peak0.113 V peak

1.4 DC Baseline Removal1.4.1 Range +/-11.0 Vpk1.4.2 Resolution (17 bits) 168 uV1.4.3 Accuracy +/-(Vbl*6 + 0.5) mV1.4.4 Long Term DNL 14 bits

1.5 Input Impedance >10 Mohm

1.6 Input Capacitance <200 pF

1.7 Common Mode Rejection1.7.1 dc - 100 Hz

Amplitude Range:1.7.1.1 14.48 V - 7.24 V >80 dB1.7.1.2 5.12 V - 3.62 V >100 dB1.7.1.3 2.56 V - 226 mV >90 dB1.7.1.4 160 mV - 113 mV >105 dB1.7.2 100 Hz - 1 kHz

Amplitude range:1.7.2.1 14.48 V - 7.24 V >65 dB1.7.2.2 5.12 V - 3.62 V >80 dB1.7.2.3 2.56 V - 905 mV >70 dB1.7.2.4 640 mV - 226 mV >75 dB1.7.2.5 160 mV - 113 mV >85 dB1.7.3 1 kHz - 20 kHz

Amplitude range:1.7.3.1 14.48 V - 7.24 V >35 dB1.7.3.2 5.12 V - 3.62 V >55 dB1.7.3.3 2.56 V - 905 mV >45 dB1.7.3.4 640 mV - 226 mV >50 dB



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1.7.3.5 160 mV - 113 mV >60 dB1.7.4 20 kHz - 100 kHz

Amplitude range:1.7.4.1 14.48 V - 7.24 V >25 dB1.7.4.2 5.12 V - 3.62 V >40 dB1.7.4.3 2.56 V - 905 mV >30 dB1.7.4.4 640 mV - 226 mV >35 dB1.7.4.5 160 mV - 113 mV >50 dB1.7.5 100 kHz - 500 kHz

Amplitude range:1.7.5.1 14.48 V - 7.24 V >10 dB typical1.7.5.2 5.12 V - 3.62 V >30 dB typical1.7.5.3 2.56 V - 905 mV >15 dB typical1.7.5.4 640 mV - 226 mV >20 dB typical1.7.5.5 160 mV - 113 mV >35 dB typical

1.8 Settling Time (after change in -)1.8.1 dc Baseline <2 ms1.8.2 Voltage Range <5 ms1.8.3 "lpfilt"1.8.3.1 2 kHz <10 ms1.8.3.2 20, 100, 500 kHz <4.5 ms1.8.4 "connect" <4.5 ms1.8.5 digital filter1.8.5.1 2 kHz range <517/sample_rate1.8.5.2 5 kHz range <517/sample_rate1.8.5.3 20 kHz range <365/sample_rate1.8.5.4 100 kHz range <117/sample_rate

1.9 DC Offset <(vrng*1.5 + 1.0) mV


1.11 Capture Memory Depth 256k samples


2.0 Operating Conditions:2.0.1 Anti-aliasing Filter (lpfilt) 2 kHz2.0.2 Modulator clock = aclock/N2.0.2.1 Minimum 0.5 MHz2.0.2.2 Maximum 1 MHz2.0.3 DDFs (excl. prime #'s) 8-64

2.1 Waveform Linearity Error2.1.1 DDFs 8-16 (frequency domain)

DDFs 11-16 (time domain) +/-2 ppm2.1.2 DDFs w/ prime factors < 17 +/-3 ppm2.1.3 DDFs w/ prime factors > 17 +/-15 ppm

2.2 Input Linearity Error +/-1.0 ppm

2.3 Absolute Accuracy +/-(Vin*5 + 5) mV



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2.4 DC Offset Drift Rate - sum of:2.4.1 Waveform Drift <(vrng*0.5)(time) uV/s2.4.2 Baseline Drift Rate <10 uV + (0.2 + 0.0011(Vbl**3.5))(time) uV/s

2.5 Spectral Impurities (115 dB) <(vrng*1.3 or 3) uVrms

2.6 Noise2.6.1 Total Noise(BW), dcbase off2.6.1.1 01. HZ - 10 Hz <(vrng*2.0++0.351) uVrms2.6.1.2 50 Hz - 2 kHz2.6.1.2.1 DDFs 8-16 (110 dB) <(vrng*2.2 ++ 5) uVrms2.6.1.2.2 DDFs 18-64 w/prime factors<17(100 dB) <(vrng*7.1 ++ 5) uVrms2.6.1.2.3 DDFs with prime factors >17 (90 dB) <(vrng*22 ++ 5) uVrms2.6.2 Total Noise(BW), dcbase on2.6.2.1 01. HZ - 10 Hz <(vrng*2.0 ++18) uVrms2.6.2.2 50 Hz - 2 kHz2.6.2.2.1 DDFs 8-16 <(vrng*2.2 ++20) uVrms2.6.2.2.2 DDFs 18-64 w/prime factors<17 <(vrng*7.1 ++20) uVrms2.6.2.2.3 DDFs with prime factors >17 <(vrng*22 ++ 20) uVrms


3.0 Operating Conditions:3.0.1 Anti-aliasing Filter (lpfilt) 2 kHz3.0.2 Modulator Clock = aclock/N3.0.2.1 Minimum 0.5 MHz3.0.2.2 Maximum 1 MHz3.0.3 DDFs (excl. prime #'s > 13) 8-64

3.1 Sine Wave Amplitude Accuracy3.1.1 DDF bypass (0.02 dB) +/-(Vpk*2.3 + 1) mV3.1.1 DDFs w/ prime factors <= 13 (0.06 dB) +/-(Vpk*6.9 + 1) mV3.1.1 DDFs w/ prime factors >= 17 (1.2 dB) +/-(Vpk*148 + 1) mV

3.2 Total Harmonic Distortion3.2.1 DDFs 8 - 163.2.1.1 Fundamental <= 400 Hz (115 dB) <(Vpk*1.3 or 1.3) uVrms3.2.1.2 Fundamental > 400 Hz (110 dB) <(Vpk*2.2 or 2.1) uVrms3.2.2 DDFs 18 - 64 (105 dB) <(Vpk*4.0 or 4.1) uVrms

3.3 Non-harmonic Spurious (115 dB) <(vrng*1.3 or 3) uVrms

3.4 Noise3.4.1 Total Noise(50 Hz - 2 kHz), dcbase off3.4.1.1 DDFs 8 - 16 (105 dB) <(vrng*4.0 ++ 5) uVrms3.4.1.2 DDFs 18-64 w/prime factors<17 (100 dB) <(vrng*7.1 ++ 5) uVrms3.4.1.3 DDFs with prime factors >17 (90 dB) <(vrng*22 ++ 5) uVrms3.4.2 Total Noise(50 Hz - 2 kHz), dcbase on3.4.2.1 DDFs 8 - 16 <(vrng*4.0 ++20) uVrms3.4.2.2 DDFs 18-64 w/prime factors<17 <(vrng*7.1 ++20) uVrms3.4.2.3 DDFs with prime factors >17 <(vrng*22 ++ 20) uVrms



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4.0 Operating Conditions:4.0.1 Anti-aliasing Filter (lpfilt) 5 kHz4.0.2 Modulator Clock = aclock/N4.0.2.1 Minimum 0.5 MHz4.0.2.2 Maximum 1 MHz4.0.3 DDFs (excl. prime #'s > 13 & 34,38) 8-42

4.1 Sine Wave Amplitude Accuracy4.1.1 DDF bypass (0.02 dB) +/-(Vpk*2.3 + 1) mV4.1.2 with DDF (0.3 dB) +/-(Vpk*35 + 1) mV

4.2 Total Harmonic Distortion4.2.1 DDFs 8 - 164.2.1.1 Fundamental <= 1 kHz (110 dB) <(Vpk*2.2 or 2.2) uVrms4.2.1.2 Fundamental > 1 kHz (105 dB) <(Vpk*4.0 or 4.0) uVrms4.2.2 DDFs 18 - 42 (105 dB) <(Vpk*4.0 or 4.0) uVrms


4.4 Noise4.4.1 Total Noise(50 Hz - 5 kHz), dcbase off4.4.1.1 DDFs 8 - 16 (105 dB) <(vrng*4.0 ++ 5) uVrms4.4.1.2 DDFs 18-42 (95 dB) <(vrng*13 ++ 5) uVrms4.4.2 Total Noise(50 Hz - 5 kHz), dcbase on4.4.2.1 DDFs 8 - 16 <(vrng*4.0 ++20) uVrms4.4.2.2 DDFs 18 - 42 <(vrng*13 ++20) uVrms


5.0 Operating Conditions:5.0.1 Anti-aliasing Filter (lpfilt) 20 kHz5.0.2 Modulator clock = aclock/N5.0.2.1 Minimum 2 MHz5.0.2.2 Maximum 4 MHz5.0.3 DDFs 8-32 (excl. prime #'s)

5.1 Sine Wave Amplitude Accuracy5.1.1 DDF bypass (0.06 dB) +/-(Vpk*6.9 + 1) mV5.1.1 with DDF (0.3 dB) +/-(Vpk*35 + 1) mV

5.2 Total Harmonic Distortion5.2.1 Fundamental <= 5 kHz (100 dB) <(Vpk*7.1 or 5) uVrms5.2.2 Fundamental > 5 kHz (95 dB) <(Vpk*13.0 or 5) uVrms


5.4 Noise5.4.1 Total Noise (50 Hz - 20 kHz) dcbase off(95 dB) <(vrng*13 ++ 10) uVrms5.4.2 Total Noise (50 Hz - 20 kHz) dcbase on <(vrng*13 ++ 22) uVrms



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6.0 Operating Conditions:6.0.1 Anti-aliasing Filter (lpfilt) 100 kHz6.0.2 Modulator clock = aclock/N6.0.2.1 Minimum 5 MHz6.0.2.2 Maximum 10 MHz6.0.3 DDFs 8-16 (excl. prime #'s)

6.1 Sine Wave Amplitude Accuracy6.1.1 DDF bypass (0.6 dB) +/-(Vpk*72 + 1) mV6.1.1 with DDF (5 dB) +/-(Vpk*778 + 1) mV


6.3 Non-harmonic Spurious (90 dB) <(vrng*21 or 5) uVrms

6.4 Noise6.4.1 Total Noise (50 Hz-100 kHz) dcbase off (80 dB) <(vrng*71 ++ 15) uVrms6.4.2 Total Noise (50 Hz-100 kHz) dcbase on <(vrng*71 ++ 27) uVrms


7.0 Operating Conditions:7.0.1 Anti-aliasing Filter (lpfilt) 500 kHz7.0.2 Modulator clock = aclock/N7.0.2.1 Minimum 20 MHz7.0.2.2 Maximum 25 MHz7.0.3 DDFs none

7.1 Sine Wave Amplitude Accuracy (2.5 dB) +/-(Vpk*334 + 1) mV


7.3 Non-harmonic Spurious (65 dB) <(vrng*400) uVrms

7.4 Total Noise (50 Hz - 500 kHz) (60 dB) <(vrng*710) uVrms

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Main Menu

Specs 28 Precision Low Frequency Source

Notes:

1) Extended calibration must be enabled to achieve the stated specificationsfor THD. If extended calibration is off, the THD specifications are degradedby 10 dB.

2) The tl_plfs_get_amp_filt() function is only valid for amplitude < 7.24 Vpk.Therefore, for amplitude > 7.24 Vpk, only the wider amplitude specificationsapply.

3) Spectral Impurities include only non-harmonically related spectralcomponents.

4) Notation Notes:+ = arithmetic sumor = greater value of++ = rms sumVpk = programmed amplitudeVbl = programmed dc baseline






Main Menu

I. PRECISION LOW FREQUENCY SOURCE INSTRUMENTATION SPECIFICATIONS


1.1 Peak Output Voltage (ac + dc) +/-11.0 Vpk


1.3 DC Baseline1.3.1 Range +/-11.0 V1.3.2 Resolution (17 bits) 168 uV1.3.3 Accuracy +/-(Vbl*6 + 0.5) mV1.3.4 Long Term DNL 14 Bits

1.4 Waveform Amplitude Range & Resolution1.4.1 dc to 100 kHz <10.24 Vpk1.4.2 100 kHz to 250 kHz <5.12 Vpk1.4.2 250 kHz to 500 kHz <2.56 Vpk1.4.3 Resolution <1 mdB

1.5 Output Current Compliance Limit >20 mA

1.6 Maximum Short Circuit Current <65 mA

1.7 Overcurrent Alarm Detection Threshold <45 mA

1.8 Output Impedance (DC - 500 kHz)1.8.1 25 Ohms1.8.1.1 Accuracy +/-1 Ohm1.8.1.2 Max. Capacitive Load >1 nF1.8.2 Low Z1.8.2.1 Zout <1 Ohm1.8.2.2 Max. Capacitive Load >100 pF1.8.3 Remote Kelvin (C pin only)1.8.3.1 Zout <0.1 Ohm1.8.3.2 Max. Capacitive Load >100 pF

1.9 Slew Rate >8 V/us, nominal

1.10 Settling Time (after change in -)1.10.1 DC Baseline <2 ms1.10.2 Waveform Amplitude (attenuator change) <5 ms1.10.3 Waveform Amplitude (same attenuator) <1 ms1.10.4 "lpfilt"1.10.4.1 2 kHz <10 ms1.10.4.2 20, 100, 500 kHz <4.5 ms1.10.5 "connect" <4 ms

1.11 DC Offset <(Vpk*1 + 2) mV

1.12 Waveform integrator1.12.1 Sample rate <20 MHz




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1.14 Sample Memory Depth1.14.1 Standard 64K samples1.14.2 Optional 1M samples


2.0 Operating Conditions:2.0.1 Smoothing Filter 2 kHz2.0.2 Sample Rate2.0.2.1 Minimum 400 kHz2.0.2.2 Maximum 500 kHz


2.2 Output Linearity Error +/-1.0 ppm

2.3 Absolute Accuracy +/-(Vpk*5 + 5) mV

2.4 DC Offset Drift Rate - (sum of:)2.4.1 Waveform Drift <(Vpk*500) nV/s2.4.2 DC Baseline Drift Rate <(10 uV+(0.2+0.0011(Vbl**3.5))(time) uV/s

2.5 Spectral Impurities2.5.1 50 Hz - 100 kHz (120 dB) <(Vpk*0.71 or 10) uVrms2.5.2 100 kHz - 1 MHz(110 dB) <(Vpk*2.2 or 30) uVrms

2.6 Noise2.6.1 Total Noise (BW), dcbase off2.6.1.1 0.1Hz - 10 Hz <(Vpk*2.0 ++ 0.351) uVrms2.6.1.2 50 Hz - 20 kHz (110 dB) <(Vpk*2.2 ++ 3.5) uVrms2.6.1.3 50 Hz - 100 kHz (105 dB) <(Vpk*4.0 ++ 9.0) uVrms2.6.1.4 50 Hz - 1 MHz (95 dB) <(Vpk*13 ++ 40.0) uVrms2.6.2 Total Noise (BW), dcbase on2.6.2.1 0.1Hz - 10 Hz <(Vpk*2.0 ++ 18) uVrms2.6.2.2 50 Hz - 20 kHz <(Vpk*2.2 ++ 20) uVrms2.6.2.3 50 Hz - 100 kHz <(Vpk*4.0 ++ 22) uVrms2.6.2.4 50 Hz - 1 MHz <(Vpk*13 ++ 40) uVrms


3.0 Operating Conditions:3.0.1 Smoothing Filter 2 kHz3.0.2 Sample Rate3.0.2.1 Minimum 400 kHz3.0.2.2 Maximum 500 kHz

3.1 Sine Wave Amplitude Accuracy3.1.1 Uncorrected (+0.1 dB, -0.5 dB) +(Vpk*12 + 1) mV,

-(Vpk*59 + 1) mV3.1.2 w/tl_plfs_get_amp_filt (0.1 dB) +/-(Vpk*12 + 1) mV

3.2 Total Harmonic Distortion3.2.1 amp < 5.12 Vpk (115 dB) <(Vpk*1.3 or 2.2) uVrms3.2.2 amp > 5.12 Vpk (105 dB) <(Vpk*4.0 or 2.2) uVrms



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3.3 Spectral Impurities3.3.1 50 Hz - 100 kHz (115 dB) <(Vpk*1.3 or 10) uVrms3.3.2 100 kHz - 1 MHz (110 dB) <(Vpk*2.2 or 30) uVrms

3.4 Noise3.4.1 Total Noise (BW), dcbase off3.4.1.1 50 Hz - 20 kHz (110 dB) <(Vpk*2.2 ++ 3.5) uVrms3.4.1.2 50 Hz - 100 kHz (105 dB) <(Vpk*4.0 ++ 9.0) uVrms3.4.1.3 50 Hz - 1 MHz (95 dB) <(Vpk*13 ++ 40.0) uVrms3.4.2 Total Noise (BW), dcbase on3.4.2.1 50 Hz - 20 kHz <(Vpk*2.2 ++ 20) uVrms3.4.2.2 50 Hz - 100 kHz <(Vpk*4.0 ++ 22) uVrms3.4.2.3 50 Hz - 1 MHz <(Vpk*13 ++ 40) uVrms


4.0 Operating Conditions:4.0.1 Smoothing Filter 20 kHz4.0.2 Sample Rate4.0.2.1 Minimum 2 MHz4.0.2.2 Maximum 3 MHz

4.1 Sine Wave Amplitude Accuracy4.1.1 Uncorrected (+-0.1 dB, -0.5 dB) +(Vpk*12 + 1) mV,


4.2 Total Harmonic Distortion4.2.1 amp < 5.12 Vpk (110 dB) <(Vpk*2.2 or 2.2) uVrms4.2.2 amp > 5.12 Vpk (100 dB) <(Vpk*7.1 or 2.2) uVrms

4.3 Spectral Impurities4.3.1 50 Hz - 100 kHz (115 dB) <(Vpk*1.3 or 10) uVrms4.3.2 100 kHz - 1 MHz (110 dB) <(Vpk*2.2 or 30) uVrms

4.4 Noise4.4.1 Total Noise (BW), dcbase off4.4.1.1 50 Hz - 20 kHz (95 dB) <(Vpk*13 ++ 3.5) uVrms4.4.1.2 50 Hz - 100 kHz (95 dB) <(Vpk*13 ++ 9.0) uVrms4.4.1.3 50 Hz - 1 MHz (90 dB) <(Vpk*22 ++ 40.0) uVrms4.4.2 Total Noise (BW), dcbase on4.4.2.1 50 Hz - 20 kHz <(Vpk*13 ++ 20) uVrms4.4.2.2 50 Hz - 100 kHz <(Vpk*13 ++ 22) uVrms4.4.2.3 50 Hz - 1 MHz <(Vpk*22 ++ 40) uVrms


5.0 Operating Conditions:5.0.1 Smoothing Filter 100 kHz5.0.2 Sample Rate5.0.2.1 Minimum 6.5 MHz5.0.2.2 Maximum 8 MHz



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5.1 Sine Wave Amplitude Accuracy5.1.1 Uncorrected (+0.5 dB, - 1.0 dB) +(Vpk*59 + 1) mV


5.2 Total Harmonic Distortion5.2.1 50 Hz - 50 kHz5.2.1.1 amp < 5.12 Vpk (95 dB) <(Vpk*13 or 6.7) uVrms5.2.1.2 amp > 5.12 Vpk (85 dB) <(Vpk*40 or 6.7) uVrms5.2.2 50 kHz - 100 kHz5.2.2.1 amp < 1.28 Vpk (95 dB) <(Vpk*13 or 6.7) uVrms5.2.2.2 amp 1.28 - 5.12 Vpk (90 dB) <(Vpk*22 or 6.7) uVrms5.2.2.3 amp > 5.12 Vpk (75 dB) <(Vpk*130 or 6.7) uVrms

5.3 Spectral Impurities5.3.1 100 kHz - 1 MHz (100 dB) <(Vpk*7.1 or 30) uVrms

5.4 Noise5.4.1 Total Noise (BW), dcbase off5.4.1.1 50 Hz - 100 kHz (80 dB) <(Vpk*71 ++ 9.0) uVrms5.4.1.2 50 Hz - 1 MHz (70 dB) <(Vpk*220 ++ 40.0) uVrms5.4.2 Total Noise (BW), dcbase on5.4.2.1 50 Hz - 100 kHz <(Vpk*71 ++ 22) uVrms5.4.2.2 50 Hz - 1 MHz <(Vpk*220 ++ 40) uVrms


6.0 Operating Conditions:6.0.1 Smoothing Filter 500 kHz6.0.2 Sample Rate6.0.2.1 Minimum 20 MHz6.0.2.2 Maximum 25 MHz

6.1 Sine Wave Amplitude Accuracy6.1.1 Uncorrected (+1.0 dB, - 1.5 dB) +(Vpk*120 + 1) mV


6.2 Total Harmonic Distortion6.2.1 500 Hz - 250 kHz6.2.1.1 amp < 1.28 Vpk (75 dB) <(Vpk*130 or 6.7) uVrms6.2.1.2 amp > 1.28 Vpk (70 dB) <(Vpk*220 or 6.7) uVrms6.2.2 250 - 500 kHz (55 dB) <(Vpk*1300 or 6.7) uVrms

6.3 Spectral Impurities 100 kHz - 1 MHz (100 dB) <(Vpk*7.1 or 30) uVrms

6.4 Total Noise (BW = 50 Hz - 1 MHz)6.4.1 500 Hz - 250 kHz (60 dB) <(Vpk*710 ++ 40.0) uVrms6.4.2 250 - 500 kHz (55 dB) <(Vpk*1300 ++ 40.0) uVrms

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Specs 29 Precision Multimeter

Notes:

1) Voltages at the DIB may not exceed +/-200 V peak and currents may not exceed+/-1 A or test system damage may occur.

2) For safety reasons, the 1000 V DCV and ACV meter ranges are not supported bythe IMAGE test language and their use is specifically locked out. They arenot tested.

MEASUREMENT OF VOLTAGES GREATER THAN 200 V MAY RESULT IN TEST SYSTEM DAMAGE.

3) Accuracy Specifications are a function of the quantity being measured and theselected meter range. DC accuracy specifications are therefore expressed as<ppm of reading> + <ppm of range>. AC accuracy specifications are expressedas <% of reading> + <% of range>.

Accuracy specifications may be degraded depending on the meter's temperaturewhen making a measurement relative to its temperature when last externallycalibrated. Further degradation may occur as noted for each measurement mode;e.g., when using a 2-wire configuration instead of a 4-wire configuration forresistance measurements or when measuring non-sinusoidal AC signals.

4) Guaranteeing Meter AccuracyMeter accuracy depends heavily on three items:

(1) The time elapsed since the meter's internal standards werecalibrated against external references (a process known as externalcalibration),(2) The time elapsed since the meter was autocalibrated,(3) The internal temperature of the meter relative to its internaltemperature when last externally calibrated (TXCAL), and when lastautocalibrated (TACAL). (The meter may be interrogated for thesetemperatures.)

4.1) Elapsed Time Since Last External CalibrationSpecifications for DC Volts, DC Current, and Resistance all assumethat no more than 90 days have elapsed since the last externalcalibration. Specifications for AC Volts assume that no more than2 years have elapsed since the last external calibration.

4.2) Elapsed Time Since Last AutocalibrationAll specifications assume that no more than 24 hours have elapsedsince the last autocalibration.

4.3) Meter Temperature For Basic Accuracy SpecificationsBasic meter accuracy specifications for DCV, DCI, and OHMS modes assume



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that the meter temperature at time of measurement is within 1 degree Cof TACAL and within 5 degrees C of TXCAL.

Basic meter accuracy specifications for ACV and ACDCV modes assume thatthe meter temperature at time of measurement is within 1 degree C ofTACAL.

4.4) "With ACAL" Temperature CoefficientsFor DCV, DCI, and OHMS modes, a set of "with ACAL" tempco's is provided.They apply only when the meter's operating temperature is still within1C of TACAL but more than 5C away from TXCAL. To use the "with ACAL"tempco's, determine the absolute difference between TXCAL and themeter's operating temperature, subtract 5C, multiply the tempco by thatnumber, and add the result to the PMM's basic accuracy specification.

4.5) "Without ACAL" Temperature CoefficientsFor DCV, DCI, and OHMS modes, a set of "without ACAL" tempco's isprovided. They apply only when the meter's operating temperature is notwithin 1C of TACAL and not within 1C of TXCAL. To use the "withoutACAL" tempco's, determine the absolute difference between TXCAL and themeter's operating temperature, multiply the tempco by that number, andadd the result to the basic PMM accuracy specification.

4.6) ACV and ACDCV Mode Temperature CoefficientsFor ACV and ACDCV modes, the tempco's given apply only when the meter'soperating temperature is beyond 1C of TACAL but within 5C of TACAL;TXCAL is irrelevant. To use them, determine the difference between themeter's operating temperature and TACAL, multiply the tempco by thatnumber, and add the result to the PMM's basic accuracy specification.Operation beyond 5C of TACAL is not specified.



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1.0 DC VOLTS

1.1 ACCURACY [a]Specifications are for PRESET; NPLC 100.

Units are ppm of reading + ppm of range.Range 24 Hour [b] 90 Day [c] 1 Year [c]100 mV 2.5 + 85 5.0 + 90 9 + 901 V 1.5 + 8.5 4.6 + 9 8 + 910 V 0.5 + 0.85 4.1 + 1 8 + 1100 V 2.5 + 0.38 6.0 + 0.38 10 + 0.38

Notes:[a] These specifications apply for readings corrected by an autozeromeasurement taken immediately before each reading.

[b] 24 Hour specifications for fixed range and Tcal +/-1C. Valid overfull range. For 24 hour accuracy without fixed range, add 0.05 ppm ofRange to 10 V, 0.5 ppm of Range to 1 V, and 5 ppm of Range to 0.1 Vspecifications.

[c] 90-day and 1-year specifications are within 24 hours of lastautocalibration and +/-1C of last TACAL and within +/-5C of TXCAL.

1.1.1 PMM INPUT OFFSET VOLTAGE DRIFTWhen only a single autozero measurement is taken before a series of readings,add to the above specifications this offset voltage drift:

+/-300 nV/s per input pin, from initial autozero offset measurement

1.2 TEMPERATURE COEFFICIENTUnits are ppm of reading + ppm of range.

Range With ACAL [a] Without ACAL [b]100 mV 0.15 + 1 1.2 + 11 V 0.15 + 0.1 1.2 + 0.110 V 0.15 + 0.01 0.5 + 0.01100 V 0.15 + 0.1 2 + 0.4

[a] Additional error from TXCAL +/-5C, but still within +/-1C of last TACAL.[b] Additional error from TXCAL +/-1C, not within +/-1C of last TACAL.

1.3 SETTLING CHARACTERISTICSFor first reading or range change error, add 0.0001% of input voltage stepadditional error.

1.4 GENERALMaximum Input

Range Full Scale Resolution Impedance100 mV 120.00000 10 nV >10 G1 V 1.20000000 10 nV >10 G10 V 12.0000000 100 nV >10 G100 V 120.000000 1 uV 10 M +/- 1%



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1.5 MAXIMUM INPUT AT DUTTerminalsHI to LO +/-200 VpkLO to GUARD +/-200 VpkGUARD to EARTH +/ 200 Vpk

2.0 DC CURRENT

2.1 ACCURACY [a]Specifications are for PRESET; NPLC 100.

Units are ppm of reading + ppm of range, unless otherwise noted.

Range [b] 24 Hour [c] 90 Day [d] 1 Year [d]100 nA 10 + 3% 30 + 3% 30 + 3%1 uA 10 + 0.3% 15 + 0.3% 20 + 0.3%10 uA 10 + 300 15 + 310 20 + 310100 uA 10 + 35 15 + 38 20 + 381 mA 10 + 6 15 + 8 20 + 810 mA 10 + 3.3 15 + 5.3 20 + 5.3100 mA 25 + 3 30 + 5 35 + 51 A 100 + 10 100 + 10 110 + 10

Notes:[a] These specifications include the per-pin leakage current shown insection 6.3 (+/-3 nA).

[b] Specifications for the 100 nA, 1 uA, and 10 uA ranges are typical.

[c] 24 Hour specifications for TXCAL +/-1C.

[d] 90-day and 1-year specifications are within 24 hours of lastautocalibration and +/-1C of last TACAL and within +/-5C of TXCAL.

2.2 TEMPERATURE COEFFICIENT

Units are ppm of reading + ppm of range.

Range With ACAL [a] Without ACAL [b]100 nA 2 + 50 10 + 2001 uA 2 + 5 2 + 2010 uA 2 + 1 10 + 4100 uA 2 + 1 10 + 31 mA 2 + 1 10 + 210 mA 2 + 1 10 + 2100 mA 2 + 1 25 + 21 A 2 + 2 25 + 3

[a] Additional error from TXCAL +/-5C, but still within +/-1C of last TACAL.[b] Additional error from TXCAL +/-1C, not within +/-1C of last TACAL.

2.3 SETTLING CHARACTERISTICSFor first reading or range change error, add 0.001% of input current stepadditional error.



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2.4 GENERALMaximum Shunt Burden

Range Full Scale Resolution Impedance [a] Voltage100 nA 120.000 1 pA 545.2 k 0.055 V1 uA 1.200000 1 pA 45.2 k 0.045 V10 uA 12.000000 1 pA 5.2 k 0.055 V100 uA 120.00000 10 pA 737 0.075 V1 mA 1.2000000 100 pA 107 0.100 V10 mA 12.000000 1 nA 17 0.100 V100 mA 120.00000 10 nA 8 0.250 V1 A 1.0500000 100 nA 7.1 <1.5 V

[a] The shunt impedance value includes the resistance of the cables betweenthe meter and the test head.

2.5 MAXIMUM INPUT AT DUTTerminalsI to LO +/-1 ApkLO to GUARD +/-200 VpkGUARD to EARTH +/-200 Vpk

3.0 RESISTANCE

3.1 ACCURACY FOR 4-WIRE MODE (OHMF) [a] [b]Specifications are for PRESET; NPLC 100; OCOMP ON, OHMF (four-wireconfiguration).

Units are ppm of reading + ppm of range, unless otherwise noted.

Range 24 Hour [c] 90 Day [d] 1 Year [d]10 6 + 3 16 + 5 16 + 5100 9 + 3 16 + 5 18 + 51 k 8 + 0.2 14 + 0.5 16 + 0.510 k 62 + 0.2 68 + 0.5 70 + 0.5100 k 120 + 0.2 130 + 0.5 130 + 0.51 M 0.12% + 1 0.12% + 2 0.12% + 210 M 1.2% + 5 1.2% + 10 1.2% + 10100 M 1.25% + 10 1.25% + 10 1.25% + 101 G 1.7% + 10 1.7% + 10 1.7% + 10

Notes:[a] These specifications include the per-pin leakage current shown insection 6.3 (+/-3 nA). The leakage current adds uncertainty to therange's current source and thus increases the ppm of reading figure.

[b] Four-wire ohms mode is typical for ranges above 100K.

[c] 24-hour specifications for TCAL +/-1C.

[d] 90-day and 1-year specifications are within 24 hours of lastautocalibration and +/-1C of last TACAL and within +/-5C of TXCAL.



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3.1.1 ACCURACY FOR 2-WIRE MODE (OHM) [a] [b]Specifications are for PRESET; NPLC 100; OCOMP ON, OHM (two-wire configuration).Units are ppm of reading + ppm of range, unless otherwise noted.

Range 24 Hour [b] 90 Day [c] 1 Year [c]10 5.3 + 71% 15.3 + 72% 15.3 + 73%100 6 + 7.1% 13 + 7.2% 15 + 7.3%1 k 5 + 0.71% 11 + 0.72% 13 + 0.73%10 k 32 + 710 38 + 720 40 + 730100 k 62 + 71 68 + 72 70 + 731 M 610 + 8 610 + 9 620 + 910 M 0.6% + 5.7 0.6% + 11 0.6% + 11100 M 0.65% + 10 0.65% + 10 0.65% + 101 G 1.1% + 10 1.1% + 10 1.1% + 10

[a] Two-wire ohms mode is typical for ranges below 1M.

[b] These specifications include the per-pin leakage current shown insection 6.3 (+/-3 nA) and the loop resistance shown in section 6.2(7 ohms). The leakage current adds uncertainty to the range's currentsource and thus increases the ppm of reading figure; the loop resistancecontributes an offset and thus increases the ppm of range figure.

3.2 TEMPERATURE COEFFICIENTUnits are ppm of reading + ppm of range.Range With ACAL [a] Without ACAL [b] AZERO OFF [c]10 1 + 1 3 + 1 50100 1 + 1 3 + 1 501000 1 + 0.1 3 + 0.1 510 k 1 + 0.1 3 + 0.1 5100 k 1 + 0.1 3 + 0.1 11 M 1 + 1 3 + 1 110 M 5 + 2 20 + 20 1100 M 25 + 2 100 + 20 101 G 250 + 2 1000 + 20 100

[a] Additional error from TXCAL +/-5C, but still within +/-1C of last TACAL.[b] Additional error from TXCAL +/-1C, not within +/-1C of last TACAL.[c] For a stable environment +/-1C add this error for AZERO OFF.

(ppm of range)/C

3.3 SETTLING CHARACTERISTICSFor first reading error following range change, add the total 90 day measurementerror for the current range. Preprogrammed settling delay times are for <200 pFexternal circuit capacitance.



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3.4 GENERALMaximum Current Test Open

Range Full Scale Resolution Source Voltage Circuit10 12.00000 10 u 10 mA 0.1 V 12 V100 120.00000 10 u 1 mA 0.1 V 12 V1000 1200.0000 100 u 1 mA 1.0 V 12 V10 k 12.000000 1 m 100 uA 1.0 V 12 V100 k 120.00000 10 m 50 uA 5.0 V 12 V1 M 1.2000000 100 m 5 uA 5.0 V 12 V10 M 12.000000 1 500 nA 5.0 V 12 V100 M 120.00000 10 500 nA 5.0 V 12 V1 G 1.2000000 100 500 nA 5.0 V 12 V

Maximum MaximumRange Lead Res. Series Offset10 20 ohm 0.01 V100 200 ohm 0.01 V1000 150 ohm 0.1 V10 k 1.5 k 0.1 V100 k 1.5 k 0.5 V1 M 1.5 k10 M 1.5 k100 M 1.5 k1 G 1.5 k

3.5 MAXIMUM INPUTTerminalsHI to LO +/-200 VpkHI & LO Sense to LO +/-200 VpkLO to GUARD +/-200 VpkGUARD to EARTH +/-200 Vpk

4.0 AC VOLTS

4.1 ACV ACCURACY (ACV Function)Specifications are good for up to 2 years after last external calibration.

Specifications apply for within 24 hours of last autocalibration and +/-1C oflast TACAL.

Specifications apply for PRESET settings and for sinewave inputs (crest factor = 1.4).

Specifications do not apply for inputs below 100 mV RMS; the 10 mV and 100 mV ACrange are not specified. Otherwise, specifications apply for inputs between1/20 full-scale and full-scale RMS.

Units are % of Reading + % of Range.

10 Hz - 20 Hz - 40 Hz - 1 kHz -Range 20 Hz 40 Hz 1 kHz 20 kHz1 V 0.117 + 0.024 0.041 + 0.01 0.022 + 0.0034 0.029 + 0.003410 V 0.117 + 0.024 0.041 + 0.01 0.022 + 0.0034 0.029 + 0.0034100 V 0.13 + 0.024 0.054 + 0.01 0.036 + 0.004 0.036 + 0.015



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20 kHz - 50 kHz - 100 kHz - 200 kHz -Range 50 kHz 100 kHz 200 kHz 300 kHz1 V 0.1 + 0.004 0.5 + 0.01 2 + 0.03 3.5 + 0.0510 V 0.1 + 0.004 0.5 + 0.006 2 + 0.03 3.5 + 0.06100 V 0.12 + 0.025 0.56 + 0.012 2 + 0.12 3.5 + 0.12

300 kHz - 400 kHz -Range 400 kHz 500 kHz1 V 5.5 + 0.05 8.5 + 0.0510 V 5.5 + 0.06 8.5 + 0.06100 V 5.5 + 0.12 8.5 + 0.12

TEMPERATURE COEFFICIENTAdditional error beyond +/-1C, but still within +/-5C of last TACAL.Units are % of Reading + % of Range.Range Temp. Co.1 V - 100V 0.001 + 0.0001

4.1.1 ACDCV ACCURACY (ACDCV Function)For ACDCV accuracy add the following additional error to the ACV accuracy andtemperature coefficient. Units are % of Reading + % of Range.

DC < 10% of AC Voltage DC > 10% of AC VoltageRange Accuracy Temp. Co. Accuracy Temp. Co.1 V - 100 V 0.0 + 0.008 0 + 0.0025 0.0 + 0.07 0 + 0.025

Accuracy figures apply for temperatures within +/-1C of last TACAL.

Temperature coefficient figures apply for temperatures beyond +/-1C, but stillwithin +/-5C of last TACAL.

4.2 ADDITIONAL ERRORSAdd the following additional errors to the ACV accuracy and temperaturecoefficient if applicable.4.2.1 LOW FREQUENCY ERROR (% of reading)

ACBAND LOW_________________________________________

Signal 10 Hz - 1 kHz 1 - 10 kHz >10 kHzFrequency NPLC > 10 NPLC > 1 NPLC > 0.1200 - 500 Hz 0 0.15500 - 1 kHz 0 0.015 0.91 - 2 kHz 0 0 0.22 - 5 kHz 0 0 0.055 - 10 kHz 0 0 0.01

4.2.2 CREST FACTOR ERROR (% of reading)Crest AdditionalFactor Error1 - 2 02 - 3 0.153 - 4 0.254 - 5 0.40



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4.3 SETTLING CHARACTERISTICSFor first reading or range change error using default delays, add 0.01% ofinput voltage step additional error. The following applies for DELAY 0.

Function ACBAND LOW DC Component Settling Time to 0.01%ACV >=10 Hz DC < 10% AC 0.5 s

DC > 10% AC 0.9 sACDCV 10 Hz - 1 kHz 0.5 s

1 kHz - 10 kHz 0.08 s>=10 kHz 0.015 s

4.4 GENERALMaximum

Range Full Scale Resolution Input Impedance [a]1 V 1.20000000 1 uV 1 Meg +/- 15% shunted with <140 pF10 V 12.0000000 10 uV 1 Meg +/- 2% shunted with <140 pF100 V 120.000000 100 uV 1 Meg +/- 2% shunted with <140 pF

[a] Add capacitance shown in section 6.1 to these figures.

4.5 COMMON MODE REJECTIONFor 1000 ohm imbalance in LO lead, >90 dB for DC to 60 Hz

4.6 MAXIMUM INPUT AT DUTTerminalsHI to LO +/-200 VpkLO to GUARD +/-200 VpkGUARD to EARTH +/-200 VpkVolt-Hz Product 100,000,000

5.0 GUARD DRIVERSNOTE: Guard drivers are not present in the A510 Standard Linear test system.

The specifications given in sections 5.1 and 5.2 do not apply for theA510 Standard Linear test system.

5.1 INPUT CHARACTERISTICSMaximum Input Current: 50 pA (typical)Maximum Input Voltage: +/-11.5 V peak min.Maximum Non-Damaging

Input: +/-200 V (typical)Input Alarm Threshold: 12 V

5.2 OUTPUT CHARACTERISTICS (typical)Maximum Load Capacitance: 3 nF without slew rate degradation (typical)Slew Rate: 20 V/us with load capacitance <3 nF (typical)Full Power Bandwidth: 500 kHz (typical)Small Signal (1V p-p)

Bandwidth: 5 MHz (typical)Maximum Output Voltage: +/-11.5 V peakMaximum Output Current: +/-40 mAOvercurrent Protection: sustained short-circuit to ground without damageOutput Alarm Threshold: 40 mA steady-state output current



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6.0 PMM INPUT CHARACTERISTICS

6.1 PMM INPUT CAPACITANCE (typical)PMM Mode Input Capacitanceconfig:v guard:off 1200 pF [a]config:v guard:on 400 pF [b]

config:v_low_c guard:off 800 pF [a]config:v_low_c guard:on 160 pF [b]

[a] In the A510 standard linear test system, this figure applies only forcapacitance at the bulkhead connector; it does not include capacitance dueto user's external cables.

[b] Guard drivers are not present in the A510 Standard Linear test system; thismode of operation is not supported in the A510 Standard Linear test system.

6.2 PMM LOOP RESISTANCE<7 ohm total resistance for either pair of input pins

6.3 PMM INPUT LEAKAGE CURRENT+/-3 nA per input pin

7.0 PMM FEATURESThe PMM supports the measurements shown below. Applicable PMM programminglanguage keywords are shown in parentheses.

NOTE: Guard drivers are not present in the A510 Standard Linear test system.The user must ground or drive the guards in the A510 Standard Lineartest system.

2:1 Multiplexed Voltage Measurements (config:v)source may be single-ended or differentialguards may be grounded or driven from high-side

2:1 Multiplexed Low-Capacitance Voltage Measurements (config:v_low_c)source may be single-ended or differentialguards may be grounded or driven from high-side

4-Wire Voltage Ratio Measurements (config:ratio_ab)guards may be grounded or driven from high-sides

2:1 Multiplexed I Measure (config:i)guards may be grounded, connected to low-side, or driven from low-side

2:1 Multiplexed 2-wire Resistance Measurements (config:r_2w)guards may be grounded or driven from high-side

4-wire Resistance Measurements (config:r_4w)guards may be grounded or driven from high-side

Voltage Measurements over THADS Bus

Voltage Measurements over DC Matrix

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Specs 30 Pulse Driver

Note:

** Specifications apply at the top of DIB card.

I. PULSE DRIVER INSTRUMENTATION SPECIFICATIONS

1. General Specifications

1.1 Inputs1.1.1 Trigger bus - 1 of 6 trigger bus inputs can be used to start

a pulse output.1.1.2 CPU write - a CPU write can be used to start a pulse output.

1.2 Outputs1.2.1 Pulse Source1.2.1.1 Pogo path - thru relay mux to 1 of 4 Pogo pins1.2.1.2 RF path - thru blind mate RF connector1.2.2 Differential ECL control signal - thru Pogo block1.2.3 Time bus - all pulse outputs can be connected to time bus

trigger 7 or trigger 8 thru a local comparator.

1.3 Modes1.3.1 Single pulse1.3.2 Toggle1.3.3 Clocked1.3.4 Active high/active low

2.0 DC Specifications

2.1 Pulse out - Pogo pin2.1.1 Pulse output voltage swing(unterminated)2.1.1.1 max +/- 11 V2.1.2 Output impedance 95 Ohm typical2.1.3 Pulse Amplitude ranges (full scale-Vpp, unterminated)2.1.3.1 Attenuate by 1 22.0 Vpp2.1.3.2 Attenuate by 2 11.0 Vpp2.1.3.3 Attenuate by 4 5.5 Vpp2.1.3.4 Attenuate by 8 2.75 Vpp2.1.4 Pulse amplitude resolution 0.03% (12B FS)


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2.1.5 Pulse amplitude accuracy2.1.5.1 VOH 0.4% of range

+/-3 mV2.1.5.2 VOL 0.4% of range

+/-4 mV2.1.6 DC offset range (full scale, unterminated) +/-11 V2.1.7 Output current (short circuit) +110 mA,-220 mA nominal

2.2 Pulse out - RF path2.2.1 Pulse output voltage swing(unterminated)2.2.1.1 Max +/-5.50 V2.2.2 Output impedance 50 Ohm typical2.2.3 Pulse amplitude ranges (full scale, unterminated) +/-5.50 V2.2.4 Pulse amplitude resolution 0.03% (12B FS)2.2.5 Pulse amplitude accuracy2.2.5.1 VOH 0.3% of range

+/-3 mV2.2.5.2 VOL 0.3% of range

+/-4 mV2.2.6 DC offset range (full scale) +5.5 V/-2.75 V2.2.7 Output current (short circuit) +110 mA,-220 mA

2.3 Differential ECL control signal2.3.1 Output termination 330 Ohms to -5 V

with 47 Ohms in series

3.0 AC SPECIFICATIONS

3.1 Pulse out - Pogo pin3.1.1 Rise/fall time (10% to 90% - 20 V swing)3.1.1.1 Ro = 95 Ohms, fast slew mode <35 ns3.1.1.2 Ro = 95 Ohms, slow slew mode <85 ns3.1.2 Overshoot3.1.2.1 Fast slew mode <5% Typical3.1.2.2 Slow slew mode <1% Typical3.1.3 Settling time - 20 V to 1%3.1.3.1 Fast slew mode <100 ns3.1.3.2 Slow slew mode <250 ns

3.2 Pulse out - RF path3.2.1 Rise/fall time (10% to 90% - 10 V swing) <20 ns3.2.3 Overshoot <5% Typical3.2.4 Settling time-10 V swing to 1% <50 ns

4.0 TIMING SPECIFICATIONS

4.1 Delay/width ranges (full scale)4.1.1 100 ns4.1.2 400 ns4.1.3 1.6 us4.1.4 6.4 us4.1.5 25 us4.1.6 100 us4.1.7 400 us


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4.1.8 1.6 ms4.1.9 4 ms

4.2 Delay/width insertion delay in bypass mode from trigger 20 ns Nominal

4.3 Delay/width resolution 0.03% (12B FS)

4.4 Delay/width accuracy (ranges 100 ns-1.6 ms) +/-0.5% FS+/-2 ns

4 ms range +/-1.0% FS

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Specs 31 Quad Opamp Channel Card

Notes:

Note 1 Instrument specifications are valid at the top of the DIB.

Quad Opamp Channel Card Features1. Quad Opamp Channel Card Loops

1.1 Test Head HardwareThis channel card requires a single slot, and may be operated inAdvanced Linear, PATH and Advanced Mixed Signal test heads in any ofthe linear slots.

1.2 ExpandabilityFour loops allow the testing of up to four opamps in parallel.Up to four quad opamp channel cards can be employed in parallelper test head for a total of 16 opamps to be tested in parallel.

2. Quad Opamp Channel Card Basic Functions

2.1 Modes- Continuity

Employs fixed low value, constant current, variable voltage sourcesto be connected to DUT inputs and output. Subsequent compliancevoltage readings are used to detect device pin continuity.

- InternalThe DUT is placed in a closed loop fixed gain configurationwith programmable frequency compensation to allow theonboard measurement of input Vos and Output voltage. No loopcomponents external to the quad opamp channel card are requiredin this mode.

- ExternalThe user employs feedback divider resistors external to the quadopamp channel card, and close to the DUT, to place the DUT in aclosed loop fixed gain configuration, with programmablefrequency compensation, to allow the onboard measurement ofinput Vos and Output voltage. This mode accommodates devices thatwould otherwise be unstable due to the lead length between the DUTinputs and the feedback divider. Compensation is programmed asin the Internal mode and Vos measurements are performed in thesame manner as with the Internal Mode. Open Loop and OscillationAlarms are detected as in the Internal Mode, but Continuity Modecan only be employed on those DUT pins that are directly connectedto the Quad Opamp Channel Card. Typically only the DUT output



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would be directly connected in this mode.

2.2 Connectivity2.2.1 Matrix, THADS, User Clock, Grounds

- Two internal channel card (“cc”) busses- two matrix pins per card, each to one cc bus- two THADS connections per card, each to one cc bus- one user clock per card, connects to both cc busses

2.2.2 Pogo Block I/O2.2.2.1 Channel Card Input Signals (DUT Output)

- DUT Output voltage- 10 Megohm input impedance in LOW voltage mode- 120K ohm input impedance in HIGH voltage mode

2.2.2.2 Channel Card Output Signals- Loop output signal for use with external feedback networks

2.2.2.3 DUT Input Signals, Internal Mode- INP, 50 Ohms impedance

typically connected to DUT non-inverting input- INM, 50 Ohms impedance

typically connected to DUT inverting input2.2.3 Trigger Bus

- Accepts trigger bus 1-6 to drive commutation selector2.2.4 Measure Bus

- Driven differentially, measurable selectable eitherstatically or via commutation selector

_ A Programmable Gain Instrumentation Amplifier (PGIA) isemployed to provide 11 binary gain ranges from 1 to 1024,between the channel card measurement points and theMeasure Bus.

2.2.5 Calibration Bus- Used to transfer system reference to on-board

calibration standard

2.3 Force and Measure Functions2.3.1 DUT Output Drive

- (+/-) 80 V full scale in the HIGH voltage mode- (+/-) 20 V full scale in the LOW voltage mode

2.3.2 DUT Offset Null Mode- (+/-) 20.25 mV full scale, referred to DUT input

For use in delta-Vos tests, to maximize resolution- equivalent voltage resolution 13 bits

2.3.3 DUT Input Drive- +/-10 V full scale with input 'rsource:off' and

input 'protection:off'- voltage resolution 14 bits

2.3.4 Continuity Mode- (+/-) 9.5 V full scale force voltage compliance- 220 uA source/sink current- 10 V to 9.76 mv full scale measurement on DUT input and

output pins, in eleven binary ranges- voltage forcing resolution at DUT inputs, 8 bits- voltage forcing resolution at DUT outputs, 14 bits

2.3.5 DUT Output Loads- Loads connect to the DUT output and are driven

from the internal channel card bus by ccgnd, dc matrixor THADS



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- selectable 10K, 2K, 600 Ohm loads- 12 Ohm solid state switch- shorting relay

2.3.5.1 Low Voltage Mode- 10 Mohm to ground is always present, in parallel

with any selected loads.2.3.5.2 High Voltage Mode

- 120 Kohm to ground is always present, in parallelwith any selected loads.

2.3.7 VOS Measurement Internal Mode- X100 Closed Loop Gain: 99.0 mV to 97.0 uV full scale

in eleven binary ranges- X1000 Closed Loop Gain: 9.9 mV to 9.7 uV full scale

in eleven binary ranges- X10000 Closed Loop Gain: 990.0 uV to 970.0 nV full scale

in eleven binary ranges2.3.8 VOS Measurement Rolloff Internal Mode

- X100 Closed Loop Gain: 0.10 ms time constant- X1000 Closed Loop Gain: 0.55 ms time constant- X10000 Closed Loop Gain: 5.05 ms time constant

2.3.9 VOS Measurement External Mode- Closed Loop Gain is determined by a user specified external

loop feedback divider- Programmable Gain for Measure Bus

1 to 1024 in eleven binary ranges2.3.10 DUT Output Voltage Measurement

- 20 V to 19.5 mV full scale in low voltage modeemploying 11 binary ranges

- 80 V to 78 mV full scale in high voltage modeemploying 11 binary ranges

2.4 Alarms2.4.1 Oscillation Detector

- 20 mV to 3.32 V oscillation threshold voltage setting- threshold voltage resolution 8 bits- AC coupled input, “zero” located at 1 kHz

Oscillation amplitude detection threshold must bederated at input frequencies below 10 kHz

2.4.2 Open Loop Detector- Open loop alarm employs a fixed window threshold

to detect “railed” loop integrator.

2.5 Frequency Compensation- Loop Frequency response is programmable to allow a wide

variety of opamps to be stabilized.- Nominal DUT GBW Ranges: 1 MHz, 5 MHz, 25 MHz, 125 MHz- Nominal Zfreq Ranges: 10 Hz, 100 Hz, 1 kHz, 10 kHz

2.6 Commutation Selector- 256 possible timeslots- connects one of 8 measurables to measure bus- modulo-n operation (programmable repeats)- driven by one of trigger lines 1 - 6



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QUAD OP AMP CHANNEL CARD SPECIFICATIONS

3. Quad Opamp Channel Card Electrical Specifications(within operating environment)

3.1 Electrical Specifications, Force Voltage/Current3.1.1 Continuity DACs

3.1.2.1 Sink/Source Current 220.0 uA Nominal3.1.2.2 Input Compliance Setting +/-240 mV3.1.2.3 Output Compliance Setting +/-95 mV

3.1.2 Output Drive3.1.1.1 LOW Voltage Mode, +/-20.0V +/-0.30%3.1.1.2 HIGH Voltage Mode, +/-80.0V +/-0.35%

3.1.3 Offset Null +/-116 uv3.1.4 DUT Input Drive +/-0.3%3.1.5 External Loop Compensation Output

3.1.5.1 Range +/-10.0 V Nominal3.1.5.2 Output Impedance 100.0 Ohms Nominal3.1.5.3 Minimum External Load to Ground 900.0 Ohms Nominal

3.2 Electrical Specifications, Measure Voltage3.2.1 Measure VOS Internal or External Mode3.2.1.1 Closed Loop Gain = 100 +/-0.25% of setting

3.2.1.2 Closed Loop Gain = 1000 +/-0.25% of setting3.2.1.3 Closed Loop Gain = 10000 +/-0.50% of setting

3.2.2 Measure DUT Output Voltage Internal or External Mode3.2.2.1 Low Voltage Mode (20 V) +/-0.5% rdg

+/-2.8 mV tagn3.2.2.1 High Voltage Mode (80 V) +/-0.5% rdg

+/-11.2 mV tag3.2.3 Measure Continuity Compliance Voltage3.2.3.1 DUT Inputs +/-0.5% rdg Nominal

+/-2.8 mV tag Nominal3.2.3.2 DUT Output +/-0.5% rdg Nominal

+/-2.8 mV tag Nominal

3.3 Electrical Specifications, Other3.3.1 Loads:

3.3.1.1 10K Load Accuracy +/-0.3%3.3.1.2 2K Load Accuracy +/-0.3%3.3.1.3 600 Ohm Load Accuracy +/-0.3%3.3.1.4 Solid State Relay Resistance <24.0 Ohms3.3.1.5 Shorting Relay Resistance <1.0 Ohms

3.3.2 Frequency Compensation3.3.2.1 GBW Range, 1 MHz +/-20% of setting3.3.2.2 GBW Range, 5 MHz +/-13% of setting3.3.2.3 GBW Range, 25 MHz +/-12% of setting3.3.2.4 GBW Range, 125 MHz +/-12% of setting3.3.2.5 Zfreq Range, 10 Hz +/-2.3% of setting3.3.2.6 Zfreq Range, 100 Hz +/-2.3% of setting3.3.2.7 Zfreq Range, 1 kHz +/-3.3% of setting3.3.2.8 Zfreq Range, 10 kHz +/-18% of setting

3.3.3 Oscillation Detector Threshold 0.02 to 3.32 V Nominal(Input Signal > 10 kHz)



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4. Absolute Maximum Ratings(exceeding these ratings may damage the board)

4.1 Input Pin Ratings4.1.1 Maximum Voltage +/-15.0 V4.1.2 Maximum Current +/-75.0 mA

4.2 Output Pin Ratings4.2.1 Maximum Voltage (Low Voltage Mode) +/-75.0 V4.2.2 Maximum Voltage (High Voltage Mode) +/-100.0 V4.2.3 Maximum Voltage (Continuity Mode) +/-90.0 V4.2.4 Maximum Current 10K Load +/-3.0 mA4.2.5 Maximum Current 2K Load +/-12.0 mA4.2.6 Maximum Current 600 Ohm Load +/-30.0 mA4.2.7 Maximum Current Solid State Relay +/-200.0 mA4.2.8 Maximum Current Shorting Relay +/-200.0 mA

4.3 External Feedback Pin Ratings4.3.1 Maximum Voltage +/-15.5 V4.3.2 Maximum Current +/-25.0 mA

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Specs 32 Serial Bus Channel Card

I. SERIAL BUS CHANNEL CARD SPECIFICATIONS

1. CHANNEL COUNT FOR EACH BOARDThere can be a maximum of two boards in each test head.Clock Channel 1Drive/Receive 2Event/Trigger Bus 8Multiple Level 2

Note: One of the multiple level channels uses two of theevent/trigger bus channels as inputs and the othermultiple level channel uses three other event/triggerbus inputs.

2. VECTOR RATE

Range Vector Rate----- -----------X1 39.1 kHz to 1.67 MHzX2 19.5 kHz to 833 kHzX4 9.8 kHz to 417 kHzX8 4.9 kHz to 208 kHzX16 2.4 kHz to 104 kHz

3. DRIVER SPECIFICATIONS

3.1 VIH/VIL DC Voltage Levels (No load)3.1.1 Voltage levels -4.0 V to +10.0 V3.1.2 Voltage resolution 1.5 mV nominal3.1.3 Voltage Accuracy +/-(0.25% + 15 mV)

CONDITION: VIH must be 0.5 V greater than VIL

3.2 VIH/VIL DC Output CurrentExcluding Multiple Level Channels3.2.1 DC Output Current Hi Source 8.0 mA < I < 13.8 mA3.2.2 DC Output Current Low Sink 8.0 mA < I < 13.8 mA3.2.3 Current Alarm Current > 8.0 mA for

Duration > 2.4 us nominalMultiple Level Channels3.2.4 DC Output Current HI Source 10 mA < I < 60 mA nominal3.2.5 DC Output Current Low Sink 10 mA < I < 60 mA nominal



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3.3 Output Impedance3.3.1 Resistance, DC 100 ohms, +/-5 ohms, nominal3.3.2 Impedance 100 ohms, nominal

3.4 Rise/Fall TimeExcluding Multiple Level Channels3.4.1 3 V swing (20%-80%) 25 ns +/- 10 ns3.4.2 5 V swing (20%-80%) 25 ns +/- 10 ns3.4.3 9 V swing (20%-80%) 28 ns +/- 12 nsMultiple Level Channels3.4.4 3 V swing (20%-80%) 43 ns +/- 10 ns3.4.5 5 V swing (20%-80%) 45 ns +/- 15 ns3.4.6 9 V swing (20%-80%) 62 ns +/- 25 nsThe rise and fall measurements for all channelsare verified with the internal measurement bus. 130 pF typical

4. COMPARATOR SPECIFICATIONS

4.1 VOH/VOL DC Voltage Levels4.1.1 Voltage levels -4.0 V to +10.0 V4.1.2 Voltage resolution 1.5 mV nominal4.1.3 Voltage Accuracy +/-(0.25% + 30 mV)

4.2 Input Impedance4.2.1 Leakage +/-120 uA nominal

4.3 Lumped capacitance on the path 100 pF typical

4.4 Receiver Hysteresis 60 mV nominal

5. TIMING GENERATION

5.1 Period Timing

Range Period Delay Resolution----- ------------ ----------X1 600 ns to 25.6 us 100 nsX2 1.2 us to 51.2 us 200 nsX4 2.4 us to 102 us 400 nsX8 4.8 us to 204 us 800 nsX16 9.6 us to 409 us 1.6 us

5.2 Clock Channel Leading Edge Placement (clk_ld_edge)

Range Delay Value Resolution----- ----------- ----------X1 0ns to clk_tr_edge minus 100 ns 100 nsX2 0ns to clk_tr_edge minus 200 ns 200 nsX4 0ns to clk_tr_edge minus 400 ns 400 nsX8 0ns to clk_tr_edge minus 800 ns 800 nsX16 0ns to clk_tr_edge minus 1.6 us 1.6 us



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5.3 Clock Channel Trailing Edge Placement (clk_tr_edge)

Range Delay Value Resolution----- ------------ ----------X1 clk_ld_edge plus 100 ns to Period minus 100 ns 100 nsX1 clk_ld_edge plus 200 ns to Period minus 100 ns 200 nsX1 clk_ld_edge plus 400 ns to Period minus 100 ns 400 nsX1 clk_ld_edge plus 800 ns to Period minus 100 ns 800 nsX1 clk_ld_edge plus 1.6 us to Period minus 100 ns 1.6 us

The clock leading and trailing edge placement is programmedfrom the beginning of the period boundary.

5.4 Data DelayThe data edge for the two drive/receive channels may beprogrammed at the period boundary or to this data delay.

Range Delay Value Resolution----- ------------ ----------X1 0 ns to Period minus 100 ns 100 nsX2 0 ns to Period minus 200 ns 200 nsX4 0 ns to Period minus 400 ns 400 nsX8 0 ns to Period minus 800 ns 800 nsX16 0 ns to Period minus 1.6 us 1.6 us

5.5 Receive Timing Strobe TypeThe receive strobe for both drive/receive channels together

can be connected to either the clock channel leading ortrailing edge.

5.6 Clock Channel Time-out Delay

Range Time-out Delay Resolution----- -------------- ----------X1 200 ns to 51.2 us 200 nsX2 400 ns to 102 us 400 nsX4 800 ns to 204 us 800 nsX8 1.6 us to 409 us 1.6 usX16 3.2 us to 25.6 us 3.2 us

6. PATTERN DATA

6.1 Clock Channel Edge Pattern Programming (leading and trailing)RepeatHIZLowHigh

The clock leading and trailing edges have independent programming.

6.2 Drive/Receive Channel Drive Pattern ProgrammingRepeatHIZLowHigh



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6.3 Drive/Receive Channel Receive Pattern ProgrammingMaskExpect ValidExpect LowExpect High

6.4 Pattern Data Memory 64 k Locations

6.5 Channel Preset ConditionsThe initial state for the clock and drive/receive channelsmay be set to the following conditions.

drive lowdrive highoff

7. SEQUENCE CONTROL

7.1 Microcode Memory Depth 64 k Locations

7.2 Pattern Execution Control7.2.1 Opcodes

<blank> Continue to next vector.HALT Stop pattern execution unconditionally.

7.3 Debug Features7.3.1 History RAM 64 k LocationsThe pass/fail condition for each vector of the two I/O

channels is saved in a RAM.

7.4 System Pipelines 1 pipelineThere is one pipeline in the formatter. The pattern

may be restarted after a HLT opcode without pipelinepriming.

7.5 Pattern Start SourceComputer CommandEvent Bus Line 1Trigger Bus Line 1 through 6

8. EVENT CHANNELS8.1 Event Channel Data Source

The event channels may receive waveform data from one of thefollowing sources.

Static Data RegisterTrigger Bus Lines 1 through 6Event Bus with the following restrictions:

Event channel 4 from Event Bus 1Event channel 5 from Event Bus 2Event channel 6 from Event Bus 3Event channel 7 from Event Bus 4Event channel 8 from Event Bus 5Event channel 9 from Event Bus 6Event channel 10 from Event Bus 7Event channel 11 from Event Bus 8



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9. MULTIPLE LEVEL CHANNELS9.1 Data Inputs

Multiple Level Channel 12Event channels 7, 8, and 9

Multiple Level Channel 13Event channels 10 and 11

10. EDGE PLACEMENT ACCURACY10.1 Clock and Drive/Receive Channels 30 ns

This is the time displacement between two channelsprogrammed to the same point in time.

10.2 Event/Trigger bus Channels 50 nsThis is the time displacement between two channelsconnected to the same trigger bus input.

Edge accuracy applies at the end of two feet of 100 ohmcoax cable connected to the configuration board.

11. DC MATRIX FRONT END

11.1 DC Path Series Resistance From Kelvin Point <=5.0 ohms

12. RELAYSEach channel has three relays. There is a DUT relay to connect thechannel to test device. A Functional relay to connect the channel driverto the test device through the DUT relay and a measurement relay toconnect the test device through the DUT relay to the system matrix.

13. TIME MEASUREMENT INTERFACE TO SERIAL BUS CHANNELS

13.1 Time Measurement (TMS) access on the clock channel13.1.1 Start and/or Stop from

clock channel comparator (vol, voh)or

drive/receive channels comparator (vol, voh)or

from within the driver of the event/trigger bus channels

13.1.2 Enable channel access fromclock channel comparator (vol, voh)

ordrive/receive channels comparator (vol, voh)

orfrom within the driver of the event/trigger bus channels

13.2 Time Measurement Interface Accuracy13.2.1 Relative to Clock or Drive/Receive channel 20 ns

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Specs 33 Stored Data Performance Bits

Notes:

Note 3 Checker Circuitry for all SDB Input/Output Tests conducted in STATIONMIconsists of a DIODE connected in series with the SYSTEM MATRIX.

Note 4 The Maximum current sink allowed per station is 500 mA.

0.1 Stored Data(Performance) Bit Features

0.1.1 48 Stored Data Bits per Station Non-Multiplexed

Readback Mode is Low True Logic

0.1.2 Two Readback Modes:Latched Readback from registers (data programmed)

or True Readback from Test Head Hardware

0.1.3 Overload Alarms in both readback modes which can be enabled/disabledvia software.

0.1.4 INPUT/OUTPUT diode clamp protected between +12 V and Ground


Stored Data Performance Bits

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1. STORED DATA PERFORMANCE BIT SPECIFICATIONS

1.1 OUTPUT SPECIFICATIONS1.1.1 HIGH Output: (Vout-Hi, bit set to 0)

Vout > 4.4 @ Isource = 0 uAVout > 4.0 @ Isource = 50 uAVout > 2.5 @ Isource = 500 uA

1.1.2 LOW Output: (Vout-Lo, bit set to 1) (see Note 4)VoL < 0.4 @ Isink = 16 mAVoL < 0.7 @ Isink = 60 mAVoL < 1.4 @ Isink = 120 mA

1.1.3 Maximum Voltage out (SDB OFF) is Less Than or Equal to 5 V.

1.2 INPUT SPECIFICATIONS1.2.1 Maximum Input Voltage = +12.6 V1.2.2 Minimum Input Voltage = -0.6 V1.2.3 Logic State Voltage

0 < 1.0 V1 > 1.3 V

1.2.4 SDB Input CurrentInput Voltage Input Current

0.8 V 2 mA max, 1.6 mA typical2.0 V 1 mA max, 600 uA typical

1.3 ALARM THRESHOLD SPECIFICATIONS1.3.1 HIGH Output (SDB OFF, Bit set to 0)

1.2 mA minimum Isource required to trip overload alarm circuit.1.3.2 LOW Output (SDB ON, Bit set to 1)

Isink range for tripping overload alarm circuit.Isink: minimum typical guaranteed

200 mA 250 mA 300 mA

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Specs 34 Superclock

NOTE

The instrument has not been characterized or specified for theextended isoblock option.

I. SUPERCLOCK INSTRUMENTATION SPECIFICATIONS

1. FREQUENCY

Note: Frequency synthesizer connected to system 10 MHz reference.

1.1 Range 50 MHz to 400 MHzNote: Frequency is programmable down to 10 MHz, but

specifications are guaranteed only to 50 MHz.

1.2 Resolution1.2.1 50 MHz <= Frequency <= 250 MHz 1 Hz, nominal1.2.2 250 MHz < Frequency <= 400 MHz 2 Hz, nominal

1.3 Accuracy 1 ppm + 1 ppm/year

2. DRIVER SPECIFICATIONSDrive OnlyDifferential Outputs

Note:All specifications for Superclock are for single-ended and non-terminated (at the DUT) cases. Although termination does not improvethe quality of the signal significantly, it may be desired, in whichcase the following considerations are suggested. Termination shouldbe to Vih NOT to ground, as this may damage the hardware. Theterminator must be able to be switched out if edge skew calibrationto HSD is desired. The maximum voltage swing will be halved.Calibration does not support termination.

2.1 VIH/VIL DC Voltage Levels (No load)2.1.1 Voltage levels -2.0 V to +5.0 V2.1.2 Voltage resolution 1.22 mV nominal


Superclock

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2.1.3 Maximum voltage swing 5 V p-p to 100 MHz3.3 V p-p to 400 MHz

2.1.4 Minimum voltage swing 0.5 V p-p2.1.5 Voltage accuracy vs. programmed value2.1.5.1 Vih < 225 mV + 15% of swing

> -125 mV - 10% of swing2.1.5.1 Vil < 125 mV + 10% of swing

> -225 mV - 15% of swingVoltages are calibrated at the user specified voltages andfrequency using the midpoints of the high and low pulses.

2.2 Output Impedance 50 ohms, nominal

2.3 Rise/Fall Time20%-80% voltage p-p, all voltage levels.

2.3.1 Standard isoblocks <500 ps2.3.2 Extended isoblock option <600 ps

2.4 Overshoot/Undershoot2.4.1 Standard isoblocks <20 %2.4.2 Extended isoblock option <23 %

3. TIMING

3.1 Edge Accuracy3.1.1 Alignment to HSD3.1.1.1 D1 to HSD +/-600 ps

Note: Typical settling times required after frequency change(to within 50 ps of final position)

Original Frequency | New Frequency | Settling Time-------------------- |------------------- |-----------------200-400 MHz | 100 MHz | 250 ms200-400 MHz | 50 MHz | 550 ms100 MHz | 50 MHz | 350 ms100 MHz | 200-400 MHz | 20 us50 MHz | 100-400 MHz | 20 us

3.1.1.2 Timing resolution +/-20 ps nominal3.1.2 Duty cycle3.1.2.1 D1 to D2 Accuracy +/-200 ps

At 50% duty cycle3.1.2.2 Programing range 40% to 60%, guaranteed accuracy

5% to 95%, reduced accuracy0% / 100% to force low/high

3.1.3 Edge Jitter3.1.3.1 RMS 10 ps typical

3.2 Pattern Resynchronization Time 2-3 ms typicalWhen the Superclock must be aligned to the HSD, resynchronizationvectors must be appended to the beginning of the user pattern.Resynchronization will generally occur at the beginning of everypattern start.


Superclock

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4.0 SCL xtalk into adjacent HSD channels <128 mV p-p, nominalSuperclock programmed to largest voltage swing

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Specs 35 Synchronized Power Subsystem Base

Notes:

Note 1 Measurement resolution is determined by the system resource usedfor analog-to-digital conversion of the measurement bus signal.The standard system VM is the default converter used to capturea measurement. Its specifications can be found in the standardDC subsystem ESSD. In general, measurement accuracy is limitedby gain and offset errors. Meter resolution is not a significantportion of the measurement uncertainty.

Note 2 Depending on system type, the backplane connects to eitherAABUSII or M601 analog accessory bus, for measure bus ormod/wave/delta connections.

Note 3 Applies only to system types that include AABUSII.

Note 4 Applies only to system types that include M601 and its analogaccessory bus.

Note 5 Buffer gains convert AABUSII Wave bus full scale of 4 V tobackplane mod bus full scale of 10 V.



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0. SPS base features

0.1 Card cage0.1.1 General purpose slots 200.1.2 Dedicated interface slots 20.1.3 Backplanes per system 40.1.4 Card connectors 3 96-pin Inverse DIN0.1.5 DC power available (nominal, as a design guideline only)0.1.5.1 Voltage Total Available Per Slot0.1.5.2 +5 V 20 A 3 A0.1.5.3 -5.2 V 10 A 1 A0.1.5.4 -2 V 1.5 A 0.2 A0.1.5.5 +12 V 8 A 1 A0.1.5.6 +15 V 4 A 0.5 A0.1.5.7 -15 V 4 A 0.5 A

0.2 System Interfaces0.2.1 Low Speed TERABUS data interface0.2.1.5 Maximum address space per board 64 words0.2.2 M601 Accessory Bus Interface0.2.3 Reference Card direct connection to AD4120.2.4 Global Trigger Bus interface0.2.5 Analog Accessory Bus Interface (internal only)0.2.6 Shutdown interface

0.3 Local Trigger Bus0.3.1 Trigger Bus lines per backplane/card cage 80.3.2 Local Timers0.3.2.1 Per backplane 40.3.2.2 Output select 1 to 8 demux0.3.2.3 Input select 8 to 1 mux0.3.2.4 Independent programmable delay and width intervals0.3.3 10 MHz Clock reference selectable: local or global0.3.3.1 10 MHz Clock can drive trigger bus clock line (note 3)0.3.4 CPU interface0.3.4.1 CPU Event Input to Trigger Bus0.3.4.1.1 Pulsed0.3.4.1.2 Latched0.3.4.2 CPU Event Readback from Trigger Bus0.3.4.2.1 Strobed0.3.4.2.2 Latched0.3.5 Global Trigger Bus interface: enable per line0.3.6 Local drive/receive interface0.3.6.1 Multiple simultaneous drivers allowed0.3.6.2 Multiple simultaneous receivers allowed

0.4 Local Measure Bus0.4.1 Buses per backplane 20.4.2 Bus Type: unbalanced differential0.4.3 Output to external bus select, 2 to 1 mux0.4.3.1 M601 Accessory Bus (note 4)0.4.3.2 AABUSII Measure Bus (note 3)0.4.4 Input from AABUSII Measure Bus, drive local bus (either) (note 3)

0.5 Local Modulation Bus0.5.1 Buses per backplane 2



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0.5.2 Bus Type: unbalanced differential0.5.3 Input from external bus select, 1 to 2 demux0.5.3.1 M601 Accessory Bus (Delta Bus) (note 4)0.5.3.2 AABUSII Wave Bus (note 3)

0.6 Local Analog Bus (not during calibration)0.6.1 Buses per backplane 40.6.2 Bus type: 2 wire, relay isolated, fully floating

0.7 Local Analog Bus (during calibration)0.7.1 Buses per backplane 20.7.2 Resistance Bus type 4 wire, relay isolated, fully floating0.7.2.1 Voltage Bus type 3 wire, relay isolated, ground

referenced0.7.3 Input/Output to AD412 Cal bus select:0.7.3.1 AD412 Calibration Bus: V high to Local Bus 1 (note 4)0.7.3.2 AD412 Calibration Bus: V low sense to Local Bus 4 (note 4)0.7.3.3 low force is tied to local ground0.7.3.4 AD412 Calibration bus: R high to Local Bus 2 (note 4)0.7.3.5 AD412 Calibration bus: R low to Local Bus 3 (note 4)0.7.4 Input/Output to AABUSII Cal bus select:0.7.4.1 AABUSII Calibration Bus 2 high F/S to Local Bus 1 (note 3)0.7.4.2 AABUSII Calibration Bus 2 low sense to Local Bus 4 (note 3)0.7.4.3 low force is tied to local ground0.7.4.4 AABUSII Calibration bus 1 high F/S to Local Bus 2 (note 3)0.7.4.5 AABUSII Calibration bus 1 low F/S to Local Bus 3 (note 3)



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I. SPS Base Specifications

1. Local Timers

1.1 Ranges and accuracy (delay or width)

range resolution accuracy (nominal) accuracy (nominal)delay width

1.1.1 13,107 us 200 ns 600 ns + clk accuracy 100 ns + clk accuracy1.1.2 26,214 us 400 ns 800 ns + clk accuracy 100 ns + clk accuracy1.1.3 52,428 us 800 ns 1.2 us + clk accuracy 100 ns + clk accuracy1.1.4 104,856 us 1.6 us 2.0 us + clk accuracy 100 ns + clk accuracy1.1.5 209,712 us 3.2 us 3.6 us + clk accuracy 100 ns + clk accuracy1.1.6 419,424 us 6.4 us 6.8 us + clk accuracy 100 ns + clk accuracy1.1.7 838,848 us 12.8 us 13.2 us + clk accuracy 100 ns + clk accuracy1.1.8 1,677,696 us 25.6 us 26.0 us + clk accuracy 100 ns + clk accuracy

1.2 Clock accuracy1.2.1 Clock accuracy using local clock +/-0.01%1.2.2 Clock accuracy using system master clock, see system ESSD

1.3 Jitter1.3.1 Width jitter 2 ns RMS maximum nominal1.3.2 Delay jitter (2 ns plus resolution) RMS max nominal

2. Local trigger bus2.1 CPU pulse width 315 ns (+/-55 ns) nominal, as

generated by SPS card cage2.2 Jitter 300 ps nominal maximum RMS2.3 Pulse width 40 ns minimum, i.e., pulses

less than this will not operatereliably.

3. Local measure buses

3.1 Backplane measure buses (1 and 2)3.1.1 Full scale +/-10.24 V nominal3.1.2 Signal type unbalanced differential3.1.3 Driver output Res <100 ohms nominal3.1.4 Receiver leakage <30 nA nominal3.1.5 PARD < 0.5 mV rms nominal

(when driven by SPS card cage)buffer inputs shorted with 100 ohmsto ground, measure bandwidth 0.1 Hz to1 MHz

3.1.6 Maximum allowable voltage +/-15 V maximum, either signal toground

3.1.7 Client leakage to bus 30 nA maximum

3.2 Buffer from backplane (either bus) to system AABUSII measure busor to system M601 measure bus (note 2)

3.2.1 Gain 1.0 +/-0.02% typical3.2.2 Offset +/-1 mV typical maximum3.2.3 Settling 1 us to 1% typical maximum



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3.2.4 Bandwidth 180 kHz for amplitude +/-1% typicalminimum

3.3 Buffer to backplane (either bus) from system AABUSII measure bus(note 3)

3.3.1 Gain 1 +/-0.02% typical3.3.2 Offset +/-1 mV typical maximum3.3.3 Settling 1 us to 1% typical maximum3.3.4 Bandwidth 180 kHz for amplitude +/-1% typical

minimum

4. Local modulation buses

4.1 Backplane modulation buses (1 and 2)4.1.1 Full scale +/-10.24 V nominal4.1.2 Signal type unbalanced differential4.1.3 Driver output Res <100 ohms nominal4.1.4 Receiver leakage <100 nA nominal4.1.5 PARD <1 mV rms nominal (when driven by SPS

card cage) gain set to 2.5, bufferinputs shorted with 100 ohms, measurebandwidth 0.1 Hz to 1 MHz

4.1.6 Max allowable voltage +/-15 V maximum, either signal toground

4.1.7 Client leakage to bus 30 nA maximum

4.2 Buffer to backplane (either bus) from system M601 delta bus(note 4)

4.2.1 Settling time 1 us to 1% nominal as driven bySPS card cage from system

4.2.2 Gain values and accuracy4.2.2.1 Gain Accuracy Offset4.2.2.2 1 +/-0.15% max +/-4 mV maximum4.2.2.3 2.5 +/-0.15% max +/-7 mV maximum

4.3 Buffer to backplane (either bus) from system AABUSII wave bus(note 3)


4.3.2 Gain values and accuracy4.3.2.1 Gain Accuracy Offset4.3.2.3 2.5 +/-0.15% max +/-7 mV maximum (note 5)

4.4 Buffer from backplane (either bus) to system AABUSII wave bus(note 3)


4.4.2 Gain values and accuracy4.4.2.1 Gain Accuracy Offset4.4.2.3 0.4 +/-0.15% max +/-4 mV maximum (note 5)



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5. Local Analog buses (as used for calibration)

5.1 Resistance high and low (force and sense)5.1.1 Maximum allowable voltage +/-100 V maximum, either

signal to ground5.1.2 Client leakage to bus 1 nA max

5.2 Voltage high (force and sense)5.2.1 Maximum allowable voltage +/-100 V maximum, either

signal to ground5.2.2 Client leakage to bus 30 nA max

5.3 Voltage low (sense, force is power return)5.3.1 Maximum allowable voltage +/-2 V maximum, either signal

to ground5.3.2 Client leakage to bus 30 nA max

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Specs 36 THADS24 Channel Card

Notes:

Note 1: Throughout this document THADS is an acronym for Test Head AnalogDistribution System, a coaxial connection network which is local tothe test head.

Note 2: THADS to pin path is from backplane connector on the channel cardto the end of the Iso-pin (Advanced Mixed-Signal or Advanced LinearTest Head) or the end of a 24 inch 50 Ohm coaxial cable(Production Analog Test Head).

Note 3: Pin to pin path is from one pin to another via the internal channel cardbus. The pin is at the end of the Iso-pin (Advanced Mixed-Signal orAdvanced Linear Test Head) or the end of a 24 inch 50 Ohmcoaxial cable (Production Analog Test Head).

Note 4: Relative path length error valid only after autocalibration.

Note 5: *typical* specifications are sample tested, NOT 100% tested and areNOT guaranteed.

Note 6: *nominal* specifications are generally calculated values and areNOT guaranteed.

Note 7: Specifications are based on measurements and calculationsfor the following paths:1) Advanced Mixed-Signal (AMS) or Advanced Linear (AL) Test Head -

From the backplane connector to the Iso-pins.2) Production Analog Test Head (PATH) -

From the backplane connector to the end of 24 inch 50 Ohmcoaxial cables connected to a PATH configuration board.

Refer to the system specification for contributions of the THADS itself.


THADS24 Channel Card

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I. THADS24 INSTRUMENTATION SPECIFICATIONS

0. THADS24 Features

0.1 24 output pins

0.2 Connections between any THADS24 pin and THADS 1 or 2

0.3 Connections between any THADS24 pin and local ground

0.4 Connections between any number of THADS24 pins

0.5 Connections between user clock signal and any THADS24 pin

1. THADS24 SPECIFICATIONS

1.1 DC SPECIFICATIONS1.1.1 Max DC resistance THADS to pin 2.1 ohms nominal (Note 2)1.1.2 Max DC resistance pin to pin 3.0 ohms nominal (Note 3)1.1.3 Max DC resistance pin to local ground 2.0 ohms nominal1.1.4 Max capacitance1.1.4.1 AMS or AL Test Head 150 pF typical (Note 7)1.1.4.2 PATH 125 pF typical (Note 7)

1.2 TIME ACCESS SPECIFICATIONS1.2.1 Relative Path Length Error +/-25 ns (Note 4)

1.3 AC SPECIFICATIONS1.3.1 Crosstalk1.3.1.1 Crosstalk to quiet channel, AMS or AL Test Head, maximum, (Note 7)1.3.1.1.1 at 1 kHz -103 dB typical1.3.1.1.2 at 10 kHz -82 dB typical1.3.1.1.3 at 100 kHz -64 dB typical1.3.1.1.4 at 1 MHz -35 dB typical1.3.1.1.5 at 10 MHz -8 dB typical1.3.1.2 Crosstalk to quiet channel, PATH, maximum, (Note 7)1.3.1.2.1 at 1 kHz -103 dB typical1.3.1.2.2 at 10 kHz -84 dB typical1.3.1.2.3 at 100 kHz -65 dB typical1.3.1.2.4 at 1 MHz -40 dB typical1.3.1.2.5 at 10 MHz -10 dB typical1.3.2 Insertion Loss1.3.2.1 Insertion Loss, AMS or AL Test Head (Note 7)1.3.2.1.1 1 dB 1.5 MHz typical1.3.2.1.2 2 dB 2 MHz typical1.3.2.1.3 3 dB 3 MHz typical1.3.2.1.4 10 dB 5 MHz typical1.3.2.2 Insertion Loss, PATH (Note 7)1.3.2.2.1 1 dB 6 MHz typical1.3.2.2.2 2 dB 7 MHz typical1.3.2.2.3 3 dB 9 MHz typical1.3.2.2.4 10 dB 12 MHz typical

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Specs 37 Universal Backplane V/I Source

Notes:

1 All measurement specifications apply with the system meter filter on.

2 All specifications for voltage accuracy apply at the point theKelvin connection is made. In cases where the Kelvin connectionis made on the channel card rather than at the Device Under Test(DUT), there will be an additional voltage error term which isproportional to the current flowing. The resistance is specifiedfor the path between the channel card internal Kelvin point andthe Iso-Pin(TM).

3 UB = Universal BackplaneFV = Forcing VoltageV/I = Voltage Forcing/Current ForcingVprog = Programmed Voltage of SourceVrange = Voltage Range of SourceVmeas = Measured VoltageIprog = Programmed Current Clamp of SourceImeas = Measured CurrentFS = Full ScaleTBD = To Be Determined

4 Modulation accuracy does not include errors due to modulation source.

5 Calibrated performance holds for 1 week or a temperature drift of 5degrees Celsius, whichever happens first.

6 Area of specified performance is defined by:*Range* = extent of calibration for forced or metered parameter*Maximum Output* = boundary condition for calibrated operation of

instrument*Maximum Allowable* = absolute maximum rating to which instrument can

be subjected; specifications are not applicable at this operatingpoint



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I. UNIVERSAL BACKPLANE V/I SOURCE INSTRUMENTATION SPECIFICATIONS, Note 3

0. UB V/I FEATURES

0.1 GENERAL0.1.1 Ability to force voltage or current with automatic crossover0.1.2 Full four quadrant operation (source or sink, positive or negative)0.1.3 Three ranges of slew/settling0.1.4 Force, Sense, and Guard outputs0.1.5 One PC board, plugs into UB backplane0.1.6 Sources can be paralleled for higher current capability, up to

backplane and wiring limits0.1.7 Source functions as a matrix source (Lines 1-5) or as a DUT source.

When used as a matrix source, a jumper set selects source outputto be connected to lines 1 through 5. When used as a DUT source,output is connected to a multiplexer tied to J3, and a cable isconnected between J3 and the bulkhead/test head

0.1.8 Software readback indicates which matrix or DUT source numberis configured.

0.1.9 Ground referenced operation only, with a low sense input (DGS) whichis tied to ground at the DUT

0.2 CONNECTIONS0.2.1 Voltmeter and ammeter connected to backplane measure buses0.2.2 Trigger bus connection for source gate (any 1 of 8 trigger lines)0.2.3 Wave bus connection for modulation (voltage only)

0.3 SAFETY/ALARMS0.3.1 Shutdown signal will gate source off0.3.2 Overvoltage protected, with overvoltage driving system shutdown and

causing an alarm0.3.3 Alarm for guard current0.3.4 Alarm for open loop0.3.5 Alarm for mode error (in constant I mode when constant V expected,

or in constant V mode when constant I expected)0.3.6 Thermal sensor to measure the heat sink temperature, or the ambient

temperature0.3.7 Alarm for thermal overload (heat sink too hot)

1. VOLTAGE FORCING, Note 2, 5

1.1 Range, Note 6 0 to +/-60 V

1.2 Ranges 0.5 V, 1 V, 2 V, 5 V, 10 V, 20 V, 50 V,100 V, 200 V Full Scale

1.3 Resolution 16 bits including sign

1.4 Accuracy, Calibrated1.4.1 Vrange = 0.5 V +/-1 mV1.4.2 Vrange = 1 V +/-1 mV1.4.3 Vrange = 2 V +/-1 mV1.4.4 Vrange = 5 V +-(0.05% of Vprog or 1 mV), whichever is greater1.4.5 Vrange = 10 V +-(0.05% of Vprog or 2.5 mV), whichever is greater1.4.6 Vrange = 20 V +-(0.05% of Vprog or 5 mV), whichever is greater



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1.4.7 Vrange = 50 V +-(0.05% of Vprog or 10 mV), whichever is greater1.4.8 Vrange = 100 V +-(0.1% of Vprog or 50 mV), whichever is greater1.4.9 Vrange = 200 V +-(0.1% of Vprog or 100 mV), whichever is greater

1.5 Maximum Output Current, Note 6 +/-200 mA

1.6 Maximum Allowable Voltage, Note 6 +/-65 V, nominal

2. VOLTAGE METERING, Note 2, 5

2.1 Range, Note 6 0 to +/-60 V


2.3 Resolution depends on system meter; referencesystem meter ESSD

2.4 Accuracy, Calibrated2.4.1 Vrange = 0.5 V +/-1 mV2.4.2 Vrange = 1 V +/-1 mV2.4.3 Vrange = 2 V +/-1 mV2.4.4 Vrange = 5 V +-(0.05% of Vmeas or 1 mV), whichever is greater2.4.5 Vrange = 10 V +-(0.05% of Vmeas or 2.5 mV), whichever is greater2.4.6 Vrange = 20 V +-(0.05% of Vmeas or 5 mV), whichever is greater2.4.7 Vrange = 50 V +-(0.05% of Vmeas or 10 mV), whichever is greater2.4.8 Vrange = 100 V +-(0.1% of Vmeas or 50 mV), whichever is greater2.4.9 Vrange = 200 V +-(0.1% of Vmeas or 100 mV), whichever is greater

2.5 Maximum Output Current, Note 6 +/-200 mA


3. CURRENT FORCING, Note 5

3.1 Range, Note 6 +/-200 mA

3.2 Ranges 20 uA, 200 uA, 2 mA, 20 mA, 200 mAFull Scale


3.4 Accuracy, Calibrated +-(0.1% of Iprog + 0.05% of FS +100 nA)



4. CURRENT METERING, Note 5

4.1 Range, Note 6 +/-200 mA



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4.2 Ranges 5 uA, 10 uA, 20 uA, 50 uA, 100 uA,200 uA, 500 uA, 1 mA, 2 mA, 5 mA,10 mA, 20 mA, 50 mA, 100 mA, 200 mAFull Scale


4.4 Accuracy, Calibrated +-(0.1% of Imeas + 0.05% of FS +100 nA)



5. MODULATION

5.1 Ranges 2 V, 20 V, 200 V

5.2 Resolution depends on modulation source; referencemod. source ESSD

5.3 Accuracy, Note 4 +/-(0.5% + 0.5% of FS), typical

6. STABILITY

6.1 Maximum Capacitive Load with Stability 100 uF, typical

7. PROTECTION

7.1 Overvoltage trip point +/-(72.4 V +/- 1.4 V), nominal

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Specs 38 Universal Backplane 100 V V/I Source

Notes:

1 All measurement specifications apply with the system meter filter on.

2 All specifications for voltage accuracy apply at the point theKelvin connection is made. In cases where the Kelvin connectionis made on the channel card rather than at the device under test(DUT), there will be an additional voltage error term which isproportional to the current flowing. The resistance is specifiedfor the path between the channel card internal Kelvin point andthe Iso-Pin(TM).

3 UB = Universal BackplaneFV = Forcing VoltageV/I = Voltage Forcing/Current ForcingVprog = Programmed Voltage of SourceVrange = Voltage Range of SourceVmeas = Measured VoltageIprog = Programmed Current Clamp of SourceImeas = Measured CurrentFS = Full ScaleTBD = To Be Determined

4 Modulation accuracy does not include errors due to modulation source.

5 Calibrated performance holds for 1 week or a temperature drift of5 degrees Celsius, whichever happens first.

6 Area of specified performance is defined by:*Range* = extent of calibration for forced or measured parameter*Maximum Output* = boundary condition for calibrated operation ofthe instrument*Maximum Allowable* = absolute maximum rating to which thisinstrument can be subjected; specifications are not applicable atthis operating point.

7 Exceeding the maximum capacitive load specification may causealarms and shutdown when transitioning from High Voltage toStandard Mode.



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I. UNIVERSAL BACKPLANE 100V VI SOURCE INSTRUMENTATION SPECIFICATIONS, Note 5

0. UB 100V VI FEATURES

0.1 GENERAL0.1.1 Ability to force voltage or current with automatic crossover0.1.2 Two modes allow higher voltage capability:

Standard Mode equivalent to UB 60 V V/I; High-Voltage Mode for upto 100 V compliance

0.1.3 Full four quadrant operation (source or sink, positive ornegative)

0.1.4 Three ranges of slew/settling0.1.5 Force, Sense, and Guard outputs0.1.6 One PC board, plugs into UB backplane0.1.7 Sources can be paralleled for higher current capability, up to

backplane and wiring limits.0.1.8 Source functions as a matrix source (Lines 1-5) or as a DUT source.

When used as a matrix source, a jumper set selects source outputto be connected to lines 1 through 5. When used as a DUT source,output is connected to a multiplexer tied to J3, and a cable isconnected between J3 and the bulkhead/test head

0.1.9 Ground referenced operation only, with a low sense input (DGS)which is tied to ground at the DUT

0.1.10 Software readback indicates which matrix or DUT source numberis configured.

0.2 CONNECTIONS0.2.1 Voltmeter and ammeter connected to backplane measure buses0.2.2 Trigger bus connection for source gate (any 1 of 8 trigger lines)0.2.3 Wave bus connection for modulation (voltage only)0.2.5 Relay to close force-sense connection for test purposes

0.3 SAFETY/ALARMS0.3.1 Shutdown signal will gate source off0.3.2 Overvoltage protected, with overvoltage driving system shutdown and

causing an alarm0.3.3 Alarm for guard current0.3.4 Alarm for open loop0.3.5 Alarm for mode error (in constant I mode when constant V expected,

or in constant V mode when constant I expected)0.3.6 Thermal sensor to measure the heat sink temperature, or the ambient

temperature0.3.7 Alarm for thermal overload (heat sink too hot)

1. VOLTAGE FORCING (Notes 2, 5)

1.1 Range (Note 6)1.1.1 Standard Mode -60 V to +60 V1.1.2 High-Voltage Mode -100 V to +100 V





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1.4 Accuracy, Calibrated1.4.1 Vrange = 0.5 V +/-1 mV1.4.2 Vrange = 1 V +/-1 mV1.4.3 Vrange = 2 V +/-1 mV1.4.4 Vrange = 5 V +-(0.05% of Vprog or 1 mV), whichever is greater1.4.5 Vrange = 10 V +-(0.05% of Vprog or 2.5 mV), whichever is greater1.4.6 Vrange = 20 V +-(0.05% of Vprog or 5 mV), whichever is greater1.4.7 Vrange = 50 V +-(0.05% of Vprog or 10 mV), whichever is greater1.4.8 Vrange = 100 V +-(0.1% of Vprog or 50 mV), whichever is greater1.4.9 Vrange = 200 V +-(0.1% of Vprog or 100 mV), whichever is greater

1.5 Maximum Output Current (Note 6) +/-200 mA

1.6 Maximum Allowable Voltage, nominal (Note 6)1.6.1 Standard Mode +/-65 V1.6.2 High Voltage Mode +/-105 V

2. VOLTAGE METERING Note 1,5

2.1 Range (Note 6)2.1.1 Standard Mode 0 to +/-60 V2.1.2 High Voltage Mode 0 to +/-100 V

2.2 Ranges 0.5V, 1V, 2V, 5V, 10V, 20V, 50V,100V, 200V Full Scale


2.4 Accuracy, Calibrated2.4.1 Vrange = 0.5 V +/-1 mV2.4.2 Vrange = 1 V +/-1 mV2.4.3 Vrange = 2 V +/-1 mV2.4.4 Vrange = 5 V +-(0.05% of Vmeas or 1 mV), whichever is greater2.4.5 Vrange = 10 V +-(0.05% of Vmeas or 2.5 mV), whichever is greater2.4.6 Vrange = 20 V +-(0.05% of Vmeas or 5 mV), whichever is greater2.4.7 Vrange = 50 V +-(0.05% of Vmeas or 10 mV), whichever is greater2.4.8 Vrange = 100 V +-(0.1% of Vmeas or 50 mV), whichever is greater2.4.9 Vrange = 200 V +-(0.1% of Vmeas or 100 mV), whichever is greater

3. CURRENT FORCING (Note 5)

3.1 Range (Note 6) +/-200 mA

3.2 Ranges 20 uA, 200 uA, 2 mA, 20 mA, 200 mAFull Scale


3.4 Accuracy, Calibrated +-(0.1% of Iprog + 0.05% of FS +100 nA)

3.5 Maximum Output Voltage, nominal (Note 6)3.5.1 Standard Mode +/-60 V, up to 200 mA



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3.5.2 High Voltage Mode +/-100 V, up to 200 mA

3.6 Maximum Allowable Voltage, nominal (Note 6)3.6.1 Standard Mode +/-65 V, up to 200 mA3.6.2 High Voltage Mode +/-105 V, up to 200 mA

4. CURRENT METERING (Note 1, 5)

4.1 Range (Note 6) +/-200 mA Full Scale

4.2 Range 5 uA, 10 uA, 20 uA, 50 uA, 100 uA,200 uA, 500 uA, 1 mA, 2 mA, 5 mA, 10mA,20 mA, 50 mA, 100 mA, 200 mA


4.4 Accuracy, Calibrated +-(0.1% of Imeas + 0.05% of FS +100 nA)

4.5 Maximum Output Voltage (Note 6)) +/-100 V

4.6 Maximum Allowable Voltage (Note 6) +/-105 V

5. MODULATION

5.1 Ranges 2 V, 20 V, 200 V

5.2 Resolution depends on modulation source; referencemod. source ESSD

5.3 Accuracy (Note 8) +/-(0.5% + 0.5% of FS), typical

6. STABILITY

6.1 Maximum Capacitive Load with Stability 100 uF, typical

6.2 Maximum Capacitive Load High-Voltage modes 100 uF, typical

7. PROTECTION

7.1 Overvoltage trip point7.1.1 Standard Mode +/-(71.8 V +/- 0.8 V) typical7.1.2 High-Voltage Mode +/-(114.6 V +/- 1.2 V) typical

7.2 Mode Change Delay7.2.1 Standard mode to High Voltage mode transition 1.5 ms7.3.2 High Voltage mode to Standard mode transition 25 ms

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Specs 39 VHF Arbitrary Waveform Generator

Notes:

1) All specifications apply at the DIB "blind mate" RF connector. TheVHFAWG may also interface to the DIB via the channel card Pogo pin path.Specifications may be degraded when using the Pogo pin path.

2) All specifications assume a 50 ohm load. The software leveling calibrationallows the user to specify any resistive load and will compensate the outputlevel to achieve the programmed level at the programmed load. Spectralpurity specifications may vary as the load varies from 50 ohms when filtershigher than 10 MHz are selected, include the 80 - 200 MHz frequency range.


4) Amplitude Accuracy = Absolute Accuracy @ 10 dBm + Step Attenuator Accuracy+ Fine Amplitude Accuracy + Mismatch Errors

The error terms listed above are specified for each Frequency Range. TheAbsolute Accuracy applies only when next highest frequency filter from thefrequency being sourced is selected. Also, the Absolute Accuracy appliesonly to the Frequency Domain 80 MHz Filter, not the Time Domain 80 MHz Filter.

5) When sourcing a frequency of less than 100 kHz, the user should useLEVEL:SINE mode of level calibration and specify LEVEL_FREQ = 100kHz.

6) All specifications including those that are Frequency Range specific assumethat the waveform is stored in memory normalized to 12 bits full scale.


8) TYPICAL specifications are sample tested, are NOT 100% tested and areNOT guaranteed.


10) F(hfc) = Highest Frequency Component being sourced.

11) Sine Wave Spurious Responses are specified relative to the full scalesine wave signal in dBc down to levels of -10 dBm. Below -10 dBm, thespurious level is specified as a fixed power in dBm.



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I VHFAWG SPECIFICATIONS

1 GENERAL SPECIFICATIONS (Apply to all Frequency Ranges)

1.1 Peak Output Voltage (AC + DC Baseline)1.1.1 Load = 50 ohms +/-2.0 V max.1.1.2 Load = Open Circuit +/-4.0 V max.

1.2 AC p-p Output Voltage1.2.1 Load = 50 ohms 4.0 V max.1.2.2 Load = Open Circuit 8.0 V max.

1.3 Output Current Compliance Limit +/-40 mA typical

1.4 Output Short Circuit1.4.1 AWG Mode to 80 MHz +/-80 mA. typical1.4.2 CW Mode 80 - 200 MHz +/-70 mA. typical

1.5 AC Waveform Amplitude Control1.5.1 Step Attenuators 1, 2, 4, 8, 16, 16 dB1.5.2 Fine Amplitude Resolution <0.01 dB

1.6 DC Offset without autocal +/-50 mV

1.7 DC Offset with autocal +/-5 mV

1.8 Offset Drift +/-800 uV/C nominal

1.9 Programmable DC Baseline1.9.1 Range +/-2.0 V1.9.2 Resolution (12 Bits)1.9.3 Accuracy:1.9.3.1 Uncalibrated (dccal:off) +/-(5% + 50) mV1.9.3.2 Calibrated (dccal:on) +/-(1% + 6) mV1.9.4 Linearity:1.9.4.1 Uncalibrated (dccal:off) +/-1%1.9.4.2 Calibrated (dccal:on) +/-0.5%1.9.5 Settling Time for 4.0 V Step <2 ms to 1% of

final value

1.10 Slew Rate (filter bypass) 2000 V/us typical


1.12 Sample Clock Settling time 15 ms max.

1.13 Maximum Sample Rate 200 MHz

1.14 Minimum Sample Rate 1.5625 MHz

1.15 Waveform Memory Depth 256k, (1 M Optional)

1.16 Maximum Level of Subroutines 8



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1.17 Waveform Segment Modulus1.17.1 F(s) = 1.5625 MHz - 50 MHz Modulo = 11.17.2 F(s) = 50 MHz - 100 MHz Modulo = 21.17.3 F(s) = 100 MHz - 200 MHz Modulo = 4

1.18 Waveform Controller1.18.1 Maximum number of waveform segments 40961.18.2 Minimum number of samples/segment1.18.2.1 2*S.R.L. + 4 (1:1 Mode)1.18.2.2 2*S.R.L. + 8 (2:1 Mode)1.18.2.3 2*S.R.L. + 12 (4:1 Mode)

(S.R.L. = Subroutine Level)

1.19 Event Lines (synchronized with waveform memory) 8 (Optional)1.19.1 Event Line Start Sample Resolution Modulo 4 (1,5,9...).1.19.2 Event Line Stop Sample Resolution Modulo 4 or = segment size.

2 FREQUENCY RANGE I DC - 1 MHz

2.0 Operating Conditions2.0.1 Minimum Sample Rate (F(s) = 4 * F(hfc)2.0.2 0.5 MHz Filter Min. F(s) 1.5 MHz + F(hfc)2.0.3 1.0 MHz Filter Min. F(s) 3.0 MHz + F(hfc)

2.1 Sine Wave Amplitude Accuracy2.1.1 Absolute Accuracy @ 10 dBm +/-0.25 dB2.1.2 Step Attenuator Relative Accuracy +/-((0.15 dB + 0.01 dB/dB

change) up to 0.5 dB max.)2.1.3 Fine Amplitude Accuracy +/-0.1 dB2.1.4 Output VSWR <1.2:1 typical

2.2 Sine Wave Harmonics (2nd & 3rd) (Note: Max. Sample Frequency = 50 MHz)2.2.1 Load = 50 - 600 ohms2.2.1.1 Level = 10 - 16 dBm -45 dBc2.2.1.2 Level = 0 - 10 dBm -55 dBc2.2.1.3 Level = -30 - 0 dBm -60 dBc2.2.2 Load > 600 ohms -60 dBc

2.3 Sine Wave Spurious Responses (BW = 100 Hz - 10 MHz)2.3.1 Level = -10 - 16 dBm -60 dBc2.3.2 Level = -30 -> -10 dBm -70 dBm

2.4 Noise (BW = 100 Hz - 30 MHz) <20 uVrms (30 kHz BW)

2.5 Step Response Characteristics2.5.1 0.5 MHz Filter2.5.1.1 Risetime <750 ns typical2.5.1.2 Overshoot/Undershoot <2% typical2.5.2 1.0 MHz Filter2.5.2.1 Risetime <400 ns typical2.5.2.2 Overshoot/Undershoot <2% typical



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3 FREQUENCY RANGE II DC - 10 MHz

3.0 Operating Conditions3.0.1 Minimum Sample Rate (F(s) = 4 * F(hfc)3.0.2 2.0 MHz Filter Min. F(s) = 6.0 MHz + F(hfc)3.0.3 4.0 MHz Filter Min. F(s) = 12.0 MHz + F(hfc)3.0.4 5.5 MHz Filter Min. F(s) = 11.0 MHz + F(hfc)3.0.5 6.0 MHz Filter Min. F(s) = 18.0 MHz + F(hfc)3.0.6 10.0 MHz Filter Min. F(s) = 30.0 MHz ++ F(hfc)

3.1 Sine Wave Amplitude Accuracy3.1.1 Absolute Accuracy @ 10 dBm +/-0.25 dB3.1.2 Step Attenuator Relative Accuracy +/-(0.15 dB + 0.01 dB/dB change

up to 0.5 dB max.)3.1.3 Fine Amplitude Accuracy +/-0.1 dB3.1.4 Output VSWR <1.2:1 typical

3.2 Sine Wave Harmonics (2nd & 3rd) (Note: Max. Sample Frequency = 50 MHz)3.2.1 Frequency = 1 - 4 MHz3.2.1.1 Load = 50 - 600 ohms3.2.1.1.1 Level = 10 - 16 dBm -45 dBc3.2.1.1.2 Level = 0 - 10 dBm -55 dBc3.2.1.1.3 Level = -30 - 0 dBm -60 dBc3.2.1.2 Load > 600 ohms3.2.1.2.1 Level = 10 - 16 dBm -50 dBc3.2.1.2.2 Level = -30 - 10 dBm -60 dBc3.2.2 Frequency = 4 - 10 MHz3.2.2.1 Level = 10 - 16 dBm -45 dBc3.2.2.2 Level = 0 - 10 dBm -50 dBc3.2.2.3 Level = -30 - 0 dBm -55 dBc



3.5 Step Response Characteristics3.5.1 2.0 MHz Filter3.5.1.1 Risetime <200 ns typical3.5.1.2 Overshoot/Undershoot <2% typical3.5.2 4.0 MHz Filter3.5.2.1 Risetime <100 ns typical3.5.2.2 Overshoot/Undershoot <2% typical3.5.3 5.5 MHz Filter3.5.3.1 Risetime <80 ns typical3.5.3.2 Overshoot/Undershoot <8% typical3.5.4 6.0 MHz Filter3.5.4.1 Risetime <70 ns typical3.5.4.2 Overshoot/Undershoot <2% typical3.5.5 10.0 MHz Filter3.5.5.1 Risetime <45 ns typical3.5.5.2 Overshoot/Undershoot <2% typical

3.6 Group Delay of 5.5 MHz Filter <20 ns to 4.4 MHz typical



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3.7 NTSC Video Waveform Specifications3.7.1 Differential Gain +/-0.5% max.3.7.2 Differential Phase +/-0.5 degrees max.

4 FREQUENCY RANGE III DC - 30 MHz

4.0 Operating Conditions4.0.1 Minimum Sample Rate (F(s) = 4 * F(hfc)4.0.2 15.0 MHz Filter Min. F(s) = 45.0 MHz + F(hfc)4.0.3 20.0 MHz Filter Min. F(s) = 60.0 MHz + F(hfc)4.0.4 30 MHz Filter Min. F(s) = 90.0 MHz + F(hfc)



4.2 Sine Wave Harmonics (2nd & 3rd) (Note: Max. Sample Frequency = 120 MHz)4.2.1 Level = 10 - 16 dBm -40 dBc4.2.2 Level = -30 - 10 dBm -45 dBc



4.5 Step Response Characteristics4.5.1 15.0 MHz Filter4.5.1.1 Risetime <32 ns typical4.5.1.2 Overshoot/Undershoot <2% typical4.5.2 20.0 MHz Filter4 5.2.1 Risetime <30 ns typical4.5.2.2 Overshoot/Undershoot <2% typical4.5.3 30 MHz Filter4.5.3.1 Risetime <22 ns typical4.5.3.2 Overshoot/Undershoot <2% typical

5 FREQUENCY RANGE IV DC - 80 MHz

5.0 Operating Conditions5.0.1 Minimum Sample Rate DC - 45 MHz 3 * (highest frequency

component being sourced)5.0.2 Minimum Sample Rate 45 - 80 MHz 2.5 * (highest frequency

component being sourced)5.0.3 45.0 MHz Filter Min. F(s) = 135.0 MHz + F(hfc)5.0.4 65.0 MHz Filter Min. F(s) = 130.0 MHz + F(hfc)5.0.5 80 MHz Filter (Time Domain) Min. F(s) = 160.0 MHz + F(hfc)5.0.6 80 MHz Filter (Freq Domain) Min. F(s) = 160.0 MHz + F(hfc)



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5.1 Sine Wave Amplitude Accuracy5.1.1 Absolute Accuracy @ 10 dBm5.1.1.1 AL & AMS Test Heads +/-0.25 dB5.1.1.2 PATH Test Head +/-0.35 dB5.1.2 Step Attenuator Relative Accuracy +/-((0.3 dB +0.05 dB/dB change)

up to 1.0 dB max.)5.1.3 Fine Amplitude Accuracy +/-0.1 dB5.1.4 Output VSWR <1.2:1 typical

5.2 Sine Wave Harmonics (2nd & 3rd)5.2.1 Level = -30 - 16 dBm -40 dBc



5.5 Step Response Characteristics5.5.1 45.0 MHz Filter5.5.1.1 Risetime <18 ns typical5.5.1.2 Overshoot/Undershoot <2% typical5.5.2 65.0 MHz Filter5.5.2.1 Risetime <9.5 ns typical5.5.2.2 Overshoot/Undershoot <8% typical5.5.3 80 MHz Time Domain Filter5.5.3.1 Risetime <8 ns typical5.5.3.2 Overshoot/Undershoot <8% typical5.5.3 80 MHz Frequency Domain Filter5.5.3.1 Risetime <8 ns typical5.5.3.2 Overshoot/Undershoot <15% typical5.5.3 NO Filter5.5.3.1 Risetime <4 ns typical5.5.3.2 Overshoot/Undershoot <12% typical

6 FREQUENCY RANGE V 80 MHz - 200 MHz

6.0 Operating Conditions This Frequency Range does not use theWaveform Memory, Waveform Controller,or the Waveform DAC. In this operatingmode, the VHFAWG's sample rate clock isbuffered to the VHFAWG's channel card.

6.1 Sine Wave Amplitude Accuracy6.1.1 Absolute Accuracy @ 10 dBm6.1.1.1 AL & AMS Test Heads +/-0.25 dB6.1.1.2 PATH Test Head +/-0.45 dB6.1.2 Step Attenuator Relative Accuracy +/-((0.25 dB + 0.03 dB/dB





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7 Event Line Timing

7.0 Operating Conditions7.0.1 Valid only for presence of Consumer Digital Channel Card (AD754).7.0.2 Measured with self-test checker using Time Measurement System.

7.1 VIFAWG Channel Card Event Line to Analog Output Delay7.1.1 5.5 MHz Filter 65 +/- 35 ns7.2.2 45 MHz Filter -18 +/- 20 ns7.3.3 65 MHz Filter -22 +/- 20 ns7.3.4 80 MHz Filter (time domain) -22 +/- 20 ns7.3.5 80 MHz Filter (freq. domain) -22 +/- 20 ns

7.2 Event/Event Skew 20 ns max.

7.3 Event Rise/Fall Times (see ESSD for Consumer Digital Channel Card)

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Specs 40 VHF Arbitrary Waveform Generator, 1 Meg

Notes:




4) Amplitude Accuracy = Absolute Accuracy @ 10 dBm + Step Attenuator Accuracy+ Fine Amplitude Accuracy + Mismatch Errors.

The error terms listed above are specified for each Frequency Range. TheAbsolute Accuracy applies only when next highest frequency filter from thefrequency being sourced is selected. Also, the Absolute Accuracy appliesonly to the Frequency Domain 80 MHz Filter, not the Time Domain 80 MHz Filter.

5) When sourcing a frequency of less than 100 kHz, the user should useLEVEL:SINE mode of level calibration and specify LEVEL_FREQ = 100kHz.






11) Sine Wave Spurious Responses are specified relative to the full scalesine wave signal in dBc down to levels of -10 dBm. Below -10 dBm, thespurious level is specified as a fixed power in dBm.



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12) This revision of the VHFAWG Specification applies to the following revisionof the hardware:

LA608A or later Mainframe AND AD906-04 Channel Card AND AD754 ChannelCard (for event lines only).



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I VHFAWG 1M SPECIFICATIONS


1.1 Peak Output Voltage (AC + DC Baseline)1.1.1 Load = 50 ohms +/-2.0 V max.1.1.2 Load = Open Circuit +/-4.0 V max.

1.2 AC p-p Output Voltage1.2.1 Load = 50 ohms 4.0 V max.1.2.2 Load = Open Circuit 8.0 V max.

1.3 Output Current Compliance Limit +/-40 mA typ.

1.4 Output Short Circuit1.4.1 AWG Mode to 80 MHz +/-80 mA typ.1.4.2 CW Mode 80 - 200 MHz +/-70 mA typ.

1.5 AC Waveform Amplitude Control1.5.1 Step Attenuators 1,2,4,8,16,16 dB1.5.2 Fine Amplitude Resolution <0.01 dB




1.9 Programmable DC Baseline1.9.1 Range +/-2.0 V1.9.2 Resolution (12 Bits)1.9.3 Accuracy:1.9.3.1 Uncalibrated(dccal:off) +/-(5% + 50) mV1.9.3.2 Calibrated(dccal:on) +/-(1% + 6) mV1.9.4 Linearity:1.9.4.1 Uncalibrated(dccal:off) +/-1%1.9.4.2 Calibrated(dccal:on) +/-0.5%1.9.5 Settling Time for 4.0 V Step <2 ms to 1% of

final value

1.10 Slew Rate (filter bypass) 2000 V/us typ.





1.15 Waveform Memory Depth 1 Meg. samples




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1.17 Waveform Segment Modulus1.17.1 F(s) = 1.5625 MHz - 50 MHz Modulo = 11.17.2 F(s) = 50 MHz - 100 MHz Modulo = 21.17.3 F(s) = 100 MHz - 200 MHz Modulo = 4

1.18 Waveform Controller1.18.1 Maximum number of waveform segments 20481.18.2 Minimum number of samples/segment1.18.2.1 2*S.R.L. + 4 (1:1 Mode)1.18.2.2 4*S.R.L. + 6 (2:1 Mode)1.18.2.3 8*S.R.L. + 12 (4:1 Mode)


1.19 Event Lines (synchronized with waveform memory) 81.19.1 Event Line Start Sample Resolution Modulo 4 (1,5,9...).1.19.2 Event Line Stop Sample Resolution Modulo 4 or = segment size


2.0 Operating Conditions2.0.1 Minimum Sample Rate (F(s) = 4 * F(hfc)2.0.2 0.5 MHz Filter Min. F(s) 1.5 MHz + F(hfc)2.0.3 1.0 MHz Filter Min. F(s) 3.0 MHz + F(hfc)


change) up to 0.5 dB max.)2.1.3 Fine Amplitude Relative Accuracy +/-0.1 dB2.1.4 Output VSWR <1.2:1 typical







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3.0 Operating Conditions3.0.1 Minimum Sample Rate (F(s) = 4 * F(hfc)3.0.2 2.0 MHz Filter Min. F(s) = 6.0 MHz + F(hfc)3.0.3 4.0 MHz Filter Min. F(s) = 12.0 MHz + F(hfc)3.0.4 5.5 MHz Filter Min. F(s) = 11.0 MHz + F(hfc)3.0.5 6.0 MHz Filter Min. F(s) = 18.0 MHz + F(hfc)3.0.6 10.0 MHz Filter Min. F(s) = 30.0 MHz ++ F(hfc)

3.1 Sine Wave Amplitude Accuracy3.1.1 Absolute Accuracy @ 10 dBm +/-0.25 dB3.1.2 Step Attenuator Relative Accuracy +/- (0.15 dB + 0.01 dB/dB

change up to 0.5 dB max.)3.1.3 Fine Amplitude Relative Accuracy +/-0.1 dB3.1.4 Output VSWR <1.2:1 typical




3.5 Step Response Characteristics3.5.1 2.0 MHz Filter3.5.1.1 Risetime <200 ns typical3.5.1.2 Overshoot/Undershoot <2% typical3.5.2 4.0 MHz Filter3.5.2.1 Risetime <100 ns typical3.5.2.2 Overshoot/Undershoot <2% typical3.5.3 5.5 MHz Filter3.5.3.1 Risetime <80 ns typical3.5.3.2 Overshoot/Undershoot <8% typical3.5.4 6.0 MHz Filter3.5.4.1 Risetime <70 ns typical3.5.4.2 Overshoot/Undershoot <2% typical3.5.5 10.0 MHz Filter3.5.5.1 Risetime <45 ns typical3.5.5.2 Overshoot/Undershoot <2% typical

3.6 Group Delay of 5.5 MHz Filter <20 ns to 4.4 MHz typ.



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4.0 Operating Conditions4.0.1 Minimum Sample Rate (F(s) = 4 * F(hfc)4.0.2 15.0 MHz Filter Min. F(s) = 45.0 MHz + F(hfc)4.0.3 20.0 MHz Filter Min. F(s) = 60.0 MHz + F(hfc)4.0.4 30 MHz Filter Min. F(s) = 90.0 MHz + F(hfc)






4.5 Step Response Characteristics4.5.1 15.0 MHz Filter4.5.1.1 Risetime <32 ns typical4.5.1.2 Overshoot/Undershoot <2% typical4.5.2 20.0 MHz Filter4 5.2.1 Risetime <30 ns typical4.5.2.2 Overshoot/Undershoot <2% typical4.5.3 30 MHz Filter4.5.3.1 Risetime <22 ns typical4.5.3.2 Overshoot/Undershoot <2% typical

5 FREQUENCY RANGE IV DC - 80 MHz

5.0 Operating Conditions5.0.1 Minimum Sample Rate DC - 45 MHz 3 * (highest frequency

component being sourced)5.0.2 Minimum Sample Rate 45 - 80 MHz 2.5 * (highest frequency

component being sourced)5.0.3 45.0 MHz Filter Min. F(s) = 135.0 MHz + F(hfc)5.0.4 65.0 MHz Filter Min. F(s) = 130.0 MHz + F(hfc)5.0.5 80 MHz Filter (Time Domain) Min. F(s) = 160.0 MHz + F(hfc)5.0.6 80 MHz Filter (Freq Domain) Min. F(s) = 160.0 MHz + F(hfc)



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5.1 Sine Wave Amplitude Accuracy5.1.1 Absolute Accuracy @ 10 dBm5.1.1.1 AL & AMS Test Heads +/-0.25 dB5.1.1.2 PATH Test Head +/-0.35 dB5.1.2 Step Attenuator Relative Accuracy +/-((0.3 dB +0.05 dB/dB change)

up to 1.0 dB max.)5.1.3 Fine Amplitude Relative Accuracy +/-0.1 dB5.1.4 Output VSWR <1.5:1 typical




5.5 Step Response Characteristics5.5.1 45.0 MHz Filter5.5.1.1 Risetime <18 ns typical5.5.1.2 Overshoot/Undershoot <2% typical5.5.2 65.0 MHz Filter5.5.2.1 Risetime <9.5 ns typical5.5.2.2 Overshoot/Undershoot <8% typical5.5.3 80 MHz Time Domain Filter5.5.3.1 Risetime <8 ns typical5.5.3.2 Overshoot/Undershoot <8% typical5.5.4 80 MHz Frequency Domain Filter5.5.4.1 Risetime <8 ns typical5.5.4.2 Overshoot/Undershoot <15% typical5.5.5 NO Filter5.5.5.1 Risetime <4 ns typical5.5.5.2 Overshoot/Undershoot <12% typical

6 FREQUENCY RANGE V 80 MHz - 200 MHz

6.0 Operating Conditions This Frequency Range does not use theWaveform Memory, Waveform Controlleror the Waveform DAC. In this operatingmode, the VHFAWG 1M's sample rate clock isbuffered to the VHFAWG 1M's channel card.

6.1 Sine Wave Amplitude Accuracy6.1.1 Absolute Accuracy @ 10 dBm6.1.1.1 AL & AMS Test Heads +/-0.25 dB6.1.1.2 PATH Test Head +/-0.45 dB6.1.2 Step Attenuator Relative Accuracy +/-((0.25 dB + 0.03 dB/dB





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7 Event Line Timing

7.0 Operating Conditions7.0.1 Valid only for presence of Consumer Digital Channel Card (AD754).7.0.2 Measured with self-test checker using Time Measurement System.

7.1 VHFAWG Channel Card Event Line to Analog Output Delay7.1.1 5.5 MHz Filter 65 +/- 35 ns7.2.2 45 MHz Filter -18 +/- 20 ns7.3.3 65 MHz Filter -22 +/- 20 ns7.3.4 80 MHz Filter (time domain) -22 +/- 20 ns7.3.5 80 MHz Filter (freq. domain) -22 +/- 20 ns

7.2 Event/Event Skew7.2.1 Event/Event Skew 20 ns max.

7.3 Event Rise/Fall Times (see ESSD for Consumer Digital Channel Card)

8 VIDEO IF GENERATION

8.0 Operating Conditions8.0.1 B/G Standard, Picture Carrier = 38.9 MHz, Sound Carrier = 33.4 MHz,

using 45 MHz filter, sample rate = 155.6 MHz8.0.2 Incidental carrier phase modulation is measured by demodulating

a B/G Standard test signal consisting of a vision carrier modulatedwith 7.8125 kHz sine-wave vision information, black-to-white levelmodulation (73% to 10% carrier amplitude) plus an unmodulated soundcarrier at -13 dB. Noise is measured in accordance with DIN 45 405with 50 us de-emphasis applied and weighted according to CCIR 468-3.Signal reference is output level for 1 kHz sound modulation at50 kHz peak deviation. Signal level is such that horizontal sync.pulse period has a carrier amplitude of 100 mVrms.

8.1 Incidental Carrier Phase Modulation (measured for conditions of 8.02)8.1.1 Sound Signal-to-Noise Ratio 55 dB min.

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Specs 41 VHF Arbitrary Waveform Generator 400

Notes:





The error terms listed above are specified for each Frequency Range. TheAbsolute Accuracy applies only when next highest frequency filter from thefrequency being sourced is selected. For the 80 MHz filters, the AbsoluteAccuracy specification only applies to the Frequency Domain Filter, not theTime Domain Filter.

5) When sourcing a frequency of less than 100 kHz, use LEVEL:SINE mode of levelcalibration and specify LEVEL_FREQ = 100kHz.



8) Sine Wave Spurious Responses are specified relative to the full scalesine wave signal in dBc down to levels of -10 dBm. Below -10 dBm, thespurious level is specified as a fixed power in dBBm.

9) The VHFAWG 400 supports three different operating modes: AWG DC, AWG AC, andCW (sine). Specifications in sections 1 through 5 apply to the AWG DCmode. Specifications in sections 1 and 6 apply to the AWG AC mode andsections 1 and 7 apply to the CW (sine) mode.Both the AWG AC and CW modes are AC coupled signal paths from the waveformDAC with DC offset capability. The peak AC voltage is independent of thepeak DC offset.



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This revision of the VHFAWG Specification applies to the following revisionof the hardware:

LA654A or later Mainframe AND LA677A or later Channel Card.



Main Menu

I VHFAWG 400 Specifications

1 General Specifications (Apply to all Frequency Ranges except where noted.)

1.1 Peak Output Voltage (AC + DC Baseline)1.1.1 AWG DC Mode1.1.1.1 Load = 50 ohms +/-2.0 V max.1.1.1.2 Load = Open Circuit +/-4.0 V max.1.1.2 CW Mode1.1.2.1 Load = 50 ohms +/-4.0 V max.1.1.3 AWG AC Mode1.1.3.1 Load = 50 ohms +/-3.0 V max.

1.2 AC p-p Output Voltage1.2.1 AWG DC Mode1.2.1.1 Load = 50 ohms 4.0 V max.1.2.1.2 Load = Open Circuit 8.0 V max.1.2.2 CW Mode1.2.2.1 Load = 50 ohms 4.0 V max.1.2.2.2 Load = Open Circuit 8.0 V max.1.2.3 AWG AC Mode1.2.3.1 Load = 50 ohms 2.0 V max.1.2.3.2 Load = Open Circuit 4.0 V max.

1.3 Output Current Compliance Limit +/-40 mA typ.

1.4 Output Short Circuit1.4.1 AWG DC Mode to 80 MHz +/-80 mA typ.1.4.2 AWG AC Mode to 80 MHz +/-70 mA typ.1.4.3 CW Mode 80 - 200 MHz +/-70 mA typ.

1.5 AC Waveform Amplitude Control1.5.1 Step Attenuators 1,2,4,8,16,16 dB1.5.2 Fine Amplitude Resolution <0.01 dB




1.9 Programmable DC Baseline1.9.1 Range +/-2.0 V1.9.2 Resolution (12 Bits)1.9.3 Accuracy1.9.3.1 Uncalibrated (dccal:off) +/-(5% + 50) mV1.9.3.2 Calibrated (dccal:on) +/-(1% + 6) mV1.9.4 Linearity1.9.4.1 Uncalibrated (dccal:off) +/-1%1.9.4.2 Calibrated (dccal:on) +/-0.5%1.9.5 Settling Time for 4.0 V Step <2 ms to 1% of final value





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1.12 Sample Clock Settling Time 15 ms max.



1.15 Waveform Memory Depth 1M


1.17 Waveform Segment Modulus1.17.1 F(s) = 1.5625 MHz - 50 MHz Modulo = 11.17.2 F(s) = 1.5625 MHz - 100 MHz Modulo = 21.17.3 F(s) = 1.5625 MHz - 200 MHz Modulo = 41.17.4 F(s) = 3.1250 MHz - 400 MHz Modulo = 8

1.18 Waveform Controller1.18.1 Maximum number of waveform segments 20481.18.2 Minimum number of samples/segment1.18.2.1 2*S.R.L. + 4 (1:1 Mode)1.18.2.2 4*S.R.L. + 6 (2:1 Mode)1.18.2.3 8*S.R.L. + 12 (4:1 Mode)1.18.2.4 16*S.R.L. + 24 (8:1 Mode)


2 Frequency Range I DC - 1 MHz (Applies only to AWG DC Mode)

2.0 Operating Conditions2.0.1 0.5 MHz Filter Min. F(s) 1.5 MHz + F(hfc)2.0.2 1.0 MHz Filter Min. F(s) 3.0 MHz + F(hfc)

2.1 Sine Wave Amplitude Accuracy2.1.1 Absolute Accuracy @ 10 dBm2.1.1.1 AL and AMS Test Heads +/-0.25 dB2.1.1.2 PATH Test Head +/-0.25 dB2.1.2 Step Attenuator Relative Accuracy

+/-((0.15 dB + 0.01 dB/dB change) up to 0.5 dB max.)2.1.3 Fine Amplitude Relative Accuracy +/-0.1 dB2.1.4 Output VSWR <1.2:1 typical






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2.5 Step Response Characteristics2.5.1 0.5 MHz Filter2.5.1.1 Rise Time <750 ns typical2.5.1.2 Overshoot/Undershoot <2% typical2.5.2 1.0 MHz Filter2.5.2.1 Rise Time <400 ns typical2.5.2.2 Overshoot/Undershoot <2% typical

3 Frequency Range II DC - 10 MHz (Applies only to AWG DC Mode)

3.0 Operating Conditions3.0.1 2.0 MHz Filter Min. F(s) 6.0 MHz + F(hfc)3.0.2 4.0 MHz Filter Min. F(s) 12.0 MHz + F(hfc)3.0.3 5.5 MHz Filter Min. F(s) 11.0 MHz + F(hfc)3.0.4 6.0 MHz Filter Min. F(s) 18.0 MHz + F(hfc)3.0.5 10.0 MHz Filter Min. F(s) 30.0 MHz + F(hfc)

3.1 Sine Wave Amplitude Accuracy3.1.1.1 AL and AMS Test Heads +/-0.25 dB3.1.1.2 PATH Test Head +/-0.25 dB3.1.2 Step Attenuator Relative Accuracy

+/-(0.15 dB + 0.01 dB/dB change up to 0.5 dB max.)3.1.3 Fine Amplitude Relative Accuracy +/-0.1 dB3.1.4 Output VSWR <1.2:1 typical




3.5 Step Response Characteristics3.5.1 2.0 MHz Filter3.5.1.1 Rise Time <200 ns typical3.5.1.2 Overshoot/Undershoot <2% typical3.5.2 4.0 MHz Filter3.5.2.1 Rise Time <100 ns typical3.5.2.2 Overshoot/Undershoot <2% typical3.5.3 5.5 MHz Filter3.5.3.1 Rise Time <80 ns typical3.5.3.2 Overshoot/Undershoot <8% typical



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3.5.4 6.0 MHz Filter3.5.4.1 Rise Time <70 ns typical3.5.4.2 Overshoot/Undershoot <2% typical3.5.5 10.0 MHz Filter3.5.5.1 Rise Time <45 ns typical3.5.5.2 Overshoot/Undershoot <2% typical

3.6 Group Delay of 5.5 MHz Filter <20 ns to 4.4 MHz typical


4 Frequency Range III DC - 30 MHz (Applies only to AWG DC Mode.)

4.0 Operating Conditions4.0.1 15.0 MHz Filter Min. F(s) 45.0 MHz + F(hfc)4.0.2 20.0 MHz Filter Min. F(s) 60.0 MHz + F(hfc)4.0.3 30 MHz Filter Min. F(s) 90.0 MHz + F(hfc)

4.1 Sine Wave Amplitude Accuracy4.1.1.1 AL and AMS Test Heads +/-0.25 dB4.1.1.2 PATH Test Head +/-0.25 dB4.1.2 Step Attenuator Relative Accuracy





4.5 Step Response Characteristics4.5.1 15.0 MHz Filter4.5.1.1 Rise Time <32 ns typical4.5.1.2 Overshoot/Undershoot <2% typical4.5.2 20.0 MHz Filter4 5.2.1 Rise Time <30 ns typical4.5.2.2 Overshoot/Undershoot <2% typical4.5.3 30 MHz Filter4.5.3.1 Rise Time <22 ns typical4.5.3.2 Overshoot/Undershoot <2% typical

5 Frequency Range IV DC - 80 MHz (Applies only to AWG DC Mode)

5.0 Operating Conditions5.0.1 45.0 MHz Filter Min. F(s) = 135.0 MHz + F(hfc)5.0.2 65.0 MHz Filter Min. F(s) = 130.0 MHz + F(hfc)



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5.0.3 80 MHz Filter (Time Domain) Min. F(s) = 160.0 MHz + F(hfc)5.0.4 80 MHz Filter (Freq Domain) Min. F(s) = 160.0 MHz + F(hfc)

5.1 Sine Wave Amplitude Accuracy5.1.1 Absolute Accuracy @ 10 dBm5.1.1.1 AL & AMS Test Heads +/-0.25 dB5.1.1.2 PATH Test Head +/-0.35 dB5.1.2 Step Attenuator Relative Accuracy

+/-((0.3 dB +0.05 dB/dB change) up to 1.0 dB max.)5.1.3 Fine Amplitude Relative Accuracy +/-0.1 dB5.1.4 Output VSWR <1.5:1 typical




5.5 Step Response Characteristics5.5.1 45.0 MHz Filter5.5.1.1 Rise Time <18 ns typical5.5.1.2 Overshoot/Undershoot <2% typical5.5.2 65.0 MHz Filter5.5.2.1 Rise Time <9.5 ns typical5.5.2.2 Overshoot/Undershoot <8% typical5.5.3 80 MHz Time Domain Filter5.5.3.1 Rise Time <8 ns typical5.5.3.2 Overshoot/Undershoot <8% typical5.5.4 80 MHz Frequency Domain Filter5.5.4.1 Rise Time <8 ns typical5.5.4.2 Overshoot/Undershoot <15% typical5.5.5 NO Filter5.5.5.1 Rise Time <4 ns typical5.5.5.2 Overshoot/Undershoot <12% typical

6 Frequency Range V 5 - 160 MHz (Applies only to AWG AC Mode.)Note: This frequency range is an AC coupled path with a lower cut off of5 MHz. The lower -3 db frequency is 1 MHz typical.

6.0 Operating Conditions6.0.1 100.0 MHz Filter Min. F(s) 200.0 MHz + F(hfc)6.0.2 130.0 MHz Filter Min. F(s) 200.0 MHz + F(hfc)6.0.3 160.0 MHz Filter Min. F(s) 240.0 MHz + F(hfc)


+/-((0.3 dB +0.05 dB/dB change) up to 1.0 dB max.)6.1.3 Fine Amplitude Relative Accuracy +/-0.15 dB6.1.4 Output VSWR <1.5:1 typical



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6.2 Sine Wave Harmonics (2nd & 3rd)6.2.1 Level = -30 - +10 dBm -40 dBc

6.3 Sine Wave Spurious Responses (BW = 5 MHz - 400 MHz)6.3.1 Level = -10 -> +10 dBm -45 dBc6.3.2 Level = -30 -> -10 dBm -55 dBm

6.4 Noise (BW = 10 MHz - 400 MHz) <30 uVrms (30 kHz BW)

6.5 Square Wave Response Characteristics6.5.1 100.0 MHz Filter6.5.1.1 Rise Time <8 ns6.5.1.2 Overshoot/Undershoot <8% typical6.5.2 130.0 MHz Filter6.5.2.1 Rise Time <7 ns6.5.2.2 Overshoot/Undershoot <8% typical6.5.3 160 MHz Time Domain Filter6.5.3.1 Rise Time <5 ns6.5.3.2 Overshoot/Undershoot <8% typical6.5.4 NO Filter6.5.4.1 Rise Time <4 ns typical6.5.4.2 Overshoot/Undershoot <12% typical

7 Frequency Range VI 80 MHz - 200 MHz (Applies only to CW Mode)

7.0 Operating ConditionsThis Frequency Range uses the Waveform Memory, Waveform Controller, andthe Waveform DAC to generate a square wave. In this operating mode, the squarewave is buffered to the VHFAWG's channel card where it is filtered to eliminatethe higher order frequency components.




7.3 Sine Wave Spurious Responses (BW = 100 Hz - 200 MHz)7.3.1 Level = -10 -> +16 dBm -40 dBc7.3.2 Level = -30 -> -10 dBm -50 dBm


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Specs

42 VHF Arbitrary Waveform Generator 400Differential

Notes:

1. All guaranteed specifications apply at the DIB “blind mate” RF connectors.The amplitude accuracy specifications are typical specifications whenusing the Pogo pin path. See the frequency range sections (2 through 8) forthe amplitude accuracy specifications for the Pogo pin path.

The Sine Wave Harmonic, Sine Wave Spurious, Noise, and Step ResponseCharacteristics are all typical specifications, not guaranteed, when thePogo pin path is used.

2. All specifications assume a 50 ohm load. The software leveling calibrationallows the user to specify any resistive load and will compensate the outputlevel to achieve the programmed level at the programmed load. Spectralpurity specifications may vary as the load varies from 50 ohms when filtershigher than 10 MHz are selected, include the 80 -200 MHz frequency range.

3. Level Accuracy specifications assume that software calibration is not dis-abled (level:none is not selected).

4. Amplitude Accuracy = Absolute Accuracy @ 10 dBm + Step AttenuatorAccuracy

+ Fine Amplitude Accuracy + Mismatch Errors

The error terms listed above are specified for each Frequency Range. TheAbsolute Accuracy applies only when next highest frequency filter from thefrequency being sourced is selected. Also, the Absolute Accuracy appliesonly to the Frequency Domain 80 MHz Filter, not the Time Domain 80 MHzFilter.

5. When sourcing a frequency of less than 150 kHz, the user should useLEVEL:SINE mode of level calibration and specify LEVEL_FREQ = 150kHz.

6. All specifications including those that are Frequency Range specificassume that the waveform is stored in memory normalized to 12 bits fullscale.

7. All specifications are guaranteed unless noted as TYPICAL or NOMINAL.

8. TYPICAL specifications are sample tested, NOT 100% tested and are NOTguaranteed.

9. NOMINAL specifications are generally calculated values, are NOT 100%tested and are NOT guaranteed.

10. F(hfc) = Highest Frequency Component being sourced.

11. Sine Wave Spurious Responses are specified relative to the full scale sinewave signal in dBc down to levels of -10 dBm. Below -10 dBm, the spuriouslevel is specified as a fixed power in dBm.



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12. The VHFAWG 400 supports three different operating modes: AWG DC,AWG AC, and CW (Sine). The restrictions are defined below:

– Specifications in section 1 apply to all three operating modes.– Specifications in sections 2 - 5 apply to the AWG DC Differential mode

(DC to 80 MHz).– Specifications in sections 2 - 6 apply to the AWG DC Single Ended mode

(DC to 160 MHz).– Specifications in section 7 apply to the AWG AC mode (5 MHz to 160

MHz).– Specifications in section 8 apply to the sine mode (80 MHz to 200 MHz).– Both the AWG AC and CW modes are AC coupled signal paths from the

waveform DAC with DC offset capability. The peak AC voltage is inde-pendent of the peak DC offset.

13. This revision of the VHFAWG Specification applies to the following boards:

– LA654 (mainframe card)– LA681 (channel card)

14. In differential mode (both DC and AC) the amplitude programming syntaxspecifies the amplitude with respect to the load connected to ground. If theload is connected differentially (between the A and C outputs) the power orvoltage delivered to the load is doubled to what was specified in the syntax.To deliver a +10 dBm signal into a differential load the programming state-ment should specify +4 dBm.

15. The spectral purity specifications are all specified with the load connectedto ground.

16. All sine wave spectral purity specifications (Harmonic, Non Harmonic, andNoise) are valid only when next highest filter from the frequency beingsourced is selected.



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5 VHFAWG 400 DIFFERENTIAL SPECIFICATIONS

5.1 General Specifications (Apply to all Frequency Ranges)

5.2 Peak Output Voltage (AC + DC Baseline)5.2.1 Peak Output Voltage Single-ended Output A:5.2.1.1 AWG DC:5.2.1.2 Load = 50 ohms +/-2.0 V max.5.2.1.3 Load = Open Circuit +/-4.0 V max.5.2.1.4 CW Mode (80 MHz to 200 MHz):5.2.1.5 Load = 50 ohms +/-4.0 V max.5.2.1.6 AWG AC (5 MHz to 160 MHz):5.2.1.7 Load = 50 ohms +/-3.0 V max.5.2.2 Peak Output Voltage Differential Outputs A or C.5.2.2.1 AWG DC:5.2.2.2 Load = 50 ohms +/-2.0 V max.5.2.2.3 Load = Open Circuit +/-4.0 V max.5.2.2.4 CW Mode (80 MHz to 200 MHz):5.2.2.5 Load = 50 ohms +/-4.0 V max.5.2.2.6 AWG AC (5 MHz to 160 MHz):5.2.2.7 Load = 50 ohms +/-3.0 V max.

5.3 AC p-p Output Voltage5.3.1 AC p-p Output Voltage Single-ended Output A5.3.1.1 AWG DC:5.3.1.2 Load = 50 ohms 4.0 V max.5.3.1.3 Load = Open Circuit 8.0 V max.5.3.1.4 CW Mode:5.3.1.5 Load = 50 ohms 4.0 V max.5.3.1.6 Load = Open Circuit 8.0 V max.5.3.1.7 AWG AC:5.3.1.8 Load = 50 ohms 2.0 V max.5.3.1.9 Load = Open Circuit 4.0 V max.5.3.2 AC p-p Output Voltage Differential Outputs A or C5.3.2.1 AWG DC:5.3.2.2 Load = 50 ohms 2.0 V max.5.3.2.3 Load = Open Circuit 4.0 V max.5.3.2.4 CW Mode:5.3.2.5 Load = 50 ohms 2.0 V max.5.3.2.6 Load = Open Circuit 4.0 V max.5.3.2.7 AWG AC:5.3.2.8 Load = 50 ohms 2.0 V max.5.3.2.9 Load = Open Circuit 4.0 V max.

5.4 Output Current Compliance Limit +/-40 mA typical.

5.5 Output Short Circuit5.5.1 AWG DC Mode: +/-80 mA. typ.5.5.2 AWG AC Mode (5 to 160 MHz) +/-70 mA. typ.5.5.3 CW Mode (80 - 200 MHz) +/-70 mA. typ.

5.6 AC Waveform Amplitude Control5.6.1 Step Attenuators 1, 2, 4, 8, 16, 16 dB5.6.2 Fine Amplitude Resolution <0.01 dB



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5.7 DC Offset5.7.1 Without autocal +/-50 mV5.7.2 With autocal +/-5 mV5.7.3 Offset Drift +/-800 uV/C nominal

5.8 Programmable DC Baseline5.8.1 Range +/-2.0 V5.8.2 Resolution 12 bits5.8.3 Accuracy5.8.3.1 Single Ended Output A:Uncalibrated (dccal:off) +/-(5% + 50) mV nominal5.8.3.2 Single Ended Output A:Calibrated (dccal:on) +/-(1% + 6) mV5.8.3.3 Differential Output A:Uncalibrated (dccal:off) +/-(5% + 50) mV nominal5.8.3.4 Differential Output A:Calibrated (dccal:on) +/-(1.5% + 10) mV5.8.3.5 Differential Output C:Uncalibrated (dccal:off) +/-(5% + 50) mV nominal5.8.3.6 Differential Output C:Calibrated (dccal:on) +/-(1.5% + 10) mV5.8.4 Linearity5.8.4.1 Uncalibrated (dccal:off) +/-1% nominal5.8.4.2 Calibrated (dccal:on) +/-0.5%5.8.5 Settling Time for 4.0 V Step <2 ms nominal to 1% of final value






5.14 Waveform Memory Depth 1 Meg Samples


5.16 Waveform Segment Modulus5.16.1 F(s) = 1.5625 MHz - 50 MHz Modulo = 15.16.2 F(s) = 1.5625 MHz - 100 MHz Modulo = 25.16.3 F(s) = 1.5625 MHz - 200 MHz Modulo = 45.16.4 F(s) = 3.1250MHz - 400 MHz Modulo = 8

5.17 Waveform Controller5.17.1 Maximum number of waveform segments 20485.17.2 Minimum number of samples/segment5.17.2.1 2*S.R.L. + 4 (1:1 Mode)5.17.2.2 4*S.R.L. + 6(2:1 Mode)5.17.2.3 8*S.R.L. + 12 (4:1 Mode)5.17.2.4 16*S.R.L. + 24(8:1 Mode)5.17.2.5 (S.R.L. = Subroutine Level)


6.1 Operating ConditionsNote: Specifications in this section apply to AWG DC mode both Single Endedand Differential.

6.1.0.1 AWG DC Mode:6.1.0.2 0.5 MHz Filter Min. F(s) = 1.5 MHz + F(hfc)6.1.0.3 1.0 MHz Filter Min. F(s) = 3.0 MHz + F(hfc)



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6.2 Sine Wave Amplitude Accuracy6.2.1 RF Pipe Outputs6.2.1.1 Single Ended Output A: Absolute Accuracy @ 10 dBm6.2.1.1.1 AL and AMS Test Heads +/-0.25 dB6.2.1.1.2 PATH Test Head +/-0.25 dB6.2.1.2 Differential Output A: Absolute Accuracy @ 10 dBm6.2.1.2.1 AL and AMS Test Heads +/-0.25 dB6.2.1.2.2 PATH Test Head +/-0.25 dB6.2.1.3 Differential Output C: Absolute Accuracy @ 10 dBm6.2.1.3.1 AL and AMS Test Heads +/-0.75 dB6.2.1.3.2 PATH Test Head +/-0.75 dB6.2.2 Pogo Pin Outputs6.2.2.1 Single Ended Output A: Absolute Accuracy @ 10 dBm6.2.2.1.1 AL, AMS and PATH Test Heads +/-0.25 dB typical6.2.2.2 Differential Output A: Absolute Accuracy @ 10 dBm6.2.2.2.1 AL, AMS and PATH Test Heads +/-0.25 dB typical6.2.2.3 Differential Output C: Absolute Accuracy @ 10 dBm6.2.2.3.1 AL, AMS and PATH Test Heads +/-0.45 dB typical6.2.3 Step Attenuator Relative Accuracy +/-((0.15 dB + 0.01 dB/dB change) up to 0.5 dB max.)6.2.4 Fine Amplitude Relative Accuracy +/-0.1 dB6.2.5 Output VSWR <1.2:1 typical

6.3 Sine Wave Harmonics (2nd & 3rd) (Note: Max. Sample Freq. = 50 MHz)6.3.1 Single Ended Output A6.3.1.1 Level = 10 to 16 dBm -45 dBc6.3.1.2 Level = 0 to 10 dBm -55 dBc6.3.1.3 Level = -30 to 0 dBm -60 dBc6.3.2 Differential Output A6.3.2.1 Level = -6 to 4 dBm -40 dBc6.3.2.2 Level = -30 to -6 dBm -50 dBc6.3.3 Differential Output C6.3.3.1 Level = -6 to 4 dBm -40 dBc typical6.3.3.2 Level = -30 to -6 dBm -50 dBc typical

6.4 Sine Wave Spurious Responses (BW = 10 kHz - 10 MHz)6.4.1 Single Ended Output A:Level = -10 to +16 dBm -60 dBc6.4.2 Single Ended Output A:Level = -30 to -10 dBm -70 dBm6.4.3 Differential Output A: Level = -10 to +10 dBm -50 dBc6.4.4 Differential Output A: Level = -30 to -10 dBm -60 dBm6.4.5 Differential Output C: Level = -10 to +10 dBm -50 dBc typical6.4.6 Differential Output C: Level = -30 to -10 dBm -60 dBm typical

6.5 Noise (BW = 100 Hz - 30 MHz)6.5.1 Single Ended Output A <20 uVrms (30 kHz BW)6.5.2 Differential Output A <20 uVrms (30 kHz BW)6.5.3 Differential Output C <20 uVrms (30 kHz BW) typical




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7.1.1 AWG DC Mode:7.1.1.1 2.0 MHz Filter Min. F(s) = 6.0 MHz + F(hfc)7.1.1.2 4.0 MHz Filter Min. F(s) = 12.0 MHz + F(hfc)7.1.1.3 5.5 MHz Filter Min. F(s) = 11.0 MHz + F(hfc)7.1.1.4 6.0 MHz Filter Min. F(s) = 18.0 MHz + F(hfc)7.1.1.5 10.0 MHz Filter Min. F(s) = 30.0 MHz + F(hfc)

7.2 Sine Wave Amplitude Accuracy7.2.1 RF Pipe Outputs7.2.1.1 Single Ended Output A: Absolute Accuracy @ 10 dBm7.2.1.1.1 AL and AMS Test Heads +/-0.25 dB7.2.1.1.2 PATH Test Head +/-0.25 dB7.2.1.2 Differential Output A: Absolute Accuracy @ 10 dBm7.2.1.2.1 AL and AMS Test Heads +/-0.25 dB7.2.1.2.2 PATH Test Head +/-0.25 dB7.2.1.3 Differential Output C: Absolute Accuracy @ 10 dBm7.2.1.3.1 AL and AMS Test Heads +/-0.75 dB7.2.1.3.2 PATH Test Head +/-0.75 dB7.2.2 Pogo Pin Outputs7.2.2.1 Single Ended Output A: Absolute Accuracy @ 10 dBm7.2.2.1.1 AL, AMS and PATH Test Heads +/-0.25 dB typical7.2.2.2 Differential Output A: Absolute Accuracy @ 10 dBm7.2.2.2.1 AL, AMS and PATH Test Heads +/-0.25 dB typical7.2.2.3 Differential Output C: Absolute Accuracy @ 10 dBm7.2.2.3.1 AL, AMS and PATH Test Heads +/-0.45 dB typical7.2.3 Step Attenuator Relative Accuracy +/-(0.15 dB + 0.01 dB/dB change up to 0.5 dB max.)7.2.4 Fine Amplitude Relative Accuracy +/-0.1 dB7.2.5 Output VSWR <1.2:1 typical

7.3 Sine Wave Harmonics (2nd & 3rd) (Note: Max. Sample Freq. = 50 MHz)7.3.1 Single Ended Output A: Frequency = 1 - 4 MHz7.3.1.1 Level = 10 to 16 dBm -45 dBc7.3.1.2 Level = 0 to 10 dBm -55 dBc7.3.1.3 Level = -30 to 0 dBm -60 dBc7.3.2 Single Ended Output A: Frequency = 4 - 10 MHz7.3.2.1 Level = 10 to 16 dBm -45 dBc7.3.2.2 Level = 0 to 10 dBm -50 dBc7.3.2.3 Level = -30 to 0 dBm -55 dBc7.3.3 Differential Output A: Frequency = 1 - 4 MHz7.3.3.1 Level = -6 to 4 dBm -40 dBc7.3.3.2 Level = -30 to -6 dBm -50 dBc7.3.4 Differential Output A: Frequency = 4 - 10 MHz7.3.4.1 Level = -6 to 4 dBm -40 dBc7.3.4.2 Level = -30 to -6 dBm -50 dBc7.3.5 Differential Output C: Frequency = 1 - 4 MHz7.3.5.1 Level = -6 to 4 dBm -40 dBc typical7.3.5.2 Level = -30 to -6 dBm -50 dBc typical7.3.6 Differential Output C: Frequency = 4 - 10 MHz7.3.6.1 Level = -6 to 4 dBm -40 dBc typical7.3.6.2 Level = -30 to -6 dBm -50 dBc typical



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7.4 Sine Wave Spurious Responses (BW = 10 kHz - 100 MHz)7.4.1 Single Ended Output A7.4.1.1 Level = -10 to +16 dBm -55 dBc7.4.1.2 Level = -30 to -10 dBm -65 dBm7.4.2 Differential Output A7.4.2.1 Level = -10 to +10 dBm -50 dBc7.4.2.2 Level = -30 to -10 dBm -60 dBm7.4.3 Differential Output C7.4.3.1 Level = -10 to +10 dBm -50 dBc typical7.4.3.2 Level = -30 to -10 dBm -60 dBm typical


7.6 Step Response Characteristics7.6.1 2.0 MHz Filter7.6.1.1 Risetime <200 ns typical7.6.1.2 Overshoot/Undershoot <2% typical7.6.2 4.0 MHz Filter7.6.2.1 Risetime <100 ns typical7.6.2.2 Overshoot/Undershoot <2% typical7.6.3 5.5 MHz Filter7.6.3.1 Risetime <80 ns typical7.6.3.2 Overshoot/Undershoot <8% typical7.6.4 6.0 MHz Filter7.6.4.1 Risetime <70 ns typical7.6.4.2 Overshoot/Undershoot <2% typical7.6.5 10.0 MHz Filter7.6.5.1 Risetime <45 ns typical7.6.5.2 Overshoot/Undershoot <2% typical7.6.6 Group Delay of 5.5 MHz Filter <20 ns to 4.4 MHz typ.




8.1.1 AWG DC Mode:8.1.1.1 15.0 MHz Filter Min. F(s) = 45.0 MHz + F(hfc)8.1.1.2 20.0 MHz Filter Min. F(s) = 60.0 MHz + F(hfc)8.1.1.3 30 MHz Filter Min. F(s) = 90.0 MHz + F(hfc)

8.2 Sine Wave Amplitude Accuracy8.2.1 RF Pipe Outputs8.2.1.1 Single Ended Output A: Absolute Accuracy @ 10 dBm8.2.1.1.1 AL and AMS Test Heads +/-0.25 dB8.2.1.1.2 PATH Test Head +/-0.25 dB8.2.1.2 Differential Output A: Absolute Accuracy @ 10 dBm8.2.1.2.1 AL and AMS Test Heads +/-0.25 dB8.2.1.2.2 PATH Test Head +/-0.25 dB



Main Menu

8.2.1.3 Differential Output C: Absolute Accuracy @ 10 dBm8.2.1.3.1 AL and AMS Test Heads +/-0.75 dB8.2.1.3.2 PATH Test Head +/-0.75 dB8.2.2 Pogo Pin Outputs8.2.2.1 Single Ended Output A: Absolute Accuracy @ 10 dBm8.2.2.1.1 AL, AMS and PATH Test Heads +/-0.35 dB typical8.2.2.2 Differential Output A: Absolute Accuracy @ 10 dBm8.2.2.2.1 AL, AMS and PATH Test Heads +/-0.35 dB typical8.2.2.3 Differential Output C: Absolute Accuracy @ 10 dBm8.2.2.3.1 AL, AMS and PATH Test Heads +/-0.50 dB typical8.2.3 Step Attenuator Relative Accuracy +/-((0.25 dB + 0.01 dB/dB change) up to 0.5 dB max.)8.2.4 Fine Amplitude Relative Accuracy +/-0.1 dB8.2.5 Output VSWR <1.5:1 typical

8.3 Sine Wave Harmonics(2nd & 3rd) (Note: Max. Sample Freq. = 120 MHz)8.3.1 Single Ended Output A8.3.1.1 Level = 10 to 16 dBm -40 dBc8.3.1.2 Level = -30 to +10 dBm -45 dBc8.3.2 Differential Output A8.3.2.1 Level = -30 to +4 dBm -40 dBc8.3.3 Differential Output C8.3.3.1 Level = -30 to +4 dBm -40 dBc typical

8.4 Sine Wave Spurious Responses (BW = 10 KHz - 150 MHz)8.4.1 Single ended Output A8.4.1.1 Level = -10 to +16 dBm -45 dBc8.4.1.2 Level = -30 to -10 dBm -55 dBm8.4.2 Differential Output A8.4.2.1 Level = -10 to +10 dBm -45 dBc8.4.2.2 Level = -30 to -10 dBm -55 dBm8.4.3 Differential Output C8.4.3.1 Level = -10 to +10 dBm -45 dBc typical8.4.3.2 Level = -30 to -10 dBm -55 dBm typical


8.6 Step Response Characteristics8.6.1 15.0 MHz Filter8.6.1.1 Risetime <32 ns typical8.6.1.2 Overshoot/Undershoot <2% typical8.6.2 20.0 MHz Filter8.6.2.1 Risetime <30 ns typical8.6.2.2 Overshoot/Undershoot <2% typical8.6.3 30 MHz Filter8.6.3.1 Risetime <22 ns typical8.6.3.2 Overshoot/Undershoot <2% typical



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9 FREQUENCY RANGE IV DC - 80 MHz (Applies only to AWG DC Mode)


9.1.1 AWG DC Mode9.1.1.1 45.0 MHz Filter Min. F(s) = 135.0 MHz + F(hfc)9.1.1.2 65.0 MHz Filter Min. F(s) = 130.0 MHz + F(hfc)9.1.1.3 80 MHz Filter (Time Domain) Min. F(s) = 160.0 MHz + F(hfc)9.1.1.4 80 MHz Filter (Freq Domain) Min. F(s) = 160.0 MHz + F(hfc)

9.2 Sine Wave Amplitude Accuracy9.2.1 RF Pipe Outputs9.2.1.1 Single Ended Output A: Absolute Accuracy @ 10 dBm9.2.1.1.1 AL and AMS Test Heads +/-0.25 dB9.2.1.1.2 PATH Test Head +/-0.35 dB9.2.1.2 Differential Output A: Absolute Accuracy @ 10 dBm9.2.1.2.1 AL and AMS Test Heads +/-0.25 dB9.2.1.2.2 PATH Test Head +/-0.35 dB9.2.1.3 Differential Output C: Absolute Accuracy @ 10 dBm9.2.1.3.1 AL and AMS Test Heads +/-1.00 dB9.2.1.3.2 PATH Test Head +/-1.10 dB9.2.2 Pogo Pin Outputs9.2.2.1 Single Ended Output A: Absolute Accuracy @ 10 dBm9.2.2.1.1 AL, AMS and PATH Test Heads +0.35/-0.60 dB typical9.2.2.2 Differential Output A: Absolute Accuracy @ 10 dBm9.2.2.2.1 AL, AMS and PATH Test Heads +0.35/-0.50 dB typical9.2.2.3 Differential Output C: Absolute Accuracy @ 10 dBm9.2.2.3.1 AL, AMS and PATH Test Heads +0.50/-0.75 dB typical9.2.3 Step Attenuator Relative Accuracy +/-((0.3 dB + 0.05 dB/dB change) up to 1.0 dB max.)9.2.4 Fine Amplitude Relative Accuracy +/-0.1 dB9.2.5 Output VSWR <1.5:1 typical

9.3 Sine Wave Harmonics (2nd & 3rd)9.3.1 Single Ended Output A9.3.1.1 Level = -30 to +16 dBm -40 dBc9.3.2 Differential Output A9.3.2.1 Level = -6 to +4 dBm -33 dBc9.3.2.2 Level = -30 to -6 dBm -35 dBc9.3.3 Differential Output C9.3.3.1 Level = -6 to +4 dBm -33 dBc typical9.3.3.2 Level = -30 to -6 dBm -35 dBc typical

9.4 Sine Wave Spurious Responses (BW = 10 KHz - 200 MHz)9.4.1 Single ended Output A9.4.1.1 Level = -10 to +16 dBm -45 dBc9.4.1.2 Level = -30 to -10 dBm -55 dBm9.4.2 Differential Output A9.4.2.1 Level = -10 to +10 dBm -40 dBc9.4.2.2 Level = -30 to -10 dBm -50 dBm9.4.3 Differential Output C9.4.3.1 Level = -10 to +10 dBm -40 dBc typical9.4.3.2 Level = -30 to -10 dBm -50 dBm typical

9.5 Noise (BW = 100 Hz - 200 MHz)



Main Menu

9.5.1 Single Ended Output A <20 uVrms (30 kHz BW)9.5.2 Differential Output A <20 uVrms (30 kHz BW)9.5.3 Differential Output C <20 uVrms (30 kHz BW) typical

9.6 Step Response Characteristics9.6.1 45.0 MHz Filter9.6.1.1 Risetime <18 ns typical9.6.1.2 Overshoot/Undershoot <2% typical9.6.2 65.0 MHz Filter9.6.2.1 Risetime <9.5 ns typical9.6.2.2 Overshoot/Undershoot <8% typical9.6.3 80 MHz Time Domain Filter9.6.3.1 Risetime <8 ns typical9.6.3.2 Overshoot/Undershoot <8% typical9.6.4 80 MHz Frequency Domain Filter9.6.4.1 Risetime <8 ns typical9.6.4.2 Overshoot/Undershoot <15% typical9.6.5 No Filter9.6.5.1 Risetime <4 ns typical9.6.5.2 Overshoot/Undershoot <12% typical

10 FREQUENCY RANGE V DC - 160 MHz (AWG DC SE Only)

10.1 Operating ConditionsNote: Specifications in this section apply to AWG DC mode in Single Endedoperation only.

10.1.1 AWG DC Mode:10.1.1.1 100.0 MHz Filter Min. F(s) = 200.0 MHz + F(hfc)10.1.1.2 130.0 MHz Filter Min. F(s) = 200.0 MHz + F(hfc)10.1.1.3 160.0 MHz Filter Min. F(s) = 240.0 MHz + F(hfc)

10.2 Sine Wave Amplitude Accuracy10.2.1 RF Pipe Output10.2.1.1 Single Ended Output A: Absolute Accuracy @ 10 dBm10.2.1.1.1 AL and AMS Test Heads +/-0.35 dB10.2.1.1.2 PATH Test Head +/-0.45 dB10.2.2 Pogo Pin Output10.2.2.1 Single Ended Output A: Absolute Accuracy @ 10 dBm10.2.2.1.1 AL, AMS and PATH Test Heads +0.45/-1.00 dB typical10.2.3 Step Attenuator Relative Accuracy +/-((0.3 dB + 0.05 dB/dB change) up to 1.25 dB max.)10.2.4 Fine Amplitude Relative Accuracy +/-0.15dB10.2.5 Output VSWR <1.5:1 typical

10.3 Sine Wave Harmonics (2nd & 3rd)10.3.1 Single Ended Output A10.3.1.1 Level = -30 to +16 dBm -40 dBc

10.4 Sine Wave Spurious Responses (BW = 10 KHz - 400 MHz)10.4.1 Single ended Output A10.4.1.1 Level = -10 to +16 dBm -40 dBc10.4.1.2 Level = -30 to -10 dBm -50 dBm

10.5 Noise (BW = 100 Hz - 400 MHz)10.5.1 Single Ended Output A <30 uVrms (30 kHz BW)



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10.6 Step Response Characteristics10.6.1 100.0 MHz Filter10.6.1.1 Risetime <8 ns10.6.1.2 Overshoot/Undershoot <8% typical10.6.2 130.0 MHz Filter10.6.2.1 Risetime <7 ns10.6.2.2 Overshoot/Undershoot <8% typical10.6.3 160 MHz Filter10.6.3.1 Risetime <5 ns10.6.3.2 Overshoot/Undershoot <8% typical10.6.4 No Filter10.6.4.1 Risetime <4 ns typical10.6.4.2 Overshoot/Undershoot <12% typical

11 FREQUENCY RANGE VI 5 - 160 MHz (Applies only to AWG AC Mode)

11.1 Operating ConditionsNote: The lower -3 dB frequency of the AWG AC path is 1 MHz typical.

11.1.1 AWG AC Mode (5 to 160 MHz):11.1.1.1 15.0 MHz Filter Min. F(s) = 45.0 MHz + F(hfc)11.1.1.2 20.0 MHz Filter Min. F(s) = 60.0 MHz + F(hfc)11.1.1.3 30 MHz Filter Min. F(s) = 90.0 MHz + F(hfc)11.1.1.4 45.0 MHz Filter Min. F(s) = 135.0 MHz + F(hfc)11.1.1.5 65.0 MHz Filter Min. F(s) = 130.0 MHz + F(hfc)11.1.1.6 80 MHz Filter (Time Domain) Min. F(s) = 160.0 MHz + F(hfc)11.1.1.7 80 MHz Filter (Freq Domain) Min. F(s) = 160.0 MHz + F(hfc)11.1.1.8 100 MHz Filter Min. F(s) = 200.0 MHz + F(hfc)11.1.1.9 130 MHz Filter Min. F(s) = 200.0 MHz + F(hfc)11.1.1.10 160 MHz Filter Min. F(s) = 240.0 MHz + F(hfc)

11.2 Sine Wave Amplitude Accuracy11.2.1 RF Pipe Outputs11.2.1.1 Single Ended Output A: Absolute Accuracy @ 10 dBm11.2.1.1.1 AL and AMS Test Heads +/-0.25 dB11.2.1.1.2 PATH Test Head +/-0.45 dB11.2.1.2 Differential Output A: Absolute Accuracy @ 10 dBm11.2.1.2.1 AL and AMS Test Heads +/-0.25 dB11.2.1.2.2 PATH Test Head +/-0.45 dB11.2.1.3 Differential Output C: Absolute Accuracy @ 10 dBm11.2.1.3.1 AL & AMS Test Heads +/-1.00 dB11.2.1.3.2 PATH Test Head +/-1.20 dB11.2.2 Pogo Pin Outputs11.2.2.1 Single Ended Output A: Absolute Accuracy @ 10 dBm11.2.2.1.1 AL, AMS and PATH Test Heads +0.45/-1.00 dB typical11.2.2.2 Differential Output A: Absolute Accuracy @ 10 dBm11.2.2.2.1 AL, AMS and PATH Test Heads +0.45/-1.00 dB typical11.2.2.3 Differential Output C: Absolute Accuracy @ 10 dBm11.2.2.3.1 AL, AMS and PATH Test Heads +0.50/-1.25 dB typical11.2.3 Step Attenuator Relative Accuracy +/-((0.3 dB + 0.05 dB/dB change) up to 1.0 dB max.)11.2.4 Fine Amplitude Relative Accuracy +/-0.15dB11.2.5 Output VSWR <1.5:1 typical



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11.3 Sine Wave Harmonics (2nd & 3rd)11.3.1 Single Ended Output A11.3.1.1 Level = -30 to +10 dBm -40 dBc11.3.2 Differential Output A11.3.2.1 Level = -30 to +10 dBm -40 dBc11.3.3 Differential Output C11.3.3.1 Level = -30 to +10 dBm -40 dBc typical

11.4 Sine Wave Spurious Responses (BW = 5 MHz - 400 MHz)11.4.1 Single ended Output A11.4.1.1 Level = -10 to +10 dBm -40 dBc11.4.1.2 Level = -30 to -10 dBm -50 dBm11.4.2 Differential Output A11.4.2.1 Level = -10 to +10 dBm -40 dBc11.4.2.2 Level = -30 to -10 dBm -50 dBm11.4.3 Differential Output C11.4.3.1 Level = -10 to +10 dBm -40 dBc typical11.4.3.2 Level = -30 to -10 dBm -50 dBm typical

11.5 Noise (BW = 10 MHz - 400 MHz)11.5.1 Single Ended Output A <30 uVrms (30 kHz BW)11.5.2 Differential Output A <30 uVrms (30 kHz BW)11.5.3 Differential Output C <30 uVrms (30 kHz BW) typical

11.6 Square Wave Response Characteristics11.6.1 15.0 MHz Filter11.6.1.1 Risetime <32 ns typical11.6.1.2 Overshoot/Undershoot <2% typical11.6.2 20.0 MHz Filter11.6.2.1 Risetime <30 ns typical11.6.2.2 Overshoot/Undershoot <2% typical11.6.3 30 MHz Filter11.6.3.1 Risetime <22 ns typical11.6.3.2 Overshoot/Undershoot <2% typical11.6.4 45.0 MHz Filter11.6.4.1 Risetime <18 ns typical11.6.4.2 Overshoot/Undershoot <2% typical11.6.5 65.0 MHz Filter11.6.5.1 Risetime <9.5 ns typical11.6.5.2 Overshoot/Undershoot <8% typical11.6.6 80 MHz Time Domain Filter11.6.6.1 Risetime <8 ns typical11.6.6.2 Overshoot/Undershoot <8% typical11.6.7 80 MHz Frequency Domain Filter11.6.7.1 Risetime <8 ns typical11.6.7.2 Overshoot/Undershoot <15% typical11.6.8 100.0 MHz Filter11.6.8.1 Risetime <8 ns11.6.8.2 Overshoot/Undershoot <8% typical11.6.9 130.0 MHz Filter11.6.9.1 Risetime <7 ns11.6.9.2 Overshoot/Undershoot <8% typical11.6.10 160 MHz Filter11.6.10.1 Risetime <5 ns11.6.10.2 Overshoot/Undershoot <8% typical



Main Menu

11.6.11 No Filter11.6.11.1 Risetime <4 ns typical11.6.11.2 Overshoot/Undershoot <12% typical

12 FREQUENCY RANGE VII 80 MHz - 200 MHz (Sine Wave Only)

12.1 Operating ConditionsThis frequency range uses the Waveform Memory, Waveform Controller andthe Waveform DAC to generate a square wave. In this operating mode, thesquare wave sample is buffered to the VHFAWG’s channel card where it is fil-tered to eliminate the higher order frequency components.

12.2 Sine Wave Amplitude Accuracy12.2.1 RF Pipe Outputs12.2.1.1 Single Ended Output A: Absolute Accuracy @ 10 dBm12.2.1.1.1 AL and AMS Test Heads +/-0.25 dB12.2.1.1.2 PATH Test Head +/-0.45 dB12.2.1.2 Differential Output A: Absolute Accuracy @ 10 dBm12.2.1.2.1 AL and AMS Test Heads +/-0.25 dB12.2.1.2.2 PATH Test Head +/-0.45 dB12.2.1.3 Differential Output C: Absolute Accuracy @ 10 dBm12.2.1.3.1 AL and AMS Test Heads +/-1.00 dB12.2.1.3.2 PATH Test Head +/-1.20 dB12.2.2 Pogo Pin Outputs12.2.2.1 Single Ended Output A: Absolute Accuracy @ 10 dBm12.2.2.1.1 AL, AMS and PATH Test Heads +0.45/-1.25 dB typical12.2.2.2 Differential Output A: Absolute Accuracy @ 10 dBm12.2.2.2.1 AL, AMS and PATH Test Heads +0.45/-1.25 dB typical12.2.2.3 Differential Output C: Absolute Accuracy @ 10 dBm12.2.2.3.1 AL, AMS and PATH Test Heads +0.50/-1.50 dB typical12.2.3 Step Attenuator Relative Accuracy +/-((0.25 dB + 0.03 dB/dB change) up to 1.25 dB max.)12.2.4 Fine Amplitude Relative Accuracy +/-0.15 dB12.2.5 Output VSWR <1.5:1 typical

12.3 Sine Wave Harmonics (2nd & 3rd)12.3.1 Single Ended Output A12.3.1.1 Level = -30 to +16 dBm -40 dBc12.3.2 Differential Output A12.3.2.1 Level = -30 to +10 dBm -40 dBc12.3.3 Differential Output C12.3.3.1 Level = -30 to +10 dBm -40 dBc typical

12.4 Sine Wave Spurious Responses (BW = 5 MHz - 200 MHz)12.4.1 Single ended Output A12.4.1.1 Level = -10 to +16 dBm -40 dBc12.4.1.2 Level = -30 to -10 dBm -50 dBm12.4.2 Differential Output A12.4.2.1 Level = -10 to +10 dBm -40 dBc12.4.2.2 Level = -30 to -10 dBm -50 dBm12.4.3 Differential Output C12.4.3.1 Level = -10 to +10 dBm -40 dBc typical12.4.3.2 Level = -30 to -10 dBm -50 dBm typical



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12.5 Noise (BW = 5 MHz - 500 MHz)12.5.1 Single Ended Output A < 65 uVrms (300 kHz BW)12.5.2 Differential Output A < 65 uVrms (300 kHz BW)12.5.3 Differential Output C < 65 uVrms (300 kHz BW) typical

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Specs 43 VHF Continuous Wave Source

Notes:

1) For A5 type systems, all specifications apply at the DIB "blind mate" RFconnector. The VHFCW may also interface to the DIB via the channel cardPogo pin path. Specifications may be degraded when using the Pogo pin path.

For Catalyst systems, all specifications apply at the VHFCW_DIR Pogo pin.The VHFCW also interfaces to the DIB via the VHFCW_ALT Pogo pin.Specifications may be degraded when using the VHFCW_ALT Pogo pin.









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I VHF CW SPECIFICATIONS


1.1 Frequency1.1.1 Range 1 to 249.999 999 MHz1.1.2 Resolution 1 Hz

1.2 Peak Output Voltage (AC + DC Baseline) +/-2.0 V max.

1.3 AC p-p Output Voltage 4.0 V max.

1.4 Output Current Compliance Limit +/-40 mA typical

1.5 Output Short Circuit Current1.5.1 1 - 5.477 MHz +/-80 mA typical1.5.2 5.477 MHz - 250 MHz +/-70 mA typical

1.6 AC Amplitude1.6.1 Level Range +16 to -31 dBm1.6.2 Step Attenuators 1, 2, 4, 8, 16, 16 dB1.6.3 Fine Amplitude Resolution <0.01 dB1.6.4 Absolute Accuracy @ 10 dBm +/-0.25 dB1.6.5 Step Attenuator Relative Accuracy1.6.5.1 1 - 100 MHz

+/-((0.15 dB + 0.01 dB/dB change) up to 0.5 dB max.)1.6.5.2 100 - 185 MHz

+/-((0.25 dB + 0.01 dB/dB change) up to 0.75 dB max.)1.6.5.3 185 - 250 MHz

+/-((0.25 dB + 0.03 dB/dB change) up to 1.25 dB max.)1.6.6 Fine Attenuator Accuracy1.6.6.1 1 - 185 MHz +/-0.1 dB1.6.6.2 185 - 250 MHz +/-0.2 dB1.6.7 Output VSWR1.6.7.1 1 - 30 MHz <1.2:1 typical1.6.7.2 30 - 250 MHz <1.3:1 typical

1.7 Harmonic Spurious (2nd through 5th)1.7.1 1 - 185 MHz1.7.1.1 Level = 10 - 16 dBm -65 dBc1.7.1.2 Level = -31 - 10 dBm -70 dBc1.7.2 185 - 250 MHz -30 dBc

1.8 Non Harmonic Spurious1.8.1 1 - 185 MHz -65 dBc1.8.2 185 - 250 MHz -60 dBc

1.9 Programmable DC Baseline1.9.1 Range +/-2.0 V1.9.2 Resolution (12 bits)1.9.3 Accuracy1.9.3.1 Uncalibrated (dccal:off) +/-(5% + 50) mV1.9.3.2 Calibrated (dccal:on) +/-(1% + 6) mV



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1.9.4 Linearity1.9.4.1 Uncalibrated (dccal:off) +/-1%1.9.4.2 Calibrated (dccal:on) +/-0.5%1.9.5 Settling Time for 4.0 V step <2 ms to 1% of

final value

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Specs 44 VHF Measure Module

Notes:

1 All specifications apply at the DIB “blind mate” RF connector.

2 To calculate the incremental error of the IF output when moving fromone input level to another, include a 0.2 dB error for anyinput level change, and 0.05 dB for each dB away from the originalinput level.

For example, the down-converter input power is -5 dBm. It is decreasedby 3 dB. The output will decrease by 3 dB +/-(0.2 + 3*0.05 dB),or 3 dB +/-0.35 dB, from whatever level it was at.

To calculate the total error at the output for any input level,add 0.2 dB and then 0.05 dB for each dB below 10 dBm. For example,the input power is 0 dBm. The output power will be

0 dBm + VHFMM Down-conv. gain +/- (frequency response errors, see note 8)+/-(0.2 dB + (10-0)*0.05 dB)

3 The second harmonic distortion specification of the VHFMM can befound nominally by using the following formula:

Second Harmonic Dist.

< -(Value of 2nd Order Intercept - DUT Output Power + 9.5) dBc

To measure distortion lower than calculated above, add anattenuator on the DIB before the VHFMM input. This lowersthe signal level into the VHFMM. The new formula is

< -(Value of 2nd Order Intercept - (DUT Output Power - atten) + 9.5) dBc

where atten = loss of added attenuator

These formulas are only valid until the spurious and noise floorsare reached. See 4.2.4 below.

4 The third harmonic distortion specification of the VHFMM can befound nominally by using the following formula:

Third Harmonic Dist.

< -((Value of 3rd Order Intercept - DUT Output Power)*2 + 6) dBc


VHF Measure Module

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To measure distortion lower than calculated above, add anattenuator on the DIB before the VHFMM input. This lowersthe signal level into the VHFMM. The new formula is

< -((Value of 3rd Order Intercept - (DUT Output Power - atten))*2 + 6) dBc

where atten = loss of an attenuator

These formulas are only valid until the spurious and noise floorsare reached. See 4.2.4 below.

5 These specifications are useful when an entire spectrum is capturedfrom the IF filter with a digitizer.

6 Signals with two tones can intermodulate in the IF amp as well asat the RF of the mixer. This specification separates out the IFcontribution. IF harmonics included are 2nd through 5th or 900 kHz,whichever is lower.

7 If spurious products interfere with measurement, tune input signalsone at a time to one IF frequency or retune to a new IF frequency.

8 Assuming Pi is the input power to the Down-converter, then Po,expressed below for different circumstances, is the value of theoutput power of the Down-converter including error introduced bythe VHFMM.

Generally:

Po = Pi + Nom. Gain +/- (Flatness + IF flatness + Rel. acc.)

(When IF=500 kHz then IF flatness = 0 dB)

RF freq. is varied between 5 MHz & 250 MHz. IF freq. = 500KHz:

Po = Pi + 2.7+/- (1.5 dB + 0.0 dB + [0.2 dB + 0.05 dB/dB*(10 dBm - Pi)])

RF is constant at 70 MHz. IF frequency is varied between100 kHz & 900 kHz:


RF is constant at 120 MHz. IF frequency is varied between400 kHz & 600 kHz:


Please note that the above expressions do not include all errorcontributions in a source and measure setup. For example, if theHFDIG is being used for measurement, its relevant specificationsmust be included in the above error expressions.


VHF Measure Module

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VHF MEASURE MODULE SPECIFICATIONS

0. Features0.1 Modes Down-converter, Sampler0.2 Connections THADS, MAT A

1. Measurement Frequency1.1 Range 5 MHz to 250 MHz1.2 Resolution 1 Hz1.3 Accuracy see LA302 System Frequency Reference

2. Input Signal2.1 Down-converter Mode2.1.1 Input Amplitude +10 dBm to -75 dBm

+10 dBm to -90 dBm, typical2.1.2 Passband Gain at IF = 500 kHz2.1.2.1 5 MHz to 100 MHz 3.2 dB, nominal2.1.2.2 100 MHz to 250 MHz 2.4 dB, nominal2.1.2.3 5 MHz to 250 MHz 2.7 dB, nominal2.1.3 Amplitude Flatness at +10 dBm2.1.3.1 5 MHz to 100 MHz +/-1.0 dB2.1.3.2 100 MHz to 250 MHz +/-1.4 dB2.1.3.3 5 MHz to 250 MHz +/-1.5 dB

+/-1.0 dB, typical2.1.4 Relative Amplitude Accuracy +/-(0.2 dB + 0.05 dB/dB change) (Note2)2.2 Sampler Mode2.2.1 See High Frequency Sampler specifications.2.3 Input Impedance 50 Ohms nominal2.4 Input VSWR <2:1, typical

3. Spectrum3.1 2nd Order Intercept +50 dBm (Note 3)

+60 dBm, typical3.2 3rd Order Intercept +23 dBm (Note 4)

+30 dBm, typical3.3 LO-IF Leakage <-70 dBm3.4 LO-RF Leakage <-34 dBm3.5 Image Rejection 0 dB

4. IF Output (Note 5)4.1 IF Nominal Center Frequency 500 kHz4.2 IF Passband4.2.1 Frequency Range 100 kHz to 900 kHz4.2.2 IF Flatness4.2.2.1 100 kHz to 900 kHz <+/-1.2 dB4.2.2.2 400 kHz to 600 kHz <+/-0.75 dB4.2.3 IF Distortion <-42 dBc (Note 6)4.2.4 IF Spurious <-50 dBm (Note 7)

for input signals < 2.0 dBm<-56 dBcfor input signals > 2.0 dBm

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spec_565

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