sreejeshvhdl dataflow modeling [compatibility mode]

STTP

STTP OverviewDecember 31, 2012

Sreejeesh S.GSTA,VLSI Design Group

National Institute of Electronics and Information Technology, Calicut

[email protected]

STTP on VHDL| S.S.G VLSI Design Group. NIELIT

We are going to learn...

Today:Dataflow Modeling Behavioral Modeling Structural ModelingTest BenchesTest Benches

STTP on VHDL| S.S.G VLSI Design Group. NIELITSTTP on VHDL| S.S.G VLSI Design Group. NIELITSTTP on VHDL| S.S.G VLSI Design Group. NIELITSTTP on VHDL| S.S.G VLSI Design Group. NIELITSTTP on VHDL| S.S.G VLSI Design Group. NIELITSTTP on VHDL| S.S.G VLSI Design Group. NIELITSTTP on VHDL| S.S.G VLSI Design Group. NIELITSTTP on VHDL| S.S.G VLSI Design Group. NIELIT

HOW CAN YOU DESCRIBE A SYSTEM ??HOW CAN YOU DESCRIBE A SYSTEM ??

It can be done using two basic parts.

Interface- which handles the communication between

environment and the system.

Body which provides the architecture or the functionality of

the system.


What is interface?? What is body ??


VHDL Design Entry VHDL Design Entry VHDL Design Entry VHDL Design Entry

Entity

Entity describes the external view of a design/component

Architecture

Architecture describes the internal behavior/structure of the component behavior/structure of the

component


VHDL Design UnitsVHDL Design Units

Entity Package Primary Design Units Primary Design Units Configuration

Architecture Secondary Design UnitsSecondary Design Units Package body


What is an ENTITY ??What is an ENTITY ??What is an ENTITY ??What is an ENTITY ??

Declares the design name. (Always Provide some

relevant names)

Provides the port information.

Describes the interface of the design entity.

The interface includes all inputs, outputs and bi-

directional signals and generics.

Declarations are visible to all the architectures assigned

to the entity.


Terms in Last Slide..

The name of the entity can be any legal VHDL name.

The square brackets indicate an optional item.

The input and output signals are specified using the

keyword PORT. keyword PORT.

Whether each port is an input, output, or

bidirectional signal is specified by the mode of the

port.


Example

entity fulladder is

port ( -- I/O ports

a: in bit; --input

b: in bit; -- -- inputb: in bit; -- -- input

cin : in bit; -- -- carry input

sum: out bit; -- -- sum output

cout : out bit); -- -- carry output

end fulladder;


ExampleExample


Ports description


Another ExampleAnother ExampleAnother ExampleAnother Example

add4a

b44

Sum4add4b

ci4

co

EntityEntity add4


Entity for add4Entity for add4Entity for add4Entity for add4

Entity add4 isport ( a,b : in bit_vector(3 downto 0);ci : in bit;ci : in bit;

sum : out bit_vector(3 downto 0);co : out bit);

end add4;


ARCHITECTUREARCHITECTUREARCHITECTUREARCHITECTUREARCHITECTUREARCHITECTUREARCHITECTUREARCHITECTURE

An ARCHITECTURE provides the circuit

details for an entity.

It describes the Functionality

Can be done in

Structural

Behavioral

Dataflow

Mixed mode


Example of Full adder RealizationExample of Full adder RealizationExample of Full adder RealizationExample of Full adder RealizationExample of Full adder RealizationExample of Full adder RealizationExample of Full adder RealizationExample of Full adder Realization

library ieee ;use ieee.std_logic_1164.all ;ENTITY fulladd ISPORT ( Cin, x, y : IN STD_LOGIC ;S, Cout : OUT STD_LOGIC ) ;END fulladd ;END fulladd ;ARCHITECTURE LogicFunc OF fulladd ISBEGINs

DataflowHere we describe the system in terms of the flow of data through

the entity ,which is done using concurrent signal assignment

statements.

Concurrent Signal Assignment is done with the Assignment

operator operator

ExampleExampleExampleExample


Example of Data Flow Style---------------------------------------------Entity Declaration--------------------------------------------

entity FULLADDER isport (A,B,Cin: in std_logic ; SUM , Cout: out std_logic);end FULLADDER ;

---------------------------------------------Architecture---------------------------------------architecture vl500 of FULLADDER is

begin begin SUM

ExampleExampleExampleExample

architecture struct of FA issignal x,y,w: bit ;

BeginS

Conditional Signal Assignment Statement

The conditional signal assignment selects differentvalues for the target signal based on the specified ,possibly different conditions.Conditions are checked one by oneOutput is assigned based on the first true conditionEquivalent if elsif else end if in process.


When elseWhen else

A signal is assigned a value based on a condition being TRUE.signal_name

Eg when else

Architecture conditional of tri_state_buf isbeginbuf_out

Mux eg

Architecture mux421_a of mux421 isbegin

o

Lab Exercises Lab Exercises Lab Exercises Lab Exercises

All basic gates.

Two input gates

Three input gates

Some Combinational Circuits

Like Fulladder ,Full Subtractor, Multiplexer etc


Behavioral Style of ModelingBehavioral Style of ModelingBehavioral Style of ModelingBehavioral Style of Modeling

Sreejeesh S.GSreejeesh S.GSreejeesh S.GSreejeesh S.G


ProcessProcess

Here we specify the behavior of the system usingsequential statements in a specified order. A setof sequential statements are specified inside aPROCESS statement which are executedsequentially.


sequentially.Here we dont care about the structure of system,

we only take the behavior into consideration.

Process

Process statement is used for behavior description.

It is set of sequential statements.

Process statements are concurrent.

For a simulation time multiple process statements For a simulation time multiple process statements

can be active.

Process execution starts during initialization phase

in sequence.

Process is self repeating.


Process Statement


Syntax IISyntax IISyntax IISyntax II

Process -- sensitivity list is absent

Declarations

begin

sequential statements;

Wait on some signals;Wait on some signals;

end process;


Process ..


E.g.

In D-flip-flop the output should copy input at either at a positive or negative transition of clock.

Asynchronous reset

If reset =1 then q should be 0 regardless of the condition of clk.condition of clk.


The program will look like this


If statement

An if statement selects a sequence of statements for execution based on the value of a condition.


If statement nested..

IF expression THEN

statement ;

{statement ;}

ELSIF expression THEN

statement ;

{statement ;}{statement ;}

ELSE

statement ;

{statement ;}

END IF ;


Wait statements

Process can be suspended by means of a sensitivity Process can be suspended by means of a sensitivity list .list .

When a process has a sensitivity list, it always When a process has a sensitivity list, it always suspend after executing the last sequential suspend after executing the last sequential statement in the process.statement in the process.statement in the process.statement in the process.

The wait statement provides an alternate way to The wait statement provides an alternate way to suspend the execution of a process.suspend the execution of a process.


Wait Statement

There are basically three types of wait statements

Wait on sensitivity list;

Wait until Boolean-expression;

Wait for time-expression;


Wait for time expression

Causes suspension of the process for a period of time given by the evaluation of time expression.

e.g.

Wait for 10 ns;Wait for 10 ns;

Wait for 200 ns;

etc


Wait on signal

Causes a process to suspend execution until anevent occurs on one or more signals in a group of signals

e.g.

Wait on a , b , c;Wait on a , b , c;

Wait on clock;

etc


Wait until condition( boolean exp);

Causes the process to suspend until the Boolean condition becomes True.

e.g.

Wait until sum>90;

Wait until clk=1;Wait until clk=1;

etc


Wait Statements

They may also be combined in a single wait statement E.g.Wait on clk until (b=20) for 20ns;


Wait on clk until (b=20) for 20ns;

Case statement

The case statement selects one of the branches for execution based on the value of the expression.

General Form :

CASE expression ISCASE expression ISWHEN constant_value => statement ;

WHEN constant_value => statement ;

WHEN OTHERS => statement ;

END CASE ;


Case -Example

Architecture behave of mux is

BeginProcess (a, b, c, d, sel)variable temp :std_logic;Begincase sel is

entity mux is port (a, b, c, d: in std_logic;Sel : in std_logic_vector (0 to 1); case sel is

when 00 =>temp:=a;when 01 =>temp:=b;when 10 =>temp:=c;when 11 =>temp:=d;when others=>temp:=X;

end case;Z

Null Statement

Null is a sequential statementIt does not cause any actionThe execution progress to next statementMostly used in case statements

case sel is

when 00 =>temp:=a;when 00 =>temp:=a;when 01 =>temp:=b;when 10 =>temp:=c;when 11 =>temp:=d;when others =>null;

end case;


Loop statements

VHDL provides two types of loop statements:

1. WHILE-LOOP

2. FOR-LOOP

These statements are used to repeat one or more These statements are used to repeat one or more These statements are used to repeat one or more These statements are used to repeat one or more sequential assignment statements.sequential assignment statements.


Structural Modeling Structural Modeling Structural Modeling Structural Modeling Structural Modeling Structural Modeling Structural Modeling Structural Modeling



FulladderFulladderFulladderFulladder


Example of fulladderExample of fulladderExample of fulladderExample of fulladder

architecture struct of FA issignal x,y,w: bit;

component halfadder isport (a,b:in bit; s,c:out bit);end component;

component orgate isport (a,b:in bit; gateout: out bit);

end component;beginHA: halfadder port map (Ain,Bin,x,y);HA4: halfadder port map (Cin,x,Sum,w);xor2:orgate port map (y,w,Carry);end struct;


Test BenchesTest BenchesTest BenchesTest BenchesTest BenchesTest BenchesTest BenchesTest Benches



Test benches


Example: Test bench for and gate.

library ieee;use ieee. std_logic_1164.all;

entity test_and isend test_and;

architecture test of test_and iscomponent and2port (a,b: in std_logic;

c: out std_logic);end component;

signal m,n,k: std_logic;


E.g.E.g.

Begin

process

beginm

Lab

Behavioral Modeling 4 bit up Counter 4 bit up/down counter using mode control4-1 Mux.J-K Flipflop.J-K Flipflop.Sum of natural numbers upto N (N is input integer).Structural ModelingFulladder using HAs and gates.4 Bit FA using 1 bit FAs4 Bit Counter using JK FFs.T FF using J-K


Any Queries


Thanks

C o n t a c t D e t a i l s

S r e e j e e s h S . G - s r e e @ c a l i c u t . n i e l i t . i n ( 9 4 4 7 7 6 9 7 5 6 )

Y o u m a y c o n t a c t u s f o r a n y t e c h n i c a l h e l p


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