st malo, 13 th april 2002václav vrba, institute of physics, as cr 1 václav vrba institute of...
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St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 1
Václav Vrba
Institute of Physics, AS CR, Prague
Silicon pad sensors for W-Si ECal
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 2
Outline
• Sensor tile outer dimensions
• Pad array design consideration
• Time schedule - towards the first prototype
• Tests outlines
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 3
Sensor tile outer dimensions
Outcome from the meetingat EP:
- 4” high resistivity wafers- tile side: 62.0+0.0 -0.1 mm- scribe line: 100 m- scribe safety zone: 200 m- guard ring width: cca 750 m (cca 1.5 * wafer thickness)
The dead zone width is about 1 mm
Wafer book keeping information
1.0 mm
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 4
Pad array design consideration
Along with the diodes, the technique used for fabrication of bias resistors and coupling capacitors represents an important issue:
a) polysilicon resistors – production of the tile needs about 7-8 masks; can be the source of additional yield reduction.
b) punch through resistors – production of the tile needs about 5 masks; easy to produce – needs to check whether required parameters can be achieved.
c) deposited resistors (amorphous silicon) – achievement of EP;
- needs about 4-5 masks for production of the diodes array; on top of that additional fabrication of resistor and capacitors.
d) ion implantation resistors – not considered here.
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 5
Design consideration: Polysilicon resistors
Bias resistor
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Coupling capacitor
Direct contact on diode – e.g. for testing
Bias lines
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 6
Design consideration: Polysilicon resistors
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 7
Design consideration: Punch through resistors
Coupling capacitor
Direct contact on diode – e.g. for testing
Bias resistor
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Bias lines
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 8
Deposited resistors – before deposition
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 9
Deposited resistors – after deposition
Bias lines
e.g.Wire bonding, Flex cable gluing, etc.
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 10
Design consideration: a partial summary
a) polysilicon resistors:
- should not be a problem to have resistors 10 M;
- capacitors 1-10 nF.
b) punch through resistors:
- resistors to be tested; if acceptable then it is a simple solution;
- capacitors as a).
c) deposited resistors:
- will be considered in the first prototype submission to test the deposition technology of capacitors and resistors
Compatibility of process for variants a), b) and c) on one wafer? To
try all variants separately could be quite costly! Option c) as a
baseline for main sensor tile?
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 11
Design consideration: a partial summary
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 12
Time schedule
• Pre-prototyping using existing masks to evaluate some effects
of:
- high resistive Silicon;
- guard rings, scribe lines, etc.
- #wafers thickness [m]
- 4 SSP Wacker 500
- 3 DSP Topsil 500
- 4 DSP Topsil 300
• Mask design preparation GDS file
• First 10-16 wafers ready for testing
now in process
By end of April 2002
By end of June 2002
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 13
Pre-prototypingActive area cca 0.3 cm2
Active area cca 10 cm2
Wafer diameter: 100 mm
Wafer backside all Al metallized
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 14
Tests outlines
A) Diode testsa) C-V curves: determination of Vfull-depletion; Vop = Vfull-depletion + 50 V.
b) I-V curves:
- Vbreak-down Vop
- Ileak @ Vop < cca 30 nA/cm2
c) Long term stability tests:
- Ileak @ Vop .
Tile should be rejected if:
- Vbreak-down < Vop
- Ileak > I crit (to be defined).
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 15
Electric characterization
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 16
Long term current stability on Tile
x 10sx 10s
timetime
Measured @ 150VMeasured @ 150V
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 17
Tests outlines
B) Bias resistorsa) shorts
b) breaks
c) outside specifications
C) Capacitance couplingsa) shorts
b) breaks
c) outside specifications
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 18
Manual Probestation
St Malo, 13th April 2002 Václav Vrba, Institute of Physics, AS CR 19
Manual Probestation