st9d3ms . ddr3 m integrated module himod

STACKED Technologies Incorporated www.stackedtechnologies.com 1

4.0 Gb, DDR3, 64M x 64 Integrated Module (HiMOD)

June 6, 2015 STDS-ST9D364M64SBG2-AHigh Performance Highly Integrated Memory Module Product

ST9D364M64SBG2

DDR3 SDRAM Integrated Module [HiMOD]:

•VDD=VDDQ=1.5V±0.075V •1.5Vcenter-terminated,push/pullI/O

•Package:16mmx22mmx1.2mm,13x21matrixw/271balls

•Matrixballpitch:1.00mmSpacesavingfootprintThermallyenhanced,Impedancematched,integratedpackagingDifferential,bi-directionaldatastrobe8n-bitprefetcharchitecture 8internalbanks(perword,4wordsintegratedinpackage) Nominalanddynamicon-dietermina-tion(ODT)fordata,strobe,andmasksignals. ProgrammableCAS(READ)latency(CL):7,8,10,and11 CAS(WRITE)latency(CWL):6,7,8,

FEATURES

9,and11 Fixedburstlength(BL)of8andburstchop(BC)of4 SelectableBC4orBL8on-the-fly(OTF) Self/AutoRefreshmodes OperatingTemperatureRange(ambienttemp=TA)

•Commercial:0°Cto70°C •Industrial:-40°Cto85°C •Extended:-40°Cto105°C •Mil-Temp:-55°Cto125°C COREclockingfrequencies:400,533,667,800MHz DataTransferRates:800,1066,1333,1600MbpsWritelevelingMultipurposeregisterOutputDriverCalibration

40%spacesavingswhileprovid-ingasurfacemountfriendlypitch(1.00mm) ReducedI/Orouting(34%) 30%improvementinroutingsforyourmemoryarray Reducedtracelengthsduetothehighlyintegrated,impedancematchedpackaging Thermallyenhancedpackagingtechnologyallowsiliconintegrationwithoutperformancedegradationduetopowerdissipation(heat) HighTCEorganiclaminateinterposerforimprovedglassstabilityoverawideoperatingtemperature SuitabilityofuseinHighReliabilityapplicationsrequiringMil-temp,non-hermeticdeviceoperation

Benefits

*Note: This integrated product and/or its specifications

are subject to change without notice. The latest document

should be retrieved from STACKED Technologies prior to

your design consideration.

Order Number Speed Grade pkG FOOtpriNt i/O pitch pkG NO.

16mmx22mm 271

iMOD Part Information

BG21.00mm

ST9D364M64SBG2x125

ST9D364M64SBG2x15

ST9D364M64SBG2x187

ST9D364M64SBG2x25

DDR3-1600

DDR3-1333

DDR3-1066

DDR3-800

Sample Part Number: ST9D364M64SBG2

Word = 64MB

Speed Grade

2.5ns / 400MHz

1.875ns / 533MHz

1.5ns / 666MHz

25

187

15

125

64MST9D3

Temperature

Industrial (-40oC to 85oC)

Extended (-40oC to 105oC)

Military (-55oC to 125oC)

I

EM

Note: Not all options can be combined. Please see our Part Catalog for available offerings.

64S BG2

DDR3 HiMOD

Wordwidth x64

S = Single Channel

16 x 22mm PBGA

Code

Code

X XXX

Commercial (0oC to 70oC) C

1.25ns / 800MHz


June 6, 2015 STDS-ST9D364M64SBG2-A


ST9D364M64SBG2

High Performance Highly Integrated Memory Module Product

STACKEDTECHNOLOGIES INC

FEATURES

FiGure 1 - himOd part NumberS

Configuration

RefreshCount

ROWAddressing

BackAddressing

ColumnAddressing

[8Megx8banksx16]x4

8K

8K(A[12:0])

8(BA[2:0])

1K(A[9:0])

Parameter 64 Meg x 64

table 1: addreSSiNG

STACKED Technologies Incorporated www.stackedtechnologies.com3


ST9D364M64SBG2

June 6, 2015 STDS-ST9D364M64SBG2-AHigh Performance, Highly Integrated Memory Module Product


List of Figures

Figure1:DDR3PartNumbers 2Figure2:SimplifiedStateDiagram 8Figure3:FunctionalBlockDiagram 10Figure4:SDRAM-DDR3PinoutTopView 11Figure5:MechanicalDrawing 15Figure6:InputSignal 31Figure7:OvershootSpecifications 32Figure8:UndershootSpecifications 32Figure9:VIXforDifferentialSignals 34Figure10:Single-EndedRequirementsforDifferentialSignals 34Figure11:DefinitionofDifferentialAC-SwingandtDVAC 35Figure12:NominalSlewRateDefinitionforSingle-EndedInputSignals 37Figure13:NominalDifferentialInputSlewRateDefinitionforDQS,DQS#andCK,CK# 38Figure14:ODTLevelsandI-VCharacteristics 39Figure15:ODTTimingReferenceLoad 41Figure16:tAON and tAOFDefinitions 42Figure17:tAONPDandtAOFPDDefinition 43Figure 18: tADCDefinition 43Figure19:OutputDriver 44Figure20:DQOutputSignal 49Figure21:DifferentialOutputSignal 50Figure22:ReferenceOutputLoadforACTimingandOutputSlewRate 50Figure23:NominalSlewRateDefinitionforSingle-EndedOutputSignals 51Figure24:NominalDifferentialOutputSlewRateDefinitionforDQS,DQS# 52Figure25:NominalSlewRateandtVACfortIS(CommandandAddress-Clock) 64Figure26:NominalSlewRatefortIH(CommandandAddress-Clock) 65Figure27:TangentLinefortIS(CommandandAddress-Clock) 66Figure28:TangentLinefortIH(CommandandAddress-Clock) 67Figure29:NominalSlewRateandtVACfortDS(DQ-Strobe) 70Figure30:NominalSlewRatefortDH(DQ-Strobe) 71Figure31:NominalSlewRateandtVACfortDS(DQ-Strobe) 72Figure32:NominalSlewRatefortDH(DQ-Strobe) 73Figure33:RefreshMode 77Figure34:DLLEnableModetoDLLDisableMode 79Figure35:DLLDisableModetoDLLEnableMode 80Figure36:DLLDisabletDQSCKTiming 81Figure37:ChangeFrequencyDuringPrechargePower-Down 82Figure38:WriteLevelingConcept 83Figure39:WriteLevelingSequence 85Figure40:ExitWriteLeveling 86Figure41:InitializationSequence 88Figure42:MRS-to-MRSCommandTiming(tMRD) 89Figure43:MRS-to-nonMRSCommandTiming(tMOD) 90Figure44:ModeRegister0(MR0)Definitions 91Figure45:READLatency 93Figure46:ModeRegister1(MR1)Definition 94Figure47:READLatency(AL=5,CL=6) 96Figure48:ModeRegister2(MR2)Definition 97



ST9D364M64SBG2



Figure49:CASWriteLatency 98Figure50:ModeRegister3(MR3)Definition 99Figure51:MultipurposeRegister(MPR)BlockDiagram 103Figure52:MPRSystemReadCalibrationwithBL8-FixedBurstOrderSingleReadout 103Figure53:MPRSystemReadCalibrationwithBL8-FixedBurstOrder,Back-to-BackReadout 104Figure54:MPRSystemReadCalibrationwithBC4-LowerNibble,thenUpperNibble 105Figure55:MPRSystemReadCalibrationwithBC4-UpperNibble,thenLowerNibble 106Figure56:ZQCalibrationTiming(ZQCLandZQCS) 108Figure57:Example-MeetingtRRD(MIN)andtRCD(MIN) 109Figure58:Example-tFAW 109Figure59:READLatency 110Figure60:ConsecutiveREADBursts(BL8) 111Figure61:ConsecutiveREADBursts(BC4) 112Figure62:NonconsecutiveREADBursts 113Figure63:READ(BL8)toWRITE(BL8) 114Figure64:READ(BC4)toWRITE(BC4)OTF 115Figure65:READtoPRECHARGE(BL8) 116Figure66:READtoPRECHARGE(BC4) 117Figure67:READtoPRECHARGE(AL=5,CL=6) 118Figure68:READwithAutoPrecharge(AL=4,CL=6) 119Figure69:DataOutputTiming-tDQSQandDataValidWindow 121Figure70:DataStrobeTiming-READs 123Figure71:MethodforCalculatingtLZandtHZ 124Figure72:tRPRETiming 125Figure73:tRPSTTiming 125Figure74:tWPRETiming 126Figure75:tWPSTTiming 126Figure76:WriteBurst 128Figure77:ConsecutiveWRITE(BL8)toWRITE(BL8) 129Figure78:ConsecutiveWRITE(BC4)viaMRSorOTF 129Figure79:NonconsecutiveWRITEtoWRITE 130Figure80:WRITE(BL8)toREAD(BL8) 130Figure81:WRITEtoREAD(BC4ModeRegisterSetting) 131Figure82:WRITE(BC4OTF)toREAD(BC4OTF) 132Figure83:WRITE(BL8)toPRECHARGE 133Figure84:WRITE(BC4ModeRegisterSetting)toPRECHARGE 133Figure85:WRITE(BC4OTF)toPRECHARGE 134Figure86:DataInputTiming 134Figure87:SelfRefreshEntry/ExitTiming 136Figure88:ActivePower-DownEntryandExit 139Figure89:PrechargePower-Down(Fast-ExitMode)EntryandExit 139Figure90:PrechargePower-Down(Slow-ExitMode)EntryandExit 140Figure91:Power-DownEntryAfterREADorREADwithAutoPrecharge(RDAP) 140Figure92:Power-DownEntryAfterWRITE 141Figure93:Power-DownEntryAfterWRITEwithAutoPrecharge(WRAP) 141Figure94:REFRESHtoPower-DownEntry 142Figure95:ACTIVATEtoPower-DownEntry 142Figure96:PRECHARGEtoPower-DownEntry 143Figure97:MRSCommandtoPower-DownEntry 143Figure98:Power-DownExittoRefreshtoPower-DownEntry 144



ST9D364M64SBG2



Figure99:RESETSequence 145Figure100:On-DieTermination 146Figure101:DynamicODT-ODTAssertedBeforeandAftertheWRITE,BC4 149Figure102:DynamicODT-WithoutWRITECommand 149Figure103:DynamicODT-ODTPinAssertedTogetherwithWRITECommandfor6ClockCycles,BL8 150Figure104:DynamicODT-ODTPinAssertedwithWRITECommandfor6ClockCycles,BC4 150Figure105:DynamicODT-ODTPinAssertedwithWRITECommandfor4Clockcycles,BC4 151Figure106:SynchronousODT 152Figure107:SynchronousODT(BC4) 153Figure108:ODTDuringREADs 153Figure109:AsynchronousODTtimingwithFastODTTransition 154Figure110:SynchronoustoAsynchronousTransitionDuringPrechargePower-Down(DLLOff)Entry 155Figure111:AsynchronoustoSynchronousTransitionDuringPrechargePower-Down(DLLOff)Exit 157Figure112:TransitionPeriodforShortCKELOWCycleswithEntryandExitPeriodOverlapping 158Figure113:TransitionPeriodforShortCKEHIGHCycleswithEntryandExitPeriodOverlapping 158



ST9D364M64SBG2



List of Tables

Table1:Addressing 2Table2:Ball/SignalLocationandDescription 12Table3:AbsoluteMaximumRatings 16Table4:Input/OutputCapacitance 16Table5:TimingParametersforIDDMeasurements-ClockUnits 17Table6:IDD0MeasurementLoop 18Table7:IDD1MeasurementLoop 19Table8:IDDMeasurementConditionsforPower-DownCurrents 20Table9:IDD2N/IDD3NMeasurementLoop 21Table10:IDD2NTMeasurementLoop 22Table11:IDD4RMeasurementLoop 23Table12:IDD4WMeasurementLoop 24Table13:IDD5BMeasurementLoop 25Table14:IDDMeasurementLoop 26Table15:IDD7MeasurementLoop 27Table16:IDDMaximumLimits 28Table17:DCElectricalCharacteristicsandOperatingConditions 29Table18:DCElectricalCharacteristicsandInputConditions 29Table19:InputSwitchingConditions 30Table20:ControlandAddressPins 32Table21:Clock,Data,Strobe,andMaskPins 32Table22:DifferentialInputOperatingConditions(CKx,CKx\,DQSx,andDQSx\) 33Table23:DifferentialInputOperatingConditions(tDVAC)forCKx,CKx\,DQSx,andDQSx\ 35Table24:Single-EndedInputSlewRate 36Table25:DifferentialInputSlewRateDefinition 38Table26:On-DieTerminationDCElectricalCharacteristics 39Table27:RTTEffectiveImpedances 40Table28:ODTSensitivityDefinition 41Table29:ODTTemperature&VoltageSensitivity 41Table30:ODTTimingDefinitions 42Table31:ReferenceSettingsforODTTimingMeasurements 42Table32:34ΩDriverImpedanceCharacteristics 44Table33:34ΩDriverPull-UpandPull-DownImpedanceCalculations 45Table34:34ΩDriverIOH/IOLCharacteristics-VDD=VDDQ=1.5V 45Table35:34ΩDriverIOH/IOLCharacteristics-VDD=VDDQ=1.575V 45Table36:34ΩDriverIOH/IOLCharacteristics-VDD=VDDQ=1.425V 46Table37:34ΩOutputDriverSensitivityDefinition 46Table38:34ΩOutputDriverVoltageandTemperatureSensitivity 46Table39:40ΩDriverImpedanceCharacteristics 47Table40:40ΩOutputDriverSensitivityDefinition 47Table41:40ΩOutputDriverVoltageandTemperatureSensitivity 48Table42:Single-EndedOutputDriverCharacteristics 48Table43:DifferentialOutputDriverCharacteristics 49Table44:Single-EndedOutputSlewRate 51Table45:DifferentialOutputSlewrateDefinition 52Table46:SpeedBins 53Table47:ElectricalCharacteristicsandACOperatingConditions 54Table48:CommandandAddressSetupandHoldValuesReferencedat1V/ns-AC/DCBased 62



ST9D364M64SBG2



Table49:DeratingValuesfortIS/tIH-AC175/DC100-Based 62Table50:DeratingValuesfortIS/tIH-AC150/DC100-Based 63Table51:MinimumRequiredTimetVACaboveVIH(AC)foraValidTransition 63Table52:DataSetupandHoldValuesat1V/ns(DQSx,DQSx\at2V/ns)-AC/DCbased 68Table53:DeratingValuefortDS/tDH-AC175/DC100-Based 68Table54:DeratingValuefortDS/tDH-AC150/DC100-Based 69Table55:RequiredTimetVACAboveVIH(AC)(BelowVIL[AC])ForaValidTransition 69Table56:TruthTable-Command 74Table57:TruthTable-CKE 75Table58:ReadCommandSummary 76Table59:WriteCommandSummary 76Table60:BurstOrder 92Table61:BurstOrder 101Table62:BurstOrder 102Table63:SELFREFRESHTemperatureandAUTOSELFREFRESHDescription 137Table64:SELFREFRESHModeSummary 137Table65:COMMANDtoPOWER-DOWNEntryParameters 138Table66:POWER-DOWNModes 138Table67:POWER-DOWNModes 146Table68:ODTParameter 147Table69:DynamicODTSpecificParameters 148Table70:MODEREGISTERSforRTT_NOM 148Table71:MODEREGISTERSforRTT-WR 148Table72:TIMINGDIAGRAMSforDYNAMICODT 148Table73:SYNCHRONOUSODTParameters 152Table74:ASYNCHRONOUSODTtimingParametersforAllSpeedBins 154Table75:ODTParametersforPOWER-DOWN(DLLOff)EntryandExitTransitionPeriod 155

BankActive

ReadingWriting

Activating

Refreshing

Selfrefresh

Idle

ActivePower-Down

ZQCalibration

From anystate

Powerapplied

ResetProcedure

Poweron

InitializationMRS, MPR,

writeleveling

PrehargePower-Down

Writing

AutomaticSequence

CommandSequence

Preharging

READ

READ READ

READ AP

READ AP

READ AP

PRE, PREA

PRE, PREA PRE, PREA

WRITE

WRITE

CKE L CKE L

CKE L

WRITE

WRITE AP

WRITE AP

WRITE AP

PDE

PDE

PDX

PDX

SRX

SRE

REF

MRS

ACT

RESET

ZQCL

ZQCL/ZQCS

Reading

ACT = ACTIVATE PREA=PRECHARGE ALL SRX = Self refresh exitMPR = Multipurpose register READ = RD, RDS4, RDS8 WRITE = WR, WRS4, WRS8MRS = Mode register set READ AP = RDAP, RDAPS4, RDAPS8 WRITE AP = WRAP, WRAPS4, WRAPS8PDE = Power-down entry REF = REFRESH ZQCL = ZQ LONG CALIBRATIONPDX = Power-down exit RESET = START RESET PROCEDURE ZQCS = ZQ SHORT CALIBRATIONPRE = PRECHARGE SRE = Self refresh entry



ST9D364M64SBG2



STATE DIAGRAM

FiGure 2 - SimpliFied State diaGram




ST9D364M64SBG2



ThisDDR3SDRAMModuleusesdoubledataratearchitecturetoachievehighspeedoperation.Thedoubledatarate(DDR)architectureisan8nprefetchwithaninterfacedesignedtotransfertwodatawordsperclockcycleattheI/Opins.AsingleREADorWRITEaccessfortheDRAMconsistsofasingle8n-bit-wide,one-clock-cycledatatransferattheinternalmemorycoreandeightcorre-spondingn-bit-wide,one-half-clock-cycledatatransferattheI/Opin.

The differential strobes (DQSx,DQSx\) are transmitted externally, alongwithdata,foruseindatacaptureattheDRAMinputreceiver.DQSiscen-ter-alignedwithdata forWRITEs. TheREADdata is transmittedby theDRAMandedge-alignedtothedatastrobes.

TheDRAMoperates fromadifferentialclock (CKx,CKx\). ThecrossingofCKgoingHIGHandCK\goingLOWisreferredtoasthepositiveedgeofClock(CK).Control,Command,andAddresssignalsareregisteredateverypositiveedgeofCK.InputdataisregisteredonthefirstrisingedgeofDQSaftertheWRITEpreamble,andoutputdataisreferencedonthefirstrisingedgeofDQSaftertheREADpreamble.

READandWRITEaccessesto theDRAMareburst-oriented. Accessesstartataselectedlocationandcontinueforaprogrammednumberofloca-tions in a programmed sequence. Accesses beginwith the registrationofanACTIVATEcommand,whichisthenfollowedbyaREADorWRITEcommand.TheaddressbitsregisteredcoincidentwiththeACTIVATEcom-mandareusedtoselectthebankandthestartingcolumnlocationfortheburstaccess.

DRAM devices use READ andWRITE BL8 and BC4. An AUTOPRE-CHARGE function may be enabled to provide a self-timed ROW PRE-CHARGEthatisinitiatedattheendoftheburstaccess.

AswithstandardDRAMdevices,thepipelined,multi-bankarchitectureoftheDRAMallows for concurrentoperation, therebyprovidinghighband-widthbyhidingROWPRECHARGEandACTIVATIONtime.

ASELFREFRESHmode isprovided forall temperaturegradeofferingsalongwithAUTOSELFREFRESHforIndustrialproduct,aswellas,power-saving,POWER-DOWNmode.

FUNCTIONAL DESCRIPTION iNduStrial temperature

The industrial temperature (I) device requires the ambient temperaturenotexceed-40°Cor+85°C.JEDECspecificationsrequiretheREFRESHratetodoublewhenTAexceeds+85°C;thisalsorequiresuseofthehigh-temperatureSELFREFRESHoption. Additionally,ODTresistanceandthe INPUT/OUTPUT impedancemustbederatedwhen theTA is<0°Cor>+85°C.

exteNded temperature

TheExtendedtemperature(E)devicerequirestheambienttemperaturenotexceed-40°Cor+105°C.JEDECspecificationsrequiretherefreshratetodoublewhenTAexceeds+85°C;thisalsorequiresuseofthehigh-temperatureSELFREFRESHoption. Additionally,ODTresistanceandthe INPUT/OUTPUT impedancemustbederatedwhen theTA is<0°Cor >85°C.

military, extreme OperatiNG temperature

TheMil-Temp (M)device requires theambient temperaturenotexceed-55°Cor+125°C.JEDECrequirestheREFRESHratedoublewhenTA exceeds +85°C and STACKED recommends an additional derating asspecified in thisdocumentas toproperlymaintain theDRAMcorecellchargeattemperaturesaboveTA>105°C.

D0

RST\ VSS VSSQ VDD VDDQ WE\ CKE CAS\ RAS\ CS\

A0-A12, BA0-2A, BA

CK0

CK0\

DM0

DM1

DQ 0•••

DQ 7DQ 8•••

DQ 15

DQ 0•••

DQ 7DQ 8•••

DQ 15

A, BA

D1

DQ 0•••

DQ 7DQ 8•••

DQ 15

DQ 16•••

DQ 23DQ 24

•••

DQ 31

A, BA

D2

DQ 0•••

DQ 7DQ 8•••

DQ 15

DQ 32•••

DQ 39DQ 40

•••

DQ 47

A, BA

D3

DQ 0•••

DQ 7DQ 8•••

DQ 15

DQ 48•••

DQ 55DQ 56

•••

DQ 63

CK1

CK1\

DM2

DM3

CK2

CK2\

DM4

DM5

CK3

CK3\

DM6

DM7

CS\

RAS\

CAS\

CKE

WE\

VDDQ

VDD

VSSQ

VSS

RESET\




DQS0, DQS0#

DQS1, DQS1#

DQS0, DQS0#

DQS1, DQS1#

DQS2, DQS2#

DQS3, DQS3#

DQS2, DQS2#

DQS3, DQS3#

DQS4, DQS4#

DQS5, DQS5#

DQS4, DQS4#

DQS5, DQS5#

DQS6, DQS6#

DQS7, DQS7#

DQS6, DQS6#

DQS7, DQS7#




ST9D364M64SBG2



FiGure 3 - FuNctiONal blOck diaGram

VrefDA

VrefCAVss

RFU

BA2 RFU

DM2

CK2

VssQ

VssQ

VssQ

DQ2

DQ1 DQ4 DQ20

DQ30 DQ14 DQ9 DQ12

DQ62

DQ59

BA1

A7

A3 A12 RFU

A1

BA0 A5

VssQ

VssQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDD

VDD

VDDDL

VDD

VDDVDD

VDD

VDD

VDD

VDD

VDD

VDDVDD

Vss

Vss

Vss

Vss

Vss

Vss

VssDL

Vss

Vss

Vss

Vss

Vss

VDDQ VDDQVss

Vss

Vss

Vss

A8

Vss

Vss

Vss

Vss

VDDQ

Vss

Vss

1 2 3 4 5 6 7 8 9 10 11 12 13

A VssQ VDDQ VDDQ Vss Vss VssQ Vss Vss VDDQ A

B VssQ VDD Vss B

C VssVssVssVssVDDQ C

D D

E DQ35 DQ51 E

F DQ36 F

G DM6 DM4 G

H DQ38 DQ54 H

J DM7 DQ44 J

K K

L L

M M

N

ZQ3 ZQ2

N

P DQ13 DQ29 DQ8 P

R DQS0\ DQ10 DQ26 DQ23 R

T DQ0 DQ16 T

1 2 3 4 5 6 7 8 9 10 11 12 13

AddressUNPOPULATED

Level REF

V + (I/O Power) CNTRL

GND (Core)

Data IO

VDDQ

VDD

VDDQ

Vss

Vss

Vss

VDDQ

Vss

VDDQ

VDDQ

VssQ

VssQ VssQ

Vss

VDD

Vss

U

V

W

Y

AA

U

V

W

Y

AA

VssQ

Vss

DQ52

VDD

Vss

VDD

DQS3\

DQS2\

CK0

Vss

Vss

A6 A10 A9

A0 A11

A2 A4

VDD

DQS3 DQS1

CK0\

CK1\

Vss

VDD

VDDQ

VDD

DQS2

DQ5

CK1

Vss

Vss

VDDQ

VDD

DQ33

DQ49

DQ60

DQ41

Vss

RESET\

DQ43

DQ57

DQ46

ZQ0 ZQ1

DQ15

DQ24 DQ31

DQS1\

Vss Vss Vss

Vss Vss Vss Vss Vss

Vss Vss Vss Vss

VssVss

Vss Vss Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

VssVss

Vss

Vss

Vss

VDD VDD

VDD

VDD

VDD

VDD

VssQ VssQ

DQ63

DQ55

DQ39

DQ50

DQ34

DQ53

DQ58

DQ56

DQ47

DQ42

DQ40 DQ61 DQ45

DQ48 DQ32

DQ25 DQ28 DQ22 DQ6

DQ27 DQ11 DQ17

DQ19 DQ3

DQ7

DQ21 DQ18

DQ37

VssQ

CK3 CK3\

CK2\

DQS4 DQS6

DQS4\

DQS5\ DQS5 DQS7

DM1

ODT

DQS0

RAS\ CAS\

CS\

CKE WE\

DM5

DQS6\

DQS7\

DM3

DM0

GND (I/O)

V + (Core Power)

271BGA-1.00MM PITCH - X64, SCB

VSSDL VDDDL




ST9D364M64SBG2



FiGure 4 - Sdram - ddr3 piNOut tOp View

BALL /SIGNAL LOCATION (PBGA)




ST9D364M64SBG2



table 2 - ball/SiGNal lOcatiON aNd deScriptiON

Ball Assignments Symbol Type Description

L3,L10,M3,K9,M4,

M10,K3,M11,M5,K5,

K4,L4,K10

M9,L11,F6

K11,G7,F7

U2,U3,V4,V3,E12,

E11,D10,D11

U9

W6

R11,P8,R12,N12,

G3,H6,G2,

J2

V6

V7

U10

A0, A1, A2,

A3, A4, A5,

A6, A7, A8,

A9, A10 /AP,

A11, A12 /BC

BA0, BA1,

BA2

RFU

CKX, CKX\

CKE

CS\

DMx

RAS\

CAS\

WE\

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Address Inputs: ProvidetheROWaddressforACTIVATEcommands,andthecolumnaddress

andautoprechargebit(A10)forREADY/WRITEcommands,toselectonelocationoutofthe

memoryarrayintherespectivebank.A10sampledduringaPRECHARGEcommanddetermines

whetherthePRECHARGEappliestoonebank(A10LOW),bankselectedbyBA[2:0]orallbanks

(A10HIGH).Theaddressinputsalsoprovidetheop-codeduringaLOADMODEcommand.

AddressinputsarereferencedtoVrefCA.A12/BC#:whenenabledinthemoderegister(MR),A12

issampledduringREADandWRITEcommandstodeterminewhetherburstchop,LOW=BC4

burstchop).

Bank Address Inputs: BA[2:0]definethebanktowhichanACTIVATE,READ,WRITE,or

PRECHARGEcommandisbeingapplied.BA[2:0]definewhichmoderegister(MR0,MR1,MR2,or

MR3)isloadedduringtheLOADMODEcommand.BA[2:0]arereferencedtoVrefCA.

FutureAddress:A13,A14,A15

Clock: CKxandCKx\aredifferentialclockinputs,onedifferentialpairperWORD,fourWORDs

containedintheL9D3xxG64product.Allcontrolandaddressinputsignalsaresampledonthe

crossingofthepositiveedgeofCKxandthenegativeedgeofCKx\.Outputdatastrobes(UDQSx/

UDQSx\andLDQSx/LDQSx\)isreferencedtothecrossingofCKxandCKx\.

Clock Enable: CKEenablesanddisablesinternalcircuitryandclocksontheSDRAM.The

specificcircuitrythatisenabled/disabledisdependentupontheDDR3SDRAMconfigurationand

operatingmode.TakingCKELOWprovidesPRECHARGEpower-downandSELFREFRESH

operations(allbanksidle),oractivepower-down(rowactiveinanybank).CKEissynchronous

forpower-downentryandexitandforselfrefreshentry.CKEisasynchronousforselfrefresh

exit.Inputbuffers(excludingCKx,CKx\,CKE,RESET#,andODT)aredisabledduringSELF

REFRESH.CKEisreferencedtoVrefCA.

Chip Select: CS\enables(registeredLOW)anddisablesthecommanddecoder.Allcommands

aremaskedwhenCS\isregisteredHIGH.CS\providesforexternalrankselectiononsystemswith

multiple ranks.CS\isconsideredpartofthecommandcode.CS\isreferencedtoVrefCA.

Input Data Mask: DMxisthebytewidedatamaskfortherespective8-bitdatafields.Thedata

maskinput,masksWRITEdata.BytedataismaskedwhenDMxissampledHIGH.DMxpinsare

structuredasinputsonly,thepinselectricalloadingisdesignedtomatchthatoftheDQ,DQSx,

DQSx#pins.

ROW Address Strobe/Select: DefinesthecommandbeingenteredalongCAS\,WE\,andCS\.

ThisinputpinisreferencedtoVrefCA.

COLUMN Address Strobe/Select: DefinesthecommandbeingenteredalongwithRAS\,WE\,

andCS\.ThisinputpinisreferencedtoVrefCA.

WRITE Enable Input: DefinesthecommandbeingenteredalongwithCAS\,RAS\,,andCS\.This

inputpinisreferencedtoVrefCA.



ST9D364M64SBG2



table 2 - ball/SiGNal lOcatiON aNd deScriptiON cONtiNued


R7

F5

T5,R3,T4,R2,F9,G11,

F10,G12

N4,N6,N3,N2,J10,J8,

J11,J12

T2,T10,V5,U12,T11,

U4,P12,T6

P4,N10,R4,R9,N11,

P2,N9,N5

T3,R10,U6,U11,T12,

U5,P11,R6

P5,P9,R5,R8,P10,P3,

N8,P6

F12,F4,D9,E2,F3,

E10,H2,F8

H10,J4,G10,G5,J3,

H12,J5,J9

ODT

RESET\

DQS0-7,

DQS0-7\

DQ0, DQ1,

DQ2, DQ3,

DQ4, DQ5,

DQ6, DQ7

DQ8, DQ9,

DQ10, DQ11,

DQ12, DQ13,

DQ14, DQ15

DQ16, DQ17,

DQ18, DQ19,

DQ20, DQ21,

DQ22, DQ23

DQ24, DQ25,

DQ26, DQ27,

DQ28, DQ29,

DQ30, DQ31

DQ32, DQ33,

DQ34, DQ35,

DQ36, DQ37,

DQ38, DQ39

DQ40, DQ41,

DQ42, DQ43,

DQ44, DQ45,

DQ46, DQ47

Input

Input

Input

I/O

I/O

I/O

I/O

I/O

I/O

On-Die Termination: ODTenables(whenregisteredHIGH)anddisablesterminationresistance

internaltotheDDR3SDRAM.Whenenabledinnormaloperation,ODTisonlyappliedtoeachof

thefollowingsignals:DQ[63:0],LDQXx\,UDQSx\,UDMx,andLDMx.TheODTinputisignoredif

disabledviatheLOADMODEregistercommand.ODTisreferencedtoVrefCA.

RESET: Aninputcontrolpin,activeLOWreferencedtoVss.TheRESET\inputreceiverisa

CMOSinputdefinedasarailtorailsignalwithDCHIGH≥0.8xVDDandDCLOW≤0.2xVDDQ.

RESET\assertionandde-assertionareasynchronous.

Data Strobe, Byte (per WORD): Output,edge-alignedwithREADdata.Input,center-alignedwith

WRITEdata.

Data Input/Output: LOWByte,LOWWORD(WORD1).PinreferencedtoVrefDQ.

Data Input/Output: HIGHByte,LOWWORD(WORD1).PinreferencedtoVrefDQ.

Data Input/Output: LOWByte,WORD2.PinreferencedtoVrefDQ.

Data Input/Output: HIGHByte,WORD2.PinreferencedtoVrefDQ.

Data Input/Output: LOWByte,WORD3.PinreferencedtoVrefDQ.

Data Input/Output: HIGHByte,WORD3.PinreferencedtoVrefDQ.



ST9D364M64SBG2



F11,G4,E8,E3,F2,E9,

H3,G8

H9,H5,G9,G6,H4,

H11,J6,H8

B3,B5,B6,B8,B9,B11,

C2,C12,J7,K2,K6,K8,

K12,L5,L9,M2,M6,M8,

N7,W2,W12,Y3,Y5,

Y6,Y8,Y9,Y11,B2

A3,A4,A10,A11,C1,

C13,D1,D13,K1,K13,

M1,M13,V13,W1,W13,

AA3,AA4,AA10,AA11

B4,B7,B10,C3,C11,

D2,D12,H7,K7,L2,L6,

L8,M7,P7,V2,V12,

W3,W11,Y2,Y4,Y7,

Y10,Y12,B12,A5,A6,

A8,A9,C4,C7,C8,C9,

C10,D3,D4,D7,D8,E1,

E4,E5,E13,F1,F13,

G1,G13,H1,H13,J1,

J13,N1,N13,P1,P13,

R1,R13,T1,T7,T8,T9,

T13,U1,U7,U8,U13,

V8,V9,V10,V11,W4,

W5,W7,W8,W9,W10,

AA5,AA6,AA8,AA9,E6

A2,A7,A12,A13,B1,

B13,L1,L13,Y1,Y13,

AA1,AA2,AA7,AA12,

AA13

L12

M12

E7

L7

C5,C6,D5,D6

A1,B2

table 2 - ball/SiGNal lOcatiON aNd deScriptiON cONtiNued


DQ48, DQ49,

DQ50, DQ51,

DQ52, DQ53,

DQ54, DQ55

DQ56, DQ57,

DQ58, DQ59,

DQ60, DQ61,

DQ62, DQ63

VDD

VDDQ

Vss

VssQ

VSSDL

VDDDL

VrefCA

VrefDQ

ZQx

UNPOPULATED

Supply

Supply

Supply

Supply

Supply

Supply

Supply

Supply

Ref.

Data Input/Output: LOWByte,HIGHWORD(WORD4).PinreferencedtoVrefDQ.

Data Input/Output: HIGHByte,HIGHWORD(WORD4).PinreferencedtoVrefDQ.

PowerSupply:1.5V±0.075V

DataI/OSupply:1.5V±0.075V

Ground

DataI/OGround:IsolatedfromCoreforimprovednoiseimmunity

GroundforDLL

SupplyforDLL

VoltageReferenceCORE:VrefCAmustbemaintainedatalltimes

VoltageReferenceI/O:VrefDQmustbemaintainedatalltimes.

ExternalReferenceforoutputdrivecalibration

Unpopulated,un-platedmatrixlocation(s)

1.00NOM1.00NOM

12.00NOM

0.6±0.1

Note:Alldimensionsinmm

1.2MAX

20.00 NOM

Ø 271x0.75NOM13121110987654321

A BCDEFGHJKLMNPRTUVWYAA

22.00±0.10

16.00±0.10



ST9D364M64SBG2



FiGure 5 - mechaNical drawiNG

PackaGe OutliNe dimeNSiONS



ST9D364M64SBG2



NOTES:

1.VDDandVDDQmustbewithin300mVofeachotheratalltimesandVREFmustnotbegreaterthan0.6xVDDQ.WhenVDD and VDDQarelessthan500MV,VREFmaybe≤300mV.

2.Maxoperatingambienttemperature.TAismeasuredinthecenterofthepackage.

3.DeviceFunctionalityisnotguaranteediftheDRAMdeviceexceedstheMaximumTAduringoperation.

NOTES:

1.VDD=+1.5V±0.075mV,VDDQ=VDD,VREF=Vss,f=100MHz,TA=25°C,VOUT(DC)=0.5xVDDQ,VOUT (peaktopeak)=0.1V

2.DMinputisgroupedwithI/Opins,reflectingthesignalisgroupedwithDQandthereforematchedinloading.

3.ExcludesCK,CK\

Capacitance Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES

CKandCK\

Single-endI/O:DQ,DM

DifferentialI/O:DQS,DQS\

Inputs(RAS\,CAS\,WE\,CS\,CKE,RESET\,ADDR,/BA0-2)

table 4: iNput/Output capacitaNce

CCK

CI0

CI0

CI_Shared

0.8

1.5

1.5

3.0

1.6

3.0

3.0

5.6

1.6

3.0

3.0

5.6

0.8

1.5

1.5

3.0

1.6

2.5

2.5

5.6

pF

pF

pF

pF

2

0.8

1.5

1.5

3.0

Symbol Parameter MIN MAX UNITS NOTES VDD

VDDQ

VIN,VOUT

TAIndustrial

TAExtended

TAMiltemp

TSTG

V

V

V

°C

°C

°C

°C

1

1

1

2,3

2,3

3

2,3

table 3: abSOlute maximum ratiNGS

1.975

1.975

1.975

85

105

125

120

-0.4

-0.4

-0.4

-40

-40

-55

-55

VDDSupplyVoltagerelativetoVss

VDDSupplyVoltagerelativetoVssQ

VoltageonanypinrelativetoVss

OperatingAmbientTemperature

OperatingAmbientTemperature

OperatingCaseTemperature

StorageTemperature

0.8

1.5

1.5

3.0

1.6

2.5

2.5

5.6

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600



ST9D364M64SBG2



tCK(MIN)IDD

CLIDD

tRCD(MIN)IDD

tRC(MIN)IDD

tRAS(MIN)IDD

tRP(MIN)IDD

tFAW

tRRD IDD

tRFC

IDD Parameter 7-7-7 8-8-8 10-10-10 11-11-11

table 5: timiNG parameterS FOr idd meaSuremeNtS - clOck uNitS

ns

CK

CK

CK

CK

CK

CK

CK

CK

1.5

10

10

34

24

10

30

5

74

1.875

8

8

28

20

8

27

6

59

DDR3-800

-25

DDR3-1066

-19

DDR3-1333

-15

x64

x64

64Mx16(4X)

2.5

7

21

15

6

20

4

44

DDR3-1600

-12

1.25

11

11

39

28

11

32

6

90

CK, CK\

CKE

Sub-Loop

CS\

RAS\

CAS\

WE\

ODT

BA [2:0]

A [15:11]

A [10]

A [9:7]

A [6:3]

A [2:0]0

01

10

00

00

00

10

00

00

00

00

01

00

00

00

00

00

11

11

00

00

00

01

11

10

00

00

00

00

10

00

00

00

0

00

11

00

00

0F

01

00

00

00

00

F0

10

00

00

00

0F

01

11

10

00

00

F0

11

11

00

00

0F

0

00

10

00

00

0F

0

1 2 3 4 5 6 7R

epea

t sub

-loop

0, u

se B

A [2

:0] =

6R

epea

t sub

-loop

0, u

se B

A [2

:0] =

7

-- - - - - - -

Rep

eat c

ycle

s n

RC

+1

thro

ugh n

RC

+4

until

2 x

RC

- 1,

trun

cate

if n

eede

dR

epea

t sub

-loop

0, u

se B

A [2

:0] =

1R

epea

t sub

-loop

0, u

se B

A [2

:0] =

2R

epea

t sub

-loop

0, u

se B

A [2

:0] =

3R

epea

t sub

-loop

0, u

se B

A [2

:0] =

4R

epea

t sub

-loop

0, u

se B

A [2

:0] =

5

D\

D\

PR

E

Rep

eat c

ycle

s 1

thro

ugh

4 un

til n

RA

S -

1, tr

unca

te if

nee

ded

Rep

eat c

ycle

s 1

thro

ugh

4 un

til n

RC

- 1,

trun

cate

if n

eede

d

Rep

eat c

ycle

s n

RC

+1

thro

ugh n

RC

+4

until

nR

C -

1 + n

RA

S -

1, tr

unca

te if

nee

ded

- - - -

D\

D\

PR

E

AC

TD D

4 x n

RC

6 x n

RC

8 x n

RC

10 x

nR

C12

x n

RC

14 x

nR

C

nR

C +

3n

RC

+ 4

-n

RC

+ n

RA

S-

2 x

nRC

-n

RA

S-

nR

Cn

RC

+ 1

nR

C +

2

Cycle Number

Command

0

Data

1 2

AC

TD D

3 4

0

Static HIGH

Toggling

Not

es: 1

. Onl

y se

lect

ed b

ank

activ

e

2. D

Q, D

QS,

DQ

S# a

re a

t VD

D/2

3.

DM

is lo

w



ST9D364M64SBG2



table 6: idd0 meaSuremeNt lOOp

CK, CK\

CKE

Sub-Loop

CS\

RAS\

CAS\

WE\

ODT

BA [2:0]

A [15:11]

A [10]

A [9:7]

A [6:3]

A [2:0]

00

11

00

00

00

01

00

00

00

00

00

10

00

00

00

00

01

11

10

00

00

00

11

11

00

00

00

0

01

01

00

00

00

0

00

10

00

00

00

0

00

11

00

00

0F

01

00

00

00

00

F0

10

00

00

00

0F

01

11

10

00

00

F0

11

11

00

00

0F

0

01

01

00

00

0F

0

00

10

00

00

0F

0

1 2 3 4 5 6 7

Cycle Number

Command

Data

0 1 2

AC

TD D

-

3 4 -n

RC

D-

nR

AS

-n

RC

n

RC

+1

nRC

+2

nR

C +

3n

RC

+4

-n

RC

+ n

RC

D-

nR

C +

nR

AS

2 x n

RC

2 x n

RC

2 x n

RC

2 x n

RC

2 x n

RC

2 x n

RC

2 x n

RC

D\

D\

RD

PR

E

AC

TD D D\

D\

RD

PR

E

Rep

eat s

ub-lo

op 0

, use

BA

[2:0

] = 1

-

0011

0011

-

Rep

eat s

ub-lo

op 0

, use

BA

[2:0

] = 2

R

epea

t sub

-loop

0, u

se B

A [2

:0] =

3

Rep

eat s

ub-lo

op 0

, use

BA

[2:0

] = 4

R

epea

t sub

-loop

0, u

se B

A [2

:0] =

5

Rep

eat s

ub-lo

op 0

, use

BA

[2:0

] = 6

R

epea

t sub

-loop

0, u

se B

A [2

:0] =

7

Rep

eat c

ycle

s 1

thro

ugh

4 un

til n

RC

D -

1, tr

unca

te if

nee

ded

Rep

eat c

ycle

s 1

thro

ugh

4 un

til n

RA

S -

1, tr

unca

te if

nee

ded

Rep

eat c

ycle

s 1

thro

ugh

4 un

til n

RC

- 1,

trun

cate

if n

eede

d

Rep

eat c

ycle

s nR

C +

1 th

roug

h nR

C +

4 u

ntil

nRC

+ n

RC

D -

1, tr

unca

te if

nee

ded

Rep

eat c

ycle

s nR

C +

1 th

roug

h nR

C +

4 u

ntil

nRC

+ n

RA

S -

1, tr

unca

te if

nee

ded

- - - -- - - -

0000

0000

-

Toggling

Static HIGH

0

Rep

eat c

ycle

nR

C +

1 th

roug

h nR

C +

4 u

ntil

2 x

nRC

- 1,

trun

cate

if n

eede

d

Not

es: 1

. DM

is lo

w

2. O

nly

sele

cted

ban

k is

act

ive

3.

DQ

, DQ

S, D

QS#

are

at V

DD

/2 u

nles

s dr

ived

by

Read

com

man

d

4. B

urst

seq

uenc

e is

driv

en o

n ea

ch D

Q s

igna

l by

Read

com

man

d



ST9D364M64SBG2






ST9D364M64SBG2



table 8: idd meaSuremeNt cONditiONS FOr pOwer-dOwN curreNtS

Name

TimingPattern

CKE

ExternalClock

tCK

tRC

tRAS

tRCD

tRRD

tRC

CL

AL

CS\

CommandInputs

ROW/COLUMNAddr

BankAddress

DM

DataI/O

OutputBufferDQ,DQS

ODT

BurstLength

ACTIVEBank(s)

IDLEBank(s)

SpecialNotes

n/a

LOW

Toggling

tCK(MIN)IDD

n\a

n\a

n\a

n\a

n\a

n\a

n\a

HIGH

LOW

LOW

LOW

LOW

Mid-level

Enabled

Enabled,OFF

8

None

All

n\a

n/a

LOW

Toggling

tCK(MIN)IDD

n\a

n\a

n\a

n\a

n\a

n\a

n\a

HIGH

LOW

LOW

LOW

LOW

Mid-level

Enabled

Enabled,OFF

8

None

All

n\a

n/a

HIGH

Toggling

tCK(MIN)IDD

n\a

n\a

n\a

n\a

n\a

n\a

n\a

HIGH

LOW

LOW

LOW

LOW

Mid-level

Enabled

Enabled,OFF

8

None

All

n\a

n/a

LOW

Toggling

tCK(MIN)IDD

n\a

n\a

n\a

n\a

n\a

n\a

n\a

HIGH

LOW

LOW

LOW

LOW

Mid-level

Enabled

Enabled,OFF

8

None

All

n\a

IDD2P0

Precharge Power-

Down Current

(Slow Exit)

IDD2P1

Precharge Power-

Down Current

(Fast Exit)

IDD2Q

Precharge Quiet

Standby Current

IDD3P

Active Power-

Down Current

NOTES:

1.“Enabled,off”=MRbitsenablesbysingalislow

2.MR[12]=1:Fastexit

3.MR[12]=0:Slowexit

CK, CK\

CKE

Sub-Loop

CS\

RAS\

CAS\

WE\

ODT

BA [2:0]

A [15:11]

A [10]

A [9:7]

A [6:3]

A [2:0]

10

00

00

00

00

01

00

00

00

00

00

11

11

00

00

0F

01

11

10

00

00

F0

1 2 3 4 5 6 7

Cycle Number

Command

Data

010

D D2

D\

3D

\

Rep

eat s

ub-lo

op 0

, use

BA

[2:0

] = 7

- - - -4-

78-

11R

epea

t sub

-loop

0, u

se B

A [2

:0] =

1R

epea

t sub

-loop

0, u

se B

A [2

:0] =

2R

epea

t sub

-loop

0, u

se B

A [2

:0] =

3R

epea

t sub

-loop

0, u

se B

A [2

:0] =

4R

epea

t sub

-loop

0, u

se B

A [2

:0] =

5R

epea

t sub

-loop

0, u

se B

A [2

:0] =

6

Static HIGH

Toggling

12-1

516

-19

20-2

324

-27

28-3

1

Not

es: 1

. All

bank

s cl

osed

dur

ing

IDD

2N

2.

All

bank

s op

en d

urin

g ID

D3N

3.

DM

is lo

w

4. D

Q, D

QS,

DQ

S# a

t mid

leve

l



ST9D364M64SBG2



table 9: idd2N / idd3N meaSuremeNt lOOp

CK, CK\

CKE

Sub-Loop

CS\

RAS\

CAS\

WE\

ODT

BA [2:0]

A [15:11]

A [10]

A [9:7]

A [6:3]

A [2:0]1

00

00

00

00

00

10

00

00

00

00

01

11

10

00

00

F0

11

11

00

00

0F

01 2 3 4 5 6 7

Cycle Number

Command

Data

Toggling

Static HIGH

0

0 3

12-1

5

28-3

1

D-

1D

-2

D\

-D

\-

4-7

Rep

eat s

ub-lo

op 0

, use

BA

[2:0

] = 1

; OD

T =

08-

11R

epea

t sub

-loop

0, u

se B

A [2

:0] =

2; O

DT

= 1

Rep

eat s

ub-lo

op 0

, use

BA

[2:0

] = 3

; OD

T =

116

-19

Rep

eat s

ub-lo

op 0

, use

BA

[2:0

] = 4

; OD

T =

020

-23

Rep

eat s

ub-lo

op 0

, use

BA

[2:0

] = 5

; OD

T =

024

-27

Rep

eat s

ub-lo

op 0

, use

BA

[2:0

] = 6

; OD

T =

1R

epea

t sub

-loop

0, u

se B

A [2

:0] =

7; O

DT

= 1

Not

es: 1

. All

bank

s op

en

2. D

M is

low

3.

DQ

, DQ

S, D

QS#

at m

id le

vel w

hen

not d

riven

4.

Bur

st d

riven

on

each

DQ

by

Read

Com

man

d



ST9D364M64SBG2



table 10: idd2Nt meaSuremeNt lOOp

CK, CK\

CKE

Sub-Loop

CS\

RAS\

CAS\

WE\

ODT

BA [2:0]

A [15:11]

A [10]

A [9:7]

A [6:3]

A [2:0]

01

01

00

00

00

01

00

00

00

00

00

11

11

00

00

00

01

11

10

00

00

00

01

01

00

00

0F

01

00

00

00

00

F0

11

11

00

00

0F

01

11

10

00

00

F0

1 2 3 4 5 6 7

Data

0

Static HIGH

Toggling

56-6

3

0 1 2 5 8-15Cycle

Number

Command RD D D\

D\

RD

3 4-

D D\

D\

6 7

32-3

9

16-2

324

-31

40-4

748

-55

0000

0000

- - -00

1100

11

Rep

eat s

ub-lo

op 0

, use

BA

[2:0

] = 7

- -R

epea

t sub

-loop

0, u

se B

A [2

:0] =

1R

epea

t sub

-loop

0, u

se B

A [2

:0] =

2R

epea

t sub

-loop

0, u

se B

A [2

:0] =

3R

epea

t sub

-loop

0, u

se B

A [2

:0] =

4R

epea

t sub

-loop

0, u

se B

A [2

:0] =

5R

epea

t sub

-loop

0, u

se B

A [2

:0] =

6

Not

es: 1

. All

bank

s op

en

2. D

M is

low

3.

DQ

, DQ

S, D

QS#

at m

id le

vel w

hen

not d

riven

4.

Bur

st d

riven

on

each

DQ

by

Read

Com

man

d



ST9D364M64SBG2



table 11: idd4r meaSuremeNt lOOp

CK, CK\

CKE

Sub-Loop

CS\

RAS\

CAS\

WE\

ODT

BA [2:0]

A [15:11]

A [10]

A [9:7]

A [6:3]

A [2:0]

01

00

10

00

00

01

00

01

00

00

00

11

11

10

00

00

01

11

11

00

00

00

01

00

10

00

0F

01

00

01

00

00

F0

11

11

10

00

0F

01

11

11

00

00

F0

1 2 3 4 5 6 7

Data

1D

-W

R

Toggling

Stac HIGH

0

0 3 62D\

-

0000

0000

Cycle Number

Command D\-

4W

R00

1100

115

D-

D\-

7D\

-8-

15Re

peat

sub-

loop

0, u

se B

A [2

:0] =

116

-23

Repe

at su

b-lo

op 0

, use

BA

[2:0

] = 2

24-3

1Re

peat

sub-

loop

0, u

se B

A [2

:0] =

332

-39

Repe

at su

b-lo

op 0

, use

BA

[2:0

] = 4

40-4

7Re

peat

sub-

loop

0, u

se B

A [2

:0] =

548

-55

Repe

at su

b-lo

op 0

, use

BA

[2:0

] = 6

56-6

3Re

peat

sub-

loop

0, u

se B

A [2

:0] =

7

Not

es: 1

. All

bank

s op

en

2. D

M is

low

3.

DQ

, DQ

S, D

QS#

at m

id le

vel w

hen

not d

riven

4.

Bur

st d

riven

on

each

DQ

by

Read

Com

man

d



ST9D364M64SBG2



table 12: idd4w meaSuremeNt lOOp

CK, CK\

CKE

Sub-Loop

CS\

RAS\

CAS\

WE\

ODT

BA [2:0]

A [15:11]

A [10]

A [9:7]

A [6:3]

A [2:0]0 1b 1c 1d 1e 1f 1g 1h 2

9-12

13-1

6Cycle Number

Command

Data

10

17-2

021

-24

25-2

829

-32

33-n

RFC

-1

Rep

eat s

ub-lo

op 1

a, u

se B

A [2

:0] =

1R

epea

t sub

-loop

1a,

use

BA

[2:0

] = 2

1a2 3 4 5-8

Static HIGH

Toggling

RE

FD D D\

D\

Rep

eat s

ub-lo

op 1

a, u

se B

A [2

:0] =

4R

epea

t sub

-loop

1a,

use

BA

[2:0

] = 5

Rep

eat s

ub-lo

op 1

a, u

se B

A [2

:0] =

6

Rep

eat s

ub-lo

op 1

a, u

se B

A [2

:0] =

3

Rep

eat s

ub-lo

op 1

a, u

se B

A [2

:0] =

7R

epea

t sub

-loop

1a

thro

ugh

1h u

ntil nR

FC -

1, tr

unca

te if

nee

ded

Not

es: 1

. DM

is lo

w

2. D

Q, D

QS,

DQ

S# a

t mid

leve

l



ST9D364M64SBG2



table 13: idd5b meaSuremeNt lOOp




ST9D364M64SBG2



table 14: idd meaSuremeNt lOOp

IDD Test IDD8: ResetIDD6E/M: Self Refresh

CurrentIDD6: Self Refresh

Current

ExtendedorMilTemperatureRange,TA=-40°Cto85°Cor-55°Cto125°C

IndustrialRangeTA=-40°Cto85°C

CKE

ExternalClock

tCK

tRC

tRAS

tRCD

tRRD

tRC

CL

AL

CS\

CommandInputs

ROW/COLMUNaddresses

BANKaddresses

DataI/O

OutputbufferDQ,DQS

ODT

BurstLength

ActiveBANKS

IDLEBANKS

SRT

ASR

LOW

Off,CKandCK\=LOW

n\a

n\a

n\a

n\a

n\a

n\a

n\a

n\a

Mid-level

Mid-level

Mid-level

Mid-level

Mid-level

Enabled

Enabled,Mid-level

n\a

n\a

n\a

Disabled(normal)

Disabled

LOW

Off,CKandCK\=LOW

n\a

n\a

n\a

n\a

n\a

n\a

n\a

n\a

Mid-level

Mid-level

Mid-level

Mid-level

Mid-level

Enabled

Enabled,Mid-level

n\a

n\a

n\a

Enabled(extended)

Disabled

Mid-level

Mid-level

n\a

n\a

n\a

n\a

n\a

n\a

n\a

n\a

Mid-level

Mid-level

Mid-level

Mid-level

Mid-level

Mid-level

Mid-level

n\a

None

All

n\a

n\a

1. Power must be stable and RESET low for at least 1ms at first power-on2. RESET mus be low for at least 200ns +trfc on “warm” RESET 3. “Enabled, mid-level” = MR command enabled, signal; at mid level

CK, CK\

CKE

Sub-Loop

CS\

RAS\

CAS\

WE\

ODT

BA [2:0]

A [15:11]

A [10]

A [9:7]

A [6:3]

A [2:0]

00

11

00

00

00

00

10

10

00

10

00

10

00

00

00

00

0

00

11

01

00

0F

00

10

10

10

10

F0

10

00

01

00

0F

0

2 31

00

00

30

00

F0

5 6 7 81

00

00

70

00

F0

00

11

00

00

0F

00

10

10

00

10

F0

10

00

00

00

0F

0

00

11

01

00

00

00

10

10

10

10

00

10

00

01

00

00

0

12 131

00

00

30

00

00

15 16 17 181

00

00

70

00

00

Cycle Number

Command

Data

10 2

-00

0000

00-

3n

RR

Dn

RR

D +

1n

RR

D +

2n

RR

D +

32

x n

RR

D3x

nR

RD

4 x n

RR

D4

x n

RR

D +

1n

FAW

nFA

W +

nR

RD

nFA

W +

2xn

RR

Dn

FAW

+ 3

xnR

RD

nFA

W +

4xn

RR

Dn

FAW

+ 4

xnR

RD

+12

x n

FAW

2

x n

FAW

+ 1

2 x n

FAW

+ 2

3 x

nFA

W +

nR

RD

3 x

nFA

W +

2x

nRR

D

2 x n

FAW

+ 3

2 x n

FAW

+ n

RR

D2

x n

FAW

+ n

RR

D+1

2 x n

FAW

+ n

RR

D+2

2 x n

FAW

+ n

RR

D+3

2 x

nFA

W +

2x n

RR

D

1 4 9 10 11 14

Static HIGH

Toggling

AC

TR

DA

D AC

T

3 x

nFA

W +

3x

nRR

D3

x nF

AW

+ 4

x nR

RD

3 x

nFA

W +

4x

nRR

D +

1

0

D AC

TR

DA

-R

epea

t cyc

le 2

x n

FAW

+ 2

unt

il 2

x n

FAW

+ n

RR

D -

1

19

2 x n

FAW

+ 3

x n

RR

D2

x n

FAW

+ 4

x n

RR

D2

x n

FAW

+4x n

RR

D+1

3 x

nFA

W

Rep

eat s

ub-lo

op 1

1, u

se B

A[2

:0] =

3

- - -

Rep

eat s

ub-lo

op 1

, use

BA

[2:0

] = 5

Rep

eat s

ub-lo

op 0

, use

BA

[2:0

] = 6

Rep

eat s

ub-lo

op 1

, use

BA

[2:0

] = 7

Rep

eat c

ycle

nFA

W +

4 x

nR

RD

unt

il 2

x n

FAW

- 1,

if n

eede

d

RD

A

D-

D

Rep

eat c

ycle

2 u

ntil n

RR

D -

1

Rep

eat c

ycle

nR

RD

+ 2

unt

il 2

x n

RR

D -

1R

epea

t sub

-loop

0, u

se B

A[2

:0] =

2R

epea

t sub

-loop

0, u

se B

A[2

:0] =

3

Rep

eat c

ycle

4 x

nR

RD

unt

il n

FAW

- 1,

if n

eede

d

0011

0011

Rep

eat s

ub-lo

op 1

0, u

se B

A[2

:0] =

2

- -

RD

AD

-

0011

0011

Rep

eat s

ub-lo

op 0

, use

BA

[2:0

] = 4

D AC

T

D

Rep

eat c

ycle

2 x

nFA

W +

nR

RD

+ 2

unt

il 2

x n

FAW

+ 2

x n

RR

D -

1

0000

0000

-

Rep

eat c

ycle

3 x

nFA

W +

4 x

nR

RD

unt

il 4

x n

FAW

- 1,

if n

eede

d

Rep

eat c

ycle

2 x

nFA

W +

4 x

nR

RD

unt

il 3

x n

FAW

- 1,

if n

eede

dR

epea

t sub

-loop

10,

use

BA

[2:0

] = 4

Rep

eat s

ub-lo

op 1

1, u

se B

A[2

:0] =

5R

epea

t sub

-loop

10,

use

BA

[2:0

] = 6

Rep

eat s

ub-lo

op 1

1, u

se B

A[2

:0] =

7D

Not

es: 1

. AL=

AC-1

2.

DM

= L

ow

3. D

M, D

QS,

DQ

S# a

t mid

leve

l unl

ess

driv

en b

y RE

AD

Com

man

d

4. B

urst

seq

uenc

e dr

iver

on

each

DQ

by

Read

Com

man

d



ST9D364M64SBG2






ST9D364M64SBG2



NOTES:TA=0°Cto≤ 85°C;SRTandASRaredisabled,enablingASRcouldincreaseIDDxbyuptoanadditional2mA.

IDD DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 UNITS

IDD0

IDD1

IDD2P0

IDD2P1

IDD2Q

IDD2N

IDD3P

IDD3N

IDD4R

IDD4W

IDD5B

IDD6

IDD7

IDD8

Speed Bin

360

440

36

120

184

200

120

200

960

960

800

24

1400

IDD2P+2mA

IDD2P+2.1mA

IDD2P+2.4mA

400

520

36

140

212

220

140

220

1040

1160

880

24

1520

IDD2P+2mA

IDD2P+2.1mA

IDD2P+2.1mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

table 16: idd maximum limitS

440

600

36

160

240

260

160

240

1200

1420

960

24

1680

IDD2P+2mA

IDD2P+2mA

IDD2P+2mA

IND

EXT

MIL-TEMP

480

680

36

180

268

280

180

260

1400

1720

1040

24

18400

IDD2P+2mA

IDD2P+2mA

IDD2P+2mA





ST9D364M64SBG2



NOTES:

1. VDDandVDDQmusttrackoneanother,VDDQmustbelessthanorequal

toVDD,Vss=VssQ.

2. VDDandVDDQmayincludeACnoiseof±50mV(250kHzto20MHz)in

additiontotheDC(0Hzto250kHz)specifications,VDDandVDDQmust

beatthesamelevelforvalidACtimingparameters.

3. VREF(seeTable19).

4. Theminimum limit requirement is for testingpurposes. The leakage

currentontheVREFpinshouldbeminimal.

NOTES:

1. VREFCA(DC)isexpectedtobeapproximately0.5xVDDandtotrackvari-

ationsintheDClevel.Externallygeneratedpeaknoise(noncommon

mode)onVREFCAmaynotexceed±1%xVDDaroundtheVREFCA(DC)

value.Peak-to-peakACnoiseonVREFCAshouldnotexceed±2%of

VREFCA(DC).

2. DCvaluesaredeterminedtobelessthan20MHzinfrequency.DRAM

must meet specifications if the DRAM induces additional AC noise

greaterthan20MHzinfrequency.

3. VREFDQ(DC) is expected to be approximately 0.5 xVDD and to track

variationsintheDClevel.Externallygeneratedpeaknoise(noncom-

mon mode) on VREFDQ may not exceed ± 1% x VDD around the

VREFDQ(DC)value.Peak-to-peakACnoiseonVREFDQshouldnot

exceed±2%ofVREFDQ(DC).

4. VREFDQ(DC)may transition toVREFDQ(SR)andback toVREFDQ(DC)

when in SELF zREFRESH, within restrictions outlined in the SELF

REFRESHsection.

5. VTT isnotapplieddirectly to thedevice. VTT isasystemsupply for

signalterminationresistors.MINandMAXvaluesaresystem-depen-

dent.

Parameter/Condition Symbol MIN TYP MAX Supply Voltage

I/O Supply Voltage

Input Leakage Current:

Anyinput0V≤VIN≤VDD,VREFpin0V≤VIN≤1.1V

Allotherpinsnotundertest=0V

VREF Supply Leakage Current:

VREFDQ=VDD/2orVREFCA=VDD/2

Allotherpinsnotundertest=0V

V

V

µA

µA

1,2

1,2

3,4

table 17: dc electrical characteriSticS aNd OperatiNG cONditiONS

1.575

1.575

8

4

1.5

1.5

-

-

1.425

1.425

-8

-4

AllVoltagesarereferencedtoVss

VDD

VDDQ

II

IVREF

Parameter/Condition Symbol MIN TYP MAX VIN low; DC/commands/address busses

VIN high; DC/commands/address busses

Input reference voltage command/address bus

I/O reference voltage DQ bus

I/O reference voltage DQ bus in SELF REFRESH

Command/address termination voltage (systemlevel,not

directDRAMinput)

V

V

V

V

V

V

1,2

2,3

4

5

table 18: dc electrical characteriSticS aNd iNput cONditiONS

SeeTable17

VDD

0.51xVDD

0.51xVDD

VDD

-

n/a

n/a

0.5xVDD

0.5xVDD

0.5xVDD

0.5xVDDQ

Vss

SeeTable17

0.49xVDD

0.49xVDD

Vss

-

AllVoltagesarereferencedtoVss

VIL

VIH

VREFCA(DC)

VREFDQ(DC)

VREFDQ(SR)

VTT



ST9D364M64SBG2



Input high AC voltage: Logic 1


Input high DC voltage: Logic 1










+175

+150

+100

-100

-150

-175

-

+150

+100

-100

-150

-

+175

+150

+100

-100

-150

-175

+175

+150

+100

-100

-150

-175

VIH(AC175)MIN

VIH(AC150)MIN

VIH(DC100)MIN

VIL(DC100)MAX

VIL(AC150)MAX

VIL(AC175)MAX

VIH(AC175)MIN

VIH(AC150)MIN

VIH(DC100)MIN

VIL(DC100)MAX

VIL(AC150)MAX

VIL(AC175)MAX

NOTES:

1. AllvoltagesarereferencedtoVREF,VREF isVREFCAforcontrol,com-

mand,andaddress.Allslewratesandsetup/holdtimesarespecifiedat

theDRAMball.VREFisVREFDQforDQandDMinputs.

2. Inputsetuptimingparameters(tIS and tDS)arereferencedatVIL(AC)/

VIH(AC),notVREF(DC).

3. Inputholdtimingparameters(tIH and tDH)arereferencedatVIL(DC)/

VIH(DC),notVREF(AC).

4. Single-ended input slew rate = 1V/ns;maximum input voltage swing

undertestis900mV(peak-to-peak).

Parameter/Condition Symbol DDR3-800

CommandandAddress

table 19: iNput SwitchiNG cONditiONS

DQ and DM

DDR3-1066 DDR3-1333

mV

mV

mV

mV

mV

mV

mV

mV

mV

mV

mV

mV

Notes: 1. Numbers in diagrams reflect nominal values.

Minimum VIL and VIH levels

0.925V

0.850V

0.780V0.765V0.750V0.735V0.720V

0.650V

0.575V

VIH (AC)

VIH (DC)

VIL (DC)

VIL (AC)

VIL and VIH levels with ringback

1.90V

1.50V

0.925V

0.850V

0.780V0.765V0.750V0.735V0.720V

0.650V

0.575V

0.0V

-0.40V

VDDQ + 0.4V narrow pulse width

VDDQ

VIH (AC)

VIH (DC)

VREF + AC noiseVREF + DC errorVREF + DC errorVREF + AC noise

VIL (DQ)

VIL (AC)

VSS

VSS 0.4V narrow pulse width



ST9D364M64SBG2



OPERATING CONDITIONS

FiGure 6 - iNput SiGNalS

FiGure 7 & 8: OVerShOOt/uNderShOOt SpeciFicatiONS

Maximum amplitude Overshoot area

VDD/VDDQ

Time (ns)

Volts (V)

Maximum amplitudeUndershoot area

Time (ns)VSS/VSSQ

Volts (V)

Figure 7: Overshoot

Figure 8: Undershoot

AC OVERSHOOT/UNDERSHOOT SPECIFICATION



ST9D364M64SBG2





Parameter DDR3-800 DDR3-1066 DDR3-1333 Maximum peak amplitude allowed for overshoot area

(seeFigure7)

Maximum peak amplitude allowed for underrshoot area

(seeFigure8)

Maximum overshoot area above VDD (seeFigure7)

Maximum undershoot area below Vss (seeFigure8)

table 20: cONtrOl aNd addreSS piNS

0.4V

0.4V

0.4Vns

0.4Vns

0.4V

0.4V

0.67Vns

0.67Vns

0.4V

0.4V

0.5Vns

0.5Vns

Parameter DDR3-800 DDR3-1066 DDR3-1333 DDR3-Maximum peak amplitude allowed for overshoot area

(seeFigure7)

Maximum peak amplitude allowed for undershoot area

(seeFigure8)

Maximum overshoot area above VDD/ VDDQ

(seeFigure7)

Maximum undershoot area below Vss/ VssQ

(seeFigure8)

table 21: clOck, data, StrObe, aNd maSk piNS

0.4V

0.4V

0.15Vns

0.15Vns

0.4V

0.4V

0.25Vns

0.25Vns

0.4V

0.4V

0.19Vns

0.19Vns

0.4V

0.4V

0.3Vns

0.3Vns

0.4V

0.4V

0.15Vns

0.15Vns




ST9D364M64SBG2



Parameter/Condition Symbol MIN MAX Differential input voltage, logic high - slew

Differential input voltage, logic low - slew

Differential input voltage, logic high

Differential input voltage, logic low

Differential input crossing voltage relative to VDD/2

for DQS, DQS\, CK, CK\

Differential input crossing voltage relative to VDD/2

for CK, CK\

Single-ended high level for strobes

Single-ended high level for CK, CK\

Single-ended low level for strobes

Single-ended low level for CK, CK\

mV

mV

mV

mV

mV

mV

mV

mV

4

4

5

6

7

7,8

5

6

table 22: diFFereNtial iNput OperatiNG cONditiONS (ckx, ckx\, dQSx, aNd dQSx\)

n/a

-200

VDD/VDDQ

2x(VREF-VIL(AC))

VREF(DC)+150

VREF(DC)+175

VDDQ

VDD

VDDQ/2-VIL(AC)

VDD/2-VIL(AC)

+200

n/a

2x(VIH(AC)-VREF)

Vss/VssQ

VREF(DC)-150

VREF(DC)-175

VDDQ/2+VIH(AC)

VDD/2+VIH(AC

VssQ

Vss

VIH DIFF(AC)slew

VILDIFF(AC)slew

VIH DIFF(AC)

VILDIFF(AC)

VIX

VIX(175)

VSHE

VSEL

NOTES:

1. Clock is referenced toVDDD andVss. Data strobe is referenced to

VDDQandVssQ.

2. ReferenceisVREFCA(DC)forclockandforVREFDQ(DC)forstrobe.

3. Differentialinputslewrate=2V/ms.

4. Definesslewratereferencepointsrelativetoinputcrossingvoltages.

5. MAX limit is relative tosingle-endedsignals, theovershootspecifica-

tionsareapplicable.

6. MINlimitisrelativetosingle-endedsignals,theundershootspecifica-

tionsareapplicable.

7. ThetypicalvalueofVIX(AC)isexpectedtobeabout0.5xVDDofthe

transmittingdeviceandVIX(AC)isexpectedtotrackvariationsinVDD.

VIX(AC) indicates the voltageatwhichdifferential input signalsmust

cross.

8. TheVIXextendedrange(±175mV)isallowedonlyfortheclockandthis

VIXextendedrangeisonlyallowedwhenthefollowingconditionsare

met: Thesingle-ended inputsignalsaremonotonic,havethesingle-

endedswingVSEL,VSEHofatleastVDD/2±250mV,andthedifferential

slewrateofCK,CK\isgreaterthan3V/ns.



ST9D364M64SBG2



OVERSHOOT/UNDERSHOOT SPECIFICATIONS

FiGure 9 - Vix FOr diFFereNtial SiGNalS

VIX

X

X

X

X

VDD, VDDQ VDD, VDDQ

CK#, DQS# CK#, DQS#

VIX

VIX

VIX

CK, DQS CK, DQS

VSS, VSSQ VSS, VSSQ

VDD/2, VDDQ/2 VDD/2, VDDQ/2

FiGure 10 - SiNGle-eNded reQuiremeNtS FOr diFFereNtial SiGNalS

VSS or VSS Q

VDD or VDD Q

VSEL (MAX)

VSEH (MIN)

VSEH

VSEL

VDD /2 or VDD Q/2

CK or DQS



ST9D364M64SBG2



OVERSHOOT/UNDERSHOOT SPECIFICATIONS

FiGure 11 - deFiNitiON OF diFFereNtial ac-SwiNG aNd tdVac

V IHDIFF (A C) MIN

V IHDIFF (DC) MIN

0.0

V ILDIFF (DC) MAX

V ILDIFF (MAX)

tDVAC

V IHDIFF (MIN)

V ILDIFF (A C) MAX

half cycle tDVAC

CK - CK#DQ S - DQS #


Slew Rate (V/ns) 350mV 300mV-4.0

4.0

3.0

2.0

1.9

1.6

1.4

1.2

1.0

<1.0

table 23: diFFereNtial iNput OperatiNG cONditiONS (tdVac) FOr ckx, ckx\, dQSx, aNd dQSx\

175

170

167

163

162

161

159

155

150

150

75

57

50

38

34

29

22

13

0

0

BelowVIL(AC)

tDVAC (ps) at [VIHDIFF(AC) to VILDiff(AC)]


Input Edge From To Calculation

Setup

Hold

table 24: SiNGle-eNded iNput Slew rate

Input Slew Rate (Linear Signals)

Rising

Falling

Rising

Falling

Measured

VREF

VREF

VIL(DC)Max

VIH(DC)MIN

VIH(AC)MIN

VIL(AC)MAX

VREF

VREF

VIH(AC)MIN-VREF

∆TFS

VREF-VIL(AC)MAX

∆TFS

VREF-VIL(DC)MAX

∆TFH

VIH(DC)MIN-VREF

∆TRSH



ST9D364M64SBG2



SLEW RATE DEFINITIONS FOR SINGLE-ENDED INPUT SIGNALS

Setup (tIS and tDS)nominalslew rate fora risingsignal isdefinedas theslew-ratebetween the lastcrossingofVREFand thefirstcrossingVIH(AC)MIN. Setup (tIS and tDS)nominal slew rate for a falling signal is definedas theslewratebetweenthe lastcrossingofVREFan thefirstcrossingofVIL(AC)MAX.

Hold(tIH and tDH)nominalslewrateforarisingsignalisdefinedastheslewratebetweenthelastcrossingofVIL(DC)MAXandthefirstcrossingofVREF. Hold(tIH and tDH)nominalslewrateforafallingsignalisdefinedastheslewratebetweenthelastcrossingofVIH(DC)MINandthefirstcrossingofVREF.



ST9D364M64SBG2



SLEW RATE DEFINITIONS FOR SINGLE-ENDED INPUT SIGNALS

FiGure 12 - NOmiNal Slew rate deFiNitiON FOr SiNGle-eNded iNput SiGNalS

ΔTRS

ΔTFS

ΔTRH

ΔTFH

VREFDQ orVREFCA

VIH(AC) MIN

VIH(DC) MIN

VIL(AC) MAX

VIL(DC) MAX

VREFDQ or VREFCA

VIH(AC) MIN

VIH(DC) MIN

VIL(AC) MAX

VIL(DC) MAX

Setup

Hold

Sin

gle-

ende

d in

put v

olta

ge (D

Q,

CM

D,

AD

DR

)S

ingl

e-en

ded

inpu

t vol

tage

(DQ

, CM

D,

AD

DR

)


Input Edge From To Calculation

CK and DQS

Reference

table 25: diFFereNtial iNput Slew rate deFiNitiON

Input Slew Rate (Linear Signals)

Rising

Falling

Measured

VREF

VREF

VIH(AC)MIN

VIL(AC)MAX

VIH(DIFF)MIN-VIL(DIFF)MAX

∆TR(DIFF)

VIH(DIFF)MIN- VIL(DIFF)MAX

∆TF(DIFF)



ST9D364M64SBG2



SLEW RATE DEFINITIONS FOR DIFFERENTIAL INPUT SIGNALS

Inputslewratefordifferentialsignals(CKx,CKx\,UDQSx,UDQSx\,LDQSxandLDQSx\)aredefinedandmeasuredasshowninTable25.ThenominalslewrateforarisingsignalisdefinedastheslewratebetweenVIL(DIFF)MAXandVIH(DIFF)MIN.ThenominalslewrateforafallingsignalisdefinedastheslewratebetweenVIH(DIFF)MINandVIL(DIFF)MAX.

FiGure 13 - NOmiNal diFFereNtial iNput Slew rate deFiNitiON FOr dQS, dQS# aNd ck, ck#

ΔTRDIFF

ΔTFDIFF

VIH(DIFF) MIN

VIL(DIFF) MAX

0

Diff

eren

tial i

nput

vol

tage

(DQ

S, D

QS

#; C

K, C

K#)



ST9D364M64SBG2



ODT CHARACTERISTICS

RTTPU

RTTPD

ODT

Chip in termination mode

VDDQ

DQ

VSSQ

IOUT = IPD - IPU

IPU

IPD

IOUT

VOUT

Toothercircuitrysuch as RCV, . . .

ODT’seffectiveresistanceRTTisdefinedbyMR1[9,6and2].ODTisappliedtotheDQx,andDQSx,DQSx\.TheODTtargetvaluesarelistedinTable29.

Parameter/Condition Symbol MIN TYP MAX RTTeffectiveimpedance

DeviationofVMwithrespecttoVDDQ/2 %

1,2,4

1,2,3,4

table 26: ON-die termiNatiON dc electrical characteriSticS

5

RTT_EFF

∆VM -5

SeeTable27

NOTES:

1. Tolerance limits are applicable after a proper ZQ calibration has been

performedatastabletemperatureandvoltage(VDDQ=VDD,VssQ-Vss).

Referto“ODTSensitivity”onpage36ifeitherthetemperatureorvoltage

changesaftercalibration.

2. MeasurementdefinitionforRTT: ApplyVIH(AC)toapinundertestand

measurethecurrentI[VIH(AC)],thenapplyVIL(AC)topinundertestand

measurecurrentI[VIL(AC)]:

VIL(AC)-VIL(AC)

I[VIH(AC))-I(VIL(AC))]

3. Measurevoltage(VM)atthetestedpinwithnoload:

4. Forextendedtemperaturedevices,theminimumvaluesarederatedby6%

whenthedeviceisbetween-40°Cand0°C(TA).

RTT =

2xVM

VDDQ∆VM= -1x100

FiGure 14 - Odt leVelS aNd i-V characteriSticS




ST9D364M64SBG2



MR1 [9,6,2]

0, 1, 0

0, 0, 1

0, 1, 1

1, 0, 1

1, 0, 0

table 27: rtt eFFectiVe impedaNceS

0.2xVDDQ

0.5xVDDQ

0.8xVDDQ

0.2xVDDQ

0.5xVDDQ

0.8xVDDQ

VIL(AC)toVIH(AC)

0.2xVDDQ

0.5xVDDQ

0.8xVDDQ

0.2xVDDQ

0.5xVDDQ

0.8xVDDQ

VIL(AC)toVIH(AC)

0.2xVDDQ

0.5xVDDQ

0.8xVDDQ

0.2xVDDQ

0.5xVDDQ

0.8xVDDQ

VIL(AC)toVIH(AC)

0.2xVDDQ

0.5xVDDQ

0.8xVDDQ

0.2xVDDQ

0.5xVDDQ

0.8xVDDQ

VIL(AC)toVIH(AC)

0.2xVDDQ

0.5xVDDQ

0.8xVDDQ

0.2xVDDQ

0.5xVDDQ

0.8xVDDQ

VIL(AC)toVIH(AC)

RTT Resistor VOUT MIN TYP MAX

120Ω

60Ω

40Ω

30Ω

20Ω

0.6

0.9

0.9

0.9

0.9

0.9

0.9

0.6

0.9

0.9

0.9

0.9

0.9

0.9

0.6

0.9

0.9

0.9

0.9

0.9

0.9

0.6

0.9

0.9

0.9

0.9

0.9

0.9

0.6

0.9

0.9

0.9

0.9

0.9

0.9

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.1

1.1

1.4

1.4

1.1

1.1

1.6

1.1

1.1

1.4

1.4

1.1

1.1

1.6

1.1

1.1

1.4

1.4

1.1

1.1

1.6

1.1

1.1

1.4

1.4

1.1

1.1

1.6

1.1

1.1

1.4

1.4

1.1

1.1

1.6

RZQ/1

RZQ/1

RZQ/1

RZQ/1

RZQ/1

RZQ/1

RZQ/2

RZQ/2

RZQ/2

RZQ/2

RZQ/2

RZQ/2

RZQ/2

RZQ/4

RZQ/3

RZQ/3

RZQ/3

RZQ/3

RZQ/3

RZQ/3

RZQ/6

RZQ/4

RZQ/4

RZQ/4

RZQ/4

RZQ/4

RZQ/4

RZQ/8

RZQ/6

RZQ/6

RZQ/6

RZQ/6

RZQ/6

RZQ/6

RZQ/12

RTT120PD240

RTT120PU240

RTT60PD120

RTT60PU240

RTT40PD80

RTT40PU80

RTT30PD60

RTT30PU60

RTT20PD40

RTT20PU40

120Ω

60Ω

40Ω

30Ω

20Ω



ST9D364M64SBG2



ODT SENSITIVITY

IfeitherthetemperatureorvoltagechangesafterI/Ocalibration,thetolerancelimitslistedinTable26canbeexpectedtowidenaccordingtoTables28and29.

Symbol MIN MAX RTT RZQ/(2,4,6,8,12)

table 28: Odt SeNSitiVity deFiNitiON

1.6+dRTTdTx[DT]+dRTTdVx[DV]0.9-dRTTdTxdRTTdVx[DV]

table 29 - Odt temperature & VOltaGe SeNSitiVity

Change MIN MAX UNITS dRTTdT

dRTTdV

0

0

1.5

0.15

%/°C

%/°C

ODTloadingdiffersfromthatusedinACtimingmeasurements.Twoparam-etersdefinewhenODTturnsonoroffsynchronously,twodefinewhenODTturnsonoroffAsynchronouslyand,anotherdefineswhenODTturnsonoroffdynamically.Table30outlinesandprovidesdefinitionandmeasurementreferencesettingsforeachparameter.

ODT turn-on timebeginswhen theoutput leavesHIGH-ZandODTresis-tancebeginstoturnon.ODTturn-offtimebeginswhentheoutputleavesLOW-ZandODTresistancebeginstoturn-off.

ODT TIMING DEFINITIONS

Timing reference point

DQ, DMDQS, DQS#

DUT VREF

VTT = VSSQ

VDDQ/2

ZQRZQ = 240Ω

VSSQ

RTT = 25ΩCK, CK#

All RZQs are embedded in module

FiGure 15 - Odt timiNG reFereNce lOad

PDF: 09005aef826aa906/Source: 09005aef82a357c3 Micron Technology, Inc., reserves the right to change products or specifications without notice.DDR3_D3.fm - Rev G 2/09 EN 55 ©2006 Micron Technology, Inc. All rights reserved.

CK

CK#

tAON

VSSQ

DQ, DM

DQS, DQS#

Begin point: Rising edge of CK - CK#defined by the end point of ODTL on

VSW1

End point: Extrapolated point at VSSQ

TSW1

TSW2

CK

CK#

VDDQ/2

tAOF

End point: Extrapolated point at VRTT_NOM

VRTT_NOM

VSSQ

tAON tAOF

VSW2 VSW2

VSW1

TSW1

TSW1

Begin point: Rising edge of CK - CK#defined by the end point of ODTL off



ST9D364M64SBG2




Symbol Begin Point Definition End Point Definition

tAON

tAOF

tAONPD

tAOFPD

tADC

table 30: Odt timiNG deFiNitiONS

Figure25

Figure25

Figure26

Figure26

Figure27

ExtrapolatedpointatVssQ

ExtrapolatedpointatVRTT_NORM

ExtrapolatedpointatVssQ

ExtrapolatedpointatVRTT_NOM

ExtrapolatedpointsatVRTT_WRandVRTT_NOM

RisingedgeofCK-CK\definedbytheendpointofODTLon

RisingedgeofCK-CK\definedbytheendpointofODTLoff

RisingedgeofCK-CK\withODTfirstbeingregisteredHIGH

RisingedgeofCK-CK\withODTfirstbeingregisteredLOW

RisingedgeofCK-CK\definedbytheendpointofODTLCNW,

ODTLCWN4,orODTLCWN8


Parameter RTT_NORM Setting RTT_WR_Setting VSW1

tAON

tAOF

tAONPD

tAOFPD

tADC

table 31: reFereNce SettiNGS FOr Odt timiNG meaSuremeNtS

100mV

200mV

100mV

200mV

100mV

200mV

100mV

200mV

300mV

50mV

100mV

50mV

100mV

50mV

100mV

50mV

100mV

200mV

n/a

n/a

n/a

n/a

n/a

n/a

n/a

n/a

RZQ/2(120Ω)

RZQ/4(60Ω)

RZQ/12(20Ω)

RZQ/4(60Ω)

RZQ/12(20Ω)

RZQ/4(60Ω)

RZQ/12(20Ω)

RZQ/4(60Ω)

RZQ/12(20Ω)

RZQ/12(20Ω)

Measured

FiGure 16 - taON aNd taOF deFiNitiONS

ODT TIMING DEFINITIONS

CK

CK#

tAONPD

VSSQDQ, DMDQS, DQS#

Begin point: Rising edge of CK - CK#with ODT first registered HIGH

VSW1

End point: Extrapolated point at VSSQ

TSW2

CK

CK#

VDD Q/2

tAOFPD

End point: Extrapolated point at VRTT_NOM

VRTT_NOM

VSSQ

tAONPD tAOFPD

TSW1TSW2

TSW1VSW2 VSW2

VSW1

Begin point: Rising edge of CK - CK#with ODT first registered LOW



ST9D364M64SBG2



ODT CHARACTERISTICS

FiGure 17 - taONpd aNd taOFpd deFiNitiON

FiGure 18 - tadc deFiNitiON

CK

CK#

tADC

DQ, DMDQS, DQS#

End point:Extrapolatedpoint at VRTT_NOM

TSW21

tADC

End point: Extrapolated point at VRTT_WR

VDDQ/2

VSSQ

VRTT_NOM

VRTT_WR

VRTT_NOM

TSW11

VSW1

VSW2

TSW12

TSW22

Begin point: Rising edge of CK - CK#defined by the end point of ODTLCNW

Begin point: Rising edge of CK - CK#defined by the end point of ODTLCNW4 or ODTLCNW8

RONPU

RONPD

Output driver

Toothercircuitrysuch asRCV, . . .

Chip in drive mode

VDDQ

VSSQ

IPU

IPD

IOUT

VOUT

DQ



ST9D364M64SBG2



OUTPUT DRIVER IMPEDANCE

FiGure 19 - Output driVer 34 Ohm Output driVer impedaNce

The34Ωdriver(MR1[5,1]=01)isthedefaultdriver.Unlessotherwisestated,alltimingsandspecificationslistedhereinapplytothe34Ωdriveronly.ItsimpedanceRON is definedby the valueof the external reference resistorRZQasfollows:RON34=RZQ/7(withnominalRZQ=240Ω±1%)andisactu-ally34.3Ω±1%.The34ΩoutputdriverimpedancecharacteristicsarelistedinTable32.


MR1[5,1] RON RESISTOR VOUT MIN TYP MAX UNITS

0, 1

table 32: 34Ω driVer impedaNce characteriSticS

RZQ/7

RZQ/7

RZQ/7

RZQ/7

RZQ/7

RZQ/7

%

1

1

1

1

1

1

1,2

0.2/VDDQ

0.5/VDDQ

0.8/VDDQ

0.2/VDDQ

0.5/VDDQ

0.8/VDDQ

0.5/VDDQ

34.3Ω

RON34PD

RON34PU

0.6

0.9

0.9

0.9

0.9

0.6

-10

1.0

1.0

1.0

1.0

1.0

1.0

n/a

1.1

1.1

1.4

1.4

1.1

1.1

10Pull-Up/Pull-Down mismatch (MMPUPD)

NOTES:

1. TolerancelimitsassumeRZQof240Ω(±1%)andareapplicableafterproperZQcalibrationhasbeenperformedatastabletemperatureandvoltage

(VDDQ=VDD,VssQ=Vss).Referto“34Ohmdrivesensitivity”ifeitherthetemperatureorthevoltagechangesaftercalibration

2. Measurementdefinitionformismatchbetweenpull-upandpull-down(MMPUPD).MearurebothRONPU and RONPDat0.5xVDDQ:

MMPUD =

RONNOM

RONPU-RONPD



ST9D364M64SBG2



34 Ohm OUTPUT DRIVER IMPEDANCE

34 Ohm driVer

The34Ωdriver’scurrentrangehasbeencalculatedandsummarizedinTable34forVDD=1.5V,Table35forVDD=1.575VandTable36forVDD=1.425V.Theindividualpull-upandpull-downresistors(RON34PDandRON34PU)aredefinedasfollowswiththeImpedanceCalculationslistedinTable36.

•RON34PD=(VOUT)/[IOUT]:RON34PUisturnedoff

•RON34PU=(VDDQ-VOUT)/[IOUT]:RON34PDisturnedoff


MR1[5,1] RON RESISTOR VOUT MIN TYP

0, 1

table 33: 34Ω driVer pull-up aNd pull-dOwN impedaNce calculatiONS

Ω

Ω

Ω

Ω

Ω

Ω

0.2/VDDQ

0.5/VDDQ

0.8/VDDQ

0.2/VDDQ

0.5/VDDQ

0.8/VDDQ

34.3Ω

RON34PD

RON34PU

2.04

30.5

30.5

30.5

30.5

20.4

34.3

34.3

34.3

34.3

34.3

34.3

38.1

38.1

48.5

48.5

38.1

38.1

242.4

34.6

240

34.3

237.6

33.9

Ω

Ω

RON MIN TYP RZQ = 240Ω±1%

RZQ = (240Ω±1%)/7



0, 1

mA

mA

mA

mA

mA

mA

[email protected]

[email protected]

[email protected]

[email protected]

[email protected]

[email protected]

34.3Ω

RON34PD

RON34PU

15.5

25.8

41.2

41.2

25.8

15.5

9.2

23

36.8

36.8

23

9.2

8.3

20.7

26

26

20.7

8.3

table 35: 34Ω driVer iOh/iOl characteriSticS: Vdd=VddQ=1.575V



0, 1

mA

mA

mA

mA

mA

mA

[email protected]

[email protected]

[email protected]

[email protected]

[email protected]

[email protected]

34.3Ω

RON34PD

RON34PU

14.7

24.6

39.3

39.3

24.6

14.7

8.8

21.9

35

35

21.9

8.8

7.9

19.7

24.8

24.8

19.7

7.9

table 34: 34Ω driVer iOh/iOl characteriSticS: Vdd = VddQ = 1.5V



ST9D364M64SBG2



34 Ohm OUTPUT DRIVER IMPEDANCE



0, 1

mA

mA

mA

mA

mA

mA

[email protected]

[email protected]

[email protected]

[email protected]

[email protected]

[email protected]

34.3Ω

RON34PD

RON34PU

14

23.3

37.3

37.3

23.3

14

8.3

20.8

33.3

33.3

20.8

8.3

7.5

18.7

23.5

23.5

18.7

7.5

table 36: 34Ω driVer iOh/iOl characteriSticS: Vdd=VddQ=1.425V

34Ω OUTPUT DRIVER SENSITIVITY

IfeitherthetemperatureorvoltagechangesafterZQcalibration,thetolerancelimitslistedinTable32canbeexpectedtowidenaccordingtoTable37and38.

Symbol MIN MAX

RON(PD) @ 0.2 x

VDDQ

RON(PD) @ 0.5 x

VDDQ

RON(PD) @ 0.8 x

VDDQ

RZQ/7

RZQ/7

RZQ/7

RZQ/7

RZQ/7

RZQ/7

table 37: 34Ω Output driVer SeNSitiVity deFiNitiON

1.1+dRONdTLx[∆T]+dRONdVLx[∆V]

1.1+dRONdTMx[∆T]+dRONdVMx[∆V]

1.4+dRONdTHx[∆T]+dRONdVHx[∆V]




0.6-dRONdTLx[∆T]-dRONdVLx[∆V]

0.9-dRONdTMx[∆T]-dRONdVMx[∆V]

0.9-dRONdTHx[∆T]-dRONdVHx[∆V]




Change MIN MAX

dRONdTM

dRONdVM

dRONdTL

dRONdVL

dRONdTH

dRONdVH

%/°C

%/mV

%/°C

%/mV

%/°C

%/mV

table 38: 34Ω Output driVer VOltaGe aNd temperature SeNSitiVity

1.5

0.13

1.5

0.13

1.5

0.13

0

0

0

0

0

0

1. Note: ∆T=T-T(@calibration),∆V=VDDQ-VDDQ(@calibration),VDD=VDDQ



ST9D364M64SBG2



ALTERNATIVE 40 OHM DRIVER


MR1[5,1] RON RESISTOR VOUT MIN TYP MAX UNITS NOTES

0, 1

table 39 - 40Ω driVer impedaNce characteriSticS

RZQ/6

RZQ/6

RZQ/6

RZQ/6

RZQ/6

RZQ/6

%

1

1

1

1

1

1

1,2

0.2/VDDQ

0.5/VDDQ

0.8/VDDQ

0.2/VDDQ

0.5/VDDQ

0.8/VDDQ

0.5/VDDQ

40.0Ω

RON40PD

RON40PU

0.6

0.9

0.9

0.9

0.9

0.6

-10

1.0

1.0

1.0

1.0

1.0

1.0

n/a

1.1

1.1

1.4

1.4

1.1

1.1

10Pull-Up/Pull-Down mismatch (MMPUPD)

NOTES:

1. TolerancelimitsassumeRZQof240Ω(±1%)andareapplicableafterproperZQcalibrationhasbeenperformedatastabletemperatureandvoltage

(VDDQ=VDD,VssQ=Vss).Referto“40Ohmdrivesensitivity”ifeitherthetemperatureorthevoltagechangesaftercalibration

2. Measurementdefinitionformismatchbetweenpull-upandpull-down(MMPUPD).MearurebothRONPUandRONPDat0.5xVDDQ:

MMPUPD =

RONNOM

RONPU-RONPD x100

40Ω OUTPUT DRIVER SENSITIVITY

IfeitherthetemperatureorvoltagechangesafterI/Ocalibration,thetolerancelimitslistedinTable39canbeexpectedtowidenaccordingtoTable40and41.

table 40: 40Ω Output driVer SeNSitiVity deFiNitiON

Symbol MIN MAX

RON(PD) @ 0.2 x

VDDQ

RON(PD) @ 0.5 x

VDDQ

RON(PD) @ 0.8 x

VDDQ

RZQ/6

RZQ/6

RZQ/6

RZQ/6

RZQ/6

RZQ/6















ST9D364M64SBG2



ALTERNATIVE 40 OHM DRIVER

Change MIN MAX dRONdTM

dRONdVM

dRONdTL

dRONdVL

dRONdTH

dRONdVH

%/°C

%/mV

%/°C

%/mV

%/°C

%/mV

table 41: 40Ω Output driVer VOltaGe aNd temperature SeNSitiVity

1.5

0.15

1.5

0.15

1.5

0.15

0

0

0

0

0

0

OUTPUT CHARACTERISTICS AND OPERATING CONDITIONS

TheSDRAMusesbothsingle-endedanddifferentialoutputdrivers.Thesingle-endedoutputdriver issummarizedinTable42whilethedifferentialoutputdriverissummarizedinTable43.


Parameter/Condition Symbol MIN MAX

Output leakage current:DQaredisabled;

0V≤VOUT≤VDDQ;ODTisdisabled;ODTisHIGH

Output slew rate:Single-ended;forrisingandfalling

edges,measurebetweenVOL(AC)=VREF-0.1xVDDQ

andVOH(AC)=VREF+0.1xVDDQ

Single-ended DC high-level output voltage

Single-ended DC mid-point level output voltage

Single-ended DC low-point level output voltage

Single-ended DC high-point level output voltage

Single-ended DC low-point level output voltage

Delta RON between pull-up and pull-down for DQ/DQS

Test load for AC timing and output slew rates

uA

V/ns

V

V

V

V

V

%

1

1,2,3,4

1,2,5

1,2,5

1,2,5

1,2,3,6

1,2,3,6

1,7

3

table 42: SiNGle-eNded Output driVer characteriSticS

5

6

10

-5

2.5

-10

IOZ

SRQSE

VOH(DC)

VOM(DC)

VOL(DC)

VOH(AC)

VOL(AC)

MMPUPD

0.8xVDDQ

0.5xVDDQ

0.2xVDDQ

VTT+0.1xVDDQ

VTT-0.1xVDDQ

OutputtoVTT(VDDQ/2)via25Ωresistor

5. SeeTable32IVcurvelinearity.DonotuseACTestload.

6. SeeTable44foroutputslewrate.

7. SeeTable32foradditionalinformation.

8. SeeFigure29foranexampleofasingle-endedoutputsignal.

NOTES:

1. RZQof240Ω(±1%)withRZQ/7enabled(default34Ωdriver)andisappli-

cableafterproperZQcalibrationhasbeenperformedatastable tem-

peratureandvoltage(VDDQ=VDD,VssQ=Vss).

2. VTT=VDDQ/2

3. SeeFigure31forthetestloadconfiguration.

4. The6V/nsmaximumisapplicableforasingleDQsignalwhenitisswitch-

ingfromeitherHIGHtoLOWorLOWtoHIGHwhiletheremainingDQ

signalsinthesamebytelanearecombinations,themaximumlimitof6V/

nsmaximumisreducedto5V/ns.



ST9D364M64SBG2




Parameter/Condition Symbol MIN MAX

Output leakage current:DQaredisabled;

0V≤VOUT≤VDDQ;ODTisHIGH

Output slew rate:Differential;forrisingandfallingedges,

measurebetweenVOLDIFF(AC)=-0.2xVDDQandVOH

(AC)=+0.2xVDDQ

Output differential cross-point voltage

Differential high-level output voltage

Differential low-level output voltage

Delta RON between pull-up and pull-down for DQ/DQS

Test load for AC timing and output slew rates

uA

V/ns

mV

V

V

%

1

1

1,2,3

1,4

1,4

1,5

3

table 43: diFFereNtial Output driVer characteriSticS

5

12

VREF+150

10

-5

5

VREF-150

-10

IOZ

SRQDIFF

VOX(AC)

VOHDIFF(AC)

VOLDIFF(AC)

MMPUPD

+0.2xVDDQ

-0.2xVDDQ

OutputtoVTT(VDDQ/2)via25Ωresistor

4. SeeTable47onpage47fortheoutputslewrate.

5. SeeTable32onpage57foradditionalinformation.

6. SeeFigure30onpage66foranexampleofadifferentialoutputsignal.

NOTES:

1. RZQof240Ω(±1%)withRZQ/7enabled(default34Ωdriver)andisappli-

cableafterproperZQcalibrationhasbeenperformedatastable tem-

peratureandvoltage(VDDQ=VDD,VssQ=Vss).

2. VREF=VDDQ/2

3. SeeFigure31onpage67forthetestloadconfiguration.

FiGure 20 - dQ Output SiGNal

VOH(AC)

MIN output

MAX output

VOL(AC)



ST9D364M64SBG2



FiGure 21 - diFFereNtial Output SiGNal

VOH(DIFF)

MIN output

MAX output

VOL(DIFF)

VOX(AC) MAX

VOX(AC) MINX

X

X

X

OUTPUT CHARACTERISTICS AND OPERATING CONDITIONS

REFERENCE OUTPUT LOAD

Figure22representstheeffectivereferenceloadof25ΩusedindefiningtherelevantdeviceACtimingparameters(exceptODTreferencetiming)aswellastheoutputslewratemeasurements.ItisnotintendedtobeapreciserepresentationofaparticularsystemenvironmentoradepictionoftheactualloadpresentedbyanyspecificIndustrytestsystem/apparatus.SystemdesignersshoulduseIBISorothersimulationtoolstocorrelatethetimingreferenceloadpresentedorexhibitedonthesystemorsystemenvironment.

FiGure 22 - reFereNce Output lOad FOr ac timiNG aNd Output Slew rate

Timing Reference Point

DQDQS

DQS#

DUT VREF

VTT = VDDQ/2

VDDQ/2

ZQRZQ = 240Ω

VSS

RTT = 25Ω

All RZQs are embedded in module


Output Edge From To Calculation

DQ

table 44: SiNGle-eNded Output Slew rate

Output Slew Rate (Linear Signals)

Rising

Falling

Measured

VOL(AC)

VOH(AC)

VOH(AC)

VOL(AC)

VOH(AC)-VOL(AC)

∆TRSE

VOH(AC)-VOL(AC)

∆TFSE



ST9D364M64SBG2



SLEW RATE DEFINITIONS FOR SINGLE-ENDED OUTPUT SIGNALS

Thesingle-endedoutputdriverissummarizedinTable42.Withthereferenceloadfortimingmeasurements,theoutputslew-rateforfallingandrisingedgesisdefinedandmeasuredbetweenVOL(AC)andVOH(AC)forsingle-endedsignalsasindicatedinTable44andFigure23.

FiGure 23 - NOmiNal Slew rate deFiNitiON FOr SiNGle-eNded Output SiGNalS

ΔTRSE

ΔTFSE

VOH(AC)

VOL(AC)

VTT


Output Edge From To Calculation

DQS, DQS\

table 45: diFFereNtial Output Slew rate deFiNitiON

Output Slew Rate (Linear Signals)

Rising

Falling

Measured

VOLDIFF(AC)

VOHDIFF(AC)

VOHDIFF(AC)

VOLDIFF(AC)

VOHDIFF(AC)-VOLDIFF(AC)

∆TRDIFF

VOHDIFF(AC)-VOLDIFF(AC)

∆TFDIFF



ST9D364M64SBG2



SLEW RATE DEFINITIONS FOR DIFFERENTIAL OUTPUT SIGNALS

ThedifferentialoutputdriverissummarizedinTable43.Withthereferenceloadfortimingmeasurements,theoutputslewrateforfallingandrisingedgesisdefinedandmeasuredbetweenVOL(AC)andVOH(AC)fordifferentialsignals,asshowninTable45andFigure33.

FiGure 24 - NOmiNal diFFereNtial Output Slew rate deFiNitiON FOr dQS, dQS#

ΔTFDIFF

VOH(DIFF) AC

VOL(DIFF) AC

0



ST9D364M64SBG2




Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX

ACTIVATEtointernalREADorWRITEdelaytime

PRECHARGEcommandperiod

ACTIVATE-to-ACTIVATEorREFRESHcommandperiod

ACTIVATE-to-PRECHARGEcommandperiod

CL=5

CL=6

CL=8

CL=11

SupportedCLSettings

SupportedCWLSettings

1

2

3

3

2

3

3

3

2,3

3

3

3

2,3

table 46: Speed biNS

-25(DDR3-800)-19(DDR3-1066)-15(DDR3-1333)-12(DDR3-1600)

tRCD

tRP

tRC

tRAS

tCK(AVG)

tCK(AVG)

tCK(AVG)

tCK(AVG)

tCK(AVG)

tCK(AVG)

tCK(AVG)

tCK(AVG)

tCK(AVG)

tCK(AVG)

tCK(AVG)

tCK(AVG)

15

15

52.5

37.5

3

2.5

5,65,6,85,6,8,10 5,6,8,10

-

-

-

60ms

3.3

3.3

15

15

52.5

37.5

3

2.5

1.875

-

-

-

60ms

3.3

3.3

<2.5

15

15

51

36

3

2.5

1.875

1.5

-

-

-

60ms

3.3

3.3

<2.5

<1.875

CWL=5

CWL=6

CWL=7

CWL=5

CWL=6

CWL=7

CWL=5

CWL=6

CWL=7

CWL=6

CWL=7

55,65,6,7 5,6,7

3. Reserved(filledblocks)settingsarenotallowed.

NOTES:

1. tREFIdependsontOPER

2. TheCLandCWLsetting result in tCK requirements. Whenmakinga

selectionoftCK,bothCLandCWLrequirementsettingsneedtobeful-

filled.

13.75

13.75

48.75

35

3

2.5

1.875

1.5

-

-

-

60ms

3.3

3.3

<2.5

<1.875

[CWL=2.5;6-6-6][CWL=1.875;8-8-8][CWL=1.5;10-10-10][CWL=1.25;11-11-11]

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

CK

CK



ST9D364M64SBG2



table 47 (Sheet 1 OF 6) - electrical characteriSticS aNd ac OperatiNG cONditiONS

MIN

MAX

MIN

MAX

MIN

MAX

878

008

7800

878

008

3900

839

008

3900

829

008

2900

829

00

0.47

0.53

0.47

0.53

0.47

0.53

0.47

0.53

0.47

0.53

0.47

0.53

-100

100

-90

90-8

080

-90

90-8

080

-70

70

-147

147

-132

132

-118

118

-175

175

-157

157

-140

140

-194

194

-175

175

-155

155

-209

209

-188

188

-168

168

-222

222

-200

200

-177

177

-232

232

-209

209

-186

186

-241

241

-217

217

-193

193

-249

249

-224

224

-200

200

-257

257

-231

231

-205

205

-263

263

-237

237

-210

210

-269

269

-242

242

-215

215

Units

Note

s[C

WL=

1.5;

10-

10-1

0]Sy

mbo

lPa

ram

eter

-25

(DDR

3-80

0)-1

9 (D

DR3-

1066

)[C

WL=

2.5;

6-6

-6]

[CW

L=1.

875;

8-8

-8]

-15

(DDR

3-13

33)

11 C

ycle

s12

Cyc

les

0.43

-

0.43

-

t ERR

nPER

MIN

= (1

+0.6

8ln[

n]) x

t JIT

PER

MIN

t ERR

nPER

MAX

= (1

+0.6

8ln[

n]) x

t JIT

PER

MAX

0.43

-0.

43-

9,42

9,42

9,42

10,1

112 12 13 13 16 16 17 17 17 17 17 17 17 17 17 17 1714 15 17

180

160

140

180

160

t ERRn

PER

t JITCC

t JITCC

, LCK

t ERR6

PERR

t ERR7

PERR

t ERR8

PERR

n =

13, 1

4 …

49,

50

Cycle

s

t ERR2

PERR

t ERR3

PERR

t ERR4

PERR

t ERR5

PERR

200

t ERR9

PERR

t ERR1

0PER

Rt ER

R11P

ERR

t ERR1

2PER

R

Cum

ula

ve e

rror

acr

oss

2 Cy

cles

3 Cy

cles

4 Cy

cles

5 Cy

cles

6 Cy

cles

7 Cy

cles

8 Cy

cles

9 Cy

cles

10 C

ycle

s

Cloc

k pe

riod

JITTE

R

Cycle

-to-C

ycle

JITT

ER

DLL L

OCKE

DDL

L LOC

KING

DLL L

OCKE

DDL

L LOC

KING

Cloc

k ab

solu

te p

erio

d

Cloc

k ab

solu

te H

IGH

pusle

wid

th

Cloc

k ab

solu

te LO

W p

ulse

wid

th

t CLK

(ABS

)

t CKDL

L_DI

S

t CL (A

VG)

t CH (A

BS)

t CL (A

BS)

Cloc

k pe

riod

aver

age:

DLL

ena

ble

mod

eHI

GH p

ulse

wid

th a

vera

geLO

W p

ulse

wid

th a

vera

ge

Cloc

k pe

riod

aver

age:

DLL

di

sabl

e m

ode

TC =

85˚

C to

105

˚C

0.43

-

t JITPE

Rt JIT

PER,

LCK

t CK (A

VG)

-0.

43

ns CK CK ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps

t CK

(AVG

)

psns

t CK

(AVG

)

MIN

=tCK

(AVG

) MIN

+tJIT

PER

MIN

; MAX

=tCK

(AVG

)MAX

+tJIT

PER

MAX

TC =

0˚C

to <

85˚C

TC =

>10

5˚C

to ≤

125˚

C

t CH (A

VG)

See

SPEE

D BI

N TA

BLE

(#49

) for

tCK

rang

e al

low

ed

[CW

L=1.

25; 1

1-11

-11]

-12

(DDR

3-16

00)

MIN

MAX

878

008

3900

829

00

0.47

0.53

0.47

0.53

-70

70-6

060

-103

103

-122

122

-136

136

-147

147

-155

155

-163

163

-169

169

-175

175

-180

180

-184

184

-188

188

0.43

-

120

140

-0.

43



ST9D364M64SBG2




MIN

MAX

MIN

MAX

MIN

MAX

75-

25-

--

250

-20

0-

--

125

-75

-30

-27

5-

250

-18

0-

150

-10

0-

65-

250

-20

0-

165

-60

0-

490

-40

0-

-20

0-

150

-12

5

-800

400

-600

300

-500

250

-40

0-

300

-25

0

-0.2

50.

25-0

.25

0.25

-0.2

50.

250.

450.

550.

450.

550.

450.

550.

450.

550.

450.

550.

450.

550.

2-

0.2

-0.

2-

0.2

-0.

2-

0.2

-0.

9-

0.9

-0.

9-

0.3

-0.

3-

0.3

-

-400

400

-300

300

-255

255

0.38

-0.

38-

0.4

-0.

38-

0.38

-0.

4-

-800

400

-600

300

-500

250

-40

0-

300

-25

00.

9No

te 2

40.

9No

te 2

40.

9No

te 2

40.

3No

te 2

70.

3No

te 2

70.

3No

te 2

7

Data

SET

UP

me

to D

QS,

DQ

S\t DS

AC1

50

Data

HO

LD

me

from

DQ

S,

DQS\

VREF

@ 1

V/ns

Data

SET

UP

me

to D

QS,

DQ

S\t DS

AC1

75

Base

(spe

cifica

on)

[CW

L=1.

875;

8-8

-8]

VREF

@ 1

V/ns

Base

(spe

cifica

on)

VREF

@ 1

V/ns

Base

(spe

cifica

on)

DQ H

IGH-

A m

e fro

m C

K, C

K\

DQS,

DQ

S\ D

IFFE

RENT

IAL R

EAD

post

ambl

et RP

ST

DQS,

DQ

S\ D

IFFE

RENT

IAL O

utpu

t HIG

H m

e

DQ LO

W-Z

m

e fro

m C

K, C

K\

DQ S

trob

e In

put T

imin

g

DQS,

DQ

S\ D

IFFE

RENT

IAL W

RITE

pos

tam

ble

Para

met

er

-25

(DDR

3-80

0)-1

9 (D

DR3-

1066

)-1

5 (D

DR3-

1333

)[C

WL=

2.5;

6-6

-6]

[CW

L=1.

5; 1

0-10

-10]

Sym

bol

DQS,

DQ

S\ F

ALLI

NG S

etup

to C

K, C

K\ R

ISIN

Gt DS

S

DQ O

utpu

t Tim

ing

DQS,

DQ

S\ to

DQ

SKE

W, p

er a

cces

s

DQ O

utpu

t HO

LD

me

from

DQ

S, D

QS\

t DQSS

DQS,

DQ

S\ D

IFFE

RENT

IAL I

nput

Low

pul

se w

idth

t WPS

T

DQS,

DQS\

RIS

ING

to C

K, C

K\ R

ISIN

Gt DQ

SLDQ

S, D

QS\

DIF

FERE

NTIA

L Inp

ut H

IGH

pulse

wid

tht DQ

SH

DQS,

DQ

S\ D

IFFE

RENT

IAL R

EAD

prea

mbl

et RP

RE

DQS,

DQ

S\ F

ALLI

NG H

old

from

CK,

CK\

RIS

ING

t DSH

DQS,

DQ

S\ D

IFFE

RENT

IAL W

RITE

pre

ambl

et W

PRE

DQ S

trob

e O

utpu

t Tim

ing

1

t QSH

DQS,

DQ

S\ D

IFFE

RENT

IAL O

utpu

t LO

W

me

t QSL

DQS,

DQ

S\ R

ISIN

G to

/fro

m R

ISIN

G CK

, CK\

t DQSC

K

DQS,

DQ

S\ H

IGH-

Z m

e (R

L+BL

/2)

t HZ (D

QS)

DQS,

DQ

S\ LO

W-Z

m

e (R

L-1)

t LZ (D

QS)

101

10DQ

S, D

QS\

RIS

ING

to/f

rom

RIS

ING

CK, C

K\ w

hen

DLL i

s disa

bled

t DQSK

DLL_

DIS

101

t DH A

C100

Min

imum

Dat

a Pu

lse W

idth

t DIPW

t QH

0.38

-

t DQSQ

-0.

38-

Units ps ps ps ps ps ps ps ps ps ps CK CK CK CK CK CK CK ps CK CK ps ps CK CKns

tCK

(AVG

)

18,1

919

,20

18,1

919

,20

18,1

919

,20

41 22,2

322

,23

25 25 25 23 21 21 22,2

322

,23

23,2

423

,27

Note

s

2621

t HZ (D

Q)

t LZ (D

Q)

0.38

-12

(DDR

3-16

00)

[CW

L=1.

25; 1

1-11

-11]

MIN

MAX

- - 10 160

45 145

360 -

-450 -

-0.2

70.

450.

450.

180.

18 0.9

0.3

-225 0.4

0.4

-450 - 0.9

0.310.

38

- - - - - - - 100

225

225

0.27

0.55

0.55 - - - - 225 - - 225

225

Note

24

Note

27

10-

DQ In

put T

imin

g



ST9D364M64SBG2




MIN

MAX

MIN

MAX

MIN

MAX

512

-51

2-

-20

0-

125

--

375

-30

0-

-35

0-

275

--

500

-42

5-

-27

5-

--

--

-90

0-

780

--

40-

37.5

-30

-50

-50

-45

-

MUL

TIPU

RPO

SE R

EGIS

TER

READ

bur

st e

nd to

mod

e re

gist

er se

t for

m

ulp

urpo

se re

gist

er e

xit

t MPR

RM

IN =

1CK

; MAX

= n

/a

MIN

= 4

CK; M

AX =

n/a

MIN

= g

reat

er o

f 12C

K or

15n

s; M

AX =

n/a

MO

DE R

EGIS

TER

SET

com

man

d cy

cle

me

t MRD

MIN

= g

reat

er o

f 4CK

or 7

.5ns

; MAX

= n

/aM

IN =

4CK

; MAX

= n

/a

Auto

pre

char

ge W

RITE

reco

very

+ P

RECH

ARGE

m

et DA

LM

IN =

WR

+ t RP

/t CK (A

VG);

MAX

= n

/a

CAS\

-to-C

AS\ c

omm

and

dela

yt CC

D

MIN

= 1

5ns;

MAX

= n

/a

Dela

y fro

m st

art o

f int

erna

l WRI

TE tr

ansa

con

to in

tern

al R

EAD

com

man

dt W

TRM

IN =

gre

ater

of 4

CK o

r 7.5

ns; M

AX =

n/a

WRI

TE re

cove

ry

me

t WR

MO

DE R

EGIS

TER

SET

com

man

d up

date

del

ayt M

OD

Four

ACT

IVAT

E w

indo

ws f

or 2

KB p

age

size

Four

ACT

IVAT

E w

indo

ws f

or 1

KB p

age

size

t FAW

READ

-to-P

RECH

ARE

me

t RTP

[CW

L=2.

5; 6

-6-6

][C

WL=

1.87

5; 8

-8-8

][C

WL=

1.5;

10-

10-1

0]Sy

mbo

lPa

ram

eter

-25

(DDR

3-80

0)-1

9 (D

DR3-

1066

)-1

5 (D

DR3-

1333

)

Com

man

d an

d Ad

dres

s Tim

ing

CTRL

, CM

D, A

DDR

setu

p to

CK,

CK

\Ba

se (s

pecifi

cao

n)VR

EF @

1V/

nsCT

RL, C

MD,

ADD

R se

tup

to C

K,

CK\

Base

(spe

cifica

on)

VREF

@ 1

V/ns

CTRL

, CM

D, A

DDR

hold

to C

K,

CK\

Base

(spe

cifica

on)

VREF

@ 1

V/ns

DLL L

ocki

ng

me

t DLLK

See

"Spe

ed B

in T

able

(#49

) for

tRCD

See

"Spe

ed B

in T

able

(#49

) for

tRP

See

"Spe

ed B

in T

able

(#49

) for

tRAS

Min

imum

CTR

L, C

MD,

ADD

R pu

lse w

idth

t IPW

ACTI

VATE

to In

tern

al R

EAD

or W

RITE

del

ayt RC

DPR

ECHA

RGE

com

man

d pe

riod

t RP

1KB

page

size

MIN

=gre

ater

of 4

CK

or 1

0ns

MIN

=gre

ater

of 4

CK

or 7

.5ns

ACTI

VATE

-to-P

RECH

ARGE

com

man

d pe

riod

t RAS

ACTI

VATE

-to-A

CTIV

ATE

com

man

d pe

riod

t RCD

See

"Spe

ed B

in T

able

(#49

) for

tRC

MIN

=gre

ater

of 4

CK

or 6

ns

CK ps ps ps ps ps ps ps ns ns ns ns ns ns CK CK CK CK CKCKCK CKUnits CKCK

28 29,3

020

,30

29,3

020

,30

29,3

020

,30

41 31 31 31,3

231 31 31

31,3

2,33

31,3

4

Note

s

3131AC

TIVA

TE-to

-ACT

IVAT

E m

inim

um co

mm

and

perio

d2K

B pa

ge si

ze

t RRD

MIN

=gre

ater

of 4

CK o

r 10n

s

MIN

MAX

[CW

L=1.

25; 1

1-11

-11]

-12

(DDR

3-16

00)

- - - - - - - -

MIN

=gre

ater

of 4

CK

or 6

ns

MIN

=gre

ater

of 4

CK o

r 7.5

ns

30-

40-

375

200

300

t IS A

C175

t IS A

C150

t IH D

C100

512

65 240

190

340

140

240

620

512

45 220

170

320

120

220

560



ST9D364M64SBG2




MIN

MAX

MIN

MAX

MIN

MAX

256

-25

6-

256

-64

-64

-64

-

Valid

cloc

ks a

er S

ELF

REFR

ESH

entr

y or

PO

WER

-DO

WN

entr

yt CK

SRE

MIN

= g

reat

er o

f 5CK

or 1

0ns;

MAX

= n

/a

Valid

cloc

ks b

efor

e SE

LF R

EFRE

SH e

xit,

POW

ER-D

OW

N ex

it, o

r RES

ET

exit

t CKSR

XM

IN =

gre

ater

of 5

CK o

r 10n

s; M

AX =

n/a

EXIT

SEL

F RE

FRES

H TO

com

man

ds re

quiri

ng a

lock

ed D

LLt XS

DLL

MIN

= t DL

LK (M

IN);

MAX

= n

/a

MIN

IMUM

CKE

LOW

pul

se w

idth

for S

ELF

REFR

ESH

entr

y to

SEL

F RE

FRES

H ex

it m

ing

t CKES

RM

IN =

t CKE

(MIN

) + C

K; M

AX =

n/a

SELF

REF

RESH

Tim

ing

Exit

SELF

REF

RESH

TO

com

man

ds n

ot re

quiri

ng a

lock

ed D

LLt XS

MIN

= g

reat

er o

f 5CK

or t RF

C +

10ns

; MAX

= n

/a

Max

imum

REF

RESH

pe

riod/

inte

rval

TC ≤

85˚

Ct RE

FI7.

8TC

>85

˚C ≤

105

˚C3.

9TC

>10

5˚C

≤ 12

5˚C

2.9

TC ≤

85˚

C-

TC >

105˚

C ≤

125˚

C24

TC >

85˚C

≤ 1

05˚C

Max

imum

REF

RESH

per

iod

Begi

n po

wer

supp

ly ra

mp

to p

ower

supp

lies s

tabl

et VD

DPR

MIN

= n

/a; M

AX =

200

REFR

ESH-

to-A

CTIV

ATE

or R

EFRE

SH co

mm

and

perio

dt RF

CM

IN =

110

; MAX

= 9

x t RE

FI

REFR

ESH

Tim

ing

RESE

T\ LO

W to

pow

er su

pplie

s sta

ble

t RPS

MIN

= 0

; MAX

= 2

00RE

SET\

LOW

to I/

O a

nd R

TT H

IGH-

Zt IO

ZM

IN =

n/a

; MAX

= 2

00

ZQCS

com

man

d: S

hort

Cal

ibra

on

Tim

et ZQ

CS

Exit

RESE

T fro

m C

KE H

IGH

to a

val

id co

mm

and

t XPR

MIN

= g

reat

er o

f 5CK

or t

RFC

+ 10

ns; M

AX =

n/a

Ini

aliza

on

and

RESE

T Ti

min

g

-51

2-

512

-ZQ

CL co

mm

and:

Long

Ca

libra

on

me

POW

ER-U

P an

d RE

SET

oper

aon

Norm

al o

pera

on

t ZQIN

ITt ZQ

OPER

512

35 36 36 36 36 36 36 28

Note

s[C

WL=

2.5;

6-6

-6]

[CW

L=1.

875;

8-8

-8]

[CW

L=1.

5; 1

0-10

-10]

Sym

bol

Calib

rao

n Ti

min

gPa

ram

eter

-25

(DDR

3-80

0)-1

9 (D

DR3-

1066

)-1

5 (D

DR3-

1333

)

CK CK CK ms ns ms

ms

ms

µs µs µs CK CKCK CKCKms nsCKUnits

MIN

MAX

[CW

L=1.

25; 1

1-11

-11]

-12

(DDR

3-16

00)

256

-64

-

512

-

64 (1

X)32

(2X)



ST9D364M64SBG2




MIN

MAX

MIN

MAX

MIN

MAX

MIN

= G

reat

er o

f 3CK

or 7

.5ns

; MAX

= n

/a

MIN

= G

reat

er o

f 10C

K or

24n

s; M

AX =

n/a

BL8

(OTF

, MRS

) BC4

OTF

t WRA

PDEN

MIN

= W

L + 4

+ W

R +

1

MIN

= W

L + 2

+ W

R +

1

BL8

(OTF

, MRS

) BC4

OTF

t WRP

DEN

t WRP

DEN

MIN

= W

L + 4

+ t W

R/t CK

(AVG

)

t WRA

PDEN

BC4M

RSM

IN =

WL +

2 +

t WR/

t CK (A

VG)

WRI

TE w

ith A

UTO

PRE

CHAR

GE

com

man

d to

PO

WER

-DO

WN

entr

yBC

4MRS

DLL o

n, a

ny v

alid

com

man

d, o

r DLL

off

to co

mm

ands

not

requ

iring

DLL

lo

cked

t XP

READ

/REA

D w

ith A

UTO

PRE

CHAR

GE co

mm

ant t

o PO

WER

-DO

WN

entr

yt RD

PDEN

MIN

= R

L + 4

+ 1

WRI

TE C

omm

and

to P

OW

ER-

DOW

N en

try

REFR

ESH

com

man

d to

PO

WER

-DO

WN

entr

yt RE

FPDE

NM

IN =

1M

RS co

mm

and

to P

OW

ER-D

OW

N en

try

t MRS

PDEN

MIN

= t M

OD (M

IN)

t ACTP

DEN

MIN

= 1

PREC

HARG

E/PR

ECHA

RGE

ALL c

omm

and

to P

OW

ER-D

OW

N en

try

t PRPD

ENM

IN =

1

Com

man

d pa

ss d

isabl

e de

lay

t CPDE

DM

IN =

1; M

AX =

n/a

POW

ER-D

OW

N en

try

to P

OW

ER-D

OW

N ex

it m

ing

t PDM

IN =

tCKE

(MIN

); M

AX =

60m

s

POW

ER-D

OW

N en

try

perio

d: O

DT e

her

sync

hron

ous o

r asy

nchr

onou

sPD

EGr

eate

r of t

ANPD

or t

RFC

- REF

RESH

com

man

d to

CKE

LOW

m

e

POW

ER-D

OW

N ex

it pe

riod:

ODT

eith

er sy

nchr

onou

s or a

sync

hron

ous

PDX

t ANPD

+ t XP

DLL

Grea

ter o

f 3CK

or

7.5n

sGr

eate

r of 3

CK o

r 5.

625n

sGr

eate

r of 3

CK o

r 5.

625n

s

Begi

n PO

WER

-DO

WN

perio

d pr

ior t

o CK

E re

gist

ered

HIG

Ht AN

PDW

L - 1

CK

POW

ER-D

OW

N Ti

min

g

POW

ER-D

OW

N En

try

MIN

IMUM

Tim

ing

POW

ER-D

OW

N Ex

it Ti

min

g

PREC

HARG

E PO

WER

-DO

WN

with

DLL

off

to co

mm

and

requ

iring

DLL

lo

cked

t XPDL

L

CKE

MIN

pul

se w

idth

t CKE

(MIN

)

ACTI

VATE

com

man

d to

PO

WER

-DO

WN

entr

y

Para

met

er

-25

(DDR

3-80

0)-1

9 (D

DR3-

1066

)-1

5 (D

DR3-

1333

)

CK CK CK CK CK CK CK CK CKCKCKCKCKCK CK CKCKUnits

37 28

Note

s[C

WL=

2.5;

6-6

-6]

[CW

L=1.

875;

8-8

-8]

[CW

L=1.

5; 1

0-10

-10]

Sym

bol

MIN

MAX

-12

(DDR

3-16

00)

[CW

L=1.

25; 1

1-11

-11]

MIN

= G

reat

er o

f 3CK

or 6

.0ns

; MAX

= n

/a

Grea

ter o

f 3CK

or

5ns



ST9D364M64SBG2




MIN

MAX

MIN

MAX

MIN

MAX

-400

400

-300

300

-250

250

0.3

0.7

0.3

0.7

0.3

0.7

0.3

0.7

0.3

0.7

0.3

0.7

40-

40-

40-

25-

25-

25-

09

09

09

02

02

02

WRI

TE Le

velin

g ou

tput

err

ort W

LOE

t WLS

t WLH

195

-

WRI

TE Le

velin

g ou

tput

del

ayt W

LO

WRI

TE Le

velin

g HO

LD fr

om ri

sing

DQS,

DQ

S\ cr

ossin

g to

risin

g CK

, CK\

cr

ossin

g32

5-

245

DQS;

DQ

S\ d

elay

t WLD

QSE

NW

RITE

Leve

ling

SETU

P fro

m ri

sing

CK, C

K\ cr

ossin

g to

risin

g DQ

S, D

QS\

cr

ossin

g32

5-

245

-19

5-

6CK

+ OD

TL O

FFRT

T dy

nam

ic ch

ange

skew

t ADC

Firs

t DQ

S, D

QS\

RIS

ING

edge

t WLM

RD

-

RTT_

NOM

-to=R

TT_W

R ch

ange

skew

ODTL

CNW

WL -

2CK

RTT_

WR-

to-R

TT_N

OM

chan

ge sk

ew -

BC4

ODTL

CNW

44C

K +

ODTL

OFF

RTT_

WR-

to-R

TT_N

OM

chan

ge sk

ew -

BC8

ODTL

CNW

8

ODT

HIG

H m

e w

ithou

t WRI

TE co

mm

and

or w

ith W

RITE

com

man

d an

d BC

8OD

T H8

MIN

= 6

; MAX

= n

/a

ODT

HIG

H m

e w

ithou

t WRI

TE co

mm

and

or w

ith W

RITE

com

man

d an

d BC

4OD

T H4

MIN

= 4

; MAX

= n

/a

Asyn

chro

nous

RTT

TUR

N-O

FF d

elay

(PO

WER

-DO

WN

with

DLL

OFF

)t AO

FPD

MIN

= 2

; MAX

= 8

.5

t AON

RTT

TURN

-OFF

from

ODT

L OFF

refe

renc

et AO

F

Asyn

chro

nous

RTT

TUR

N-O

N de

lay

(PO

WER

-DO

WN

with

DLL

OFF

)t AO

NPD

MIN

= 2

; MAX

= 8

.5

ODT

Tim

ing

Dyna

mic

ODT

Tim

ing

WRI

TE Le

velin

g Ti

min

g

RTT

sync

hron

ous T

URN-

ON

dela

yOD

TL o

nRT

T sy

nchr

onou

s TUR

N-O

FF d

elay

ODTL

off

RTT

TURN

-ON

from

ODT

L ON

refe

renc

e

Para

met

er

-25

(DDR

3-80

0)-1

9 (D

DR3-

1066

)-1

5 (D

DR3-

1333

)

CK CK ps CK CK CK CK CK CK CK ns nspspsCK CKns nsUnits

38 40 23,3

839

,40

3938 40

Note

s[C

WL=

2.5;

6-6

-6]

[CW

L=1.

875;

8-8

-8]

[CW

L=1.

5; 1

0-10

-10]

Sym

bol

MIN

MAX

-12

(DDR

3-16

00)

[CW

L=1.

25; 1

1-11

-11]

-225

225

0.3

0.7

0.3

0.7

40-

25-

07.

50

2

165

-

165

-



ST9D364M64SBG2



NOteS

1. Parametersareapplicablewith0°C≤ TA ≤+95°CandVDD/VDDQ=+1.5V±0.075V.

2. AllvoltagesarereferencedtoVss.

3. OutputtimingsareonlyvalidforRON34outputbufferselection.

4. Unit tCK(AVG)representstheactualtCK(AVG)oftheinputclockunderoper-ation.UnitCKrepresentsoneclockcycleoftheinputclock,countingtheactualclockedges.

5. ACtimingandIDDtestsmayuseaVIL-to-VIHswingofupto900mVinthetestenvironment,butinputtimingisstillreferencedtoVREF(excepttIS,tIH,tDS,andtDHusetheAC/DCtrippointsandCK,CK\andDQS,DQS\usetheircrossingpoints).Theminimumslewratefortheinputsignalsusedtotestthedeviceis1V/nsforsingle-endedinputsand2V/nsfordifferentialinputsintherangebetweenVIL(AC)andVIH(AC).

6. Alltimingsthatusetime-basedvalues(ns,µs,ms)shouldusetCK(AVG)todeterminethecorrectnumberofclocks(Table47usesCKorCK(AVG)inter-changeably).Fornon-intergerresults,allminimumlimitsaretoberoundeduptothenearestwholeinteger.

7. TheuseofSTROBEorDQSDIFFreferstotheDQSandDQS\differentialcross-ingpointwhenDQSistherisingedge.TheuseofCLOCKorCKreferstotheCKandCK\differentialcrossingpointwhenCKisthe risingedge.

8. ThisoutputloadisusedforallACtiming(exceptODTreferencetiming)andslewrates.Theactual testloadmaybedifferent.TheoutputsignalvoltagereferencepointisVDDQ/2forsingle-endedsignalsandthecrossingpointfordifferentialsignals.

9. WhenoperatinginDLLdisablemode,STACKEDdoesnotwarrantcompliancewithnormalmodetimingsorfunctionality.

10. Theclock’stCK(AVG)istheaverageclockoverany200consecutiveclocksand tCK(AVG)MINisthesmallestclockrateallowed,withtheexceptionofadeviationduetoclockjitter.Inputclockjitter is allowed provided itdoesnotexceedvaluesspecifiedandmustbeofarandomGaussiandistribu-tion in nature.

11. Spreadspectrumisnotincludedinthejitterspecificationvalues.However,theinputclockcanaccommodatespread-spectrumatasweeprateintherangeof20-60kHzwithandadditional1%oftCK(AVG)asalong-termjittercomponent;however,thespread-spectrummaynotuseaclockratebelowtCK(AVG)MIN.

12. Theclock’stCH(AVG)andtCL(AVG)aretheaveragehalfclockperiodoverany200consecutiveclocksandisthesmallestclockhalfperiodallowed,withtheexceptionofvaluesspecifiedandmustofarandomGaussiandistributioninnature.

13. Theperiodjitter(tJITPER)isthemaximumdeviationintheclockperiodfromtheaverageornominalclock.Itisallowedineitherthepositiveornegativedirection.

14. tCH(ABS)istheabsoluteinstantaneousclockhighpulsewidthasmeasuredfromonerisingedgetothefollowingfallingedge.

15. tCL(ABS)istheabsoluteinstantaneousclocklowpulsewidthasmeasuredfromonefallingedgetothefollowingrisingedge.

16. Thecycle-to-cyclejitter(tJITCC)istheamounttheclockperiodcandeviatefromonecycletothenext.Itisimportanttokeepcycle-to-cyclejitterataminimumduringtheDLLlockingtime.

17. The cumulative jitter error (tERRnPER), where n is the number ofclocksbetween2and50,istheamountofclocktimeallowedtoaccu-mulateconsecutivelyaway from theaverageclockovernnumberofclockcycles.

18. tDS(base)andtDH(base)valuesareforasingle-ended1V/nsDQslewrateand2V/nsfordifferentialDQS,DQS\slewrate.

19. Theseparametersaremeasuredfromadatasignal(DM,DQ0,DQ1…DQnandsoforth) transitionedgeto itsrespectivedatastrobesignal(DQS,DQS\)crossing.

20. Thesetupandholdtimesarelistedconvertingthebasespecificationvalues(towhichderatingtablesapply)toVREFwhentheslewrateis1V/ns.Thesevalues,withaslewrateof1V/nsareforreferenceonly.

21. Whenthedeviceisoperatedwithinputclockjitter,thisparameterneedstobederatedbytheactualtJITPER(largeroftJITPER(MIN)ortJITPER(MAX)oftheinputclock(outputderatingsarerelativetotheSDRAMinputclock).

22. Single-endedsignalparameter.

23. Theoutputtimingisalignedtothenominaloraverageclock.Outputparametersmustbederatedbytheactualjittererrorwheninputclockjitterispresent,evenwhenwithinspecification.Thisresultsineachparameterbecominglarger.ThefollowingparametersarerequiredtobederatedbysubtractingtERRI0PER(MAX);tDQSCK(MIN),tLZ(DQS)MIN,tLZ(DQ)MAX,and tAON(MIN).ThefollowingparametersarerequiredtobederatedbysubtractingtERRI0PER(MIN);tDQSCK(MAX),tLZ(DQS)MAX,tLZ(DQ)MAX,and tAON(MAX).TheparametertRPRE(MIN)isderatedbysubtractingtJITPER (MAX),whiletRPRE(MAX)isderatedbysubtractingtJITPER(MIN).

24. ThemaximumpreambleisboundbytLZDQS(MAX).

25. Theseparametersaremeasuredfromadatastrobesignal(DQS,DQS\)crossingtoitsrespectiveclocksignal(CK,CK\)crossing.Thespeci-fication valuesarenot affectedby theamount of clock jitter applied,as theseare relative to theclocksignalcrossing. Theseparametersshouldbemetwhetherclockjitterispresentornot.

26. ThetDQSCKDLL_DISparameterbeginsCL+AL-1cyclesaftertheREADcommand.

27. ThemaximumpostambleisboundbytHZDQS(MAX).

28. Commandsrequiringa lockedDLLare:READ(andRDAP)andsyn-chronousODT commands. In addition, after any change of latencytXPDLL,timingmustbemet.

29. tIS(base)andtIH(base)valuesareforasingle-ended1V/nscontrol/command/addressslewrateand2V/nsCK,CK#differentialslewrate.

30. Theseparametersaremeasuredfromacommand/addresssignaltran-sitionedgetoitsrespectiveclock(CK,CK\)signalcrossing.Thespeci-fication values are not affected by the amount of clock jitter appliedas thesetupandhold timesare relative to theclocksignal crossingthatlatchesthecommand/address.Theseparametersshouldbemetwhetherclockjitterispresentornot.

31. Fortheseparameters,thedevicesupportstnPARAM(nCK)=RU(tPARAM[ns]/tCK[AVG][ns]),assumingallinputclockjitterspecificationsaresatisfied.Forexample,thedevicewillsupporttnRP(nCK)=RU(tRP)/tCK[AVG])ifallinputclockjitterspecificationsaremet.ThismeansforDDR2-800;6-6-6,ofwhichtRP=15ns,thedevicewillsupporttnRP=RU(tRP/tCK[AVG])=6aslongastheinputclockjitterspecificationsaremet.Thatis,thePRECHARGEcommandatT0andtheACTIVATEcommandatT0+6arevalidevenifsix



ST9D364M64SBG2



NOteS cONtiNued

clocksarelessthan15nsduetoinputclockjitter.

32. During READs and WRITEs with AUTO PRECHARGE, the DDR3SDRAMwill holdoff the internalPRECHARGEcommanduntil tRAS (MIN)hasbeensatisfied.

33. Whenoperating inDLLdisablemode, thegreaterof4CKor15ns issatisfiedfortWR.

34. Thestartofthewriterecoverytimeisdefinedasfollows:

•ForBL8(fixedbyMRSandOTF):RisingclockedgefourclockcyclesafterWL.

•ForBC4(OTF):RisingclockedgefourclockcyclesafterWL.

•ForBC4(fixedbyMRS):RisingclockedgetwoclockcyclesafterWL.

35. RESET\shouldbeLOWassoonaspowerstartstoramptoensuretheoutputsareinHIGH-ZUntilRESET\isLOW,theoutputsareatriskofdrivingthebusandcouldresultinexcessivecurrent,dependingonthebusactivity.

36. The refreshperiod is64mswhenTA is less thanorequal to85°C.Thisequatestoanaveragerefreshrateof7.8124µs.However,nineREFRESHcommandsshouldbeassertedatleastonceevery70.3µs.WhenTAisgreaterthan85°C,therefreshperiodis32msandwhenTAisgreaterthan105°C,therefreshperiodis24ms.

37. AlthoughCKEisallowedtoberegisteredLOWafteraREFRESHcommandwhentREFPDEN(MIN)issatisfied,therearecaseswhereadditionaltimesuchastXPDLL(MIN)isrequired.

38. ODTturn-ontimeMINiswhenthedeviceleavesHIGH-ZandODTresis-

tancebeginstoturnon.ODTturn-ontimemaximumiswhentheODTresistanceisfullyon.TheODTreferenceloadisshowninFigure23.

39. Half-clockoutputparametersmustderatedbytheactualtERRI0PERandtJITDTYwheninputclockjitterispresent.Thisresultsineachparameterbecominglarger.TheparameterstADC(MIN)andtAOF(MIN)areeachrequiredtobederatedbysubtractingbothtERRI0PER(MAX)andtJITDTY (MAX).TheparameterstADC(MAX)andtAOF(MAX)arerequiredtobederatedbysubtractingbothtERRI0PER(MAX)andtJITDTY(MAX).

40. ODTturn-offtimeminimumiswhenthedevicestartstoturnoffODTresistance.ODTturn-off timemaximumiswhentheSDRAMbufferis inHIGH-Z.TheODTreferenceloadisshowninFigure24. ThisoutputloadisusedforODTtimings(seeFigure31).

41. Pulsewidth of an input signal is defined as thewidth between thefirstcrossingofVREF(DC)andtheconsecutivecrossingofVREF(DC).

42. ShouldtheclockratebelargerthantRFC(MIN),anAUTOREFRESHcommandshouldhaveat leastoneNOPcommandbetween itandanother AUTOREFRESH command. Additionally, if the clock rateisslowerthan40ns(25MHz)allREFRESHcommandsshouldbefol-lowedbyaPRECHARGEALLcommand.



ST9D364M64SBG2



COMMAND AND ADDRESS SETUP, HOLD, AND DERATING

ThetotaltIS(setuptime)andtIH(holdtime)requirediscalculatedbyaddingthedatasheettIS(base)andtIH(base)values(Tables48)tothe∆tIS and ∆tIHderatingvalues(Table49),respectively.Set-upandholdtimesarebasedonmeasurementsatthedevice.Notethataddressandcontrolpinspresentthecapacitanceofmultipledietothesystem.Thiscapacitanceislessthantheequivalentnumberofdiscretedevicesduetothehigherlevelofdieintegration;however,itmustbeaccountedforwhendrivingthesepins.Slewratesonthesepinswillbeslowerthanpinswithonlyonedieloadunlessmeasuresaremadetoincreasethestrengthofthesignaldriverandlowerthetraceimpedanceproportionallyonsignalsconnectingtomultipleinternal die.

Althoughthetotalsetuptimeforslowslewratesmightbenegative,avalidinputsignalisstillrequiredtocompletethetransi-tionandtoreachVIH(AC)/VIL(AC)(seeFigure14forinputsignalrequirements).ForslewrateswhichfallbetweenthevalueslistedinTable49andTable50,thederatingvaluesmaybeobtainedbylinearinterpolation.

Setup(tIS)nominalslewrateforarisingsignalisdefinedastheslewratebetweenthelastcrossingofVREF(DC)andthefirstcrossingofVIH(AC)MIN.Setup(tIS)nominalslewrateforafallingsignalisdefinedastheslewratebetweenthelastcrossingofVREF(DC)andthefirstcrossingofVIL(AC)MAX.Iftheactualsignalisalwaysearlierthanthenominalslewratelinebetweentheshaded“VREF(DC)-to-ACregion”,usethenominalslewrateforderatingvalue(seeFigure25).Iftheactualsignalislaterthanthenominalslewratelineanywherebetweentheshaded“VREF(DC)-to-ACregion”,theslewrateofatangentlinetotheactualsignalfromtheACleveltotheDClevelisusedforthederatingvalue(seeFigure27).

Hold(tIH)nominalslewrateforarisingsignalisdefinedastheslewratebetweenthelastcrossingofVIL(DC)MAXandthefirstcrossingofVREF(DC).Hold(tIH)nominalslewrateforafallingsignalisdefinedastheslewratebetweenthelastcrossingof

Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 UNITS REFERENCE tIS(base) AC175

tIS(base)(AC150)

tIH(base)DC100

VIH(AC)/VIL(AC)

VIH(AC)/VIL(AC)

VIH(AC)/VIL(AC)

table 48: cOmmaNd aNd addreSS Setup aNd hOld ValueS reFereNced at 1V/NS – ac/dc baSed

65

190

140

200

350

275

125

275

200

ps

ps

ps

∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

table 49: deratiNG ValueS FOr tiS/tih – ac175/dc100-baSed

CMD/ADDR Slew Rate V/ns

88

59

0

-2

-6

-11

-17

-35

-62

50

34

0

-4

-10

-16

-26

-40

-60

88

50

0

-2

-6

-11

-17

-35

-62

50

34

0

-4

-10

-16

-26

-40

-60

88

59

0

-2

-6

-11

-17

-35

-62

50

34

0

-4

-10

-16

-26

-40

-60

96

67

8

6

2

-3

-9

-27

-54

58

42

8

4

-2

-8

-18

-32

-52

96

67

8

6

2

-3

-9

-27

-54

66

50

16

12

6

0

-10

-24

-44

112

83

24

22

18

13

7

-11

-38

74

58

24

20

14

8

-2

-16

-36

120

91

32

30

26

21

15

-2

-30

84

68

34

30

24

18

8

-6

-26

128

99

40

38

34

29

23

5

-22

100

84

50

46

40

34

24

10

-10

4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/

CK, CK\ Differential Slew Rate

Shaded cells indicate slew-rate combinations not supported

∆tIS, ∆tIH Derating (ps) - AC/DC-Based, AC175 Threshold; VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV

45

170

120



ST9D364M64SBG2



∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

table 50: deratiNG ValueS FOr tiS/tih – ac150/dc100-baSed

CMD/ADDR Slew Rate V/ns

75

50

0

0

0

0

-1

-10

-25

50

34

0

-4

-10

-16

-26

-40

-60

75

50

0

0

0

0

-1

-10

-25

50

34

0

-4

-10

-16

-26

-40

-60

75

50

0

0

0

0

-1

-10

-25

50

34

0

-4

-10

-16

-26

-40

-60

83

58

8

8

8

8

7

-2

-17

58

42

8

4

-2

-8

-18

-32

-52

91

66

16

16

16

16

15

6

-9

66

50

16

12

6

0

-10

-24

-44

99

74

24

24

24

24

23

14

-1

74

58

24

20

14

8

-2

-16

-36

107

82

32

32

32

32

31

22

7

84

68

34

30

24

18

8

-6

-26

115

90

40

40

40

40

39

30

15

100

84

50

46

40

34

24

10

-10

4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns

CK, CK\ Differential Slew Rate

∆tIS, ∆tIH Derating (ps) - AC/DC-Based, AC150 Threshold; VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV


Slew Rate (V/ns) tVAC at 175mV(ps) tVAC >2.0

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

<0.5

175

170

167

163

162

161

159

155

150

150

table 51: miNimum reQuired time tVac abOVe Vih(ac) FOr a Valid traNSitiON

75

57

50

38

34

29

22

13

0

0

Below VIL(AC)



ST9D364M64SBG2



Notes: 1. Both the clock and the strobe are drawn on different time scales.

VSS

Setup slew raterising signal

Setup slew ratefalling signal

∆TF ∆TR

==

VDDQ

VIH(AC) MIN

VIH(DC) MIN

VREF(DC)

VIL(DC) MAX

VIL(DC) MAX

Nominalslew rate

VREF to ACregion

tVAC

tVAC

DQS

DQS#

CK#

CK

tIS t IH t IS t IH

Nominalslew rate

VREF to ACregion

VREF(DC) - VIL(AC) MAX

∆TF

VIH(AC) MIN - VREF(DC)

∆TR

FiGure 25 - NOmiNal Slew rate aNd tVac FOr tiS (cOmmaNd aNd addreSS – clOck)



ST9D364M64SBG2



FiGure 26 - NOmiNal Slew rate FOr tih (cOmmaNd aNd addreSS – clOck)


VSS

Hold slew ratefalling signal

Hold slew raterising signal

∆TR ∆TF

= =

VDDQ

VIH(AC) MIN

VIH(DC) MIN

VREF(DC)

VIL(DC) MAX

VIL(AC) MAX

Nominalslew rate

DC to VREF

region

DQS

DQS#

CK#

CK

tIS t IH t IS t IH

DC to VREF

region

Nominalslew rate

VREF(DC) - VIL(DC) MAX

∆TR

VIH(DC) MIN - VREF(DC)

∆TF



ST9D364M64SBG2



FiGure 27 - taNGeNt liNe FOr tiS (cOmmaNd aNd addreSS – clOck)


VSS



∆TF

∆TR

=

=

VDDQ

VIH(AC) MIN

VIH(DC) MIN

VREF(DC)

VIL(DC) MAX

VIL(AC) MAX

Tangentline

VREF to ACregion

Nominalline

tVAC

tVAC

DQS

DQS#

CK#

CK

tIS t IH t IS t IH

VREF to ACregion

Tangentline

Nominalline

Tangent line (VIH [DC] MIN - VREF[DC ])

∆TR

Tangent line (VREF [DC] - VIL[AC] MAX)

∆TF



ST9D364M64SBG2



FiGure 28 - taNGeNt liNe FOr tih (cOmmaNd aNd addreSS – clOck)


VSS


∆TR

=

VDDQ

VIH(AC) MIN

VIH(DC) MIN

VREF(DC)

VIL(DC) MAX

VIL(AC) MAX

Tangentline

DC to VREF

region

Hold slew raterising signal =

DQS

DQS#

CK#

CK

tIS t IH t IS t IH

DC to VREF

region

Tangentline

Nominalline

Nominalline

∆TR

Tangent line (VREF [DC] - VIL[DC] MAX)

∆TR

Tangent line (VIH [DC] MIN - VREF[DC])

∆TF



ST9D364M64SBG2



DATA SETUP, HOLD AND DERATING

Thetotal tDS(setuptime)andtDH(holdtime)requirediscalculatedbyaddingthedatasheettDS(base)andtDH(base)values(seeTable52)tothe∆tDS and ∆tDHderatingvalues(seeTable53),respectively.

Althoughthetotalsetuptimeforslowslewratesmightbenegative,avalidinputsignalisstillrequiredtocompletethetransitionandtoreachVIH/VIL(AC).ForslewrateswhichfallbetweenthevalueslistedinTable54,thederatingvaluesmaybeobtainedbylinearinterpolation.

Setup(tDS)nominalslewrateforarisingsignalisdefinedastheslewratebetweenthelastcrossingofVREF(DC)andthefirstcrossingofVIH(AC)MIN.Setup(tDS)nominalslewrateforafallingsignalisdefinedastheslewratebetweenthelastcrossingofVREF(DC)andthefirstcrossingofVIL(AC)MAX.Iftheactualsignalisalwaysearlierthanthenominalslewratelinebetweentheshaded“VREF(DC)-to-ACregion”,usethenominalslewratederatingvalue(seeFigure29).Iftheactualsignalislaterthanthenominalslewratelineanywherebetweentheshaded“VREF(DC)-to-ACregion”,theslewrateofatangentlinetotheactualsignalfromtheACleveltotheDClevelisusedforthederatingvalue(seeFigure31).

Hold(tDH)nominalslewrateforarisingsignalisdefinedastheslewratebetweenthelastcrossingofVIL(DC)MAXandthefirstcrossingofVREF(DC).Hold(tDH)nominalslewrateforafallingsignalisdefinedastheslewratebetweenthelastcrossingofVIH(DC)MINandthefirstcrossingofVREF(DC).Iftheactualsignalisalwayslaterthanthenominalslewratelinebetweentheshaded“DC-to-VREF(DC)region”,usethenominalslewrateforderatingvalue(seeFigure30).Iftheactualsignalisearlierthanthenominalslewratelineanywherebetweentheshaded“DC-to-VREF(DC)region”,theslewrateofatangentlinetotheactualsignalfromthe“DC-to-VREF(DC)region”,isusedforthederatingvalue(seeFigure32).

Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 UNITS REFERENCE tDS(base)AC175

tDS(base)AC150

tDS(base)DC100

VIH(AC)/VIL(AC)

VIH(AC)/VIL(AC)

VIH(AC)/VIL(AC)

table 52: data Setup aNd hOld ValueS at 1V/NS (dQSx, dQSx\ at 2V/NS) - ac/dc baSed

-

-

65

75

125

150

25

75

100

ps

ps

ps

-

-

45

∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

table 53: deratiNG Value FOr tdS/tdh – ac175/dc100 - baSed

DQSlew Rate V/ns


DQS, DQS# Differential Slew Rate

ΔtDS, ΔtDH Derating (ps) – AC175/D100-Based


88

59

0

50

34

0

88

59

0

-2

50

34

0

-4

88

59

0

-2

-6

50

34

0

-4

-10

67

8

6

2

-3

42

8

4

-2

-8

16

14

10

5

-1

16

12

6

0

-10

22

18

13

7

-11

20

14

8

-2

-16

26

21

15

-2

-30

24

18

8

-6

-26

29

23

5

-22

34

24

10

-10

∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

table 54: deratiNG Value FOr tdS/tdh – ac150/dc100 - baSed

DQ Slew Rate V/ns


DQS, DQS# Differential Slew Rate

ΔtDS, ΔtDH Derating (ps) – AC150/DC100-Based




ST9D364M64SBG2



75

50

0

50

34

0

75

50

0

0

50

34

0

-4

75

50

0

0

0

50

34

0

-4

-10

58

8

8

8

8

42

8

4

-2

-8

16

16

16

16

15

16

12

6

0

-10

24

24

24

23

14

20

14

8

-2

-16

32

32

31

22

7

24

18

8

-6

-26

40

39

30

15

34

24

10

-10

Slew Rate (V/ns) tVAC at 175mV(ps) [MIN] tVAC >2.0

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

<0.5

175

170

167

163

162

161

159

155

150

150

table 55: reQuired time tVac abOVe Vih(ac) (belOw Vil[ac]) FOr a Valid traNSitiON

75

57

50

38

34

29

22

13

0

0



ST9D364M64SBG2



FiGure 29 - NOmiNal Slew rate aNd tVac FOr tdS (dQ – StrObe)


VSS


Setup slew rate

∆TF ∆TR

= =

VDDQ

VIH(AC) MIN

VIH(DC) MIN

VREF(DC)

VIL(DC) MAX

VIL(AC) MAX

Nominalslew rate

VREF to AC region

tVAC

tVAC

tDHtDS

DQS

DQS#

tDHtDS

CK#

CK

VREF to AC region

Nominalslew rate

VIH(AC) MIN - VREF (DC)

∆TR

VREF(DC) - VIL(AC) MAX

∆TFrising signal



ST9D364M64SBG2



FiGure 30 - NOmiNal Slew rate FOr tdh (dQ – StrObe)


VSS


Hold slew raterising signal

∆TR ∆TF

==

VDDQ

VIH(AC) MIN

VIH(DC) MIN

VREF(DC)

VIL(DC) MAX

VIL(AC) MAX

Nominalslew rateDC to VREF

region

tDHtDS

DQS

DQS#

tDHtDS

CK#

CK

DC to VREF

region

Nominalslew rate

VREF(DC) - VIL(DC) MAX

∆TR

VIH(DC) MIN - VREF(DC)

∆TF



ST9D364M64SBG2



FiGure 31 - NOmiNal Slew rate aNd tVac FOr tdS (dQ – StrObe)


VSS



∆TF

∆TR

=

=

VDDQ

VIH(AC) MIN

VIH(DC) MIN

VREF(DC)

VIL(DC) MAX

VIL(AC) MAX

Tangentline

VREF to ACregion

Nominalline

tVAC

tVAC

tDHtDS

DQS

DQS#

tDHtDS

CK#

CK

VREF to ACregion

Tangentline

Nominalline

∆TR

Tangent line (VREF[DC] - VIL[AC] MAX)

∆TF

Tangent line (V IH[AC] MIN - VREF [DC])



ST9D364M64SBG2



FiGure 32 - NOmiNal Slew rate FOr tdh (dQ – StrObe)


VSS


∆TF∆TR

=

VDDQ

VIH(AC) MIN

VIH(DC) MIN

VREF(DC)

VIL(DC) MAX

VIL(AC) MAX

Tangentline

DC to VREF

region

Hold slew rate=

DQS

DQS#

CK#

CK

DC to VREF

region

Tangentline

Nominalline

Nominalline

Tangent line (VIH [DC] MIN - VREF[DC])

∆TF

Tangent line (VREF[DC] - VIL[DC] MAX)

∆TR

tDS tDH tDS tDH

falling signal



ST9D364M64SBG2




Function Symbol Cycle Cycle CS\ RAS\ CAS\ WE\ BA[2:0] An A12

Mode Register Set

REFRESH

SELF REFRESH entry

SELF REFRESH exit

Single-Bank PRECHARGE

PRECHARGE all banks

Bank ACTIVATE

NO OPERATION

Device DESELECTED

POWER-DOWN entry

POWER-DOWN exit

ZQ CALIBRATION LONG

ZQ CALIBRATION SHORT

6

6,7

8

8

8

8

8

8

8

8

8

8

8

8

9

10

6

6,11

12

table 56: truth table - cOmmaNd

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

H

H

H

H

H

H

H

H

H

H

H

H

H

X

H

H

L

L

L

L

L

L

H

H

H

H

H

H

H

H

H

H

H

H

H

X

H

H

L

H

H

L

L

H

L

L

L

L

L

L

H

H

H

H

H

H

H

X

L

L

BA

V

V

V

VBA

V

BA

BA

BA

BA

BA

BA

BA

BA

BA

BA

BA

BA

BA

V

X

V

V

X

X

V

V

V

V

V

RFU

RFU

RFU

RFU

RFU

RFU

RFU

RFU

RFU

RFU

RFU

RFU

V

X

V

V

X

X

V

V

V

V

V

V

L

H

V

L

H

V

L

H

V

L

H

V

X

V

V

X

X

V

V

V

L

H

L

L

L

H

H

H

L

L

L

H

H

H

V

X

V

V

H

L

V

V

V

V

V

RA

CA

CA

CA

CA

CA

CA

CA

CA

CA

CA

CA

CA

V

X

V

V

X

X

MRS

REF

SRE

SRX

PRE

PREA

ACT

WR

WRS4

WRS8

WRAP

WRAPS4

WRAPS8

RD

RDS4

RDS8

RDAP

RDAPS4

RDAPS8

NOP

DES

PDE

PDX

ZQCL

ZQCS

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

WRITE

WRITE with AUTO

PRECHARGE

READ

READ with AUTO

PRECHARGE

BL8MRSBC4MRS

BC4OTF

BL8OTF

BL8MRSBC4MRS

BC4OTF

BL8OTF

BL8MRSBC4MRS

BC4OTF

BL8OTF

BL8MRSBC4MRS

BC4OTF

BL8OTF

HL

LHLH

VH

VH

VH

HV

HV

HV

HV

HV

HV

CKE

Prev Next

8. Burst READs orWRITEs cannot be terminated or interrupted,MRS

(fixed)andOTFBL/BCaredefinedinMR0.

9. ThepurposeoftheNOPcommandistopreventtheDRAMfromregistering

anyunwantedcommands.ANOPwillnotterminateandoperationthatis

inexecution.

10. TheDESandNOPcommandsperformsimilarly.

11. ThePOWER-DOWNmode does not perform anyREFRESHopera-

tions.

12. ZQCALIBRATIONLONG isused foreitherZQINT (firstZQCLcom-

mandduringinitialization)orZQOPER(ZQCLcommandafterinitializa-

tion).

NOTES:1. CommandsaredefinedbystatesofCS\,RAS\,CAS\,WE\,andCKEat

therisingedgeof theclock. TheMSBofBA,RA,andCAaredevice-

densityandconfiguration-dependent.

2. RESET\isLOWenabledandusedonlyforasynchronousRESET.Thus,

RESET\mustbeheldHIGHduringanynormaloperation.

3. ThestateofODTdoesnotaffectthestatesdescribedinthistable.

4. Operationsapplytothebankdefinedbythebankaddress.ForMRS,BA

selectsoneoffourmoderegisters.

5. “V”means“H”or“L”(adefinedlogiclevel),and“X”means“Don’tCare”.

6. SeeTable57foradditionalinformationonCKEtransition.

7. SELFREFRESHexitisasynchronous.

COMMANDS TRUTH TABLE



ST9D364M64SBG2



Current State 3 POWER-DOWN

SELF REFRESH

Bank(s) ACTIVE

READING

WRITING

PRECHARGING

REFRESHING

All Banks IDLE

table 57: truth table - cke

L

H

L

H

L

L

L

L

L

L

(n-1)

Previous Cycle 4 (n)

Present Cycle 4 (RAS\, CAS\, WE\, CS\)

Command 5 Action 5 NotesL

L

L

H

H

H

H

H

H

H

“Don’tCare”

DESorNOP

“Don’tCare”

DESorNOP

DESorNOP

DESorNOP

DESorNOP

DESorNOP

DESorNOP

REFRESH

MaintainPOWER-DOWN

POWER-DOWNexit

MaintainSELFREFRESH

SELFREFRESHexit

ActivePOWER-DOWNentry

POWER-DOWNentry

POWER-DOWNentry

PRECHARGEPOWER-DOWNentry

PRECHARGEPOWER-DOWNentry

SELFREFRESH

1,2

1,2

1,2

1,2

1,2

1,2

1,2

1,2

1,2,6

CKE

4. CKE(n)isthelogicstateofCKEatclockedgen,CKE(n-1)wasthe

stateofCKEatthepreviousclockedge.

5. COMMANDisthecommandregisteredat theclockedge(mustbea

legal command as defined inTable 56). Action is a result ofCOM-

MAND.ODTdoesnotaffectthestatesdescribedinthistableandis

notlisted.

6. Idlestate=allbanksareclosed,nodataburstsareinprogress,CKEis

HIGHandalltimingsfrompreviousoperationsaresatisfied.AllSELF

REFRESHexitandPOWER-DOWNexitparametersarealsosatisfied.

NOTES:

1. Allstatesandsequencesnotshownareillegalorreservedunlessexplic-

itlydescribedelsewhereinthisdocument.2. tCKE(MIN)meansCKEmustberegisteredatmultipleconsecutiveposi-

tiveclockedges.CKEmustremainatthevalidinputleveltheentiretime

ittakestoachievetherequirednumberofregistrationclocks.Thus,after

anyCKEtransition,CKEmaynottransitionfromitsvalidlevelduringthe

timeperiodoftIS+tCKE(MIN)+tIH.

3. Currentstate=ThestateoftheSDRAMimmediatelypriortoclockedge

n.

DESELECT (DES)

TheDEScommand(CS\HIGH)preventsnewcommandsfrombeingexe-cutedbytheSDRAM.Operationsalreadyinprogressarenotaffected.

NO OPERATION (NOP)

TheNOPcommand(CS\LOW)preventsunwantedcommandsfrombeingregisteredduring idleorwaitstates. Operationsalready inprogressarenotaffected.

ZQ CALIBRATION

ZQ Calibration LONG (ZQCL)

TheZQCLcommandisusedtoperformtheinitialcalibrationduringapower-upinitializationandresetsequence.Thiscommandmaybeissuedatanytimebythecontrollerdependingonthesystemenvironment.TheZQCLcommandtriggersthecalibrationengineinsidetheSDRAM.Aftercalibrationisachieved,thecalibratedvaluesaretransferredfromthecalibrationenginetotheSDRAMI/O,whicharereflectedasupdatedRONandODTvalues.

TheSDRAMisallowedatimingwindowdefinedbyeithertZQINITortZQOPERtoperformthefullcalibrationandtransferofvalues.WhenZQCLisissuedduringtheinitializationsequence,thetimingparametertZQINITmustbesatisfied.Wheninitializationiscomplete,subsequentZQCLcommandsrequirethetimingparametertZQOPERtobesatisfied.

ZQ Calibration SHORT (ZQCS)

TheZQCScommandisusedtoperformperiodiccalibrationstoaccountforsmallvoltageandtemperaturevariations.TheshortertimingwindowisprovidedtoperformthereducedcalibrationandtransferofvaluesasdefinedbytimingparametertZQCS.AZQCScommandcaneffectivelycorrectaminimumof0.5%RON and RTTimpedanceerrorswithin64clockcycles,assumingthemaximumsensitivitiesspecifiedinTable37andTable38.



ST9D364M64SBG2



ACTIVATE

TheACTIVATEcommandisusedtoopen(orACTIVATE)arowinaparticularbankforasubsequentaccess.ThevalueontheBA[2:0]inputsselectsthebank,andtheaddressprovidedoninputsA[n:0]selectstherow.Thisrowremainsopen(orACTIVE)foraccessesuntilaPRECHARGEcommandisissuedtothatbank.

APRECHARGEcommandmustbeissuedbeforeopeningadiffer-entrowinthesamebank.

READ

TheREADcommandisusedtoinitiateaburstREADaccesstoanACTIVErow.TheaddressprovidedoninputsA[2:0]selectsthestartingcolumnaddressdependingontheburstlengthandbursttypeselected.ThevalueoninputA10determineswhetherornotautoprechargeisused.Ifautoprechargeisselected,therowbeingaccessedwillbePRECHARGEDattheendoftheREADburst.IfAUTOPRE-CHARGEisnotselected,therowwillremainopenforsubsequentaccesses.ThevalueoninputA12(ifenabledintheMODEREGIS-TER)whentheREADcommandisissued,determineswhetherBC4(chop)orBL8isused.AfteraREADcommandisissued,theREADburstmaynotbeinterrupted.AsummaryofREADcommandsisshowninTable58.

table 58: read cOmmaNd Summary


L

L

L

L

L

L

H

H

H

H

H

H

L

L

L

L

L

L

H

H

H

H

H

H

BA

BA

BA

BA

BA

BA

RFU

RFU

RFU

RFU

RFU

RFU

V

L

H

V

L

H

L

L

L

H

H

H

CA

CA

CA

CA

CA

CA

RD

RDS4

RDS8

RDAP

RDAPS4

RDAPS8

H

H

H

H

H

H

CKE

Prev Next

READ

READ with AUTO

PRECHARGE

BL8MRSBC4MRS

BC4OTF

BL8OTF

BL8MRSBC4MRS

BC4OTF

BL8OTF

WRITE

TheWRITEcommandisusedtoinitiateaburstWRITEaccesstoanACTIVErow.ThevalueontheBA[2:0]inputsselectsthebank.ThevalueoninputA10determineswhetherornotAUTOPRECHARGEisused.ThevalueoninputA12(ifenabledintheMODEREGISTER[MR])whentheWRITEcommandisissued,determineswhetherBC4(chop)orBL8isused.TheWRITEcommandsummaryisshowninTable62.

table 59: write cOmmaNd Summary


L

L

L

L

L

L

H

H

H

H

H

H

L

L

L

L

L

L

L

L

L

L

L

L

BA

BA

BA

BA

BA

BA

RFU

RFU

RFU

RFU

RFU

RFU

V

L

H

V

L

H

L

L

L

H

H

H

CA

CA

CA

CA

CA

CA

WR

WRS4

WRS8

WRAP

WRAPS4

WRAPS8

H

H

H

H

H

H

CKE

Prev Next

WRITE

WRITE with AUTO

PRECHARGE

BL8MRSBC4MRS

BC4OTF

BL8OTF

BL8MRSBC4MRS

BC4OTF

BL8OTF



ST9D364M64SBG2



ThePRECHARGEcommandisusedtoDEACTIVATEtheopenrowinaparticularbankorinallbanks.Thebank(s)areavailableforasub-sequentrowaccessataspecifiedtime(tRP)afterthePRECHARGEcommandisissued,exceptinthecaseofconcurrentAUTOPRE-CHARGE.AREADorWRITEcommandtoadifferentbankisallowedduringconcurrentAUTOPRECHARGEaslongasitdoesnotinterruptthedatatransferinthecurrentbankanddoesnotviolateanyothertimingparameters.InputA10determineswhetheroneorallbanksareprecharged.Inthecasewhereonlyonebankisrecharged.InputsBA[2:0]selectthebank;otherwise,BA[2:0]aretreatedas“Don’tCare”.AfterabankisPRECHARGED,itisintheidlestateandmustbeacti-vatedpriortoanyREADorWRITEcommandsbeingissuedtothatbank.APRECHARGEcommandistreatedasaNOPifthereisnoopenrowinthatbank(idlestate)orifthepreviouslyopenrowisalreadyintheprocessofprecharging.However,thePRECHARGEperiodisdeterminedbythelastPRECHARGEcommandissuedtothebank.

PRECHARGE

REFRESHisusedduringnormaloperationoftheSDRAMandisanalo-goustoCAS\-beforeRAS\(CBR)refreshorAUTOREFRESH.Thiscom-mandisnon-persistent,soitmustbeissuedeachtimeaREFRESHisrequired.TheaddressingisgeneratedbytheinternalREFRESHcom-mand.TheSDRAMrequiresREFRESHcyclesatanaverageintervalof7.8µs(maximumwhenTA≤85°Cor3.9µsMAXwhenTA≤95°C).TheREFRESHperiodbeginswhentheREFRESHcommandisregisteredandendstRFC(MIN)later.

Toallowforimprovedefficiencyinschedulingandswitchingbetweentasks,someflexibilityintheabsoluteREFRESHintervalisprovided.AmaximumofeightREFRESHcommandscanbepostedtoanygivenSDRAM,meaningthatthemaximumabsoluteintervalbetweenanyREFRESHcommandandthenextREFRESHcommandisninetimesthemaximumaverageintervalrefreshrate.SELFREFRESHmaybeenteredwithuptoeightREFRESHcommandsbeingposted.AfterexitingSELFREFRESH(whenenteredwithpostedREFRESHcommands)additionalpostingofREFRESHcommandsisallowedtotheextentthemaximumnumberofcumulativepostedREFRESHcommands(bothpreandpostSELFREFRESH)doesnotexceedeightREFRESHcommands.

REFRESH

FiGure 33 - reFreSh mOde

Notes: 1. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH commands, but may be inactive at other times (see “Power-Down Mode”.

NOP1NOP1 NOP1PRE

RA

Bank(s) 3 BA

REF NOP1 REF2 NOP1 ACTNOP1

One bank

All banks

tCK tCH tCL

RA

tRFC2tRP tRFC (MIN)

T0 T1 T2 T3 T4 Ta0 Tb0Ta1 Tb1 Tb2

Don’t CareIndicates A Break in Time Scale

Valid 1 Valid 1 Valid 1

CK

CK#

Command

CKE

Address

A10

BA[2:0]

DQ4

DM4

DQS, DQS#4



ST9D364M64SBG2



TheSELFREFRESHcommandisusedtoretaindataintheSDRAM,eveniftherestofthesystemispowereddown.WhenintheSELFREFRESHmode,theSDRAMretainsdatawithoutexternalclocking.TheSELFREFRESHmodeisalsoaconvenientmethodusedtoenable/disabletheDLLaswellastochangetheclockfrequencywithintheallowedsynchronousoperatingrange.Allpowersupplyinputs(includingVREFCAandVREFDQ)mustbemaintainedatvalidlevelsuponentry/exitandduringSELFREFRESHmodeoperation.Allpowersupplyinputs(includingVREFCAandVREFDQ)mustbemaintainedatvalidlevelsuponentry/exitandduringSELFREFRESHmodeundercertainconditions:

•Vss<VREFDQ<VDDismaintained•VREFDQisvalidandstablepriortoCKEgoingbackHIGH•ThefirstWRITEoperationmaynotoccurearlierthan512clocksafterVREFDQisvalid•AllotherSELFREFRESHmodeexittimerequirementsaremet.

SELF REFRESH

IftheDLLisdisabledbytheMODEREGISTER(MR1[0]canbeswitchedduringinitializationorlater),theSDRAMistargeted,butnotguaranteedtooperatesimilarlytotheNORMALmodewithafewimportantexceptions:

• TheSDRAMsupportsonlyonevalueofCASlatency(CL=6)andonevalueofCASWRITElatency(CWL=6).• DLLDISABLEmodeaffectstheREADdataclock-to-datastroberelationship(tDQSCK),butnottheREADdata-to-datastroberelationship(tDQSQ,tQH).SpecialattentionisneededtolinetheREADdataupwiththecontrollertimedomainwhentheDLLisdisabled.

• InNORMALoperation(DLLon),tDQSCKstartsfromtherisingclockedgeAL+CLcyclesaftertheREADcommand.InDLLDISABLEmode,tDQSCKstartsAL=CL–1cyclesaftertheREADcommand.Additionally,withtheDLLdisabled,thevalueoftDQSCKcouldbelargerthantCK.

TheODTfeatureisnotsupportedduringDLLDISABLEmode(includingdynamicODT).TheODTresistorsmustbedisabledbycontinuouslyregisteringtheODTballLOWbyprogrammingRTT_NORMMR1[9,6,2]andRTT_WRMR2[10,9]to“0”whileinDLLDISABLEmode.

SpecificstepsmustbefollowedtoswitchbetweentheDLLenableandDLLDISABLEmodesduetoagapintheallowedclockratesbetweenthetwomodes(tCK[AVG]MAXandtCK[DLLDISABLE]MIN,respectively).TheonlytimetheclockisallowedtocrossthisclockrategapisduringSELFREFRESHmode.Thus,therequiredprocedureforswitchingfromtheDLLENABLEtoDLLDISABLEmodeistochangefrequencycuringselfrefresh(seeFigure34):

1. StartingfromtheIDLEstate(allbanksarePRECHARGED,alltimingsarefulfilled,ODTisturnedoff,andRTT_NOMandRTT_

DLL DISABLE MODE



ST9D364M64SBG2



FiGure 34 - dll eNable mOde tO dll diSable mOde

Command

T0 T1 Ta0 Ta1 Tb0 Tc0

76

Td0 Td1 Te0 Te1 Tf0

CKCK#

ODT9 Valid1

Don’t Care

Valid1

SRE3 NOPMRS2 NOP SRX4 MRS5 Valid1NOP NOP

Indicates a Break in Time Scale

tMOD tCKSRE tMODtXS

tCKESR

CKE

tCKSRX8

NOTES:

1. Anyvalidcommand.

2. DisableDLLbysettingMR1[0]to“1.”

3. WaittXS,thensetMR1[0]to“0”toenableDLL.

4. WaittMRD,thensetMR0[8]to“1”tobeginDLLRESET.

5. WaittMRD,updateregisters(CL,CWL,andwriterecoverymaybenecessary).

6. WaittMOD,anyvalidcommand.

7. Startingwiththeidlestate.

8. Changefrequency.

9. ClockmustbestableatleasttCKSRX.

10. StaticLOWincaseRTT_NOM or RTT_WRisenabled;otherwise,staticLOWorHIGH.

AsimilarprocedureisrequiredforswitchingfromtheDLLdisablemodebacktotheDLLenablemode.Thisalsorequireschangingthefre-quencyduringselfrefreshmode(seeFigure44onpage99).

1.Startingfromtheidlestate(allbanksareprecharged,alltimingsarefulfilled,ODTisturnedoff,andRTT_NOMandRTT_WRareHigh-Z),enterselfrefreshmode.

2.AftertCKSREissatisfied,changethefrequencytothenewclockrate.

3.SelfrefreshmaybeexitedwhentheclockisstablewiththenewfrequencyfortCKSRX.AftertXSissatisfied,updatethemoderegisterswiththeappropriatevalues.Ataminimum,setMR1[0]to“0”toenabletheDLL.WaittMRD,thensetMR0[8]to“1”toenableDLLRESET.

4.AfteranothertMRDdelayissatisfied,thenupdatetheremainingmoderegisterswiththeappropriatevalues.

5.TheDRAMwillbereadyforitsnextcommandintheDLLenablemodeafterthegreateroftMRD or tMODhasbeensatis-fied.However,beforeapplyinganycommandorfunctionrequiringalockedDLL,adelayoftDLLKafterDLLRESETmustbesatisfied.AZQCLcommandshouldbeissuedwiththeappropriatetimingsmetaswell.



ST9D364M64SBG2



FiGure 35- dll diSable mOde tO dll eNable mOde


tC

tDLLK

CKE

T0 Ta0 Ta1 Tb0 Tc0 Tc1 Td0 Te0 Tf0 Tg0

CKCK#

ODT10

SRE1 NOPCommand NOP SRX2 MRS3 MRS4 MRS5 Valid6

Valid

Don’t Care

87 tCKSRE

Th0

tCKSRX9

ODTL off + 1 × tCK

tXS tMRD tMRD

KESR

NOTES:

1. EnterSELFREFRESH.

2. ExitSELFREFRESH.

3. WaittXS,thensetMR1[0]to“0”toenableDLL.

4. WaittMRD,thensetMR0[8]to“1”tobeginDLLRESET.

5. WaittMRD,updateregisters(CL,CWL,andwriterecoverymaybenecessary).

6. WaittMOD,anyvalidcommand.

7. Startingwiththeidlestate.

8. Changefrequency.

9. ClockmustbestableatleasttCKSRX.

10. StaticLOWincaseRTT_NOM or RTT_WRisenabled;otherwise,staticLOWorHIGH.

TheclockfrequencyrangefortheDLLdisablemodeisspecifiedbytheparametertCKDLL_DIS.Duetolatencycounterandtimingrestrictions,onlyCL=6andCWL=6aresupported.

DLLdisablemodewillaffectthereaddataclocktodatastroberelationship(tDQSCK)butnotthedatastrobetodatarelationship(tDQSQ,tQH).Specialattentionisneededtothecontrollertimedomain.

ComparedtotheDLLonmodewheretDQSCKstartsfromtherisingclockedgeAL+CLcyclesaftertheREADcommand,theDLLdisablemodetDQSCKstartsAL+CL-1cyclesaftertheREADcommand(seeFigure45onpage100).

WRITEoperationsfunctionsimilarlybetweentheDLLenableandDLLdisablemodes;however,ODTfunctionalityisnotallowedwithDLLdisablemode.



ST9D364M64SBG2



FiGure 36 - dll diSable tdQSck timiNG

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

Don’t CareTransitioning Data

Valid

NOPREAD NOP NOP NOP NOP NOP NOP NOP NOP NOP

CK

CK#

Command

Address

DI b + 3

DI b + 2

DI b + 1

DI b

DI b + 7

DI b + 6

DI b + 5

DI b + 4

DQ BL8 DLL on

DQS, DQS# DLL on

DQ BL8 DLL disable

DQS, DQS# DLL off

DQ BL8 DLL disable

DQS, DQS# DLL off

RL = AL + CL = 6 (CL = 6, AL = 0)

CL = 6

DI b + 3

DI b + 2

DI b + 1

DI b

DI b + 7

DI b + 6

DI b + 5

DI b + 4

DI b + 3

DI b + 2

DI b + 1

DI b

DI b + 7

DI b + 6

DI b + 5

DI b + 4

tDQSCK (DLL_DIS) MIN

tDQSCK (DLL_ DIS) MAX

RL (DLL disable) = AL + (CL - 1) = 5

WhentheDRAMisinitialized,itrequirestheclocktobestableduringmostNORMALstatesofoperation.Thismeansthataftertheclockfrequencyhasbeensettothestablestate,theclockperiodisnotallowedtodeviateexceptwhatisallowedforbytheclockjitterandspreadspectrumclocking(SSC)specifications.

Theinputclockfrequencycanbechangedfromonestableclockratetoanotherundertwoconditions:SELFREFRESHmodeandPRECHARGEpower-downmode.Outsideofthesetwomodes,itisillegaltochangetheclockfrequency.FortheSELFREFRESHmodecondition,whentheDDR3SDRAMhasbeensuccessfullyplacedintoSELFREFRESHmodeandtCKSREhasbeensatisfied,thestateoftheclockbecomesa“Don’tCare”.Whentheclockbecomesa“Don’tCare”,changingtheclockfrequencyispermissible,providedthenewclockfrequencyisstablepriorto tCKSRX.Whenenteringandexitingselfrefreshmodeforthesolepurposeofchangingtheclockfrequency,theSELFREFRESHentryandexitspecificationsmuststillbemet.

ThePRECHARGEpower-downmodeconditioniswhentheDRAMisinPRECHARGEpower-downmode(eitherfastexitmodeorslowexitmode).EitherODTmustbeatalogicLOWorRTT_NOMandRTT_WRmustbedisabledviaMR1andMR2.ThisensuresRTT_NOMandRTT_WRareinanoffstatepriortoenteringPRECHARGEpower-downmodewhilemaintainingCKEatalogicLOW.AminimumoftCKSREmustoccurafterCKEgoesLOWbeforetheclockfrequencycanchange.Theinputclockfrequencyisallowedtochangeonlywithintheminimumandmaximumoperatingfrequencyspecifiedfortheparticularspeed/temperaturegrade(tCK[AVG]MINtotCK[AVG]MAX)device.Duringtheinputclockfrequencychange,CKEmustbeheldatastableLOWlevel.Whentheinputclockfrequencyischanged,astableclockmustbeprovidedtotheDRAM,tCKSRXbeforePRECHARGEpower-downmaybeexited.AfterPRECHARGEpower-downisexitedandtXPhasbeensatisfied,theDLLmustberesetviatheMRS.Dependingonthenewclockfrequency,additionalMRScommandsmayneedtobeissued.DuringtheDLLlocktime,RTT_NOMandRTT_WRmustremaininanoffstate.AftertheDLLlocktime,theDRAMisreadytooperatewithanewclockfrequency(period).ThisprocessisdepictedinFigure37.

INPUT CLOCK FREQUENCY CHANGE



ST9D364M64SBG2



FiGure 37- chaNGe FreQueNcy duriNG precharGe pOwer-dOwN

CK

CK#

Command NOPNOPNOP

Address

CKE

DQ

DM

DQS, DQS#

NOP

tCK

Enter prechargepower-down mode

Exit prechargepower-down mode

T0 T1 Ta0 Tc0Tb0T2

Don’t Care

tCKE

tXP

MRS

DLL RESET

Valid

Valid

NOP

tCH

tIH t IS

tCL

Tc1 Td0 Te1Td1

tCKSRE

tCHbtCLb

tCKb

tCHbtCLb

tCKb

tCHbtCLb

tCKb

tCPDED

ODT

NOP

Te0

Previous clock frequency New clock frequency

Frequencychange


t IH t IS

t IH

t IS

tDLLK

tAOFPD/ tAOF

tCKSRX

High-Z

High-Z

NOTES:

1. Applicableforbothslow-exitandfast-exitprechargepower-downmodes.2. tAOFPDandtAOFmustbesatisfiedandoutputsHigh-ZpriortoT1(see“On-DieTermination(ODT)”for

exactrequirements).

3. IftheRTT_NOMfeaturewasenabledinthemoderegisterpriortoenteringprechargepower-down

mode, theODTsignalmustbecontinuously registeredLOWensuringRTT is inanoffstate. If

theRTT_NOMfeaturewasdisabledinthemoderegisterpriortoenteringprechargepower-down

mode,RTTwillremainintheoffstate.TheODTsignalcanberegisteredeitherLOWorHIGHin

thiscase.



ST9D364M64SBG2



Forbettersignalintegrity,DDR3SDRAMmemorysub-systemdesignshaveadopteduseoffly-bytopologyforthecommands,addresses,controlsignalsandclocks.WRITElevelingisaschemeforthememorycontrollertode-skewtheDQSxstrobe(DQSx,DQSx\)toCKrelationshipattheSDRAMwithasimplefeedbackfeatureprovideditbytheDDR3SDRAMitself.WRITElevelingisgenerallyusedaspartoftheinitializationprocess,ifrequired.ForNORMALSDRAMoperation,thisfeaturemustbedisabled.ThisistheonlySDRAMoperationwheretheDQSfunctionsasaninput(tocapturetheincomingclock)andtheDQsfunctionasoutputs(toreportthestatoftheclock).NotethatnonstandardODTschemesarerequired.

ThememorycontrollerusingtheWRITElevelingproceduremusthaveadjustabledelaysettingonitsDQSstrobetoaligntherisingedgeofDQStotheclockattheSDRAMpins.ThisisaccomplishedwhentheSDRAMasynchronouslyfeedsbacktheCKstatusviatheDQbusandsampleswiththerisingedgeofDQS.ThecontrollerrepeatedlydelaystheDQSstrobeuntilaCKtransitionfrom“0”to“1”isdetected.TheDQSdelayestablishedthroughthisprocedurehelpsensuretDQSS,tDSS,andtDSHspecificationsinsystemsthatuseflybytopologybyde-skewingthetracelengthmismatch.A

WRITE LEVELING

FiGure 38- write leVeliNG cONcept

CK

CK#

Source

Differential DQS

Differential DQS

Differential DQS

DQ

DQ

CK

CK#

Destination

Destination

Push DQS to capture 0–1 transition

T0 T1 T2 T3 T4 T5 T6 T7

T0 T1 T2 T3 T4 T5 T6 Tn

CK

CK# T0 T1 T2 T3 T4 T5 T6 Tn

Don’t Care

1 1

0 0



ST9D364M64SBG2



WhenWRITElevelingisenabled,therisingedgeofDQSsamplesCKandtherimeDQoutputsthesampledCK’sstatus.TheprimeDQforeachofthe(4)wordscontainedintheHiMODisDQ0forthelowbyte,DQ8forthehighbyte.ItoutputsthestatusofCKsampledbyDQSxandDQSx.AllotherDQs(DQ[7:1],DQ[15:9]forthelowword,DQ[23:17],DQ[31:25]forthenextword,DQ[39:33],DQ[47:41]forthenextandDQ[55:49],DQ[63:57]fortheHIGHword)continuetodriveLOW.TwoprimeDQoneachofthe(4)wordscontainedintheHiMODalloweachbytelanetobeleveledindependently.

WRITE LEVELING

AmemorycontrollerinitiatestheDRAMWRITELevelingmodebysettingtheMR1[7]toa“1”,assumingtheotherprogrammablefeatures(MR0,MR1,MR2,andMR3)arefirstsetandtheDLLisfullyresetandlocked.TheDQballsentertheWRITELevelingmodegoingfroma“HIGH-Z”statetoanunde-fineddrivingstatesotheDQbusshouldnotbedriven.DuringWRITELevelingmode,onlytheNOPandDEScommandsareallowed.Thememorycontrollershouldattempttolevelonlyonerankatatime;thus,theoutputsofotherranksshouldbedisabledbysettingMR1[12]toa“1”.ThememorycontrollermayassertODTafteratMODdelayastheSDRAMwillbereadytoprocesstheODTLondelay(WL-2tCK),provideditdoesnotviolatetheaforementionedtMODdelayrequirement.

ThememorycontrollermaydriveDQSx,LOWandDQSx\,HIGHaftertWLDQSENhasbeensatisfied.ThecontrollermaybegintotoggleDQSx,DQSxaftertWLMRD(oneDQSstoggleisDQSstransitioningfromaLOWstatetoaHIGHstatewithDQSx\transitioningfromaHIGHstatetoaLOWstate,thenbothtransitionbacktotheiroriginalstates).Ataminimum,ODTLonandtAONmustbesatisfiedatleastoneclockpriortoDQStoggling.

AftertWLMRDandDQSLOWpreamble(tWPRE)havebeensatisfied,thememorycontrollermayprovideeitherasingleDQSxtoggleormultipleDQSxtogglestosampleCKforagivenDQSxtoCKskew.EachDQStogglemustnotviolatetDQSL(MIN)andtDQSH(MIN)specifications.tDQSL(MAX)andtDQSH(MAX)specificationsarenotapplicableduringWRITElevelingmode.TheDQSxmustbeabletodistinguishtheCK’srisingedgewithintWLSand tWLH.TheprimeDQwilloutputtheCK’sstatusasynchronouslyfromtheassociatedDQSxrisingedgeCKcapturewithintWLO.TheremainingDQsthatalwaysdriveLOWwhenDQSistogglingmustbeLOWwithintWLOEafterthefirsttWLOissatisfied(theprimeDQsgoingLOW).Aspreviouslynoted,DQSxisaninputandnotanoutputduringthisprocess.Figure39depictsthebasictimingparametersfortheoverallwritelevelingprocedure.

ThememorycontrollerwilllikelysampleeachapplicableprimeDQstateanddeterminewhethertoincrementordecrementitDQSdelaysetting.AfterthememorycontrollerperformsenoughDQSxtogglestodetecttheCK’s“0-1”transition,thememorycontrollershouldlocktheDQSdelayset-

WRITE LEVELING PROCEDURE



ST9D364M64SBG2



FiGure 39- write leVeliNG SeQueNce

CK CK#

Command

T1 T2

Early remaining DQ

Late remaining DQ

tWLOE

NOP2 NOP MRS1 NOP NOP

tWLStWLH

Don’t CareUndefined Driving ModeIndicates a Break in Time Scale

Prime DQ5

Differential DQS4

ODT

tMOD

tDQSL3 tDQSH3 tDQSH3

tWLO tWLMRD

tWLDQSEN

tWLO

tWLO

tWLO

tDQSL3

NOP NOP NOP NOP NOP NOP NOP

NOTES:

1. MRS:LoadMR1toenterwritelevelingmode.

2. NOP:NOPorDES.

3. DQS,DQS#needstofulfillminimumpulsewidthrequirementstDQSH(MIN)andtDQSL(MIN)as

definedforregularwrites.Themaximumpulsewidthissystem-dependent.

4. DifferentialDQSisthedifferentialdatastrobe(DQS,DQS#).Timingreferencepointsarethezero

crossings.ThesolidlinerepresentsDQS;thedottedlinerepresentsDQS#.

5. DRAMdriveslevelingfeedbackonaprimeDQ(DQ0forx4andx8).TheremainingDQaredriven

LOWandremaininthisstatethroughoutthelevelingprocedure.

AfterthedevicehasbeenWRITEleveled,thecontrollermustexitfromWRITELevelingmodebeforetheNORMALmodecanbeused.Figure40depictsageneralprocedureinexitingWRITELeveling.AfterthelastrisingDQS(capturinga“1”atT0),thememorycontrollershouldstopdrivingtheDQSsignalsaftertWLO(MAX)delayplusenoughdelaytoenablethememorycontrollertocapturetheapplicableprimeDQstate(at–Tb0).TheDQballsbecomeundefinedwhenDQSnolongerremainsLOWandtheyremainundefineduntiltMODaftertheMRScommand(atTe1).

TheODTinputshouldbedeassertedLOWsuchthatODTLoff(MIN)expiresaftertheDQSxisnolongerdrivingLOW.WhenODTLOWsatisfiestIS,ODTmustbekeptLOW(at–Tb0)untiltheSDRAMisreadyforeitheranotherranktobeleveledoruntiltheNORMALmodecanbeused.AfterDQSterminationisswitchedoff,WRITElevelmodeshouldbedisabledviatheMRScommand(atTA2).AftertMODissatisfied(atTe1),anyvalidcommandmayberegisteredbytheSDRAM.SomeMRScommandsmaybeissuedaftertMRD(atTd1).

WRITE LEVELING EXIT MODE



ST9D364M64SBG2



FiGure 40- exit write leVeliNG

Notes: 1. The DQ result, “= 1,” between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing CK HIGH just after the T0 state.

NOP

CK

T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Tc2 Td0 Td1 Te0 Te1CK#

Command

ODT

RTT_DQ

NOP RMPONPONPONPONPON S NOP NOP

Address MR1

Valid Valid

Valid Valid

Don’t CareTransitioning

RTT DQS, RTT DQS R# TT_NOM

Undefined Driving Mode

tAOF (MAX)

tMRD


DQS, DQS#

CK = 1DQ

tIS

tAOF (MIN)

tMOD

tWLO + tWLOE

ODTL off



ST9D364M64SBG2



Initialization

Thefollowingsequenceisrequiredforpowerupandinitialization,asshowninFigure41.

1. Applypower.RESET\isrecommendedtobebelow0.2xVDDQduringpowerramptoensuretheoutputsremaindisabled(HIGH-Z)andODToff(RTTisalsoHIGH-Z).Allotherinputs,includingODTmaybeundefined.

Duringpowerup,eitherofthefollowingconditionsmayexistandmustbemet:

•Condition A:

•VDDandVDDQaredrivenfromasinglepowersourceandarerampedwithamaximumdeltavoltagebetweenthemof∆V≤300mV.Slopereversalofanypowersupplysignalisallowed.ThevoltagelevelsonallballsotherthanVDD,VDDQ,VssandVssQmustbelessthanorequaltoVDDQandVDDononesideandmustbegreaterthanorequaltoVssQandVssontheotherside.•BothVDDandVDDQpowersuppliesramptoVDD(MIN)andVDDQ(MIN)withintVDDPR=200ms.•BothVDDandVDDQpowersuppliesramptoVDD(MIN)andVDDQ(MIN)withintVDDPR=200ms.•VREFDQtracksVDDx0.5,VREFCAtracksVDDx0.5.•VTTislimitedto0.95Vwhenthepowerrampiscompleteandisnotapplieddirectlytothedevice;however,tVTDshouldbe greaterthanorequaltozerotoavoiddevicelatchup.

•ConditionB: •VDDmaybeappliedbeforeoratthesametimeasVDDQ.•VDDQmaybeappliedbeforeoratthesametimeasVTT,VREFDQandVREFCA.•Noslopereversalsareallowedinthepowersupplyrampforthiscondition.

2. Untilstablepower,maintainRESET\LOWtoensuretheoutputsremaindisabled(HIGH-Z).Afterthepowerisstable,RESET\mustbeLOWforatleast200µstobegintheinitializationprocess.ODTwillremainintheHIGH-ZstatewhileRESET\isLOWanduntilCKEisregisteredHIGH.

3. CKEmustbeLOW10nspriortoRESET\transitioningHIGH.

4. AfterRESET\transitionsHIGH,wait500µs(minusoneclock)withCKELOW.

5. AfterthisCKELOWtime,CKEmaybebroughtHIGH(synchronously)andonlyNOPorDEScommandsmaybeissued.Theclockmustbepresentandvalidforatleast10ns(andaminimumoffiveclocks)andODTmustbedrivenLOWatleasttISpriortoCKEbeingreg-isteredHIGH.WhenCKEisregisteredHIGH,itmustbecontinuouslyregisteredHIGHuntilthefullinitializationprocessiscomplete.

6. AfterCKEisregisteredHIGHandaftertXPRhasbeensatisfied,MRScommandsmaybeissued.IssueanMRS(LOADMODE)com-mandtoMR2withtheapplicablesettings(provideLOWtoBA2andBA0andHIGHtoBA1).

7. IssueanMRScommandtoMR3withtheapplicablesettings.

8. IssueanMRScommandtoMR1withtheapplicablesettings,includingenablingtheDLLandconfiguringODT.

9. IssueandMRScommandtoMR0withtheapplicablesettings,includingaDLLRESETcommand.tDLLK(512)cyclesofclockinputarerequiredtolocktheDLL.

OPERATIONS



ST9D364M64SBG2



FiGure 41- iNitializatiON SeQueNce

CKE

RTT

BA[2:0]

All voltagesupplies validand stable

T = 200µs (MIN)

DM

DQS

Address

A10

CK

CK#

tCL

Command NOP

T0 Ta0

Don’t Care

tCL

t IS

tCK

ODT

DQ

Tb0

tDLLK

MR1 withDLL enable

MR0 withDLL reset

tMRD tMOD

MRSMRS

BA0 = HBA1 = LBA2 = L

BA0 = LBA1 = LBA2 = L

Code Code

Code Code

Valid

Valid

Valid

Valid

Normaloperation

MR2 MR3

tMRD tMRD

MRSMRS

BA0 = LBA1 = HBA2 = L

BA0 = HBA1 = HBA2 = L

Code Code

Code Code

Tc0 Td0

VTT

VREF

VDDQ

VDD

RESET#

T = 500µs (MIN)

tCKSRX

Stable andvalid clock

Valid

Power-upramp

T (MAX) = 200ms

DRAM ready for external commands

T1

tZQ INIT

ZQ calibration

A10 = H

ZQCL

t IS

See power-upconditions

in the initialization

sequence text, set up 1

tXPR

Valid

= 20nst IOz


T (MIN) = 10ns

tVTD



ST9D364M64SBG2



Moderegisters(MR0-MR3)areusedtodefinevariousmodesofprogrammableoperationoftheDRAM.AmoderegisterisprogrammedviatheMODEREGISTERSET(MRS)commandduringinitializationanditretainsthestoredinformation(exceptforMR0[8]whichisself-clearing)untilitiseitherreprogrammed,RESET\goesLOW,oruntilthedevicelosespower.

Contentsofamoderegistercanbealteredbyre-executingtheMRScommand.Iftheuserchoosestomodifyonlyasubsetofthemoderegister’svariables,allvariablesmustbeprogrammedwhentheMRScommandisissued.Reprogrammingthemoderegisterwillnotalterthecontentsofthememoryarray,provideditisperformedcorrectly.

TheMRScommandcanonlybeissued(orre-issued)whenallbanksareidleandinthePRECHARGEDstate(tRPissatisfiedandnodataburstsareinprogress).AfteranMRScommandhasbeenissued,twoparametersmustbesatisfied:tMRD and tMOD.

ThecontrollermustwaittMRDbeforeinitiatinganysubsequentMRScommands(seeFigure42).

MODE REGISTERS

FiGure 42- mrS-tO-mrS cOmmaNd timiNG (tmrd)

Valid Valid

MRS1 MRS2NOP NOP NOP NOP

T0 T1 T2 Ta0 Ta1 Ta2CK#

CK

Command

Address

CKE3

Don’t CareIndicates a Break in Time Scale

tMRD

NOTES:

1. PriortoissuingtheMRScommand,allbanksmustbeidleandprecharged,tRP(MIN)mustbesatisfied,

andnodataburstscanbeinprogress.thelevelingprocedure.2. tMRDspecifiestheMRS-to-MRScommandminimumcycletime.

3. CKEmust be registeredHIGH from theMRS command until tMRSPDEN (MIN) (see “Power-Down

Mode”onpage153).

4. ForaCASlatencychange,tXPDLLtimingmustbemetbeforeanynonMRScommand.

ThecontrollermustalsowaittMODbeforeinitiatinganynonMRScommands(excludingNOPandDES),asshowninFigure52onpage110.TheDRAMrequirestMODinordertoupdatetherequestedfeatures,withtheexceptionofDLLRESET,whichrequiresadditionaltime.UntiltMODhasbeensatis-fied,theupdatedfeaturesaretobeassumedunavailable.



ST9D364M64SBG2



FiGure 43- mrS-tO-NONmrS cOmmaNd timiNG (tmOd)

CK CK#

Command

T1 T2

Early remaining DQ

Late remaining DQ

tWLOE

NOP2 NOP MRS1 NOP NOP

tWLStWLH

Don’t CareUndefined Driving ModeIndicates a Break in Time Scale

Prime DQ5

Differential DQS4

ODT

tMOD

tDQSL3 tDQSH3 tDQSH3

tWLO tWLMRD

tWLDQSEN

tWLO

tWLO

tWLO

tDQSL3

NOP NOP NOP NOP NOP NOP NOP

NOTES:

1. PriortoissuingtheMRScommand,allbanksmustbeidle(theymustbeprecharged,tRPmustbe

satisfied,andnodataburstscanbeinprogress).

2. PriortoTa2whentMOD(MIN)isbeingsatisfied,nocommands(exceptNOP/DES)maybeissued.

3. IfRTTwaspreviouslyenabled,ODTmustberegisteredLOWatT0sothatODTLissatisfiedprior

toTa1.ODTmustalsoberegisteredLOWateachrisingCKedgefromT0until tMOD(MIN)is

satisfiedatTa2.

4. CKEmustbe registeredHIGH from theMRScommanduntil tMRSPDEN(MIN),atwhich time

power-downmayoccur(see“Power-DownMode”onpage132).

MODE REGISTER 0 (MR0)

Thebaseregister,MR0isusedtodefinevariousDDR3iMODmodesofoperation.Thesedefinitionsincludetheselectionofaburstlength,bursttype,CASlatency,operatingmode,DLLRESET,WRITErecoveryandPRECHARGEpower-downmode,asshowninFigure44.



ST9D364M64SBG2




Accesseswithinagivenburstmaybeprogrammedtoeitherasequen-tialoraninterleavedorder.ThebursttypeisselectedviaMR0[3],asshowninFigure44.Theorderingofaccesseswithinaburstisdeter-minedbytheburstlength,thebursttypeandthestartingcolumnaddress,asshowninTable60.DDR3onlysupports4-bitburstchopand8-bitburstaccessmodes.Fullinterleavedaddressorderingissup-portedforREADs,whileWRITEsarerestrictedtonibble(BC4)orword(BL8)boundaries.

BURST TYPE BURST LENGTH

BurstlengthisdefinedbyMR0[1:0](seeFigure44).READandWRITEaccessestotheDDR3SDRAMiMODareburst-oriented,withtheburstlengthbeingprogrammableto“4”(chopmode).“8”(fixedburst),orselectableusingA12duringaREAD/WRITEcommand(onthefly).Theburstlengthdeterminesthemaximumnumberofcolumnloca-tionsthatcanbeaccessedforagivenREADorWRITEcommand.WhenMR0[1:0]issetto“01”duringaREAD/WRITEcommand,ifA12=0,thenBC4(chop)modeisselected.IfA12=1,thenBL8modeisselected.Specifictimingdiagrams,andturnaroundbetweenREAD/WRITEareshownintheREAD/WRITEsectionsofthisdocument.

WhenaREADorWRITEcommandisissued,ablockofcolumnsequaltotheburstlengthiseffectivelyselected.Allaccessesforthatbursttakeplacewithinthisblock,meaningthattheburstwillwrapwithintheblockifaboundaryisreached.TheblockisuniquelyselectedbyA[i:2]whentheburstlengthissetto“4”andbyA[i:3]whentheburstlengthissetto“8”(whereAiisthemostsignificantcolumnaddressbitforagivenstartinglocationwithintheblock.TheprogrammedburstlengthappliestobothREADandWRITEbursts.

FiGure 44- mOde reGiSter 0 (mr0) deFiNitiONS

Notes: 1. MR0[16, 13, 7, 2] are reserved for future use and must be programmed to “0.”

01 BLCAS# latency BTPD

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Mode register 0 (MR0)

Address bus

9 7 6 5 4 3 28 1 0

A10A12 A111AB 0AB

31 21 11 01

M3 01

READ Burst Type Sequential (nibble)

Interleaved

CAS LatencyReserved

567891011

M401010101

M500110011

M600001111

15DLL

Write RecoveryReserved

5678

1012

Reserved

WR00

M1201

Precharge PDDLL off (slow exit)DLL on (fast exit)

BA2

1601

Burst LengthFixed BL8

4 or 8 (on-the-fly via A12)Fixed BC4 (chop)

Reserved

M00101

M10011

M901010101

M1000110011

M1100001111

M14 0101

M150011

Mode Register Mode register 0 (MR0)Mode register 1 (MR1)Mode register 2 (MR2)Mode register 3 (MR3)

A13

1401 01

M801

DLL ResetNoYes



ST9D364M64SBG2



Burst Length Read/Write Address (A[2,1,0]) Type = Sequential Type = Interleaved

4CHOP

8

0,1,2,3,Z,Z,Z,Z

1,0,3,2,Z,Z,Z,Z

2,3,0,1,Z,Z,Z,Z

3,2,1,0,Z,Z,Z,Z

4,5,6,7,Z,Z,Z,Z

5,4,7,6,Z,Z,Z,Z

6,7,4,5,Z,Z,Z,Z

7,6,5,4,Z,Z,Z,Z

0,1,2,3,X,X,X,X

4,5,6,7,X,X,X,X

0,1,2,3,4,5,6,7

1,0,3,2,5,4,7,6

2,3,0,1,6,7,4,5

3,2,1,0,7,6,5,4

4,5,6,7,0,1,2,3

5,4,7,6,1,0,3,2

6,7,4,5,2,3,0,1

7,6,5,4,3,2,1,0

0,1,2,3,4,5,6,7

table 60: burSt Order

Notes1,2

1,2

1,2

1,2

1,2

1,2

1,2

1,2

1,3,4

1,3,4

1

1

1

1

1

1

1

1

1,3

Burst Type (Decimal)

0,1,2,3,Z,Z,Z,Z

1,2,3,0,Z,Z,Z,Z

2,3,0,1,Z,Z,Z,Z

3,0,1,2,Z,Z,Z,Z

4,5,6,7,Z,Z,Z,Z

5,6,7,4,Z,Z,Z,Z

6,7,4,5,Z,Z,Z,Z

7,4,5,6,Z,Z,Z,Z

0,1,2,3,X,X,X,X

4,5,6,7,X,X,X,X

0,1,2,3,4,5,6,7

1,2.3,0,5,6,7,4

2,3,0,1,6,7,4,5

3,0,1,2,7,4,5,6

4,5,6,7,0,1,2,3

5,6,7,4,1,2,3,0

6,7,4,5,2,3,0,1

7,4,5,6,3,0,1,2

0,1,2,3,4,5,6,7

000

001

010

011

100

101

110

1 1 1

0VV

1VV

000

001

010

011

100

101

110

1 1 1

VVV

READ

WRITE

READ

WRITE

Starting Column

2. Z=DataandStrobeoutputdriversintri-state.

3. X=”Don’tCare”

NOTES:1. InternalREADandWRITEoperationsstartatthesamepointintimefor

BC4astheydoforBL8.

DLLRESETisdefinedbyMR0[8](seeFigure44).ProgrammingMR0[8]to“1”activatestheDLLRESETfunction.MR0[8]isself-clearing,mean-ingitreturnstoavalueof“0”aftertheDLLRESETfunctionhasbeeninitiated.

AnytimetheDLLRESETfunctionhasbeeninitiated,CKEmustbeHIGHandtheclockheldstablefor512(tDLLK)clockcyclesbeforeaREADcommandcanbeissued.Thisistoallowtimefortheinternalclocktobesynchronizedwiththeexternalclock.Failingtowaitforsynchronizationtooccurmayresultininvalidoutputtimingspecifi-cationssuchastDQSCKtimings.

DLL RESET

WRITERECOVERYtimeisdefinedbyMR0[11:9](seeFigure44).WRITERECOVERYvaluesof5,6,7,8,10or12maybeusedbyprogrammingMR0[11:9].TheuserisrequiredtoprogramthecorrectvalueofWRITERECOVERYandiscalculatedbydividingtWR(ns)bytCK(ns)andround-ingupanon-integervaluetothenextinteger:WR(cycles)=roundup(tWR[ns]/tCK[ns]).

WRITE RECOVERY



ST9D364M64SBG2



ThePRECHARGEPDbitappliesonlywhenPRECHARGEpower-downmodeisbeingused.WhenMR0[12]issetto“0”,theDLLisoffduringPRECHARGEpower-downprovidingalowerstandbycurrentmode;however,tXPDLLmustbesatisfiedwhenexiting.WhenMR0[12]issetto“1”,theDLLcontinuestorunduringPRECHARGEpower-downmodetoenableafasterexitofPRECHARGEpower-downmode;how-ever,tXPmustbesatisfiedwhenexiting(seePower-Downmode).

PRECHARGE POWER-DOWN (PRECHARGE PD)

TheCLisdefinedbyMR0[6:4],asshowninFigure44.CASlatencyisthedelay,asmeasuredinclockcycles,betweentheinternalREADcom-mandandtheavailabilityofthefirstbitofvalidoutputdata.TheCLcanbesetto5,6,8,or10.DDR3SDRAMiMODsdonotsupporthalf-clocklatencies.

ExamplesofCL=6andCL=8areshowninFigure45(below).Ifaninter-nalREADcommandisregisteredatclockedgen,andtheCASlatencyismclocks,thedatawillbeavailablenominallycoincidentwithclockedgen+m.Table46indicatestheCLssupportedatavailableoperatingfrequencies.

CAS Latency (CL)

FiGure 45- read lateNcy

READ NOP NOP NOP NOP NOP NOPNOP

CK

CK#

Command

DQ

DQS, DQS#

DQS, DQS#

T0 T1 T2 T3 T4 T5 T6 T7 T8

Don’t Care

CK

CK#

Command

DQ

READ NOP NOP NOP NOP NOP NOPNOP

T0 T1 T2 T3 T4 T5 T6 T7 T8

DI n + 3

DI n + 1

DI n + 2

DI n + 4

DIn

DIn

NOP

NOP

AL = 0, CL = 8

AL = 0, CL = 6

Transitioning Data

NOTES:

1. Forillustrationpurposes,onlyCL=6andCL=8areshown.OtherCLvaluesare

possible.

2. ShownwithnominaltDQSCKandnominaltDSDQ.



ST9D364M64SBG2



TheMODEREGISTER1(MR1)controlsadditionalfunctionsandfeaturesnotavailableintheothermoderegisters;QOFF(OUTPUTDISABLE),DLLENABLE/DLLDISABLE,RTT_NOMvalue(ODT),WRITELEVELING,POSTEDCASADDITIVElatency,andOUTPUTDRIVESTRENGTH.ThesefunctionsarecontrolledviathebitsshowninFigure46below.TheMR1registerisprogrammedviatheMR5commandandretainsthestoredinformationuntilitisreprogrammed,untilRESET\goesLOW(true),oruntilthedevicelosespower.ReprogrammingtheMR1registerwillnotalterthecontentsofthememoryarray,providedtheoperationisperformedcorrectly.

TheMR1registermustbeloadedwhenallbanksareidleandnoburstsareinprogress.ThecontrollermustsatisfythespecifiedtimingparameterstMRD and tMODbeforeinitiatingasubsequentoperation.


FiGure 46- mOde reGiSter 1 (mr1) deFiNitiON

AL RTTQ Off

A9 A7 A6 A5 A4 A3 2A 8A A1 A0


Address bus

9 7 6 5 4 3 2 8 1 0

A10 A12 A11 1AB 0AB

31 21 11 01

M001

DLL EnableEnable (normal)

Disable

M50011

Output Drive StrengthRZQ/6 (40Ω [NOM])RZQ/7 (34Ω [NOM])

ReservedReserved

14WL 1 SDO 0 DLL RTTTDQS

M12

0

1

Q Off

Enabled

Disabled

BA2

1501

M701

Write LevelizationDisable (normal)

Enable

Additive Latency (AL)Disabled (AL = 0)

AL = CL - 1AL = CL - 2Reserved

M30101

M40011

RTT ODS

M10101

A13

1601

M11

0

1

TDQS

Disabled

Enabled

01 01

RTT_NOM (ODT)2

Non-WritesRTT_NOM disabled

RZQ/4 (60Ω [NOM])RZQ/2 (120Ω [NOM])RZQ/6 (40Ω [NOM])RZQ/12 (20Ω [NOM])RZQ/8 (30Ω [NOM])

ReservedReserved

RTT_NOM (ODT)3

WritesRTT_NOM disabled

RZQ/4 (60Ω [NOM])RZQ/2 (120Ω [NOM])RZQ/6 (40Ω [NOM])

n/an/a

ReservedReserved

M201010101

M600110011

M900001111

Mode Register Mode register set 0 (MR0)Mode register set 1 (MR1)Mode register set 2 (MR2)Mode register set 3 (MR3)

M14 0101

M150011

NOTES:

1. MR1[16,13,10,8]arereservedforfutureuseandmustbeprogrammedto“0.”

2. Duringwrite leveling, ifMR1[7]andMR1[12]are“1” thenallRTT_NOMvaluesareavailable

foruse.

3. Duringwriteleveling,ifMR1[7]isa“1,”butMR1[12]isa“0,”thenonlyRTT_NOMwritevalues

areavailableforuse.



ST9D364M64SBG2



TheDLLmaybeenabledordisabledbyprogrammingMR1[0]duringtheLOADMODEcommand,asshowninFigure46(previouspage).TheDLLmustbeenabledforNORMALoperation.DLLENABLEisrequiredduringpower-upinitializationanduponreturningtoNORMALoperationafterhavingDISABLEDtheDLLforthepurposeofdebuggingorevaluation.ENABLINGtheDLLshouldalwaysbefollowedbyresettingtheDLLusingtheappropriateLOADMODEcommand.

IftheDLLisenabledpriortoenteringSELFREFRESHmode,theDLLisautomaticallyDISABLEDwhenenteringSELFREFRESHoperationandisautomaticallyRE-ENABLEDandRESETuponexitofSELFREFRESH.IftheDLLisDISABLEDpriortoenteringSELFREFRESH,theDLLremainsDIS-ABLEDevenuponexitoftheSELFREFRESHoperationuntilithasbeenRE-ENABLEDandRESET.

TheDRAMisnottestedforcompliancewithNORMALmodetimingsorfunctionalitywhentheDLLisdisabled.AnattempthasbeenmadefortheDRAMtooperateintheNORMALmodewheneverpossiblewhentheDLLisdisabled;however,byindustrystandards,thefollowingexceptionshavebeenobserved,definedandlisted:

1. ODTisNOTALLOWEDtobeused2.TheOUTPUTDATAisnolongeredge-alignedtotheclock3. CLandCWLcanonlybesixclocks

WhentheDLLisDISABLED,timingandfunctionalitycanvaryfromtheNORMALoperationalspecificationswhentheDLLisenabled.DISABLINGtheDLLalsoimpliestheneedtochangetheclockfrequency.

DLL ENABLE/DLL DISABLE

ODTresistanceRTT_NOMisdefinedbyMR1[9,6,2](seeFigure46).TheRTTterminationvalueappliestotheDQx,DMx,DQSxandQSx\.TheDDR3devicearchitecturesupportsmultipleRTTterminationvaluesbasedonRZQ/nwherencanbe3,4,6,8or12andRZQis240Ω.

UnlikeDDR2,DDR3ODTmustbeturnedoffpriortoREADINGdataoutandmustremainoffduringREADburst.RTT_NOMterminationisallowedanytimeaftertheDRAMisinitialized,calibrated,andnotperformingREADaccesses,orinSELFREFRESHmode.Additionally,WRITEaccesseswithdynamicODTenabled(RTT_WR)temporarilyreplacesRTT_NOMwithRTT_WR.

Theactualeffectivetermination,RTT_EFF,maybedifferentfromtheRTTtargetedvalueduetonon-linearityofthetermination.ForRTT_EFFvaluesandcalculations,seetheON-DIETERMINATION(ODT)descriptionlaterinthisDS.

TheODTfeatureisdesignedtoimprovesignalintegrityofthememorydevicebyenablingtheDDR3SDRAMcontrollertoindependentlyturnON/OFFODTforanyoralldevicesintheenddesignsarray.TheODTinputcontrolpinisusedtodeterminewhenRTTisturnedon(ODTLon)andoff(ODTLoff),assumingODThasbeenENABLEDviaMR1[9,6,2].

TimingsforODTaredetailedinthe“ON-DIETermination(ODT)”description

ON-DIE TERMINATION (ODT)

TheDRAMusesaprogrammableimpedanceoutputbuffer.ThedrivestrengthmoderegistersettingisdefinedbyMR1[5:1],RZQ/7(34Ω[NOM])istheprimaryoutputdriverimpedancesettingforthedevice.Tocali-bratetheoutputdriverimpedance,andexternalprecisionresistor(RZQ)isconnectedbetweentheZQballandVssQ.Thevalueoftheresistoris240Ω±1%.

Theoutputimpedanceissetduringinitialization.Additionalimpedancecalibrationupdatesdonotaffectdeviceoperationandalldatasheettim-ingsandcurrentspecificationsaremetduringanupdate.

Tomeetthe34Ωspecification,theoutputdrivestrengthmustbesetto34Ωduringinitialization.Toobtainacalibratedoutputdriverimpedanceafterpower-up,thedeviceneedsacalibrationcommandthatispartoftheinitializationandresetprocedure.

OUTPUT DRIVE STRENGTH

TheOUTPUTENABLEfunctionisdefinedbyMR1[12],asshowninFigure46.Whenenabled(MR1[12]=0),alloutputs(DQx,DQSx,DQSx\)aretri-stated.TheoutputDISABLEfeatureisintendedtobeusedduringIDDcharacterizationoftheREADcurrentandduringtDQSSWRITELEVELINGonly.

OUTPUT ENABLE/DISABLE

TheWRITELEVELINGfunctionisenabledbyMR1[7],asshowninFigure46,WRITELEVELINGisused(duringinitialization)tode-skewtheDQSxstrobetoclockoffsetforfly-bytopologydesigns.Forsignalintegrity,someendusedesignsofmultipledevicesadoptedfly-bytopologyforthecom-mands,addresses,controlsignalsandclocks.

Thefly-bytopologybenefitsfromareducednumberofstubsandtheirlengths,however,fly-bytopologyinducesflighttimeskewbetweentheclockandDQSxstrobe(andDQx)ateachdeviceinthearray.ControllerswillhaveadifficulttimemaintainingtDQSS,tDSS and tDSHspecificationswithoutsupportingWRITELEVELINGinsystemswhichusefly-bytopologybaseddesigns.WRITELEVELINGtiminganddetailedoperationinforma-tionisprovidedin“WRITELEVELING.

WRITE LEVELING



ST9D364M64SBG2



ALissupportedtomakethecommandanddatabusefficientforsustainablebandwidthsinDDR3SRAMs.MR1[4,3]definethevalueofAL(seeFigure46).MR1[4,3]enablestheusertoprogramtheDDR3SDRAMwithanAL=0,CL-1,orCL-2.

Withthisfeature,theDDR3SDRAMenablesaREADorWRITEcommandtobeissuedaftertheACTIVATEcommandforthatbankpriortotRCD(MIN).TheonlyrestrictionisACTIVATEtoREADorWRITE+AL≥ tRCD(MIN)mustbesatisfied.AssumingtRCD(MIN)=CL,atypicalapplicationusingthisfeature,setsAL=CL–1tCK=tRCD(MIN-1tCK.TheREADorWRITEcommandisheldforthetimeoftheALbeforeitisreleasedinternallytotheDDR3SDRAMiMODdevice.READlatency(RL)iscontrolledbythesumoftheALandCASlatency(CL),RL=AL+CL,WRITElatency(WL)isthesumofCASWRITElatencyandAL,WL=AL+CWL(see“MODEREGISTER2(MR2))”.ExamplesofREADandWRITElatenciesareshowninFigure47andFigure49.

POSTED CAS ADDITIVE LATENCY (AL)

FiGure 47- read lateNcy (al = 5, cl = 6)

CK

CK#

Command

DQ

DQS, DQS#

ACTIVE n

T0 T1

Don’t Care

NOP NOP

T6 T12

NOPREAD n

T13

NOP

DO n + 3

DO n + 2

DO n + 1

RL = AL + CL = 11

T14

NOP

DO n

tRCD (MIN)

AL = 5 CL = 6

T11

BC4


Transitioning Data

T2

NOP



ST9D364M64SBG2



FiGure 48- mOde reGiSter 2 (mr2) deFiNitiON

Notes: 1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to “0.”

M14 0101

M150011

Mode RegisterMode register set 0 (MR0)Mode register set 1 (MR1)Mode register set 2 (MR2)Mode register set 3 (MR3)

A9 A7 A 6 A5 A4 A3A8 A2 A1 A0

Mode Register 2 (MR2)

Address bus

9 7 6 5 4 38 2 1 0

A10A12 A111AB 0AB

101 1121314151 CWL010

BA2

ASR16

01

A13

01 01 01 01 0101 SRTRTT_WR

M601

Auto Self Refresh(Optional)

Disabled: Manual Enabled: Automatic

M701

Self Refresh TemperatureNormal (0° C to 85° C)

Extended (0°C to 95° C)

CAS Write Latency (CWL)5 CK (tCK ≥ 2.5ns)

6 CK (2.5ns > tCK ≥ 1.875ns)7 CK (1.875ns > tCK ≥ 1.5ns)8 CK (1.5ns > tCK ≥ 1.25ns)

ReservedReservedReservedReserved

M301010101

M400110011

M500001111

M90101

M100011

Dynamic ODT ( RTT_WR )

RTT_WR disabledRZQ/4RZQ/2

Reserved

TheMODEREGISTER2(MR2)controlsadditionalfunctionsandfeaturesnotavailableintheothermoderegisters.TheseadditionalfunctionsareCASWRITElatency(CWL),AUTOSELFREFRESH(ASR),SELFREFRESHTEMPERATURE(SRT)andDYNAMICODT(RTT_WR).ThesefunctionsarecontrolledviathebitsshowninFigure48.TheMR2isprogrammedviatheMRScommandandwillretainthestoredinformationuntilitisprogrammedagainoruntilthedevicelosespower.ReprogrammingtheMR2registerwillnotalterthecontentsofthememoryarray,providedthattheoperationhasbeenperformedcorrectly.TheMR2registermustbeloadedwhenallbanksareidleandnodataburstsareinprogressandthememorycontrollermustwaitforthespecifiedtimetMRD and tMODbeforeinitiatingasubsequentoperation.




ST9D364M64SBG2



FiGure 49- caS write lateNcy

CK

CK#

Command

DQ

DQS, DQS#

ACTIVE n

BC4

T0 T1

Don’t Care

NOP NOP

T6 T12

NOPWRITE n

T13

NOP

DI n + 3

DI n + 2

DI n + 1

T14

NOP

DI n

tRCD (MIN)

NOP

AL = 5

T11

Indicates A Break in Time Scale

WL = AL + CWL = 11

Transitioning Data

T2

CWL = 6

CWLisdefinedbyMR2[5:3]andisthedelay,inclockcycles,fromthereleasingoftheinternalWRITEtothelatchingofthefirstdatain.CWLmustbecorrectlysettothecorrespondingoperatingclockfrequency(seeFigure48).TheoverallWRITELATENCY(WL)isequaltoCWL+AL(seeFigure46).

CAS WRITE LATENCY (CWL)

ModeregisterMR2[6]isusedtoDISABLE/ENABLEtheASRfunction.

WhenASRisDISABLED,theSELFREFRESHmode’sREFRESHrateisassumedtobeatthenormal85°Climit(commonlyreferredtoasthe1XREFRESHrate).IntheDISABLEDmode,ASRrequirestheusertoensuretheSDRAMneverexceedsaTAof85°CwhileinSELFREFRESHunlesstheuserenablestheSRTfeaturelistedbelow,supportinganelevatedtempupto+95°CwhileinSELFREFRESH.

ThestandardSELFREFRESHcurrenttestspecifiestestconditionstonormalambienttemperature(85°C)only,meaningifASRisenabled,thestandardSELFREFRESHcurrentspecificationdoesnotapply(seethe“EXTENDEDTEMPERATUREUSAGE”descriptionlaterinthisDS).

AUTO SELF REFRESH (ASR)REFRESHmode.ThestandardSELFREFRESHcurrenttestspecifiestestconditionstonormalambienttemperature(85°C)only,meaningifSRTisenabled,thestandardSELFREFRESHcurrentspecificationsdonotapply.

SRT vs. ASR

ModeregisterMR2[7]isusedtoDISABLE/ENABLEtheSRTfunc-tion.WhenSRTisDisabled,theSELFREFRESHmode’srefreshrateisassumedtobeatthenormal85°Climit.IntheDISABLEDmode,SRTrequirestheusertoensuretheSDRAMneverexceedstheTAlimitof85°CwhileinSELFREFRESHmodeunlesstheuserenablesASR.

WhenSRTisenabled,theSDRAMSELFREFRESHischangedinter-nallyfrom1Xto2X,regardlessoftheambienttemperature(TA).ThisenablestheusertooperatetheSDRAMbeyondthestandard85°Climituptotheoptionalextendedtemperaturerangeof+95°CwhileinSELF

SELF REFRESH TEMPERATURE (SRT)

Ifthenormalambienttemperaturelimitof85°Cisnotexceeded,thenneitherSRTnorASRisrequired,andbothcanbeDISABLEDthrough-outoperation.Iftheextendedtemperatureoptionisused,theuserisrequiredtoprovidea2Xrefreshrateduring(manual)refreshforExtendedtempdevicesor3XrefreshrateforMil-tempdevices.SRTandASRshouldbeenabledforautomaticREFRESHservicesonalldevicesusedintemperatureenvironments≤95°C

SRTforcestheSDRAMtoswitchtheinternalSELFREFRESHratefrom1Xto2X.SELFREFRESHisperformedat2XregardlessofTA.

ASRautomaticallyswitchestheSDRAM’sinternalSELFREFRESHratefrom1Xto2X,however,whileinSELFREFRESHmode,ASRenablestheREFRESHrateautomaticallyadjustbetween1Xand2XREFRESHrateoverthesupportedtemperaturerange.OneotherdisadvantagewithASRistheSDRAMcannotalwaysswitchfroma1Xtoa2XrefreshrateatanexactambientTemperatureof85°C.AlthoughtheSDRAMwillsupportdataintegritywhenitswitchesfroma1Xto2Xrate,itmayswitchatalowertemperaturethan85°C.

Sinceonlyonemodeisnecessaryatoneinstantintime,SRTandASRcannotbesimultaneouslyenabled.



ST9D364M64SBG2



DYNAMIC ODT

Themoderegister3(MR3)controlsadditionalfunctionsandfeaturesnotavailableviaMR0,MR1orMR2.CurrentlydefinedastheMULTIPURPOSEREGISTER(MPR).ThisfunctioniscontrolledviathebitsshowninFigure50.TheMR3isprogrammedviatheLOADMODEcommandandretainsthestoredinformationuntilitisprogrammedagainoruntilthedevicelosespower.ReprogrammingtheMR3registerwillnotalterthecontentsofthememoryarray,providedtheprogrammingoftheMR3hasbeenperformedcorrectly.TheMR3registermustbeloadedwhenallbanksareidleandnodataburstsareinprogressandthememorycontrollermustwaitthespecifiedtimetMRD and tMODbeforeinitiatingasubsequentoperation.

MODE REGISTER (MR3)

ThedynamicODT(RTT_WR)featureisdefinedbyMR2[10,9].DynamicODTisenabledwhenavalueisselected.ThisnewDDR3featureenablestheODTterminationvaluetochangewithoutissuinganMRScommand,essentiallychangingtheODTtermination“on-the-fly”.

WithdynamicODT(RTT_WR)whenbeginningaWRITEburstandsubsequentlyswitchesbacktoODT(RTT_WR)isenabled:ODTLCNW,ODTLCNW4,ODTLCNW*ODTH4,ODTH8andtADC.

DynamicODTisonlyapplicableduringWRITEcycles,IfODT(RTT_NOM)isdisabled,dynamicODT(RTT_WR)isstillpermitted.RTT_NOMandRTT_WRcanbeusedindependentofoneanother.DynamicODTisnotavailableduringWRITELEVELINGmode,regardlessofthestateofODT(RTT_NOM).FordetailsonODToperation,refertothe“On-Die-Termination(ODT)”section.

FiGure 50 - mOde reGiSter 3 (mr3) deFiNitiON

A9 A7 A 6 A5 A4 A3A8 A2 A1 A0


Address bus

9 7 6 5 4 38 2 1 0

A10A12 A111AB 0AB

101 112131415

A13

1 01 01 01 01 01 01 01 MPR 1

BA2

1601 01 01 01 01

M201

MPR EnableNormal DRAM operations 2

Dataflow from MPR

MPR_RF

M140101

M150011

Mode RegisterMo de register set (MR0)Mode register set 1 (MR1)Mode register set 2 (MR2)Mode register set 3 (MR3)

MPR READ FunctionPredefined pattern 3

ReservedReservedReserved

M00101

M10011

NOTES:

1. MR3[16and13:4]arereservedforfutureuseandmustallbeprogrammedto“0.”

2. WhenMPRcontrolissetfornormalDRAMoperation,MR3[1,0]willbeignored.

3. IntendedtobeusedforREADsynchronization.



ST9D364M64SBG2



MULTIPURPOSE REGISTER (MPR)

TheMULTIPURPOSEREGISTERfunctionisusedtooutputapredefinedsystemtimingcalibrationbitsequence.Bit2isthemasterbitthatenablesordisablesaccesstotheMPRregisterandbits1and0determinewhichmodetheMPRisplacedin.ThebasicconceptofthemultipurposeregisterisshowninFigure51.

IfMR3[2]isa“0”,thentheMPRaccessisdisabledandtheSDRAMoperatesinnormalmode.However,ifMR3[2]isa“1”,thenSDRAMnolongeroutputsnormalreaddatabutoutputsMPRdataasdefinedbyMR3[0,1].IfMR3[0,1]isequalto“00”,thenapredefinedreadpatternforsystemcalibrationisselected.

ToenabletheMPR,theMRScommandisissuedtoMR3andMR3[2]=1(seeTable61).PriortoissuingtheMRScommand,allbanksmustbeintheidlestate(allbanksareprecharged,andtRPismet).WhentheMPRisenabled,anysubsequentREADorRDAPcommandsareredirectedtothemultipur-poseregister.TheresultingoperationwheneitheraREADoraRDAPcommandisissuedisdefinedbyMR3[1:0]whenMPRisenabled(seeTable62).WhentheMPRisenabled,onlyREADorRDAPcommandsarealloweduntilasubsequentMRScommandisissuedwiththeMPRdisabled(MR3[2]=0).POWER-DOWN,SELFREFRESHandanyotherNONREADorRDAPcommandisnotallowed.TheRESETfunctionissupportedduringMPRenablemode.

FiGure 51 - multipurpOSe reGiSter (mpr) blOck diaGram

Memory core

MR3[2] = 0 (MPR off)

DQ, DM, DQS, DQS#

Multipurpose registerpredefined data for READs

MR3[2] = 1 (MPR on)

NOTES:

1. ApredefineddatapatterncanbereadoutoftheMPRwithanexternalREADcommand.

2. MR3[2]defineswhetherthedataflowcomesfromthememorycoreortheMPR.Whenthedata

flow isdefined, theMPRcontentscanbe readoutcontinuouslywitha regularREADorRDAP

command.



ST9D364M64SBG2



MPR MPR READ Function Function0

1

NormalOperation,noMPRtransaction.AllsubsequentREADscomefrom

theSDRAMmemoryarray.AllsubsequentWRITEsgototheSDRAM

memoryarray.

EnableMPRmode,subsequentREAD/RDAPcommandsdefinedbybits1

and2.


“Don’tCare”

A[1:0](SeeTable67)

MR3[2] MR3[1:0]

MPR FUNCTIONAL DESCRIPTION

TheMPRJEDECdefinitionallowsforeitheraprimeDQ0forlowerbyteandDQ8fortheupperbyteofeachofthe(4)wordscontainedintheLDIiMOD,tooutputtheMPRdatawiththeremainingDQsdrivenLOW,orforallDQstooutputtheMPRdata.TheMPRreadoutsupportsfixedREADburstandREADburstchop(MRSandOTFviaA12/BC#)withregularREADlatenciesandACtimingsapplicable.ThisprovidingtheDLLislockedasrequired.

MPRaddressingforavalidMPRREADisasfollows:•A[1:0]mustbesetto“00”astheburstorderisfixedpernibble•A2selectstheburstorder

•BL8,A2issetto“0”,andtheburstorderisfixedto0,1,2,3,4,5,6,7•Forburstchop4cases,theburstorderisswitchedonthenibblebaseand:

•A2=0:burstorder=0,1,2,3•A2=1:burstorder=4,5,6,7

•Burstorderbit0(thefirstbit)isassignedtoLSB,andburstorderbit7(thelastbit)isassignedtoMSB•A[9:3]area“Don’tCare”•A10isa“Don’tCare”•A11isa“Don’tCare”•A12:Selectsburstchopmodeon-the-fly,ifenabledwithinMR0



ST9D364M64SBG2



MPR REGISTER ADDRESS DEFINITIONS and BURSTING ORDER

TheMPRcurrentlysupportsasingledataformat.ThisdataformatisapredefinedREADpatternforsystemcalibration.Thepredefinedpatternisalwaysarepeating0-1bitpattern.

ExamplesofthedifferenttypeofpredefinedREADpatternburstsareshowninFigures52,53,and54.

MR3[2] MR3[1:0] Function Length A[2:0] Burst Order and Data Pattern1

1

1

1

BurstOrder:0,1,2,3,4,5,6,7

Predefinedpattern:0,1,0,1,0,1,0,1

BurstOrder:0,1,2,3

Predefinedpattern:0,1,0,1

BurstOrder:4,5,6,7

Predefinedpattern:0,1,0,1

n/a

n/a

n/a

n/a

n/a

n/a

n/a

n/a

n/a


READpredefinedpatternfor

systemcalibration

RFU

RFU

RFU

BL8

BC4

BC4

n/a

n/a

n/a

n/a

n/a

n/a

n/a

n/a

n/a

000

000

100

n/a

n/a

n/a

n/a

n/a

n/a

n/a

n/a

n/a

00

01

10

11

Burst Read



ST9D364M64SBG2



Not

es:

1.R

EAD

with

BL8

eith

er b

y M

RS

or O

TF.

2.M

emor

y co

ntro

ller m

ust d

rive

0 on

A[2

:0].

T0Ta

0Tb

0Tb

1Tc

0Tc

1Tc

2Tc

3Tc

4Tc

5Tc

6Tc

7Tc

8Tc

9Tc

10

CKCK#

MRS

PREA

READ

1NO

PNO

PNO

PNO

PNO

PNO

PNO

PNO

PM

RSN

OP

NO

PVa

lidC

omm

and

t MP

RR

Don

’t Ca

reIn

dica

tes

a B

reak

in

Tim

e S

cale

DQS,

DQ

S#

Bank

add

ress

3Va

lid3

0A[

1:0]

Valid

02

1A2

020

00A[

9:3]

Valid

00

01

A10/

APVa

lid0

0ilaV

11Ad

0

0A1

2/BC

#Va

lid1

0

0ilaV

]31:51[Ad

0

DQ

t MO

Dt R

Pt M

OD

RL

Figure 52 - MPR System Read Calibration with BL8: Fixed Burst Order Single Readout



ST9D364M64SBG2



Not

es:

1.R

EAD

with

BL8

eith

er b

y M

RS

or O

TF.

2.M

emor

y co

ntro

ller m

ust d

rive

0 on

A[2

:0].

T0Ta

TbTc

0Tc

1Tc

2Tc

3Tc

4Tc

5Tc

6Tc

7Tc

8Tc

9Tc

10Td

CK

CK#

t MP

RR

Don

’t Ca

reIn

dica

tes

a B

reak

in

Tim

e S

cale

RL

3Va

lid3

Bank

add

ress

Valid

A[1:

0]Va

lid02

020

A212

021

0

0A[

15:1

3]Va

lidVa

lid0

A[9:

3]Va

lidVa

lid00

00

A11

Valid

Valid

00

A12/

BC#

Valid

10

0

A10/

APVa

lidVa

lid0

01

RL

PREA

READ

1NO

PNO

PNO

PNO

NO

PNO

PNO

PM

RSVa

lidC

omm

and

READ

1M

RS

DQ

Valid

DQS,

DQ

S#

t RP

t MO

Dt C

CDt M

OD

NOP

NOP

Figure 53 - MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout



ST9D364M64SBG2



Not

es:

1.R

EA

D w

ith B

C4

eith

er b

y M

RS

or O

TF.

2.M

emor

y co

ntro

ller m

ust d

rive

0 on

A[1

:0].

3.A

2 =

0 se

lect

s lo

wer

4 n

ibbl

e bi

ts 0

. . .

3.

4.A

2 =

1 se

lect

s up

per 4

nib

ble

bits

4 .

. . 7

.

T0Ta

Tb

CK

CK# DQ

DQS,

DQ

S#

t MO

Dt M

PR

R

Don

’t Ca

re

Tc0

Tc1

Tc2

Tc3

Tc4

Tc5

Tc6

Tc7

Tc8

Tc9

Tc10

Td

NOP

NOP

NOP

NOP

Valid

Com

man

dM

RSPR

EARE

AD1

READ

1NO

PNO

P

Indi

cate

s a

Bre

ak in

Ti

me

Sca

le

Bank

add

ress

3Va

lid3

Valid

0A[

1:0]

Valid

0202

1A2

1403

0

00ilaV

]3:9[Ad

Valid

00

01

ilaVPA/01A

dVa

lid0

0ilaV

11Ad

Valid

0

0A1

2/BC

#Va

lid1

Valid

10

0A[

15:1

3]Va

lidVa

lid0

RL

RL

t RF

t MO

Dt C

CD

NOP

NOP

MRS

NOP

Figure 54 - MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble



ST9D364M64SBG2



Not

es:

1.R

EA

D w

ith B

C4

eith

er b

y M

RS

or O

TF.

2.M

emor

y co

ntro

ller m

ust d

rive

0 on

A[1

:0].

3.A

2 =

1 se

lect

s up

per 4

nib

ble

bits

4 .

. . 7

.4.

A2

= 0

sele

cts

low

er 4

nib

ble

bits

0 .

. . 3

.

T0Ta

Tb

01

ilaVPA/01A

dVa

lid0

CK

CK#

MRS

PREA

READ

1RE

AD1

NOP

NOP

NOP

SNO

PNO

PVa

lidC

omm

and

004

131

A2

t MO

Dt M

PR

R

3Va

lid3

Bank

add

ress

Valid 02

020

A[1:

0]Va

lid 00

ilaV]31:51[A

dVa

lid

00

ilaV11A

dVa

lid

0000

ilaV]3:9[A

dVa

lid

Don

’t Ca

re

Tc0

Tc1

Tc2

Tc3

Tc4

Tc5

Tc6

Tc7

Tc8

Tc9

Tc10

Td

Indi

cate

s a

Bre

ak in

Ti

me

Sca

le

RL

DQ

DQS,

DQ

S#

0A1

2/BC

#Va

lid1

Valid

10

RL

t RF

t MO

Dt C

CD

MR

NOP

NOP

NOP

NOP

Figure 55 - MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble



ST9D364M64SBG2



MPR READ PREDEFINED PATTERN

ThepredeterminedREADcalibrationpatternisafixedpatternof0,1,0,1,0,1,0,1.ThefollowingisanexampleofusingtheREADoutpredeterminedREADcalibrationpattern.TheexampleistoperformmultipleREADSfromtheMULTIPURPOSEREGISTER(MPR)inordertodosystemlevelREADtimingcalibrationbasedonthepredeterminedandstandardizedpattern.

ThefollowingprotocoloutlinesthestepsusedtoperformtheREADcalibration:•Prechargeallbanks•AftertRPissatisfied,setMRS,MR3[2]=1andMR3[1:0]=00.ThisredirectsallsubsequentREADsandLoadsthepredefinedpatternintotheMPR.AssoonastMRD and tMODaresatisfied,theMPRisavailable.•DataWRITEoperationsarenotalloweduntiltheMPRreturnstothenormalSDRAMstate•IssueaREADwithburstorderinformation(allotheraddresspinsare“Don’tCare”):

•A[1:0]=00(databurstorderisfixedstartingatnibble)•A2=0(forBL8,burstorderisfixedas0,1,2,3,4,5,6,7)•A12=1(useBL8)

•AfterRL=AL+CL,theSDRAMburstsoutthepredefinedREADcalibrationpattern(0,1,0,1,0,1,0,1)•ThememorycontrollerrepeatsthecalibrationREADsuntilREADdatacaptureatthememorycontrollerisoptimized•AfterthelastMPRREADburstandaftertMPRRhasbeensatisfied,issueMRS,MR3[2]=0andMR3[1:0]=“Don’tCare”tothenormalSDRAMstate.AllsubsequentREADandWRITEaccesseswillberegularREADSandWRITESfrom/totheSDRAMarray•WhentMRD and tMODaresatisfiedfromthelastMRS,theregularSDRAMcommands(suchasACTIVATEaMemorybankforregularREADorWRITEaccess)arepermitted

MODE REGISTER SET (MRS)

ThemoderegistersareloadedviainputsBA[2:0],A[13:0].BA[2:0]determineswhichmoderegisterisprogrammed:

•BA2=0,BA1=0,BA0=0forMR0•BA2=0,BA1=0,BA0=1forMR1•BA2=0,BA1=1,BA0=0forMR2•BA2=0,BA1=1,BA0=1forMR3

TheMRScommandcanonlybeissued(orreissued)whenallbanksareidleandintheprechargedstate(tRPissatisfiedandnodataburstsareinprogress).ThecontrollermustwaitthespecifiedtimetMRDbeforeinitiatingasubsequentoperationsuchasanACTIVATEcommand.ThereisalsoarestrictionafterissuinganMRScommandwithregardtowhentheupdatedfunctionsbecomeavailable.ThisparameterisspecifiedbytMOD.BothtMRD and tMODparametersareshowninFigure42and43.Violatingeitheroftheserequirementswillresultinunspecifiedoperation.

ZQ CALIBRATION

TheZQCALIBRATIONcommandisusedtocalibratetheDRAMoutputdrivers(RON)andODTvalues(RTT)overprocess,voltage,andtemperature,providedadedicated240Ω(±1%)externalresistorisconnectedfromtheSDRAM’sZQballtoVssQ.

SDRAMsneedalongertimetocalibrateRONandODTatpowerupINITIALIZATIONandSELFREFRESHexitandarelativelyshortertimetoperformperiodiccalibrations.TheDRAMdefinestwoZQCALIBRATIONcommands:ZQCALIBRATIONLONG(ZQCL)andZQCALIBRATIONSHORT(ZQCS).AnexampleofZQCALIBRATIONtimingisshowninFigure56.

AllbanksmustbePRECHARGEDandtRPmustbemetbeforeZQCLorZQCScommandscanbeissuedtotheSDRAM.Nootheractivities(otherthananotherZQCLorZQCScommandmaybeissuedtotheSDRAM)canbeperformedontheSDRAMarraybythecontrollerforthedurationoftZQINITortZQOPER.ThequiettimeontheSDRAMarrayhelpsaccuratelycalibrateRONandODT.AfterDRAMcalibrationisachieved,theSDRAMshoulddisabletheZQball’scurrentconsumptionpathtoreduceoverallpowerusage.

ZQCALIBRATIONcommandscanbeissuedinparalleltoDLLRESETandlockingtime.UponSELFREFRESHexit,anexplicitZQCLisrequiredifZQCALIBRATIONisdesired.

IndualranksystemdesignsthatsharetheZQresistorbetweendevices,thecontrollermustnotallowoverlapoftZQINT,tZQOPERortZQCSbetweenranks.



ST9D364M64SBG2



FiGure 56 - zQ calibratiON timiNG (zQcl aNd zQcS)

NOPZQCL NOP NOP Valid Valid ZQCS NOP NOP NOP ValidCommand


T0 T1 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2

Address Valid ValidValid

A10 Valid ValidValid

CK

CK#

Don’t Care

DQ High-Z High-Z3A3 ctivities Activ-ities

Valid ValidODT 2 2 Valid

1CKE 1 Valid Valid Valid

tZQCStZQINIT or tZQOPER

NOTES:

1. CKEmustbecontinuouslyregisteredHIGHduringthecalibrationprocedure.

2. ODTmustbedisabledviatheODTsignalortheMRSduringthecalibrationprocedure.

3. AlldevicesconnectedtotheDQbusshouldbeHigh-Zduringcalibration.

ACTIVATE

BeforeanyREADorWRITEcommandscanbeissuedtoabankwithintheDRAM,aROWinthatbankmustbeopened(ACTIVATED).Thisisaccom-plishedviatheACTIVATEcommand,whichselectsboththeBANKandtheROWtobeACTIVATED.

AfteraROWisopenedwithanACTIVATEcommand,aREADorWRITEcommandmaybeissuedtothatROW,subjecttothetRCDspecification.How-ever,iftheadditivelatencyisprogrammedcorrectly,aREADorWRITEcommandmaybeissuedpriortotRCD(MIN).Inthisoperation,theSDRAMenablesaREADorWRITEcommandtobeissuedaftertheACTIVATEcommandforthatbank,butpriortotRCD(MIN)(see“POSTEDCASADDITIVELATENCY(AL)).tRCD(MIN)shouldbedividedbytheclockperiodandroundeduptothenextwholenumbertodeterminetheearliestclockedgeaftertheACTIVATEcommandonwhichtheREADorWRITEcommandcanbeentered.Thesameprocedureisusedtoconvertotherspecificationlimitsfromtimeunitstoclockcycles.

Whenatleastonebankisopen,anyREAD-to-READcommanddelayorWRITE-to-WRITEcommanddelayisrestrictedtotCCD(MIN).

AsubsequentACTIVATEcommandtoadifferentROWinthesameBANKcanonlybeissuedafterthepreviousACTIVEROWhasbeenclosed(PRE-CHARGED).TheminimumtimeintervalbetweensuccessiveACTIVATEcommandstothesameBANKisdefinedbytRC.

AsubsequentACTIVATEcommandtoanotherBANKcanbeissuedwhilethefirstBANKisbeingaccessed,whichresultsinareductionoftotalROW-ACCESSoverhead.TheminimumtimeintervalbetweensuccessiveACTIVATEcommandsmaybeissuedinagiventFAW(MIN)period,andthetRRD



ST9D364M64SBG2



FiGure 57 - example: meetiNG trrd (miN) aNd trcd (miN)

Command

Don’t Care

T1T0 T2 T3 T4 T5 T8 T9

tRRD

Row Row Col

Bank x Bank y Bank y

NOPACT NOP NOPACT NOP NOP RD/WR

tRCD

BA[2:0]

CK#

Address

CK

T10 T11

NOP NOP


FiGure 58 - example: tFaw

Command

Don’t Care

T1T0 T4 T5 T8 T9 T10 T11

tRRD

Row Row

Bank a Bank b

Row

Bank c

Row

Bank d Bank y

Row

Bank y

NOPACT NOPAC AT CT NOP NOP

tFAW

BA[2:0]

CK#

Address

CK

T19 T20

NOPAC AT CT

Bank e




ST9D364M64SBG2



FiGure 59 - read lateNcy

Notes: 1. DO n = data-out from column n.2. Subsequent elements of data-out appear in the programmed order following DO n..

CK

CK#

Command READ NOP NOP NOP NOP NOP NOP NOP

AddressBank a,Col n

CL = 8, AL = 0

DQ

DQS, DQS#

DOn

T0 T7 T8 T9 T10 T11


T12 T12


READ

READburstsareinitiatedwithaREADcommand.ThestartingCOLUMNandBANKaddressesareprovidedwiththeREADcommandandAUTOPRE-CHARGEiseitherenabledordisabledforthatburstaccess.IfAUTOPRECHARGEisenabled,theROWbeingaccessedisautomaticallyPRECHARGEDatthecompletionoftheburstsequence.IfAUTOPRECHARGEisdisabled,theROWwillbeleftopenafterthecompletionoftheburst.

DuringREADbursts,thevaliddataoutelementfromthestartingcolumnaddressisavailableatREADLATENCY(RL)clockslater.RLisdefinedasthesumofPOSTEDCASADDITIVELATENCY(AL)andCASLATENCY(CL)(RL=AL+CL).ThevalueofALandCLisprogrammableinthemoderegisterviatheMRScommand.Eachsubsequentdata-outelementwillbevalidnominallyatthenextpositiveornegativeclockedge(thatis,atthenextcrossingofCKandCK\).Figure59showsanexampleofRLbasedonaCLsettingof8aswellasAL=0.

AREADburstmaybefollowedbyaPRECHARGEcommandtothesamebankprovidedAUTOPRECHARGEisnotACTIVATED.TheminimumREAD-to-PRECHARGEcommandspacingtothesamebankisfourclocksandmustalsosatisfyaminimumanalogtimefromtheREADcommand.ThistimeiscalledtRTP(READ-to-PRECHARGE).tRTPstartsALcycleslaterthantheREADcommand.ExamplesforBL8areshowninFigure65andBC4inFigure66.FollowingthePRECHARGEcommand,asubsequentcom-mandtothesamebankcannotbeissueduntiltRPismet.ThePRECHARGEcommandfollowedbyanotherPRECHARGEcommandtothesamebankisallowed.However,theprechargeperiodwillbedeterminedbythelastPRECHARGEcommandissuedtothebank.

IfA10isHIGHwhenaREADcommandisissued,theREADwithAUTOPRE-CHARGEfunctionisengaged.TheSDRAMstartsanAUTOPRECHARGEoperationontherisingedgewhichisAL+tRTPcyclesaftertheREADcommand.TheDRAMsupportsatRASlockoutfeature(seeFigure68).IftRAS(MIN)isnotsatisfiedattheedge,thestartingpointoftheAUTOPRECHARGEoperationwillbedelayeduntiltRAS(MIN)issatisfied.IncasetheinternalPRECHARGEoperationispushedoutbytRTP,tRPstartsatthepointatwhichtheinternalPRECHARGEhappens.ThetimefromREADwithAUTOPRECHARGEtothenextACTIVATEcommandthesamebankisAL+(tRTP+tRP)*,where“*”meansroundeduptothenextinteger.Inanyevent,internalRECHARGEdoesnotstartearlierthanfourclocksafterthelast8n-bitprefetch.

DQSxandDQSx\isdrivenbytheDRAMalongwiththeoutputdata.TheinitialLOWstateonDQSxandHIGHstateonDQSx\,isknownastheREADpreamble(tRPRE).TheLOWstateonDQSxandtheHIGHstateonDQSx\,coincidentwiththelastdata-outelement,isknownastheREADpostam-ble(tRPST).Uponcompletionofaburst,assumingnoothercommandshavebeeninitiated,theDQwillgoHIGH-Z.AdetailedexplanationoftDQSQ(validdata-outskew),tQH(data-outwindowhold),andthevaliddatawindowaredepictedinFigure71.AdetailedexplanationoftDQSCK(DQStransitionskewtoCK)isalsodepictedinFigure71.

DatafromanyREADburstmaybeconcatenatedwithdatafromasubse-quentREADcommandtoprovideacontinuousflowofdata.Thefirstdataelementfromthenewburstfollowsthelastelementofacompletedburst.ThenewREADcommandshouldbeissuedtCCDcyclesafterthefirstREADcommand.ThisisshownforBL8inFigure60.IfBC4isenabled,tCCDmuststillbemetwhichwillcauseagapinthedataoutput,asshowninFigure61.NonconsecutiveREADdataisreflectedinFigure62.DDR3SDRAMsdonotallowinterruptingortruncatinganyREADburst.

DatafromanyREADburstmustbecompletedbeforeasubsequentWRITEburstisallowed.AnexampleofaREADburstfollowedbyaWRITEburstforBL8isshowninFigure63.ToensuretheREADdataiscompletedbeforetheWRITEdataisonthebus,theminimumREAD-to-WRITEtimingisRL+tCCD–WL+2tCK.



ST9D364M64SBG2



Not

es:

1.N

OP

com

man

ds a

re s

how

n fo

r eas

e of

illu

stra

tion;

oth

er c

omm

ands

may

be

valid

at t

hese

tim

es.

2.

The

BL8

set

ting

is a

ctiv

ated

by

eith

er M

R0[

1:0]

= 0

0 or

MR

0[1:

0] =

01

and

A12

= 1

dur

ing

RE

AD

com

man

d at

T0

and

T4.

3.D

O n

(or

b) =

dat

a-ou

t fro

m c

olum

n n (o

r col

umn

b).

4.B

L8, R

L =

5 (C

L =

5, A

L =

0).

T0T1

T2T3

T4T5

T6T7

T8T9

T10

T11

Don

’t Ca

reTr

ansi

tioni

ng D

ata

T12

T13

T14

t RPS

T

NOP

DAERDAER

PON

PON

PON

PON

PON

PON

PON

PON

PON

PON

PON

PON

CK

CK#

Com

man

d1

DQ3

DQS,

DQ

S#

Bank

,Co

l nBa

nk,

Col b

Addr

ess2

RL

= 5

t RPR

E

t CC

D

RL

= 5DO n

+ 3

DO n+

2DO n +

1DO n

DO n+

7DO n +

6DO n +

5DO

n

+ 4

DO b +

3DO b +

2DO b

+ 1

DO bDO b +

7DO b +

6DO b +

5DO b

+ 4

Figure 60 - Consecutive READ Bursts (BL8)



ST9D364M64SBG2



Not

es:

1.N

OP

com

man

ds a

re s

how

n fo

r eas

e of

illu

stra

tion;

oth

er c

omm

ands

may

be

valid

at t

hese

tim

es.

2.Th

e B

C4

setti

ng is

act

ivat

ed b

y ei

ther

MR

0[1:

0] =

10

or M

R0[

1:0]

= 0

1 an

d A

12 =

0 d

urin

g R

EA

D c

omm

and

at T

0 an

d T4

.3.

DO

n (o

r b)

= d

ata-

out f

rom

col

umn n

(or c

olum

n b)

.4.

BC

4, R

L =

5 (C

L =

5, A

L =

0).

NOP

CK

CK#

Com

man

d1

DQ3

DQS,

DQ

S#

T0T1

T2T3

T4T5

T6T7

T8T9

Addr

ess2

T10

T11

Don

’t Ca

reTr

ansi

tioni

ng D

ata

T12

T13

T14

READ

READ

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

Bank

,Co

l nBa

nk,

Col b

t RPS

Tt R

PRE

t RPS

Tt R

PRE

RL

= 5

DO n+

3DO n +

2DO n +

1DO n

DO b+

3DO b

+ 2

DO b+

1DO b

RL

= 5

t CC

D

Figure 61 - Consecutive READ Bursts (BC4)



ST9D364M64SBG2



Not

es:

1.A

L =

0, R

L =

8.2.

DO

n (o

r b)

= d

ata-

out f

rom

col

umn

n (o

r col

umn

b).

3.S

even

sub

sequ

ent e

lem

ents

of d

ata-

out a

ppea

r in

the

prog

ram

med

ord

er fo

llow

ing

DO

n.

4.S

even

sub

sequ

ent e

lem

ents

of d

ata-

out a

ppea

r in

the

prog

ram

med

ord

er fo

llow

ing

DO

b.

Don

’t Ca

reTr

ansi

tioni

ng D

ata

T0T1

T2T3

T4T5

T6T7

T8T9

T10

T11

T12

T13

T14

T15

T16

T17

DQS,

DQ

S#

Com

man

dNO

PNO

PNO

PNO

PNO

PNO

PNO

PNO

PNO

PNO

PNO

PNO

PNO

PNO

PNO

PRE

ADNO

PRE

AD

Addr

ess

Bank

a,

Col n

Bank

a,

Col b

CKCK#

DQD

O nD

O b

CL

= 8

CL

= 8

Figure 62 - Nonconsecutive READ Bursts



ST9D364M64SBG2



Not

es:

1.N

OP

com

man

ds a

re s

how

n fo

r eas

e of

illu

stra

tion;

oth

er c

omm

ands

may

be

valid

at t

hese

tim

es.

2.Th

e B

L8 s

ettin

g is

act

ivat

ed b

y ei

ther

MR

0[1:

0] =

00

or M

R0[

1:0]

= 0

1 an

d A

12 =

1 d

urin

g th

e R

EA

D c

omm

and

at T

0, a

nd

the

WR

ITE

com

man

d at

T6.

3.D

O n

= d

ata-

out f

rom

col

umn,

DI b

= d

ata-

in fo

r col

umn

b.4.

BL8

, RL

= 5

(AL

= 0,

CL

= 5)

, WL

= 5

(AL

= 0,

CW

L =

5).

Don

’t Ca

reTr

ansi

tioni

ng D

ata

T0T1

T2T3

T4T5

T6T7

T8T9

T10

T11

T12

T13

T14

T15

CK

CK#

Com

man

d1NO

PNO

PNO

PNO

PNO

PW

RITE

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

t WPS

Tt R

PR

Et W

PR

Et R

PST

DQS,

DQ

S#

DQ3

WL

= 5

t WR

t WTR

READ

DO n

DO n +

1DO n +

2DO n +

3DO n +

4DO n +

5DO n +

6DO n +

7D

I nDI n +

1DI n +

2DI

n +

3DI n +

4DI n +

5DI n +

6DI n +

7

RE

AD

-to-W

RIT

E co

mm

and

del

ay =

RL

+ t C

CD

+ 2

t CK

- W

Lt B

L =

4 clo

cks

Addr

ess2

Bank

,Co

l bBa

nk,

Col n

RL

= 5

Figure 63 - READ (BL8) to WRITE (BL8)



ST9D364M64SBG2



Not

es:

1.N

OP

com

man

ds a

re s

how

n fo

r eas

e of

illu

stra

tion;

oth

er c

omm

ands

may

be

valid

at t

hese

tim

es.

2.Th

e B

C4

OTF

set

ting

is a

ctiv

ated

by

MR

0[1:

0] a

nd A

12 =

0 d

urin

g R

EA

D c

omm

and

at T

0 an

d W

RIT

E c

omm

and

at T

4.3.

DO

n =

dat

a-ou

t fro

m c

olum

n n;

DI n

= d

ata-

in fr

om c

olum

n b.

4.B

C4,

RL

= 5

(AL

- 0, C

L = 5

), W

L =

5 (A

L =

0, C

WL

= 5)

.

Don

’t Ca

reTr

ansi

tioni

ng D

ata

T0T1

T2T3

T4T5

T6T7

T8T9

T10

T11

T12

T13

T14

T15

CK

CK#

Addr

ess2

Bank

,Co

l nBa

nk,

Col b

Com

man

d1RE

ADNO

PNO

PNO

PW

RITE

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

t WPS

Tt W

PR

Et R

PST

DQS,

DQ

S#

DQ3

WL

= 5

RE

AD

-to-W

RIT

E co

mm

and

del

ay =

RL

+ t C

CD

/2 +

2t C

K -

WL

t WR

t WTR

t BL

= 4

clo

cks

t RP

RE

RL

= 5

DO n

DO

n+ 1

DO n+

2DO n +

3D

I nD

I n

+ 1

DI n +

2DI n+

3

Figure 64 - READ (BC4) to WRITE (BC4) OTF



ST9D364M64SBG2



Not

es:

1.N

OP

com

man

ds a

re s

how

n fo

r eas

e of

illu

stra

tion;

oth

er c

omm

ands

may

be

valid

at t

hese

tim

es.

2.Th

e B

L8 s

ettin

g is

act

ivat

ed b

y ei

ther

MR

0[1:

0] =

00

or M

R0[

1:0]

= 0

1 an

d A

12 =

1 d

urin

g th

e R

EA

D c

omm

and

at T

0, a

nd

the

WR

ITE

com

man

d at

T6.

3.D

O n

= d

ata-

out f

rom

col

umn,

DI b

= d

ata-

in fo

r col

umn

b.4.

BL8

, RL

= 5

(AL

= 0,

CL

= 5)

, WL

= 5

(AL

= 0,

CW

L =

5).

Don

’t Ca

reTr

ansi

tioni

ng D

ata

T0T1

T2T3

T4T5

T6T7

T8T9

T10

T11

T12

T13

T14

T15

CK

CK#

Com

man

d1NO

PNO

PNO

PNO

PNO

PW

RITE

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

t WPS

Tt R

PR

Et W

PR

Et R

PST

DQS,

DQ

S#

DQ3

WL

= 5

t WR

t WTR

READ

DO n

DO n +

1DO n +

2DO n +

3DO n +

4DO n +

5DO n +

6DO n +

7D

I nDI n +

1DI n +

2DI

n +

3DI n +

4DI n +

5DI n +

6DI n +

7

RE

AD

-to-W

RIT

E co

mm

and

del

ay =

RL

+ t C

CD

+ 2

t CK

- W

Lt B

L =

4 clo

cks

Addr

ess2

Bank

,Co

l bBa

nk,

Col n

RL

= 5

Figure 65 - READ to PRECHARGE (BL8)



ST9D364M64SBG2



CK

CK#

Don

’t Ca

reTr

ansi

tioni

ng D

ata

T0T1

T2T3

T4T5

T6T7

T8T9

T10

T11

T12

T13

T14

T15

T16

T17

Com

man

dNO

PNO

PNO

PNO

PNO

PNO

PNO

PNO

PNO

PAC

TNO

PNO

PNO

PNO

PNO

PRE

ADNO

PPR

E

Addr

ess

Bank

a,

Col n

Bank

a,

(or a

ll)Ba

nk a

,Ro

w b

t RP

t RTP

DQS,

DQ

S#

DQD

O nD

On

+ 1

DO

n+

2D

On

+ 3

t RAS

Figure 66 - READ to PRECHARGE (BC4)



ST9D364M64SBG2



CKCK#

Com

man

d

DQ

DQS,

DQ

S#

ACTI

VE n

T0T1

Don

’t C

are

NOP

NOP

T6T1

2

NOP

READ

n

T13

NOP

DO n+

3DO n +

2DO n +

1

RL

= AL

+ C

L =

11

T14

NOP

DO n

t RC

D (M

IN)

AL =

5C

L =

6T11

BC4

Indi

cate

s a

Brea

k in

Ti

me

Scal

eTr

ansi

tioni

ng D

ata

T2

NOP

Figure 67 - READ to PRECHARGE (AL = 5, CL = 6)



ST9D364M64SBG2



CKCK#

Com

man

dNO

PNO

PNO

PNO

P

Addr

ess

DQ

DQS,

DQ

S#

Don

’t Ca

reTr

ansi

tioni

ng D

ata

NOP

NOP

NOP

NOP

NOP

T0T1

T2T3

T4T5

T6T7

T8T9

T10

T11

T12

T13

Ta0

t RTP

(MIN

)

NOP

READ

NOP

AL

= 4

NOP

NOP

CL =

6

NOP

t RAS

(MIN

)

ACT

Indi

cate

s A

Bre

ak in

Ti

me

Sca

le

t RP

Bank

a,

Col n

Bank

a,

Row

b

DO n

DO

n+

1D

On

+ 2

DO

n+

3

Figure 68 - READ with Auto Precharge (AL = 4, CL = 6)



ST9D364M64SBG2



ADQSxtoDQoutputtimingisshowninFigure69.TheDQtransitionsbetweenvaliddataoutputsmustbewithintDQSQofthecrossingpointofDQSxandDQSx\.DQSmustalsomaintainaminimumHIGHandLOWtimeoftQSH and tQSL.PriortotheREADpreamble,theDQballswilleitherbefloatingorterminateddependingonthestatusoftheODTsignal.

Figure70showsthestrobe-to-clocktimingduringaREAD.ThecrossingpointDQSx,DQSx\musttransitionwith±tDQSCKoftheclockcrossingpoint.Thedataouthasnotimingrelationshiptoclock,onlytoDQS,asshowninFigure70.

Figure70alsoshowstheREADpreambleandpostamble.Normally,bothDQSxandDQSx\areHIGH-Ztosavepower(VDDQ).PriortodataoutputfromtheSDRAM,DQSxisdrivenLOWandDQSx\drivenHIGHfortRPRE.ThisisknownastheREADpreamble.

TheREADpostamble,tRPST,isonehalfclockfromthelastL[U]DQSx,L[U]DQSx\transition.DuringtheREADpostamble,DQSxisdrivenLOWandDQSx\drivenHIGH.Whencomplete,theDQwilleitherbedisabledorwillcontinueterminatingdependingonthestateoftheODTsignal.Figure75demonstrateshowtomeasuretRPST.

READ



ST9D364M64SBG2



Not

es:

1.N

OP

com

man

ds a

re s

how

n fo

r eas

e of

illu

stra

tion;

oth

er c

omm

ands

may

be

valid

at t

hese

tim

es.

2.Th

e B

L8 s

ettin

g is

act

ivat

ed b

y ei

ther

MR

0[1,

0] =

0, 0

or M

R0[

0, 1

] = 0

, 1 a

nd A

12 =

1 d

urin

g R

EA

D c

omm

and

at T

0.3.

DO

n =

dat

a-ou

t fro

m c

olum

n n.

4.B

L8, R

L =

5 (A

L =

0, C

L =

5).

5.O

utpu

t tim

ings

are

refe

renc

ed to

VC

CQ

/2 a

nd D

LL o

n an

d lo

cked

.6.

t DQ

SQ

def

ines

the

skew

bet

wee

n D

QS

, DQ

S#

to d

ata

and

does

not

def

ine

DQ

S, D

QS

# to

clo

ck.

7.E

arly

dat

a tra

nsiti

ons

may

not

alw

ays

happ

en a

t the

sam

e D

Q. D

ata

trans

ition

s of

a D

Q c

an v

ary

(eith

er e

arly

or l

ate)

w

ithin

a b

urst

.

T0T1

T2T3

T4T5

T6T7

T8T9

T10

Bank

,Co

l n

t RPS

T

NOP

READ

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Com

man

d1

Addr

ess 2

t DQ

SQ (M

AX)

DQS,

DQ

S#

DQ3

(last

dat

a va

lid)

DQ3

(firs

t da

ta n

o lo

nge

r val

id)

All D

Q c

olle

ctive

ly

DO nDO n+

3DO n +

2DO n+

1DO n+

7DO n+

6DO n+

5DO n+

4DO n +

2DO n+

1DO n+

7DO n +

6DO n+

5DO n+

4

DO n+

3DO n

+ 2

DO n+

1DO n

DO n+

7DO n

+ 6

DO n+

5

DO nDO n +

3

t RP

RE

Don

’t Ca

reTr

ansi

tioni

ng D

ata

Dat

a va

lidD

ata

valid

t QH

t QH

t HZ

(DQ

) MAX

DO

n+

4

RL

= A

L +

CL

t DQ

SQ (M

AX)

t LZ

(DQ

) MIN

Figure 69 - Data Output Timing – tDQSQ and Data Valid Window



ST9D364M64SBG2



tHZandtLZtransitionsoccurinthesameaccesstimeasvaliddatatransitions.Theseparametersarereferencedtoaspecificvoltagelevelwhichspeci-fieswhenthedeviceoutputisnolongerdrivingtHZ(DQS)andtHZ(DQ)orbeginsdrivingtLZ(DQS).tLZ(DQ),Figure71showsamethodtocalculatethepointwhenthedeviceisnotlongerdrivingtHZ(DQS)andtHZ(DQ)orbeginsdrivingtLZ(DQS),tLZ(DQ)bymeasuringthesignalattwodifferentvoltages.Theactualvoltagemeasurementpointsarenotcriticalaslongasthecalculationisconsistent.TheparameterstLZ(DQS),tLZ(DQ),tHZ(DQS)andtHZ(DQ)aredefinedassingle-ended.

OUTPUT TIMING



ST9D364M64SBG2



RL

mea

sure

dto

this

poi

nt

DQS,

DQ

S#ea

rly s

trobeCK

t DQ

SCK (

MIN

)

t LZ

(DQ

S) M

IN

t HZ

(DQ

S) M

IN

DQS,

DQ

S#la

te s

trobe

t DQ

SCK (

MAX

)t L

Z (D

QS)

MAX

t HZ

(DQ

S) M

AX

t DQ

SCK (

MIN

)t D

QSC

K (M

IN)

t DQ

SCK (

MAX

)t D

QSC

K (M

AX)

t DQ

SCK (

MAX

)

t DQ

SCK (

MIN

)

CK#

t RPR

E

t QSH

t QSL

t QSL

t QSL

t QSL

t QSH

t QSH

t QSH

Bit 0

Bit 1

Bit 2

Bit

7

t RPR

E

Bit 0

Bit 1

Bit 2

Bit

7Bi

t 6Bi

t 3Bi

t 4Bi

t 5Bit 6

Bit 4

Bit 3

Bit 5

t RPS

T

t RPS

T

T0T1

T2T3

T4T5

T6

Figure 70 - Data Strobe Timing – READs



ST9D364M64SBG2



Notes: 1. Within a burst, the rising strobe edge is not necessarily fixed at tDQSCK (MIN) or tDQSCK (MAX). Instead, the rising strobe edge can vary between tDQSCK (MIN) and tDQSCK (MAX).

2. The DQS high pulse width is defined by tQSH, and the DQS low pulse width is defined by tQSL. Likewise, tLZ (DQS) MIN and tHZ (DQS) MIN are not tied to tDQSCK (MIN) (early strobe case) and tLZ (DQS) MAX and tHZ (DQS) MAX are not tied to tDQSCK (MAX) (late strobe case); however, they tend to track one another.

3. The minimum pulse width of the READ preamble is defined by tRPRE (MIN). The minimum pulse width of the READ postamble is defined by tRPST (MIN).

tHZ (DQS), tHZ (DQ)

tHZ (DQS), tHZ (DQ) end point = 2 × T1 - T2

VOH - xmV

VTT - xmV

VOL + xmV

VTT + xmVVOH - 2xmV

VTT - 2xmV

VOL + 2xmV

VTT + 2xmV

tLZ (DQS), tLZ (DQ)

tLZ (DQS), tLZ (DQ) begin point = 2 × T1 - T2

T1

T1T2

T2

Figure 71 - Method for Calculating tLZ and tHZ



ST9D364M64SBG2



FiGure 72 - trpre timiNG

tRPREDQS - DQS#

DQS

DQS#

T1tRPRE begins

T2tRPRE ends

CK

CK#

VTT

Resulting differential signal relevant for tRPRE specification

tC

tA tB

tD

0V

VTT

VTT

Single-ended signal, providedas background information


FiGure 73 - trpSt timiNG

tRPSTDQS - DQS#

DQS

DQS#

T1tRPST begins

T2tRPST ends

Resulting differential signal relevant for tRPST specification

CK

CK#

VTT

tC

tA

tB

tD


0V

VTT

VTT




ST9D364M64SBG2



FiGure 74 - twpre timiNG

DQS - DQS#

T1 tWPRE begins

T2 tWPRE ends

tWPRE Resulting differential

signal relevant for tWPRE specification

0V

CK

CK#

VTT

FiGure 75 - twpSt timiNG

tWPSTDQS - DQS#

T1tWPST begins

T2tWPST ends

Resulting differential signal relevant for tWPST specification

0V

CK

CK#

VTT



ST9D364M64SBG2



WRITE

WRITEburstsareinitiatedwithaWRITEcommand.ThestartingCOLUMNandBANKaddressesareprovidedwiththeWRITEcommand,andAUTOPRECHARGEisselected,theROWbeingaccessedwillbePRECHARGEDattheendofWRITEburst.IfAUTOPRECHARGEisnotselected,theROWwillremainopenforsubsequentaccesses.AfteraWRITEcommandhasbeenissued,theWRITEburstmaynotbeinterrupted.ForthegenericWRITEcom-mandsusedinFigure76thoughFigure84,AUTOPRECHARGEisdisabled.

DuringWRITEbursts,thefirstvaliddata-inelementisregisteredonarisingedgeofDQSxfollowingtheWRITELATENCY(WL)clockslaterandsubse-quentdataelementswillberegisteredonsuccessiveedgesofDQSx.WRITELATENCY(WL)isdefinedasthesumofPOSTEDCASADDITIVELATENCY(AL)andCASWRITELATENCY(CWL):WL=AL+CWL.ThevaluesofALandCWLareprogrammedintheMR-andMR2registers,respectively.PriortothefirstvalidDQSxedge,afullcycleisneeded(includingadummycrossoverofDQSx,DQSx\)andspecifiedastheWRITEpreambleshowninFigure76.ThehalfcycleonDQSxfollowingthelastdata-inelementisknownastheWRITEpostamble.

ThetimebetweentheWRITEcommandandthefirstvalidedgeofDQSxisWLclocks±tDQSS.Figure77throughFigure84showthenominalcasewheretDQSS=0ns;however,Figure76includestDQSS(MIN)andtDQSS(MAX)cases.

DatamaybemaskedfromcompletingaWRITEusingdatamask.ThemaskoccursontheDMballalignedtotheWRITEdata.IfDMisLOW,theWRITEcompletesnormally.IfDMisHIGH,thatbitofdataismasked.

Uponcompletionofaburst,assumingnoothercommandshavebeeninitiated,theDQwillremainHIGH-Zandanyadditionalinputdatawillbeignored.

DataforanyWRITEburstmaybeconcatenatedwithasubsequentWRITEcommandtoprovideacontinuousflowofinputdata.ThenewWRITEcom-mandcanbetCCDclocksfollowingthepreviousWRITEcommand.Thefirstdataelementfromthenewburstisappliedafterthelastelementofacompletedburst.Figures77and78showconcatenatedbursts.AnexampleofnonconsecutiveWRITESisshowninFigure79.

DataforanyWRITEburstmaybefollowedbyasubsequentREADcommandaftertWTRhasbeenmet(seeFigures80,81and82).



ST9D364M64SBG2



FiGure 76 - write burSt

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.

2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE command at T0.

3. DI n = data-in for column n.4. BL8, WL = 5 (AL = 0, CWL = 5).5. tDQSS must be met at each rising clock edge.6. tWPST is usually depicted as ending at the crossing of DQS, DQS#; however, tWPST actually

ends when DQS no longer drives LOW and DQS# no longer drives HIGH.

DI n + 3

DI n + 2

DI n + 1

DI n

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10


DI n + 7

DI n + 6

DI n + 5

DIn + 4

Bank,Col n

NOPWRITE NOPNOP NOP NOP NOP NOP NOP NOP NOP

CK

CK#

Command1

DQ3

DQS, DQS#

Address2

tWPST

tWPRE tWPST

tDQSL

DQ3

DQ3

tWPST

DQS, DQS#

DQS, DQS#

tDQSL

tWPRE

tDQSS

tDQSS tDSH tDSH tDSH tDSH

tDSS tDSS tDSS tDSS tDSS

tDSS tDSS tDSS tDSS tDSS

tDSH tDSH tDSH tDSH

tDQSLtDQSH tDQSLtDQSH tDQSLtDQSH tDQSH tDQSL

tDQSL

tDQSL

tDQSLtDQSHtDQSH

tDQSH

tDQSH

tDQSLtDQSH tDQSLtDQSH tDQSH

tDQSLtDQSH tDQSLtDQSH tDQSLtDQSH tDQSH

WL = AL + CWL

tDQSS (MIN)

tDQSS (NOM)

tDQSS (MAX)

tDQSL

tWPRE

DI n + 3

DI n + 2

DI n + 1

DI n

DI n + 7

DI n + 6

DI n + 5

DIn + 4

DI n + 3

DI n + 2

DI n + 1

DI n

DI n + 7

DI n + 6

DI n + 5

DIn + 4



ST9D364M64SBG2



FiGure 77 - cONSecutiVe write (bl8) tO write (bl8)

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE commands at

T0 and T4.3. DI n (or b) = data-in for column n (or column b).4. BL8, WL = 5 (AL = 0, CWL = 5).

WL = 5

WL = 5

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

tCCD

tWPRE

T10 T11


T12 T13 T14

ValidValid

NOPWRITE WRITENOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP

CK

CK#

Command1

DQ3

DQS, DQS#

Address2

tWPST

tWRtWTR

tBL = 4 clocks

DI n + 3

DI n + 2

DI n + 1

DI n

DI n + 7

DI n + 6

DIn + 5

DIn + 4

DI b + 3

DI b + 2

DI b + 1

DI b

DI b + 7

DI b + 6

DI b + 5

DIb + 4

FiGure 78 - cONSecutiVe write (bc4) tO write (bc4) Via mrS Or OtF

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.2. BC4, WL = 5 (AL = 0, CWL = 5).3. DI n (or b) = data-in for column n (or column b).4. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and T4.

WL = 5

WL = 5

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

tCCD

tWPRE

T10 T11


T12 T13 T14

Valid Valid

NOPWRITE WRITENOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP

CK

CK#

Command1

DQ3

DQS, DQS#

Address2

tWPST

tWRtWTR

tWPST tWPRE

DI n + 3

DI n + 2

DI n + 1

DIn

DI b + 3

DI b + 2

DI b + 1

DI b

tBL = 4 clocks



ST9D364M64SBG2



FiGure 79 - NONcONSecutiVe write tO write

Notes: 1. DI n (or b) = data-in for column n (or column b).2. Seven subsequent elements of data-in are applied in the programmed order following DO n.3. Each WRITE command may be to any bank.4. Shown for WL = 7 (CWL = 7, AL = 0).

CK

CK#

Command NOP NOP NOP

Address

DQ

DM

DQS, DQS#

Transitioning Data

NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17

NOPWRITE NOP WRITE

ValidValid

NOP

DIn

DIn + 1

DIn + 2

DIn + 3

DIn + 4

DIn + 5

DIn + 6

Don't Care

DIn + 7

DIb

DIb + 1

DIb + 2

DIb + 3

DIb + 4

DIb + 5

DIb + 6

DIb + 7

WL = CWL + AL = 7WL = CWL + AL = 7

FiGure 80 - write (bl8) tO read (bl8)

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.2. tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write

data shown at T9.3. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the WRITE command at T0.

The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0.4. DI n = data-in for column n.5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).

WL = 5

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

tWPRE

T10 T11


Ta0

NOPWRITE READ

ValidValid

NOP NOP NOP NOP NOP NOP NOP NOPNOP NOP

CK

CK#

Command1

DQ4

DQS, DQS#

Address3

tWPST

tWTR 2


DIn + 3

DIn + 2

DIn + 1

DIn

DIn + 7

DIn + 6

DIn + 5

DIn + 4



ST9D364M64SBG2



FiGure 81 - write tO read (bc4 mOde reGiSter SettiNG)

Not

es:

1.N

OP

com

man

ds a

re s

how

n fo

r eas

e of

illu

stra

tion;

oth

er c

omm

ands

may

be

valid

at t

hese

tim

es.

2.t W

TR c

ontro

ls th

e W

RIT

E-to

-RE

AD

del

ay to

the

sam

e de

vice

and

sta

rts w

ith th

e fir

st ri

sing

clo

ck e

dge

afte

r the

last

writ

e da

ta s

how

n at

T7.

3.Th

e fix

ed B

C4

setti

ng is

act

ivat

ed b

y M

R0[

1:0]

= 1

0 du

ring

the

WR

ITE

com

man

d at

T0

and

the

RE

AD

com

man

d at

Ta0

.4.

DI n

= d

ata-

in fo

r col

umn

n.5.

BC

4 (fi

xed)

, WL

= 5

(AL

= 0,

CW

L =

5), R

L =

5 (A

L =

0, C

L =

5).

WL

= 5

T0T1

T2T3

T4T5

T6T7

T8T9

Ta0

Don

’t Ca

reTr

ansi

tioni

ng D

ata

NOP

WRI

TE

Valid

READ

Valid

PON

PON

PON

PON

PON

PON

PON

NOP

CK

CK#

Com

man

d1

DQ4

DQS,

DQ

S#

Addr

ess3

t WPS

T

t WTR

2

t WP

RE

Indi

cate

s a

Bre

ak in

Ti

me

Sca

le

DI n +

3DI n +

2DI n +

1DI n



ST9D364M64SBG2



FiGure 82 - write (bc4 OtF) tO read (bc4 OtF)

Not

es:

1.N

OP

com

man

ds a

re s

how

n fo

r eas

e of

illu

stra

tion;

oth

er c

omm

ands

may

be

valid

at t

hese

tim

es.

2.t W

TR c

ontro

ls th

e W

RIT

E-to

-RE

AD

del

ay to

the

sam

e de

vice

and

sta

rts a

fter t B

L.3.

The

BC4

OTF

set

ting

is a

ctiv

ated

by

MR

0[1:

0] =

01

and

A12

= 0

dur

ing

the

WR

ITE

com

man

d at

T0

and

the

RE

AD

com

man

d at

Tn.

4.D

I n =

dat

a-in

for c

olum

n n.

5.B

C4,

RL

= 5

(AL

= 0,

CL

= 5)

, WL

= 5

(AL

= 0,

CW

L =

5).

WL

= 5

RL

= 5

T0T1

T2T3

T4T5

T6T7

T8T9

t WP

RE

T10

T11

Don

’t Ca

reTr

ansi

tioni

ng D

ata

Tn

NOP

WRI

TERE

AD

Valid

Valid

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CK

CK#

Com

man

d1

DQ4

DQS,

DQ

S#

Addr

ess3

t WPS

T

t BL

= 4

clock

s

NOP

t WTR

2

Indi

cate

s a

Bre

ak in

Ti

me

Sca

le

DI n

+ 3

DI n

+ 2

DI n

+ 1

DI n



ST9D364M64SBG2



FiGure 83 - write (bl8) tO precharGe

Notes: 1. DI n = data-in from column n.2. Seven subsequent elements of data-in are applied in the programmed order following

DO n.3. Shown for WL = 7 (AL = 0, CWL = 7).

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 Ta0 Ta1

DIn + 3

DIn + 2

DIn + 1

DIn

DIn + 6

DIn + 7

DIn + 5

DIn + 4

NOPWRITE

Valid

NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PRE

CK

CK#

Command

DQ BL8

DQS, DQS#

Address

Don’t CareTransitioning DataIndicates a Break in Time Scale

tWRWL = AL + CWL

Valid

FiGure 84 - write (bc4 mOde reGiSter SettiNG) tO precharGe


2. The write recovery time ( tWR) is referenced from the first rising clock edge after the last write data is shown at T7. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank.

3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0.4. DI n = data-in for column n.5. BC4 (fixed), WL = 5, RL = 5.

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 Ta0 Ta1

DIn + 3

DIn + 2

DIn + 1

DIn

NOPWRITE

Valid

NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PRE

CK

CK#

Comman d

DQ BC4

DQS, DQS#

Address

Don’t CareTransitioning DataIndicates a Break in Time Scale

tWRWL = AL + CWL

Valid



ST9D364M64SBG2



FiGure 85 - write (bc4 OtF) tO precharGe


2. The write recovery time ( tWR) is referenced from the rising clock edge at T9. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank.

3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0.4. DI n = data-in for column n.5. BC4 (OTF), WL = 5, RL = 5.

WL = 5

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Tn

Don’t Care Transitioning Data

Bank, Col n

NOP WRITE PRENOP NOP NOP NOP NOP NOP NOP NOP

CK

CK#

Command1

DQ4

DQS, DQS #

Address3

tWPST tWPRE

Indicates a Break In Time Scale

DI n + 3

DI n + 2

DI n + 1

DI n

tWR2

Valid

DQ INPUT TIMING

FiGure 86 - data iNput timiNG

tDHtDS

DM

DQ DIb

DQ S, DQS#

Don ’t CareTransitioning Data

tDQSH tDQSLtWPRE tWPST

bythememorycontrollerafterthelastdataiswrittentotheSDRAMduringtheWRITEpostamble,tWPST.

DatasetupandholdtimesareshowninFigure86.AllsetupandholdtimesaremeasuredfromthecrossingpointsofDQSxandDQSx\.Thesesetupandholdvaluespertaintodatainputanddatamaskinput.

Additionally,thehalfperiodofthedatainputstrobeisspecifiedbytDQSH and tDQSL.

Figure76showsthestrobetoclocktimingduringaWRITE.DQSx,DQSx\musttransitionwithin0.25tCKoftheclocktransitionsaslimitedbytDQSS.Alldataanddatamasksetupandholdtimingsaremea-suredrelativetotheDQSx,DQSx\crossings,nottheclockcrossing.

TheWRITEpreambleandpostamblearealsoshown.OneclockpriortodatainputtotheSDRAM,DQSxmustbeHIGHandDQSx\mustbeLOW.Thenforahalfclock,DQSxisdrivenLOW(DQSx\isdrivenHIGH)duringtheWRITEpreamble.tWPRE,likewise,DQSxmustbekeptLOW



ST9D364M64SBG2



PRECHARGE

InputA10determineswhetheronebankorallbanksaretobePRECHARGEDandinthecasewhereonlyonebankistobeprecharged,inputsBA[2:0]selectthearrayBANK.

WhenallbanksaretobePRECHARGED,inputsBA[2:0]aretreatedas“Don’tCare”.AfterabankisPRECHARGED,itisintheIDLEStateandmustbeACTIVATEDpriortoanyREADorWRITEcommandsbeingissued.

SELF REFRESH

TheSELFREFRESHcommandisinitiatedlikeaREFRESHcommandexceptCKEisLOW.TheDLLisautomaticallydisableduponenteringSELFREFRESHandisautomaticallyenabledandresetuponexitingSELFREFRESH.Allpowersupplyinputs(includingVREFCAandVREFDQ)mustbemaintainedatvalidlevelsuponentry/exitandduringSELFREFRESHmodeoperation.VREFDQmayfloatornotdriveVDDQ/2whileintheSELFREFRESHmodeundercertainconditions:

•Vss<VREFDQ<VDDismaintained•VREFDQisvalidandstablepriortoCKEgoingbackHIGH•ThefirstWRITEoperationmaynotoccurearlierthan512clocksafterVREFDQisvalid•AllotherSELFREFRESHmodeexittimingrequirementsaremet

TheSDRAMmustbeidlewithallBANKSinthePRECHARGEstate(tRPissatisfiedandnoburstsareinprogress)beforeaSELFREFRESHentrycommandcanbeissued.ODTmustalsobeturnedoffbeforeSELFREFRESHentrybyregisteringtheODTballLOWpriortotheSELFREFRESHentrycommand(see“On-DieTermination(ODT)fortimingrequirements).IfRTT_NOMandRTT_WRaredisabledinthemoderegisters,ODTcanbea“Don’tCare”.AftertheSELFREFRESHentrycommandisregistered,CKEmustbeheldLOWtokeeptheSDRAMinSELFREFRESHmode.

AftertheSDRAMhasenteredSELFREFRESHmode,allexternalcontrolsignals,exceptCKEandRESET\,become“Don’tCare”.TheSDRAMinitiatesaminimumofoneREFRESHcommandinternallywithinthetCKEperiodwhenitentersSELFREFRESHmode.

TherequirementsforenteringandexitingSELFREFRESHmodedependonthestateoftheclockduringSELFREFRESHmode.Firstandforemost,theclockmustbestable(meetingtCKspecifications)whenSELFREFRESHmodeisentered.IftheclockremainsstableandthefrequencyinnotalteredwhileinSELFREFRESHmode,thentheSDRAMisallowedtoexitSELFREFRESHaftertCKESRissatisfied(CKEisallowedtotransitionHIGHtCKESRlaterthanwhenCKEwasregisteredLOW).SincetheclockremainsstableinSELFREFRESHmode(nofrequencychange),tCKSREandtCKSRXarenotrequired.However,iftheclockisalteredduringSELFREFRESHmode,thentCKSREandtCKSRXmustbesatisfied.WhenenteringSELFREFRESH,tCKSREmustbesatisfiedpriortoalteringtheclock’sfrequency.PriortoexitingSELFREFRESH,tCKSRXmustbesatisfiedpriortoregisteringCKEHIGH.

WhenCKEisHIGHduringSELFREFRESHexit,NOPorDESmustbeissuedfortXStime.tXSisrequiredforthecompletionofanyinternalREFRESHthatisalreadyinprogressandmustbesatisfiedbeforeavalidcommandnotrequiringalockedDLLcanbeissuedtothedevice.tXSisalsotheearliesttimethataSELFREFRESHre-entrymayoccur(seeFigure87).BeforeacommandrequiringalockedDLLcanbeapplied,aZQCLcommandmustbeissued.



ST9D364M64SBG2



FiGure 87 - SelF reFreSh eNtry/exit timiNG

Notes: 1. The clock must be valid and stable meeting tCK specifications at least tCKSRE after entering self refresh mode, and at least tCKSRX prior to exiting self refresh mode, if the clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and unchanged from entry and during self refresh mode, then tCKSRE and tCKSRX do not apply; however, tCKESR must be satisfied prior to exiting at SRX.

2. ODT must be disabled and RTT off prior to entering self re fresh at state T1. If both RTT_NOM and RTT_WR are disabled in the mode registers, ODT can be a “Don’t Care.”

3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW.4. A NOP or DES command is required at T2 after the SRE command is issued prior to the

inputs becoming “Don’t Care.”5. NOP or DES commands are required prior to exiting self refresh mode until state Te0.6. tXS is required before any commands not requiring a locked DLL.7. tXSDLL is required before any commands requiring a locked DLL.8. The device must be in the all banks idle state prior to entering self refresh mode. For exam-

ple, all banks must be precharged, tRP must be met, and no data bursts can be in progress.9. Self refresh exit is asynchronous; however, tXS and tXSDLL timings start at the first rising

clock edge where CKE HIGH satisfies t ISXR at Tc1. tCKSRX timing is also measured so that t ISXR is satisfied at Tc1.

CK

CK#

Command NOP NOP4SRE(REF)3

Address

CKE

ODT2

RESET#2

Valid

Valid6SRX (NOP) NOP5

tRP 8 tXS 6 , 9

tXSDLL7, 9

ODTL

t IStCPDEDtIS

t IS

Enter self refresh mode(synchronous)

Exit self refresh mode(asynchronous)

T0 T1 T2 Tc0 Tc1 Td0Tb0

Don’t Care

Te0

Valid

Valid7

Valid

Valid Valid

t IH

Ta0 Tf0


tCKSRX1tCKSRE1

tCKESR (MIN)1



ST9D364M64SBG2



SelfRefreshTemperature(SRT)

EXTENDED TEMPERATURE USAGE

Themodulesupportstheoptionalextendedtemperaturerangeupto≤95°CwhilesupportingSELFREFRESH/AUTOREFRESHandsupportTAtem-peratures>95°C≤125°CwithMANUALREFRESHonly.WhenusingSELFREFRESH/AUTOREFRESHandtheambienttemperatureis>85°C,SRTandASRoptionsmustbeused.

TheextendedrangetemperaturerangeDRAMmustbeREFRESHEDexternallyat2Xanytimetheambienttemperatureis>85°C.TheexternalREFRESH-INGrequirementisaccomplishedbyreducingtheREFRESHPERIODfrom64msto32ms.SELFREFRESHmoderequirestheuseofASRorSRTtosupporttheextendedtemperature.

Field MR2 Bits Description

SRT

ASR

table 63: SelF reFreSh temperature aNd autO SelF reFreSh deScriptiON

IfASRisdisabled(MR2[6]=0),SRTmustbeprogrammedtoindicatetOPERduringSELFREFRESH;

*MR2[7]=0:Normaloperatingtemperaturerange(0°Cto≤ 85°C)

*MR2[7]=1:Extendedoperatingtemperaturerange(>85°Cto≤105°C)

IfASRisenabled(MR2[7]=1),SRTmustbesetto0,eveniftheextendedtemperaturerangeissupported.

*MR2[7]=0:SRTisdisabled.

WhenASRisenabled,theSDRAMautomaticallyprovidesSELFREFRESHpowermanagementfunctions,(refreshrate

forallsupportedoperatingtemperaturevalues)

*MR2[6]=1:ASRisenabled(M7must=0)

WhenASRisnotenabled,theSRTbitmustbeprogrammedtoindicatetOPERduringSELFREFRESHoperation.

*MR2[6]=0:ASRisdisabled,mustusemanualSELFREFRESH(SRT)

7

6

AutoSelfRefresh(ASR)

SELF REFRESH Operation0

0

1

1

table 64: SelF reFreSh mOde Summary

SELFREFRESHModeissupportedinthenormaltemperaturerange.

SELFREFRESHModeissupportedinnormalandextended(≤ 95°CMAX)

temperatureranges;WhenSRTisenabled,itincreasesselfrefreshpower

consumption.

Selfrefreshmodeissupportedinnormalandextendedtemperatureranges;

Selfrefreshpowerconsumptionmaybetemperature-dependent.

Illegal.

0

1

0

1

Permitted Operating TemperatureRange for Self Refresh Mode

MR2[7](SRT)

MR2[6](ASR)

Normal(0°Cto85°C)

Normalandextended(0°Cto95°C)

Normalandextended(0°Cto95°C)

POWER-DOWN MODE

Power-downissynchronouslyenteredwhenCKEisregisteredLOWcoincidentwithaNOPorDEScommand.CKEisnotallowedtogoLOWwhileeitheranMRS,MPR,ZQCAL,READorWRITEoperationisinprogress.CKEisallowedtogoLOWwhileanyoftheotherlegaloperationsareinprogress.However,thePOWER-DOWNIDDspecificationsarenotapplicableuntilsuchoperationshavebeencompleted.DependingonthepreviousSDRAMstateandthecommandissuedpriortoCKEgoingLOW,certaintimingconstraintsmustbesatisfied(asnotedinTable65).TimingdiagramsdetailingthedifferentPOWER-DOWNmodeentryandexitsareshowninFigure88throughFigure97.



ST9D364M64SBG2



Idle or Active

Idle or Active

Active

Active

Active

Active

Active

Idle

POWER-DOWN

Idle

table 65: cOmmaNd tO pOwer-dOwN eNtry parameterS

tACTPDENtPRPDENtRDPDENtWRPDEN

tWRAPDEN

tREFPDENtXPDLL

tMRSPDEN

ACTIVATE

PRECHARGE

READorREADAP

WRITE:BL8OTF,BL8MRS,BC4OTF

WRITE:BC4MRS

WRITEAP:BL8OTF,BL8MRS,BC4OTF

WRITEAP:BC4MRS

REFRESH

REFRESH

MODEREGISTERSET

Last Command prior to CKE Low 1

1tCK

1tCK

RL+4tCK+1tCK

WL+4tCK+tWR/tCK

WL+2tCK+tWR/tCK

WL+4tCK+WR+1tCK

WL+2tCK+WR+1tCK

1tCK

Greaterof10tCKor24nstMOD

Figure 95

Figure96

Figure 91

Figure92

Figure92

Figure 93

Figure 93

Figure94

Figure 98

Figure97

SDRAM Status Parameter (MIN) Parameter Value Figure

EnteringPOWER-DOWNmodedisablestheinputandoutputbuffers,excludingCK,CK\,ODT,CKEandRESET\.NOPorDEScommandsarerequireduntil tCPDEDhasbeensatisfied,atwhichtimeallspecifiedinput/outputbufferswillbedisabled.TheDLLshouldbeinalockedstatewhenPOWER-DOWNisenteredforthefastestmodetiming.IftheDLLisnotlockedduringthePOWER-DOWNentry,theDLLmustberesetafterexitingPOWER-DOWNforproperREADoperationaswellassynchronousODToperation.

DuringPOWER-DOWNentry,ifanybankremainsopenafterallin-progresscommandsarecomplete,theSDRAMwillbeinACTIVEPOWER-DOWN.Ifallbanksareclosedafterallin-progresscommandsarecomplete,theSDRAMwillbeinPRECHARGEPOWER-DOWNmodeorfastEXITmode.WhenenteringPRECHARGEPOWER-DOWN,theDLListurnedoffinslowexitmodeorkeptoninfastEXITmode.

TheDLLremainsonwhenenteringACTIVEPOWER-DOWNaswell.ODThasspecialtimingconstraintswhenslowEXITmode,PRECHARGEPOWER-DOWNisenabledandentered.Referto“AsynchronousODTMode”fordetailedODTusagerequirementsinslowEXITmodePRECHARGEPOWER-DOWN.AsummaryofthetwoPOWER-DOWNmodesislistedinTable66.

WhileineitherPOWER-DOWNstate,CKEisheldLOW,RESET\isheldHIGH,andastableclocksignalmustbemaintained.ODTmustbeinavalidstatebutallotherinputsignalsarea“Don’tCare”.IfRESET\goesLOWduringPOWER-DOWN,theSDRAMwillswitchoutofPOWER-DOWNandgointotheRESETstate.AfterCKEisregisteredLOW,CKEmustremainLOWuntiltPD(MIN)hasbeensatisfied.ThemaximumtimeallowedforPOWER-DOWNdurationistPD(MAX)(9xtREFI).

ThePOWER-DOWNstatesaresynchronouslyexitedwhenCKEisregisteredHIGH(witharequiredNOPorDEScommand).CKEmustbemaintainedHIGHuntiltCKEhasbeensatisfied.Avalid,executablecommandmaybeappliedafterPOWER-DOWNEXITLATENCY,tXP,tXPDLLhavebeensatisfied.AsummaryofthePOWER-DOWNmodesislistedinTable66.

DLL State ACTIVE(anybankopen)

PRECHARGE(allbanksPRECHARGED)

table 66: pOwer-dOwN mOdeS

ON

ON

OFF

Relevant ParametersMR1[12]tXPtoanyothervalidCOMMANDtXPtoanyothervalidCOMMANDtXDLLtoCOMMANDSthatrequiretheDLL

tobelocked(READ,RDAP,ODTON).tXPtoanyothervalidCOMMAND.

SDRAM State“Don’tCare”

1

0

FAST

FAST

SLOW

POWER-DOWN exit



ST9D364M64SBG2



FiGure 88 - actiVe pOwer-dOwN eNtry aNd exit

CK

CK#

Command NOP NOP NOP NOP

Address

CKE

tCK tCH tCL

Enter power-downmode

Exit power-downmode

Don’t Care

ValidValid

Valid

tCPDED

Valid

t IS

t IH

t IH

t IS

T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4

NOP

tXP

tCKE (MIN)


tPD

FiGure 89 - precharGe pOwer-dOwN (FaSt-exit mOde) eNtry aNd exit

tCKEmin

tCKEmin

CK

CK#

PONPONPONPONdnammoC

CKE

tCK tCH tCL


Exit power-downmode

tPD

Valid

tCPDED

tIS

t IHt IS

T0 T1 T2 T3 T4 T5 Ta0 Ta1

NOP


tCKE (MIN)

tXP



ST9D364M64SBG2



FiGure 90 - precharGe pOwer-dOwN (SlOw-exit mOde) eNtry aNd exit

Notes: 1. Any valid command not requiring a locked DLL.2. Any valid command requiring a locked DLL.

CK

CK#

Command PON PON PON

CKE

tCK tCH tCL

Enter power-down mode

Exit power-down mode

tPD

Valid 2Valid 1PRE

tXPDLL

tCPDED

t IS

t IH t IS

T0 T1 T2 T3 T4 Ta Ta1 Tb

NOP

Don’t Care Indicates a Break in Time Scale

tXP

tCKE (MIN)

FiGure 91 - pOwer-dOwN eNtry aFter read Or read with autO precharGe (rdap)

T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9


Ta10 Ta11 Ta12

NOP

Valid

READ/RDAP NOP NOP NOP NOP NOP NOP NOP NOP NOP

CK

CK#

Command

DQ BL8

DQ BC4

DQS, DQS#

Address

CKE

tCPDEDtIS

tPD

Power-down orself refresh entry

Indicates a break inTime Scale

tRDPDEN

DIn + 3

DIn + 1

DIn + 2

DIn

RL = AL + CL

DI n + 3

DI n + 2

DI n + 1

DIn

DI n + 6

DI n + 7

DI n+ 5

DI n + 4



ST9D364M64SBG2



FiGure 92 - pOwer-dOwN eNtry aFter write

Notes: 1. CKE can go LOW 2tCK earlier if BC4MRS.

T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1 Tb2 Tb3 Tb4

NOPWRITE

Valid

NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP

CK

CK#

Command

DQ BL8

DQ BC4

DQS, DQS#

Address

CKE

tCPDED

Power-down orself refresh entry 1


tWRPDEN

DIn + 3

DIn + 1

DIn + 2

DIn

tPD


DI n + 3

DI n + 2

DI n + 1

DI n

DI n + 6

DI n + 7DI

n + 5DI

n + 4

t IS

WL = AL + CWL tWR

FiGure 93 - pOwer-dOwN eNtry aFter write with autO precharGe (wrap)

Notes: 1. tWR is programmed through MR0[11:9] and represents tWR (MIN)ns/ tCK rounded up to the next integer tCK.

2. CKE can go LOW 2tCK earlier if BC4MRS.

T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1


Tb2 Tb3 Tb4

NOPWRAP

Valid

NOP NOP NOP

CK

CK#

Command

DQ BL8

DQ BC4

DQS, DQS#

Address

A10

CKE

tPD

tWRAPDEN

Power-down orself refresh entry 2

Start internalprecharge

tCPDEDtIS


DI n + 3

DI n + 2

DI n + 1

DIn

DI n + 6

DI n + 7DI

n + 5DI

n + 4

DI n + 3

DI n + 2

DI n + 1

DI n

WR1WL = AL + CWL

NOP NOP NOP NOP NOP NOP NOP NOP



ST9D364M64SBG2



FiGure 94 - reFreSh tO pOwer-dOwN eNtry

Notes: 1. After CKE goes HIGH during tRFC, CKE must remain HIGH until tRFC is satisfied.

CK

CK#

Command REFRESH NOP NOP NOP NOP Valid

CKE

tCK tCH tCL

tCPDED

tREFPDEN

tIS

T0 T1 T2 T3 Ta0 Ta1 Ta2 Tb0

tXP (MIN)

tRFC (MIN)1

Don’t CareIndicates a Break In Time Scale

tCKE (MIN)

tPD

FiGure 95 - actiVate tO pOwer-dOwN eNtry

tCKE

CK

CK#

Command

Address

ACTIVE NOP NOP

CKE

tCK tCH tCL

Don’t Care

tCPDED

tACTPDEN

Valid

tIS

T0 T1 T2 T3 T4 T5 T6 T7

tPD



ST9D364M64SBG2



FiGure 96 - precharGe tO pOwer-dOwN eNtry

CK

CK#

Command

Address

CKE

tCK tCH tCL

Don’t Care

tCPDED

tPREPDEN

tIS

T0 T1 T2 T3 T4 T5 T6 T7

tPD

All/singlebank

PRE NOP NOP

FiGure 97 - mrS cOmmaNd tO pOwer-dOwN eNtry

CK

CK#

CKE

tCK tCH tCL tCPDED

Address

t IS

T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4

tPD


Valid

Command MRS NOPNOP NOP NOP NOP

tMRSPDEN



ST9D364M64SBG2



FiGure 98 - pOwer-dOwN exit tO reFreSh tO pOwer-dOwN eNtry

Notes: 1. tXP must be satisfied before issuing the command.2. tXPDLL must be satisfied (referenced to the registration of power-down exit) before the

next power-down can be entered.

CK

CK#

CKE

tCK tCH tCL



Exit power-downmode

tPD

tCPDED

tIS

t IHt IS

T0 T1 T2 T3 T4 Ta0 Ta1 Tb0


Command NOP NOP NOP NOPREFRESH NOPNOP

tXP1

tXPDLL2

RESET

TheRESETsignal(RESET\)isanasynchronoussignalthattriggersanytimeitdropsLOW.TherearenorestrictionsaboutwhenitcangoLOW.AfterRESET\isdrivenLOW,itmustremainLOWfor100ns.Duringthistime,theoutputsaredisabled,ODT(RTT)turnsoff(HIGH-Z)andtheDDR3SDRAMresetsitself.CKEshouldbebroughtLOWpriortoRESET\beingdrivenHIGH.AfterRESET\goesHIGH,theSDRAMmustbere-initializedasthoughanormalpowerupwereexecuted(seeFigure99).AllrefreshcountersontheSDRAMareRESETanddatastoredintheSDRAMisassumedunknownafterRESET\hasbeendrivenLOW.



ST9D364M64SBG2



FiGure 99 - reSet SeQueNce

CKE

RTT

BA[2:0]

All voltage supplies valid and stable

High-Z

DM

DQS High-Z

Address

A10

CK

CK#

tCL

Command NOP

T0 Ta0

Don’t Care

tCL

t IS

ODT

DQ High-Z

Tb0

tDLLK

MR1 with DLL ENABLE

MRS MRS

BA0 = H BA1 = L BA2 = L

BA0 = L BA1 = L BA2 = L

Code Code

Code Code

Valid

Valid

Valid

Valid

Normal operation

MR2 MR3

MRS MRS

BA0 = L BA1 = H BA2 = L

BA0 = H BA1 = H BA2 = L

Code Code

Code Code

Tc0 Td0

RESET#

Stable and valid clock

Valid Valid

DRAM ready for external commands

T1

tZQINIT

A10 = H

ZQCL

t IS

t IOZ

Valid

Valid

Valid

System RESET(warm boot)

ZQ CAL MR0 with DLL RESET

T=10ns (MIN)

T = 100ns (MIN)


T = 500µs (MIN) tXPR tMRD tMRD tMRD tMOD

T (MIN) = MAX (10ns, 5 tCK)

tCK



ST9D364M64SBG2



ON-die termiNatiON (Odt)

ODTisafeaturethatenablestheSDRAMtoenable/disableon-dieter-minationresistanceforeachDQ,DQSx,DQSx\,DQSx,DQSx\andDMxforthefourwordscontainedinLDI’sDDR3iMOD.

TheODTfeatureisdesignedtoimprovesignalintegrityofthememoryarray/sub-systembyallowingthememorycontrollertoindependentlyturnonorofftheDRAMSinternalterminationresistanceforanygroup-ingofDRAMdevices.TheODTfeatureisnotsupportedduringDLLdisablemode.AsimplefunctionalrepresentationoftheODTfeatureisshowninFigure100.TheswitchisenabledbytheinternalODTcontrollogic,whichusestheexternalODTballandothercontrolinformation.

FuNctiONal repreSeNtatiON OF Odt

ThevalueofRTT(ODTterminationvalue)isdeterminedbythesettingsofseveralmoderegisterbits(seeTable70).TheODTballisignoredwhileinSELFREFRESHmode(mustbeturnedoffpriortoSELFREFRESHentry)orifmoderegistersMR1andMR2areprogrammedtodisableODT.ODTiscomprisedofnominalODTanddynamicODTmodesandeitherofthesecanfunctioninsynchronousorasynchronousmodes(whentheDLLisoffduringPRECHARGEPOWER-DOWNorwhentheDLLissynchronizing).NominalODTisthebaseterminationandisusedinanyallowableODTstate.DynamicODTisappliedonlyduringWRITEsandprovidesOTFswitchingfromnoRTTorRTT_NOMtoRTT_WR.

Theactualeffectivetermination,RTT_EFFmaybedifferentfromtheRTTtargetedduetononlinearityofthetermination.ForRTT_EFFvaluesandcalculations,see“ODTCharacteristics”.

ODTVDDQ/2

RTT

SwitchDQ, DQS, DQS#,

To othercircuitrysuch asRCV, . . .

DM

FiGure 100 - ON-die termiNatiON NOmiNal Odt

ODT(NOM)isthebaseterminationresistanceforeachapplicableball,enabledordisabledviaMR1[9,6,2](seeFigure46),anditisturnedonoroffviatheODTball.

table 67: pOwer-dOwN mOdeS

MR1[9,6,2] ODT Pin SDRAM Termination State SDRAM State Notes

RTT_NOMdisabled,ODTOFF

RTT_NOMdisabled,ODTON

RTT_NOMenabled,ODTOFF

RTT_NOMenabled,ODTON

RTT_NOMreserved,ODTONorOFF

Anyvalid

AnyvalidexceptSELFREFRESH,READ

Anyvalid

AnyvalidexceptSELFREFRESH,READ

Illegal

1,2

1,3

1,2

1,3

000

000

000-101

000-101

110and111

0

1

0

1

X

3. ODTmustbedisabledduringREADs.TheRTT_NOMvalueisrestricted

duringWRITES.DynamicODTisapplicableifenabled.

NOTES:

1. AssumesdynamicODTisdisabled.

2. ODTisenabledandactiveduringmostWRITESforpropertermination,

butitisnotillegaltohaveitoffduringWRITES.



ST9D364M64SBG2



NominalODTresistanceRTT_NOMisdefinedbyMR1[9,6,2],asshowninFigure46.TheRTT_NOMterminationvalueappliestotheoutputpinspreviouslymentioned.DDR3SDRAMiMODssupportmultipleRTT_NOMvaluesbasedonRZQ/nwherencanbe2,4,6,8or12andRZQis240Ω±1%.RTT_NOMterminationisallowedanytimeaftertheSDRAMisinitialized,calibratedandnotperformingREADaccessesorwhenitisnotinSELFREFRESHmode.

WRITEaccessusesRTT_NOMiddynamicODT(RTT_WR)isdisabled.IfRTT_NOMisusedduringWRITEs,onlyRZQ/2,RZQ/4andRZQ/6areallowed(seeTable66).ODTtimingsaresummarizedinTable68,aswellas,listedinTable47.

table 68: Odt parameter

Symbol Description Begins at Defined to Units

ODTregisteredHIGH

ODTregisteredHIGH

ODTregisteredHIGH

ODTregisteredHIGH

ODTregisteredHIGHorWRITE

registrationwithODTHIGH

WRITEregistrationwithODTHIGH

CompletionofODTLon

CompletionofODTLoff

ODTLON

ODTLOFF

tAONPD

tAOFFPD

ODTH4

ODTH8

tAON

tAOF

ODTsynchronousturnondelay

ODTsynchronousturnoffdelay

ODTasynchronousondelay

ODTasynchronousondelay

ODTminimumHIGHtimeafterODTassertion

orWRITE(BC4)

ODTminimumHIGHtimeafterWRITE(BL8)

ODTturn-onrelativetoODTLoncompletion

ODTturn-offrelativetoODTLoffcompletion

RTT_ON±tAON

RTT_ON±tAOF

RTT_ON

RTT_OFF

ODTregisteredLOW

ODTregisteredLOW

RTT_ON

RTT_OFF

CWL+AL-2

CWL+AL-2

1-9

1-9

4tCK

6tCK

SeeTable47

0.5tCK±0.2tCK

tCK

tCK

ns

ns

tCK

tCK

ps

tCK

Definition for

All DDR3 bins

DYNAMIC ODT

Incertainapplications,tofurtherenhancesignalintegrityonthedatabus,itisdesirablethattheterminationstrength,bechangedwithoutissuinganMRScommand,essentiallychangingtheODTterminationresistanceon-the-fly.WithdynamicODT(RTT_WR)enabled,theSDRAMswitchesfromnominalODT(RTT_NOM)todynamicODTwhenbeginningaWRITEburstandsubsequentlyswitchesbacktonominalODTatthecompletionoftheWRITEburstsequence.ThisrequirementandthesupportingDYNAMICODTfeatureoftheDDR3SDRAMmakesitfeasibleandisdescribedinfurtherdetailbelow:

dyNamic Odt FuNctiONal deScriptiON:

ThedynamicODTmodeisenabledifeitherMR2[9]ormR2[10]issetto“1”.DynamicODTisnotsupportedduringDLLdisablemode,soRTT_WRmustbedisabled.ThedynamicODTfunctionisdescribed,asfollows:

•TwoRTTvaluesareavailable–RTT_NOMandRTT_WR:•ThevalueofRTT_NOMispreselectedviaMR1[9,6,2]•ThevalueforRTT_WRispreselectedviaMR2[10,9]

•DuringSDRAMoperationswithoutREADorWRITEcommands,theterminationiscontrolledasfollows:•TerminationON/OFFtimingiscontrolledviatheODTballandLATENCIESODTlonandODTLoff•NominalterminationstrengthRTT_NOMisused

•WhenaWRITEcommand(WR,WRAP,WRS4,WRS8,WRAPS4,WRAPS8)isregisteredandifdynamicODTisenabled,theODTtermi-nationiscontrolledasfollows:•AlatencyofODTLCNWaftertheWRITEcommand:terminationstrengthRTT_NOMswitchestoRTT_WR•ALatencyofODTLCWN8(forBL8,fixedorOTF)orODTLCWN4(forBC4,fixedorOTF)aftertheWRITEcommand:terminationstrengthRTT_WRswitchesbacktoRTT_NOM•ON/OFFterminationtimingiscontrolledviatheODTballanddeterminedbyODTLon,ODTLoff,ODTH4andODTH8.•DuringthetADCtransitionwindow,thevalueofRTTisundefined

ODTisconstrainedduringWRITEsandwhendynamicODTisenabled(seeTable69).

NOmiNal Odt



ST9D364M64SBG2



table 69: dyNamic Odt SpeciFic parameterS

Symbol Description Begins at Defined to

WRITEregistration

WRITEregistration

WRITEregistration

ODTLCNW

ODTLCNW

ODTLCWN4

ODTLCWN8tADC

ChangefromRTT_NOM to RTT_WR

ChangefromRTT_WRtoRTT_NOM(BC4)

ChangefromRTT_WRtoRTT_NOM(BL8)

RTTchangeskew

RTTswitchedfromRTT_NOM to RTT_WR

RTTswitchedfromRTT_WRtoRTT_NOM

RTTswitchedfromRTT_WRtoRTT_NOM

RTTtranscomplete

WL-2

4tCK+ODTLOFF

6tCK+ODTLOFF

0.5tCK±0.2tCK

tCK

tCK

tCK

tCK

Definition for

All DDR3 bins

table 70: mOde reGiSterS FOr rtt_NOm M9 M6 M2 RTT_NOM (RZQ) RTT_NOM(Ohms)

0

0

0

0

1

1

1

1

Off

RZQ/4

RZQ/2

RZQ/6

RZQ/12

RZQ/8

Reserved

Reserved

n/a

SELFREFRESH

SELFREFRESH,WRITE

n/a

n/a

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

Off

60

120

40

20

30

Reserved

Reserved

MR1(RTT_NOM)

table 71: mOde reGiSterS FOr rtt_wr M10 M2 RTT_NOM (RZQ) RTT_

0

0

1

1

n/a

n/a

n/a

n/a

RZQ/4

RZQ/2

Reserved

n/a

n/a

n/a

n/a

0

1

0

1

n/a

n/a

n/a

n/a

60

120

Reserved

n/a

n/a

n/a

n/a

MR1(RTT_NOM)

Dynamic ODT OFF: WRITE does not affect RTT_NOM

table 72: timiNG diaGramS FOr dyNamic Odt Figure Title

Figure101

Figure102

Figure103

Figure104

Figure105

DynamicODT:ODTassertedbeforeandaftertheWRITE,BC4

DynamicODT:WithoutWRITEcommand

DynamicODT:ODTpinassertedtogetherwithWRITEcommandfor6CKcycles,BL8

DynamicODT:ODTpinassertedwithWRITEcommandfor6CKcycles,BC4

DynamicODT:ODTpinassertedwithWRITEcommandfor4CKcycles,BC4



ST9D364M64SBG2



FiGure 101 - dyNamic Odt: Odt aSSerted beFOre aNd aFter the write, bc4

Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM and RTT_WR are enabled.2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example,

ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command).

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

ODTL on ODTLCWN4

ODTLCNW

WL

ODTL off

T10 T11 T12 T13 T14 T15 T17T16

CKCK#

Command

Address

RTT

ODT

DQ

DQS, DQS#

Valid

WRS4 PONPONPONPONPON NOP NOP


RTT_WRRTT_NOM RTT_NOM

DIn + 3

DIn + 2

DIn + 1

DIn

NOP NOP NOP NOP NOP NOP NOP NOPNOP NOP

ODTH4ODTH4

tAON (MIN) tADC (MIN) tADC (MIN) tAOF (MIN)

tAON (MAX) tADC (MAX) tADC (MAX) tAOF (MAX)

FiGure 102 - dyNamic Odt: withOut write cOmmaNd

Notes: 1. AL = 0, CWL = 5. RTT_NOM is enabled and R TT_WR is either enabled or disabled.2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example,

ODTH4 is satisfied. ODT registered LOW at T5 is also legal.

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

ODTL off

T10 T11

CKCK#

RTT


Command Vali d Vali d Vali d Vali d Vali d Vali d Vali d Vali d Vali d Vali d Vali d Vali d

Address

DQS, DQS#

DQ

ODTH4ODTL on

tAON (MAX)

tAON (MIN)

tAOF (MIN)

tAOF (MAX)

ODT

RTT_NOM



ST9D364M64SBG2



FiGure 103 - dyNamic Odt: Odt piN aSSerted tOGether with write cOmmaNd FOr 6 clOck cycleS, bl8

Notes: 1. Via MRS or OTF; AL = 0, CWL = 5. If RTT_NOM can be either enabled or disabled, ODT can be HIGH. RTT_WR is enabled.2. In this example, ODTH8 = 6 is satisfied exactly.

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

ODTLCWN8

ODTLON

ODTLCNW

WL

tAOF (MAX)

T10 T11

CK

CK#

Address

RTT

ODT

DQ

DQS, DQS#

DI b + 3

DI b + 2

DI b + 1

DI b

DI b + 7

DI b + 6

DI b + 5

DI b + 4

Valid


Command WRS8NOP NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP

RTT_WR

ODTH8 ODTLOFF

tADC (MAX)

tAON (MIN)

tAOF (MIN)

FiGure 104 - dyNamic Odt: Odt piN aSSerted with write cOmmaNd FOr 6 clOck cycleS, bc4

Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM and RTT_WR are enabled.2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example,

ODTH4 is satisfied. ODT registered LOW at T5 is also legal.

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

ODTL on

ODTLCNW

WL

T10 T11

CKCK#

ODTLCWN4

DQS, DQS#

Address Valid


ODTL off

Command WRS4NOP NOPNOP NOP NOP NOP NOP NOP

DQ DIn + 3

DIn + 2

DIn + 1

DIn

tADC (MIN) tAOF (MIN)

tAOF (MAX)tADC (MAX)

tADC (MAX)

tAON (MIN)

ODTH4

ODT

RTT RTT_WR RTT_NOM

NOP NOP NOP



ST9D364M64SBG2



FiGure 105 - dyNamic Odt: Odt piN aSSerted with write cOmmaNd FOr 4 clOck cycleS, bc4

Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM can be either enabled or disabled. If disabled, ODT can remain HIGH. RTT_WR is enabled.

2. In this example ODTH4 = 4 is satisfied exactly.

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

ODTL on

ODTLCNW

WL

T10 T11

CKCK#

ODTLCWN4

DQS, DQS#

Address Valid

RTT_WR

Command WRS4NOP NOPNOP NOP NOP NOP NOP NOP NOP


DQ DIn

DIn + 3

DIn + 2

DIn + 1

ODTH4

tADC (MAX)

tAON (MIN)

tAOF (MIN)

tAOF (MAX)

ODTL off

RTT RTT_WR

ODT

NOP NOP

SyNchrONOuS Odt mOde

SynchronousODTisselectedwhenevertheDLListurnedonandlockedwhileRTT_NOMorRTT_WRisenabled.BasedonthePOWER-DOWNdefinition,thesemodesare:

•AnybankACTIVEwithCKEHIGH•REFRESHmodewithCKEHIGH•DLEmodewithCKEHIGH•ACTIVEPOWER-DOWNmode(regardlessofMR0[12])•PRECHARGEPOWER-DOWNmodeifDLLisenabledduringPRECHARGEPOWER-DOWNbyMR0[12]

Odt lateNcy aNd pOSted Odt

InsynchronousODTmode,RTTturnsonODTLonclockcyclesafterODTissampledHIGHbyarisingclockedgeandturnsoffODTLoffclockcyclesafterODTisregisteredLOWbyarisingclockedge.Theactualon/offtimesvariesbytAON and tAOFaroundeachclockedge(seeTable73).TheODTLATENCYistiedtotheWRITELATENCY(WL)byODTLon=WL-2andODTLoff=WL-2.

SinceWRITELATENCYismadeupofCASWRITELATENCY(CWL)andADDITIVELATENCY(AL),theALvalueprogrammedintothemoderegisterMR1[4,3],alsoappliestotheODTsignal.TheSDRAM’sinter-nalODTsignalisdelayedanumberofclockcyclesdefinedbytheALrelativetotheexternalODTsignal.Thus,ODTLon=CWL+AL–2andODTLoff=CWL+AL–2.



ST9D364M64SBG2



SyNchrONOuS Odt timiNG parameterS

SynchronousODTmodeusesthefollowingtimingparameters:ODTLon,ODTLoff,ODTH4,ODTH8,tAON and tAOF(seeTable73andFigure106).TheminimumRTTturn-ontime(tAON[MIN])isthepointatwhichthedeviceleavesHIGH-AandODTresistancebeginstoturnon.MaximumRTTturn-ontime(tAON[MAX])isthepointatwhichODTresistanceisfullyon.BotharemeasuredrelativetoODTLon.TheminimumRTTturn-offtime(tAOF[min])isthepointatwhichthedevicestartstoturn-offODTresistance.MaximumRTTturn-offtime(tAOF[MAX])isthepointatwhichODThasreachedHIGH-Z.BotharemeasuredfromODTLoff.

WhenODTisasserted,itmustremainHIGHuntilODTH4issatisfied.IfaWRITEcommandisregisteredbytheSDRAMwithODTHIGH,thenODTmustremainHIGHuntilODTH4(BC4)orODTH8(BL8)aftertheWRITEcommand(seeFigure107).ODTH4andODTH8aremeasuredfromODTregisteredHIGHtoODTregisteredLOWorfromtheregistrationofaWRITEcommanduntilODTisregisteredLOW.

table 73: SyNchrONOuS Odt parameterS

Symbol Description Begins at Defined to Units

ODTregisteredHIGH

ODTregisteredHIGH

ODTregisteredHIGH,orWRITE

registrationwithODTHIGH

WRITEregistrationwithODTHIGH

CompletionofODTLon

CompletionofODTLoff

ODTLON

ODTLOFF

ODTH4

ODTH8

tAON

tAOF

ODTsynchronousTURN-ONdelay

ODTsynchronousTURN-OFFdelay

ODTMinimumHIGHtimeafterODT

assertionorWRITE(BC4)

ODTMinimumHIGHtimeafter

WRITE(BL8)

ODTTURN-ONrelativetoODTLon

completion

ODTTURN-OFFrelativetoODTLoff

completion

RTT_ON±tAON

RTT_OFF±tAOF

ODTregisteredLOW

ODTregisteredLOW

RTT_ON

RTT_OFF

CWL+AL-2

CWL+AL-2

4tcK

6tcK

SeeTable47

0.5tcK±0.2tcK

tCK

tCK

tCK

tCK

ps

tCK

Definition for

All DDR3 bins

FiGure 106 - SyNchrONOuS Odt

Notes: 1. AL = 3; CWL = 5; ODTL on = WL = 6.0; ODTL off = WL - 2 = 6. RTT_NOM is enabled.

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

CWL - 2AL = 3AL = 3

tAON (MAX) tAOF (MAX)

T10 T11 T12 T13 T14 T15

CKCK#

RTT

ODT


RTT_NOM

CKE

tAOF (MIN)

ODTL off = CWL + AL - 2

ODTL on = CWL + AL - 2

ODTH4 (MIN)

tAON (MIN)



ST9D364M64SBG2



FiGure 107 - SyNchrONOuS Odt (bc4)

Notes: 1. WL = 7. RTT_NOM is enabled. RTT_WR is disabled.2. ODT must be held HIGH for at least ODTH4 after assertion (T1).3. ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7).4. ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the WRITE

command with ODT HIGH to ODT registered LOW.5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must also be

satisfied from the registration of the WRITE command at T7.

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

tAOF (MAX)

tAOF (MIN)

tAON (MAX) tAOF (MAX)

T10 T11 T12 T13 T14 T15 T17T16

CKCK#

RTT

CKE

NOP WRS4NOP NOPNOP NOP NOP NOPCommand


tAON (MIN)

RTT_NOM

ODTLoff = WL - 2

ODTH4 (MIN)

ODTH4

ODTL off = WL - 2

ODTL on = WL - 2

tAON (MIN) tAON (MAX)

ODTH4

ODTL on = WL - 2

tAOF (MIN)

ODT

RTT_NOM

NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP

Odt OFF duriNG readS

AstheDDR3SDRAMcannotterminateanddriveatthesametime,RTTmustbedisabledatleastone-halfclockcyclebeforetheREADpreamblebydrivingtheODTballLOW.RTTmaynotbeenableduntiltheendofthepostambleasshowninFigure108.

FiGure 108 - Odt duriNG readS

Notes: 1. ODT must be disabled externally during READs by driving ODT LOW. For example, CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTL on = CWL + AL - 2 = 8; ODTL off = CWL + AL - 2 = 8. RTT_NOM is enabled. RTT_WR is a “Don’t Care.”

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T17T16

CKCK#

ValidAddress

DIb + 3

DIb + 2

DIb + 1

DIb

DIb + 7

DIb + 6

DIb + 5

DIb + 4

DQ

DQS, DQS#


Command NOP NOP NOP NOP NOP NOP NOPNOP NOP NOP NOP NOP NOP NOP NOP NOPNOPREAD

ODTL on = CWL + AL - 2

ODT

tAON (MAX)RL = AL + CL

ODTL off = CWL + AL - 2

tAOF (MIN)RTT RTT_NOMRTT_NOM

tAOF (MAX)



ST9D364M64SBG2



aSyNchrONOuS Odt mOde

AsynchronousODTmodeisavailablewhentheSDRAMrunsinDLLONmodeandwheneitherRTT_NOMorRTT_WRisenabled;however,theDLListemporarilyturnedoffinPRECHARGEDPOWER-DOWNstandbyviaMR0[12].Additionally,ODToperatesasynchronouslywhentheDLLissynchroniz-ingafterbeingRESET.See“POWER-DOWNMODE”fordefinitionandguidanceoverPOWER-DOWNdetails.

InasynchronousODTtimingmode,theinternalODTcommandisnotdelayedbyALrelativetotheexternalODTcommand.InasynchronousODTmode,ODTcontrolsRTTbyanalogtime.ThetimingparameterstAONPDandtAOFPD(seeTable74)replaceODTLon/tAONandODTLoff/tAOF respectively,whenODToperatesasynchronously(seeFigure109).

TheminimumRTTturn-ontime(tAONPD[MIN])isthepointatwhichthedeviceterminationcircuitleavesHIGH-ZandODTresistancebeginstoturn-on.MaximumRTTturn-ontime(tAONPD[MAX])isthepointatwhichODTresistanceisfullyon.tAONPD(MIN)andtAONPD(MAX)aremeasuredfromODTbeingsampledHIGH.

TheminimumRTTturn-offtime(tAOFPD[MIN])isthepointatwhichthedeviceterminationcircuitstartstoturnoffODTresistance.MaximumRTTturn-offtime(tAOFPD[MAX])isthepointatwhichODThasreachedHIGH-Z.tAOFPD(MIN)andtAOFPD(MAX)aremeasuredfromODTbeingsampledLOW.

table 74: aSyNchrONOuS Odt timiNG parameterS FOr all Speed biNS

Symbol Description MIN MAX Units

tAONPDtAOFPD

AsynchronousRTTTURN-ONdelay(POWER-DOWNwithDLLoff)

AsynchronousRTTTURN-OFFdelay(POWER-DOWNwithDLLoff)

2

2

8.5

8.5

ns

ns

FiGure 109 - aSyNchrONOuS Odt timiNG with FaSt Odt traNSitiON

Notes: 1. AL is ignored.

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

tAONPD (MAX) tAOFPD (MAX)

T10 T11 T12 T13 T14 T15 T17T16

CKCK#

RTT

ODT

RTT_NOM


CKEt IH t IS t IH t IS

tAOFPD (MIN)tAONPD (MIN)



ST9D364M64SBG2



table 75: Odt parameterS FOr pOwer-dOwN (dll OFF) eNtry aNd exit traNSitiON periOd

Description MIN MAX

POWER-DOWNentrytransitionperiod(POWER-DOWNentry)

POWER-DOWNentrytransition(POWER-DOWNexit)

ODT to RTTTURN-ONdelay(ODTLon=WL-2)

ODT to RTT TURN-OFFdelay(ODTLoff=WL-2)

tANPD

Greaterof:tANPD or tRFC-REFRESHtoCKELOW

tANPD+tXPDLL

WL-1(GreaterofODTLoff+1orODTLon+1)

Lesserof:tANPD(MIN)[1ns]or

ODLonxtCK+tAON(MIN)

Lesserof:tAOFPD(MIN)[1ns]or

ODLoffxtCK+tAOF(MIN)

Lesserof:tANPD(MIN)[1ns]or

ODLonxtCK+tAON(MIN)

Lesserof:tAOFPD(MIN)[1ns]or

ODLoffxtCK+tAOF(MIN)

SYNCHRONOUS TO ASYNCHRONOUS ODT MODE TRANSITION (POWER-DOWN ENTRY)

ThereisatransitionperiodaroundPOWER-DOWNENTRY(PDE)wheretheSDRAM’sODTmayexhibiteithersynchronousorasynchronousbehavior.ThistransitionperiodoccursiftheDLLisselectedtobeoffwheninPRECHARGEPOWER-DOWNmodebythesettingofMR0[12]=0.POWER-DOWNentrybeginstANPDpriortoCKEfirstbeingregisteredLOWanditendswhenCLEisfirstregisteredLOW.tANPDisequaltothegreaterofODTLoff+1tCKorODTLon+1tCK.IfaREFRESHcommandhasbeenissued,anditisinprogresswhenCKEgoesLOW,POWER-DOWNentrywillendtRFCaftertheREFRESHcommandratherthanwhenCKEisfirstregisteredLOW.POWER-DOWNENTRYwillthenbecomethegreateroftANPDandtRFC–REFRESHcommandtoCKEregisteredLOW.

ODTassertionduringPOWER-DOWNENTRYresultsinanRTTchangeasearlyasthelesseroftAONPD(MIN)andODTLonxtCK+tAON(MIN)oraslateasthegreateroftAONPD(MAX)andODTLonxtCK+tAON(MAX).ODTde-assertionduringPOWER-DOWNENTRYmayresultinanRTTchangeasearlyasthelesseroftAOFPD(MIN)andODTLoffxtCK+tAOF(MIN)oraslateasthegreateroftAOFPD(MAX)andODTLoffxtCK+tAOF(MAX).Table75summarizestheseparameters.

IftheALhasalargevalue,theuncertaintyofthestateofRTTbecomesquitelarge.ThisisbecauseODTLonandODTLoffarederivedfromtheWLandWLisequaltoCWL+AL.Figure110showsthreedifferentcases;

•ODT_A:SynchronousbehaviorbeforetANPD•ODT_B:ODTstatechangesduringthetransitionperiodwithtAONPD(MIN)lessthanODTLonxtCK+tAON(MIN)andtAONPD(MAX)greaterthanODTLonxtCK+tAON(MAX)•ODT_C:ODTstatechangesafterthetransitionperiodwithasynchronousbehavior



ST9D364M64SBG2



ASYNCHRONOUS TO SYNCHRONOUS ODT MODE TRANSITION (POWER-DOWN EXIT)

TheSDRAM’sODTmayexhibiteitherasynchronousorsynchronousbehaviorduringPOWER-DOWNEXIT(PDX).ThistransitionperiodoccursiftheDLLisselectedtobeoffwheninPRECHARGEPOWER-DOWNmodebysettingMR0[12]to“0”.POWER-DOWNexitbeginstANPDpriortoCKEfirstbeingregisteredHIGHanditendstXPDLLafterCKEisfirstregisteredHIGH.tANPDisequaltothegreaterofODTLoff+1tCKorODTLon+1tCK.ThetransitionperiodistANPDplustXPDLL.

ODTassertionduringPOWER-DOWNexitresultsinanRTTchangeasearlyasthelesseroftAONPD(MIN)andODTLonxtCK+tAON(MIN)oraslateasthegreateroftAONPD(MAX)andODTLonxtCK+tAON(MAX).ODTde-assertionduringPOWER-DOWNEXITmayresultinanRTTchangeasearlyasthelesseroftAOFPD(MIN)andOFTLoffxtCK+tAOF(MIN)oraslateasthegreateroftAOFPD(MAX)andODTLoffxtCK+tAOF(MAX).Table75summarizestheseparameters.

IftheALhasalargevalue,theuncertaintyoftheRTTstatebecomesquitelarge.ThisisbecauseODTLonandODTLoffarederivedfromtheWL,andtheWLisequaltoCWL+AL.Figure111showsthreedifferentcases.

•ODTC:AsynchronousbehaviorbeforetANPD•ODTB:ODTstatechangesduringthetransitionperiodwithtAOFPD(MIN)lessthanODTLoffxtCK+tAOF(MIN)andODTLoffxtCK+tAOF(MAX)greaterthantAOFPD(MAX)•ODTA:ODTstatechangesafterthetransitionperiodwithsynchronousresponse

FiGure 110 - SyNchrONOuS tO aSyNchrONOuS traNSitiON duriNG precharGe pOwer-dOwN (dll OFF) eNtry

Notes: 1. AL = 0; CWL = 5; ODTL off = WL - 2 = 3.

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

tAOFPD (MAX)

ODTL off

T10 T11 T12 T13 Ta0 Ta1 Ta3Ta2

CKCK#

DRAM RTT B asynchronous

or synchronousRTT_NOM

DRAM RTT Casynchronous

RTT_NOM


CKE

NOP NOP NOPNOP NOPCommand NOPREF NOP NOP NOP NOPNOP NOP NOP NOPNOP NOP NOP

PDE transition period

Indicates a Break In Time Scale

ODTL off + tAOFPD (MIN)

tAOFPD (MAX)

tAOFPD (MIN)

ODTL off + tAOFPD (MAX)

tAOFPD (MIN)

tANPD

tAOF (MIN)

tAOF (MAX)

DRAM RTT A synchronous RTT_NOM

ODT A synchronous

ODT C asynchronous

ODT B asynchronous

or synchronous

tRFC (MIN)



ST9D364M64SBG2



FiGure 111 - aSyNchrONOuS tO SyNchrONOuS traNSitiON duriNG precharGe pOwer-dOwN (dll OFF) exit

Not

es:

1.C

L =

6; A

L =

CL

- 1; C

WL

= 5;

OD

TL o

ff =

WL

- 2 =

8.

T0

T1

T2

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Tb0

Tb

1 Tb

2 Tc

0 Tc

1 Td

0 Td

1 Tc

2

CK

CK#

Don

’t Ca

re

Tran

sitio

ning

ODT

C

sync

hron

ous

PON

PON

NOP

COM

MAN

D NO

P NO

P NO

P NO

P

RTT B

as

ynch

rono

us

or s

ynch

rono

us

DRAM

RTT

A

asyn

chro

nous

DRAM

RTT

C

sync

hron

ous

RTT_

NOM

NOP

NOP

ODT

B

asyn

chro

nous

or

syn

chro

nous

CKE

t AO

F (M

IN)

R TT_

NOM

Indi

cate

s A

Bre

ak in

Ti

me

Sca

le

OD

TL o

ff +

t AO

F (M

IN)

t AO

FPD

(MA

X)

OD

TL o

ff +

t AO

F (M

AX

)

t XP

DLL

t AO

F (M

AX

) O

DTL

off

ODT

A

asyn

chro

nous

PD

X tr

ansi

tion

perio

d

t AO

FPD

(MIN

)

t AO

FPD

(MA

X) t A

NP

D

t AO

FPD

(MIN

)

RTT_

NOM

NOP

NOP

NOP

NOP

NOP



ST9D364M64SBG2



ASYNCHRONOUS TO SYNCHRONOUS ODT MODE TRANSITION (SHORT CKE PULSE)

IfthetimeinthePRECHARGEPOWERDOWNorIDLEstatesisveryshort(shortCKELOWpules),thePOWER-DOWNENTRYandPOWER-DOWNEXITtransitionperiodswilloverlap.Whenoverlapoccurs,theresponseoftheSDRAM’sRTTtoachangeintheODTstatemaybesynchronousorasynchro-nousfromthestartofthePOWER-DOWNENTRYtransitionperiodtotheendofthePOWER-DOWNEXITtransitionperiodeveniftheENTRYperiodendslaterthantheEXITperiod.(seeFigure112).

Ifthetimeintheidlestateisveryshort(shortCKEHIGHpulse),thePOWER-DOWNEXITandPOWER-DOWNENTRYtransitionperiodsoverlap.Whenthisoverlapoccurs,theresponseoftheSDRAM’sRTTtoachangeintheODTstatemaybesynchronousorasynchronousfromthestartofthePOWER-DOWNEXITtransitionperiodtotheendofthePOWER-DOWNENTRYtransitionperiod(seeFigure113).

FiGure 112 - traNSitiON periOd FOr ShOrt cke lOw cycleS with eNtry aNd exit periOd OVerlappiNG

Notes: 1. AL = 0, WL = 5, tANPD = 4.

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Ta0 Ta1 Ta2 Ta3 Ta4

CKCK#

CKE

Command

Don’t Care Transitioning

tXPDLL

tRFC (MIN)

NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP REF PON PONNOP NOP

PDE transition period

PDX transition period


tANPD

Short CKE LOW transition period (RTT change asynchronous or syn chronous)

tANPD

FiGure 113 - traNSitiON periOd FOr ShOrt cke hiGh cycleS with eNtry aNd exit periOd OVerlappiNG

Notes: 1. AL = 0, WL = 5, tANPD = 4.

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

CK CK#

Command

Don’t Care Transitioning

NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PON PON NOP NOP NOP

tANPD tXPDLL


Ta0 Ta1 Ta2 Ta3 Ta4

CKE

Short CKE HIGH transition period (RTT change asynchronous or synchonous)

tANPD

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ST9D364M64SBG2



reViSiON hiStOry

Revision By Issue Date Description Of Change

A 06.06.2015 INITIATEBV

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