stability 1 ti precision labs op amps

Stability – 1TI Precision Labs – Op Amps

Developed by Collin Wells, Art Kay, and Ian Williams

1

2

Op Amp Stability Issue

Vcc

Vcc

Vcc 5

+

-

+

U1 OPA333

CLoad 1u

R1

100k

R2

100k

VREF

T

Time (s)0.00 500.00u 1.00m

Volta

ge (V

)

0.00

2.50

5.00 T

Time (s)0.00 500.00u 1.00m

VREF

(V)

0.00

2.50

5.00Desired Measured

3

Simplified Cause of Op Amp Stability Issues

Issues happen because of too much delay from output to feedback!

Delay Delay

V-

V+

R4 499k R5 499k

C4

25p

+

Vin

Vfb

+

-

+U2 OPA333

R6 100

C3

47n

Vopa

T

Time (s)0 125u 250u

Vopa

-2.5

0.0

2.5

Vfb

-750m

0

750m

Vin

-10m

0

ab30

p

Delay Delay

V-

V+

R4 499k R5 499kC

4 25

p

+

Vin

Vfb

+

-

+U2 OPA333

R6 100

C3

47n

Vopa

4

Delay Happens in Many Circuits

V-

V+

R1 499k RF 499k

+

Vin

Vfb

VopaRo 100

C_Load 47n

Vout

Cst

ray

15p

Cin

15p

-

+

OPA333

30p

5

Circuits with Possible Stability IssuesOutput Capacitive Loads

Input Capacitance and Large Value Resistors

Transimpedance Amplifiers

Reference Buffers Cable/Shield Drive MOSFET Gate Drive

Large Value Resistors for Low-Power Circuits

-

+

IOP2

R3 499kR4 499k

+

VG2

Cin 25p Vout

-

+

OPA

Cin 1u

C1 1u

C2 1u

VIN 5Vin

Temp

GND

Vout

Trim

U1 REF5025

C3 10u

ADC_VREF

C4 100n

-

+

OPA

RL 250

Rf 20kRg 1k

+

Vin

-

+

OPA

C_Cable 10nVout

VREF 2.5

VREF

Shielded Cable

-

+

OPA

VRef 2.5

R1 20k

R2 20k

Vin 10

VRegQ1

RL 200

Transient SuppressionV+

-

+

OPA

Rf 49kRg 4.99M

Cd 200p Vout

+Vin

D1

D2TVS

Vo

Rf 1M

Rd 4.99G Cd 10p-

+

OPA

Id

Photodiode Model

Identify Stability Issues in the Lab

6

• Suggested Tools:– Oscilloscope– Signal Generator

• Other Useful Tools:– Gain / Phase Analyzer– Network / Spectrum Analyzer

• Oscilloscope – Time Domain Analysis: – Oscillations– Overshoot and Ringing– Unstable DC Voltages– High Distortion


7

Output Response to Square Wave Input

Output Response to Step Input

Sustained Output Oscillation with DC Input


8

• Gain / Phase Analyzer - Frequency Domain: - Peaking, Unexpected Gains, Rapid Phase Shifts

Simulated MeasuredT

Gai

n (d

B)

-60.00

-40.00

-20.00

0.00

20.00

Frequency (Hz)1k 10k 100k 1M 10M

Pha

se [d

eg]

-180.00

-90.00

0.00

T

Time (s)0.00 2.50m 5.00m

Out

put

2.49

2.50

2.51

Vin Vload Vopa

Solving Op Amp Stability Issues

9

T

Time (s)0.00 500.00u 1.00m

Vol

tage

(V)

1.81

2.34

2.88

Vcc

Vcc 5

+

-

+

U1 OPA333

CLoad 1u

VREF

+

Vin

Vcc

Vcc 5CLoad 1u

R3 499

R4 49k

C1 22n

Vopa

+

Vin

Vload

R1

100k+

-

+U1 OPA333

Vcc

Vcc 5CLoad 1u

R3 499

Vopa

+

Vin

R1

100k

+

-

+U1 OPA333 Vload

T

Time (s)0.00 2.50m 5.00m

Out

put

2.50

2.51

2.53

Vin Vload Vopa

Riso 499

Riso 499

10

Bode Plots – Pole

+90

-90

+45

-45

10 100 1k 10k 100k 1M 10M0

(d

egre

es)

-45o@fP

-45o/Decade

-90o

0o

0

20

40

60

80

100

10M1M100k10k1k100101Frequency (Hz)

G (d

B)

-20 dB/Decade

fP

0.707*GV/V = -3dB

Actual Function

Straight-Line Approximation

[email protected] P

[email protected] P

Pole Location = fP (Cutoff Freq)

Magnitude (f < fP) = Gdc (e.g. 100dB) Magnitude (f = fP) = -3dB Magnitude (f > fP) = -20dB/Decade

Phase (f = fP) = -45° Phase (0.1fP < f < 10fP) = -45°/Decade Phase (f > 10fP) = -90° Phase (f < 0.1fP) = 0°

Gv/v = VoutVin = Gdc𝑖ቀffPቁ+ 1 As a complex number

Gv/v = VoutVin = GdcඨቀffPቁ2 + 1

Magnitude

Θ= − tan−1൬ffP൰ Phase

GdB = 20Log൫Gv vΤ ൯ Magnitude in dB

11

Bode Plots – Zero

+90

-90

+45

-4510 100 1k 10k 100k 1M 10M

0

(d

egre

es)

+45o @ fz

+45o/Decade

+90o

0o

0

20

40

60

80

10M1M100k10k1k100101

Frequency (Hz)

G (d

B)

+20 dB/Decade

+3dB

Actual Function

Straight-Line Approximation

10f

@7.5 Z

[email protected] Z

Zero Location = fZ

Magnitude (f < fZ) = 0dB Magnitude (f = fZ) = +3dB Magnitude (f > fZ) = +20dB/Decade

Phase (f = fZ) = +45° Phase (0.1fZ < f < 10fZ) = +45°/Decade Phase (f > 10fZ) = +90° Phase (f < 0.1fZ) = 0°

Gv/v = VoutVin = Gdc 𝑖൬ffZ൰+ 1൨ As a complex number

Gv/v = VoutVin = Gdcඨ൬ffZ൰2 + 1 Magnitude

Θ= tan−1൬ffZ൰ Phase

GdB = 20Log൫Gv vΤ ൯ Magnitude in dB

Op Amp Open Loop Model

12

AolZo

Rin

Vo

Vout

Vdiff+

-

IN+

IN-

x1

13

Op Amp Closed Loop ModelAol = Open loop Gain

β = Feedback Factor = VfbVout = R1R1 + Rf Acl = Closed Loop Gain = Aol1+ Aolβ Aolβ = Loop Gain

Acl = limAol β→∞ ൬Aol1+ Aolβ൰= 1β = 1+ RfR1

14

When is an Amplifier Unstable?

AOLβ = -1 when the phase at VFB has shifted 180 ⁰relative to Vin

• A circuit is unstable when AOLβ = -1• AOLβ = -1 sets the denominator of ACL = 0• AOLβ = -1 when AOLβ(dB) = 0dB and

phase shift(AOLβ) = 180°• Phase shift is relative to the DC phase

Phase Margin (PM)How close the system is to a 180° phase shift in AOLβ• PM = Phase(AOLβ) when Gain(AOLβ) = 0dB• Ex: 10° phase margin = 170° phase shift in AOLβ

𝐀𝐂𝐋=𝐀𝐎𝐋

𝟏+𝐀𝐎𝐋𝛃

15

Loop Gain Magnitude – AOLβ1β=V OUT

V FB=RF

R1+1=10V /V

1β

(dB )=20 log (10 )=20 dB

AOL

1/β

AOLβLoop gain in dB:20 log ( AOL β )=20 log ( AOL )−20 log ( 1β )AOL β (dB )=AOL(dB)− 1β (dB)

Note:

fC

16

Loop Gain Phase – Phase(AOLβ)

1β=𝑍 𝑓

𝑍1+1

C1 introduces a zero in 1β

At DC the capacitor is open, so gain = 10V/V. At high frequency the capacitor causes Z1 to decrease, so gain increases by +20dB/decade

17

Phase Margin

Rule of thumb:Phase margin > 45° is required for optimal stability!Phase margin < 45° is considered “marginally stable.”This does not ensure a robust design over process variation.

18

Rate of Closure – Unstable Example

Rate of Closure=|Slope ( AOL)−Slope( 1β )|Rate of Closure=|−20dB−(+20 dB)|=40dB

Unstable because rate of closure > 20dB!

1β=V OUT

V FB=10( ff C +1)

1/β(dB) = 20dB at DC, then increases by +20dB/decade afterthe zero frequency

Rule of thumb:Rate of closure = 20dB is required for optimal stability!

19

Rate of Closure – Stable Example

Rate of Closure=|Slope ( AOL)−Slope( 1β )|Rate of Closure=|−20dB−0dB|=20dB

Stable because rate of closure = 20dB!

1β=V OUT

V FB=RF

R1+1=10V /V

1β

(dB )=20 log (10 )=20 dB

Rule of thumb:Rate of closure = 20dB is required for optimal stability!

20

Rate of Closure (ROC) and Phase Margin

ROC(dB/decade)

Phase Margin

(°)20 45 < PM < 90

20 < ROC < 40 45

40 0 < PM < 45

T

Frequency (Hz)1 10 100 1k 10k 100k 1M 10M

Gai

n (d

B)

0

20

40

60

80

100

120

1/β

AOL

T


Gai

n (d

B)

0

20

40

60

80

100

120

1/β

AOL

T


Gai

n (d

B)

0

20

40

60

80

100

120

1/β

AOL

21

Indirect Phase Margin Measurements

Time Domain Percent Overshoot AC Gain/Phase AC Peaking

Phase Margin can be measured indirectly on closed-loop circuits!

T

Gai

n (d

B)

-30.00

-20.00

-10.00

0.00

10.00

Frequency (Hz)100.00k 1.00M 10.00M

Pha

se [d

eg]

-270.00

-180.00

-90.00

0.00

PM = 60°PM = 30°T

Time (s)2.00u 3.50u 5.00u

Vol

tage

(V)

0.00

3.75m

7.50m

11.25m

15.00m

PM = 60°PM = 30°

22

Indirect Phase Margin MeasurementsT

Time (s)2.00u 3.50u 5.00u

Vol

tage

(V)

0.00

2.50m

5.00m

7.50m

10.00m

12.50m

15.00m

14.3mV

%Overshoot=( 14.3mV −10mV10mV )∗100%=𝟒𝟑%

43% overshoot 29° phase margin

23

Indirect Phase Margin Measurements

T

Frequency (Hz)100.00k 1.00M 10.00M

Gai

n (d

B)

-30.00

-20.00

-10.00

0.00

10.00

6dB

6dB AC peaking 29° phase margin

24

Multiple-Choice Quiz• What are some possible signs of an unstable op amp circuit?

a) oscillationsb) large overshoot and ringingc) unpredictable or unexpected responsed) all of the above

• Many common circuits inadvertently cause delay in the feedback network, resulting in stability issues.

a) trueb) false

25

Multiple-Choice Quiz• Which of these is not a cause of amplifier instability?

a) capacitance on the amplifier’s output to GNDb) capacitance on the amplifier’s inverting inputc) large value feedback resistorsd) low valued resistors on the amplifier’s output to GND

• Which common application is most likely to have a stability issue?a) photodiode transimpedance amplifierb) low-noise gain stagec) summing amplifierd) integrator

26

Multiple-Choice Quiz• Amplifiers with stability problems are __________________?

a) only sensitive to transients on the inputb) sensitive to transients on the input, output, and power supplies

• Amplifiers with DC inputs (eg. reference buffer) will not have stability issues.

a) trueb) false

27

Multiple-Choice Quiz• Which of the following is a common method for stability testing?

a) apply a sinusoidal input signal, monitor the amplifier output with an oscilloscope

b) apply a square wave input signal, monitor the amplifier output with an oscilloscope

c) apply a triangle wave input signal, monitor the amplifier output with an oscilloscope

• Which of these is not a sign of stability issues in closed loop gain/phase analyzer measurements?

a) steep magnitude roll-offsb) rapid phase shiftsc) unexpected gainsd) AC gain peaking

Quiz• Which one of these AOL and 1/β curves is unstable?

Quiz• Find the phase margin of each system according to the % overshoot.

0102030405060708090

0 20 40 60 80 100

Phas

e M

argi

n (d

eg)

Percentage Overshoot (%)

Phase margin vs Percentage Overshoot

0102030405060708090

0 20 40 60 80 100

Phas

e M

argi

n (d

eg)

Percentage Overshoot (%)

Phase margin vs Percentage Overshoot

%Overshoot=( 16.4mV −10mV20mV )∗100%=𝟑𝟐% %Overshoot=( 19.6mV −10mV

20mV )∗100%=𝟒𝟖%

38° phase margin 25° phase margin

31

0

10

20

30

40

50

60

70

0 5 10 15 20

Phas

e M

argi

n (d

eg)

ac Peaking (dB)

Phase Margin vs ac Peaking

0

10

20

30

40

50

60

70

0 5 10 15 20

Phas

e M

argi

n (d

eg)

ac Peaking (dB)

Phase Margin vs ac Peaking

Quiz• Find the phase margin of each system according to the AC peaking.

35° phase margin

4.4dB peaking

12° phase margin

~14dB peaking

32

Quiz• Find the phase margin of each system according to the Bode plot.

45° phase margin ~15° phase margin

Stability – 2TI Precision Labs – Op Amps

Developed by Collin Wells, Art Kay, and Ian Williams

33

34

Simulating Open-Loop CircuitsNo DC biasing produces erroneous results!

Wrong open loop response

Output saturated

V-

V+

V- V+

Vo

R2 1kR1 1k

Vfb

V1 -15 V2 15

-

+ +3

2

6

74

OP AMP

+

Vin

R3

10k

24.99nV

14.44V

35

Simulating Open-Loop CircuitsDC: closed loop needed for SPICE operationAC: open loop needed for stability analysisDC

AC

DC+ACV-

V+

Vo

R2 1kR1 1k

+

Vin

Vfb

C1

L1

-

+ +3

2

6

74

OP AMP

R6

10k

100uV

200uV

V-

V+

Vo

R2 1kR1 1k

+

Vin

Vfb

C1

L1

-

+ +3

2

6

74

OP AMP

R7

10k

V-

V+

Vo

R2 1kR1 1k

+

VG1

Vfb

-

+ +3

2

6

74

OP AMP

L1 1T

C1 1T

R5

10k

RL

RL

RL

36

Standard Open-Loop SPICE ConfigurationWe need an open-loop circuit (no feedback) to generate open-loop gain (AOL), 1/β, and loop gain (AOLβ) curves

AOL_LOADED = Vo / Vfb1/β = 1 / Vfb

AOLβ = Vo

V-

V+

Vo

R2 1kR1 1k

+

VG1

Vfb

-

+ +3

2

6

74

OP AMP

L1 1T

C1 1T

R5

10k

AOL

AOLβ

1/β

37

Check DC Operating Point

V-

V+

Vo

R2 1kR1 1k

+

VG1

Vfb

-

+ +3

2

67

4

OP AMP

L1 1T

C1 1T

R5

10k

C3 1n

100uV

200uV

Click Analysis DC Analysis Calculate Nodal Voltages

38

Generating Open-Loop CurvesRun an AC transfer characteristic analysis over the appropriate frequency range:

Click Analysis AC Analysis AC Transfer Characteristic

39

Generating Open-Loop CurvesClick the “Post-Processor” button to add the desired curves

40

Generating Open-Loop CurvesPerform math on the existing curves to create the new curves:

AOL = Vo / Vfb1/β = 1/VfbAOLβ = Vo

41

Generating Open-Loop CurvesUnformatted results with all curves:

42

Generating Open-Loop CurvesRemove undesired curves and format axis for easier viewing:

43

Generating Open-Loop CurvesUse a cursor to determine the frequency where Aolβ = 0dB, fC, and place legend to show corresponding magnitudes and phases

Phase Margin = Aol*β Phase @ fC

fC

44

Why Do Capacitive Loads Cause Instability?

45

Simulate the Effects of Output CapacitanceRun open-loop analysis on buffer circuit with capacitive load

V-

V+

V- V++

Vin

-

+ +3

2

6

74

OP AMP

L1 1T

C1 1T

V1 -15 V2 15

CLoad 10n

Vfb

Vo

1/β

AOL_LOADED

AOLβ

ROC = 40dB/dec

Phase Margin = 4°

fC

Pole

Capacitive Loads – Stability Theory

+

−V-

V+

Vo

+

Vin

CLoad 10n

Vfb

-

+

-

+

Aol 1M

Ro 100

V-

V+

Vo+

Vin

-

+ +3

2

6

74

OP AMP

L1 1T

C1 1T

CLoad 10n

Vfb

+

Aol

Ro 100

Vo

CLoad 10n

46

(AOL_LOADED)

(AOL_LOADED)


Gai

n (d

B)

-40

-20

0


Pha

se [d

eg]

-90

-45

0

Aol Pole

+

Vin

Ro 100

Vo

CLoad 10n

47

V o

V ¿(s)= 1

1+s∗Ro∗CLOADTransfer Function:

f POLE=1

2∗π∗Ro∗CLOADPole Equation:


X

AOL (from data sheet) AOL Load

Loaded AOL =

Gai

n (d

B)

020406080

100120


Pha

se [d

eg]

0

45

90

135

180

-20-40

48

Compensation Method 1: RISO

V+

V-

VLoad

+

Vin

-

+ +3

2

67

4

OP AMPCLoad 10n

Riso 108

49

Vo

Method 1: RISO – ResultsTheory: Adds a zero to cancel the pole in loaded AOL

V-

V+

+

Vin

-

+ +3

2

6

74

OP AMP

L1 1T

C1 1T

CLoad 10n

Vfb

Riso 108

Vo

50

1/β

AOL_LOADED

AOLβ

ROC = 20dB/dec

Phase Margin = 64°

PoleZero

fC

Method 1: RISO – Theory

V-

V+

Vo+

Vin

-

+ +3

2

6

74

OP AMP

L1 1T

C1 1T

CLoad 10n

Vfb

Riso 108

V-

V+

Vo

+

Vin

CLoad 10n

Vfb

-

+

-

+

Aol 1M

Ro 100

Riso 108

+

Aol

Ro 100

Vo

CLoad 10n

Riso 108

51

(AOL_LOADED)

(AOL_LOADED)

52

Resistor Divider Analogy

+

Vin

R1 100

R2 100

Vo +

Aol

Ro 100

Vo

CLoad 10n

Riso 108

Zero: RISO & CLOAD Pole: RO, RISO, and CLOAD

Z1

Z2Vin

V O

V ¿=

R2R2+R1

V O

V ¿=

Z2Z2+Z1

V O

V ¿=

R ISO+1

s∗CLOAD

(R ISO+1

s∗CLOAD )+RO

V O

V ¿=

1+s∗R ISO∗CLOAD

1+s∗ (R ISO+RO )∗CLOAD


+

Vin

Ro 100

Vo

CLoad 10n

Riso 108

Gai

n (d

B)

-10

-5

0


Pha

se [d

eg]

-11.3

0

Aol Pole

-22.5

Aol Zero

53

V o

V ¿

(s )=1+s∗R ISO∗CLOAD

1+s∗ (RO+R ISO )∗CLOAD

f ZERO=1

2∗π∗R ISO∗C LOAD

f POLE=1

2∗π∗(RO+R ISO)∗CLOAD

Transfer Function:

Zero Equation:

Pole Equation:


X

AOL (from data sheet) AOL Load

Loaded AOL =G

ain

(dB

)

-10

-5

0


Pha

se [d

eg]

-11.3

0

Aol Pole

-22.5

Aol Zero

Gai

n (d

B)

020406080

100120


Pha

se [d

eg]

0

4590

135

180

-20-40

Aol Pole

Aol Zero

54

Method 1: RISO – DesignDesign Steps:1.) Find the zero frequency, fZERO, where AOL_Loaded = 20 dB2.) Calculate Riso to set the zero at fZERO

This will yield between 60° and 90° degrees of phase margin

55

Riso=1

2∗π∗ f ZERO∗C LOAD

Riso=1

2∗π∗146.5 kHz∗10 nF

Riso=𝟏𝟎𝟖𝛀

RISO Equation: AOL_LOADED

1/β

fC

fZERO = 146.5kHz

20dB

1/β

AOL_LOADED

AOLβ

ROC = 20dB/dec

PoleZero

fC

Method 1: RISO – Design Summary

56

V-

V+

-

+ +3

2

6

74

OP AMP

+

Vin

Riso 108

Cload 10n

Vload

Vo

Phase Margin= 64°

57

Unstable vs. Stable Transient Results

No compensation - Unstable

Riso compensation - Stable

T

Time (s)0.00 10.00u 20.00u 30.00u

Vol

tage

(V)

0.00

5.00m

10.00m

15.00m

20.00m

Vin Vo

T

Time (s)0.00 10.00u 20.00u 30.00u

Vol

tage

(V)

0.00

5.00m

10.00m

15.00m

20.00m

Vin Vo

V-

V+

Vo

-

+ +3

2

6

74

OP AMP

+

Vin C1

10n

Riso 108

SW_Riso

Method 1: RISO – DisadvantageDisadvantage:Voltage drop across RISO may not be acceptable for certain applications!

V+

V-

Vload

+

Vin

-

+ +3

2

6

74

OP AMPCLoad 10n

Riso 108

Vo

RLoad 250

Time (s)0.0 μ 5.0 μ 10.0 μ

12.5m

0.00

VLoad

VoVin10.0m

7.5m

5.0m

2.5m

RISO Voltage Drop

58

Method 2: RISO + Dual Feedback

59

V-

V+

-

+ +3

2

6

74

OP AMP

+

Vin

Riso 108

Cload 10n

Vload

Vo

C1 470p

R1 15k

Rload 250

Cf

Rf

Method 2: RISO + Dual Feedback – TheoryDC Circuit AC Circuit

V+

V-

+

Vin

-

+ +3

2

6

74

OP AMPCLoad 10n

Riso 108

Vo

RF 15k

R2

250

VLoad

CF

Vin 1V

1V

1.43V

CF: OpenRF: Closes the feedback around RISO VLOAD = VIN

CF: ShortRF >> ZCF, therefore RF is effectively openBehaves like RISO circuit

60

V-

V+

-

+ +3

2

6

74

OP AMP

+

Vin

Riso 108

Cload 10n

Vload

Vo

Rload 250

RF

CF 470p

Method 2: RISO + Dual Feedback - DesignDesign Steps:1) Set RISO using Method 1: RISO techniques2) Set RF: RF ≥ (RISO * 100) 3) Set CF: lower values of CF = faster settling, higher overshootRule 3 ensures that the two feedback paths will never create a resonance that would cause instability

61

6∗R ISO∗CLOAD

CF≤C F≤

10∗ R ISO∗CLOAD

CF

R ISO=108Ω

RF≥ R ISO∗100

RF≥10.8kΩ

36

1/β

AOL_LOADED

AOLβ

ROC = 20dB/dec

PoleZero

fC

Phase Margin = 66°

5× 𝑅𝑖𝑠𝑜 × 𝐶𝐿𝑅𝐹 ≤ 𝐶𝐹 ≤ 10× 𝑅𝑖𝑠𝑜 × 𝐶𝐿𝑅𝐹 Find the range of CF

5× 𝑅𝑖𝑠𝑜 × 𝐶𝐿𝑅𝐹 ≤ 𝐶𝐹 ≤ 10× 𝑅𝑖𝑠𝑜 × 𝐶𝐿𝑅𝐹 Find the range of CF

Method 2: RISO + Dual Feedback - Results

Time (s)0.0 μ 25.0 μ 50.0 μ

12.5m

0.00

VLoad

Vo

Vin10.0m

7.5m

5.0m

2.5m

RISO Voltage Drop

VLOAD = VIN

62

V+

V-

+

Vin

-

+ +3

2

6

74

OP AMPCLoad 10n

Riso 108

Vo

R1 15k

R2

250

C1 470p

VLoad

• VLOAD matches VIN – No voltage divider error!• This topology has some limitations on settling time and capacitive load range

T

Time (s)0.00 2.50m 5.00m

Out

put

2.49

2.50

2.51

Vin Vload Vopa

Summary – Solving Op Amp Stability

63

T

Time (s)0.00 500.00u 1.00m

Vol

tage

(V)

1.81

2.34

2.88

Vcc

Vcc 5

+

-

+

U1 OPA333

CLoad 1u

VREF

+

Vin

Vcc

Vcc 5CLoad 1u

R3 499

R4 49k

C1 22n

Vopa

+

Vin

Vload

R1

100k+

-

+U1 OPA333

Vcc

Vcc 5CLoad 1u

R3 499

Vopa

+

Vin

R1

100k

+

-

+U1 OPA333 Vload

T

Time (s)0.00 2.50m 5.00m

Out

put

2.50

2.51

2.53

Vin Vload Vopa

Riso 499

Riso 499

Thanks for your time!

64

stability 1 ti precision labs op amps

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