state diagram proposal · state diagram proposal pete mclean maxtor corporation 2190 miller drive...

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State diagram proposal

Pete McLeanMaxtor Corporation2190 Miller Drive

Longmont, CO 80501303 678-2149

[email protected]

After all of the time and effort we have put into the flow charts for the protocols in ATA-3 andATA/ATAPI-4, I still don’t believe that they adequately describe the protocols. If we do an ATA-5standard, I propose that we replace the flow charts in clause 9 as shown below. While thematerial in this draft of this proposal may not be complete and may have errors, I believe itaffords us the opportunity to clearly define the protocols.

9 Protocol

Commands are grouped into different classes according to the protocol followed for commandexeution. The command classes with their associated protocol are defined in this clause. Statemachines defining these protocols are not normative descriptions of implementations, they arenormative descriptions of externally apparent device or host behavior. Different implementationsare possible.

9.2 Power on and hardware reset protocol

This clause describes the protocol for processing of power on and hardware resets.

If the host asserts RESET- while a device is in or going to a power management mode, then thedevice shall execute its hardware reset protocol. If the host reasserts RESET- before a devicehas completed its power on or hardware reset protocol, then the device shall restart its protocolfrom the begining.

The host should not set the SRST bit to one in the Device Control register or issue a DEVICERESET command while the BSY bit is set to one in either device Status register as a result ofexecuting the power on or hardware reset protocol. If the host sets the SRST bit in the DeviceControl register to one or issues a DEVICE RESET command before devices have completedexecution of the power on or hardware reset protocol, then the devices shall ignore the softwarereset or DEVICE RESET command.

A host should issue an IDENTIFY DEVICE and/or IDENTIFY PACKET DEVICE command afterthe power on or hardware reset protocol has completed to determine the current status offeatures implemented by the device(s).

Figure 1 and the text that follows decribes the power on or hardware reset protocol for the host.Figure 2 and the text that follows decribes the power on or hardware reset protocol for thedevices.

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HHR1: Negate wait HHR2: Check statusHHR0: Assert RESET

xx:HHR0

RESET assertedHHR0:HHR1

Timeout completeHHR1:HHR2

BSY = 1HHR1:HHR1

Power on orhardware resetrequired

BSY = 0HHR2:HI0

Hostidle

Figure 1 −− Host power on or hardware reset protocol

State HHR0 Assert RESET: This state is entered at power on or when the host recognizes that ahardware reset is required.

When in this state, the host asserts RESET-. The host shall remain in this state with RESET-asserted for at least 25 µs.

Transition HHR0:HHR1: When the host has had RESET- asserted for at least 25 µs, the hostshall transition to the Negate wait state.

State HHR1 Negate wait: This state is entered when RESET- has been asserted for at least 25µs.

When in this state, the host shall negate RESET-. The host shall remain in this state for at least2 ms after negating RESET-.

Transition HHR1:HHR2: When RESET- has been negated for at least 2 ms, the host shalltransition to the Check status state.

State HHR2 Check status: This state is entered when RESET- has been negated for at least 2ms.

When in this state the host shall read the Status register.

Transition HHR2:HHR2: When BSY is set to one, the host shall transition to the Check statusstate.

Transition HHR2:HI0: When BSY is cleared to zero, the host shall transition to the Host idlestate (see figure 6).

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RESET asserted

DHR0: RESET

xx:DHR0

RESET negatedDHR0:DHR1

DASP asserted

D0HR2:D0HR3

D0HR1: Sample DASPPDIAG- =R, DASP- =R, BSY=1

Resample DASPD0HR1:D0HR1

D0HR0: DASP waitPDIAG- =R, DASP- =R, BSY=1

Wait completeD0HR0:D0HR1

D0HR2: Sample PDIAGPDIAG- =R, DASP- =R, BSY=1

Resample PDIAG

D0HR2:D0HR2

D0HR1:D0HR2 Sample timeout

Sample timeout

D0HR4: Set bit 7PDIAG- =R, DASP- =R, BSY=1

PDIAG asserted

D0HR2:D0HR4

Bit 7 set

D0HR1:D0HR3

D0HR3: Clear bit 7PDIAG- =R, DASP- =R, BSY=1

Bit 7 cleared

D0HR3:D0HR5

D0HR4:D0HR5

D0HR5: Set statusPDIAG- =R, DASP- =R, BSY=1

D0HR5:DI1

Status set

Device idle S

D1HR0: Set DASPPDIAG- =R, DASP- =A, BSY=1

DASP assertedD1HR0:D1HR1

D1HR1: Set statusPDIAG- =A, DASP- =A, BSY=1

Status setD1HR1:DI2 Device idle NS

DHR1: Release busPDIAG- =R, BSY=1

Bus released, Device 1

Bus released, Device 0DHR1:D0HR0

DHR1:D1HR0

Figure 2 −− Device power on or hardware reset protocol

State DHR0 RESET: This state is entered when a valid assertion of the RESET signal isrecognized. The device shall not recognize a RESET assertion shorter than 20 ns as valid.Devices may recognize a RESET assertion greater that 20 ns as valid and shall recognize aRESET assertion equal to or greater than 25 µs as valid.

Transition DHR0:DHR1: When a valid RESET signal is negated, the device shall transition tothe Release Bus state.

State DHR1 Release bus: This state is entered when a valid RESET signal is negated.

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When in this state, the device shall release PDIAG-, INTRQ, IORDY, DMARQ, and DD(15:0)within 400 ns after entering this state. The device shall set BSY to one within 400 ns afterentering this state. The device shall determine if the device is Device 0 or Device 1.

Transition DHR1:D0HR0: When the device has determined that it is Device 0, has released thebus, and has set BSY to one, then the device shall transition to the DASP- wait state.

Transition DHR1:D1HR0: When the device has determined that it is Device 1, has released thebus, and has set BSY to one, then the device shall transition to the Set DASP- state.

State D0HR0 DASP- wait: This state is entered when the device has released the bus, set BSYto one, and determined that the device is Device 0.

When in this state, the device shall release DASP- within 1 ms of the negation of RESET.

Transition D0HR0:D0HR1: When at least 1 ms has elapsed since the negation of RESET andDASP- has been released, the device shall transition to the Sample DASP state.

State D0HR1 Sample DASP: This state is entered when at least 1 ms has elapsed since thenegation of RESET.

When in this state, the device should begin performing its hardware initialization and self-diagnostic testing. This may revert the device to its default condition (the device’s settings maynow be different than they were before the host asserted RESET). All Ultra DMA modes shall bedisabled.

When in this state, the device shall sample the DASP- signal.

Transition D0HR1:D0HR2: When the sample indicates that DASP- is asserted, the device shalltransition to the Sample PDIAG state.

Transition D0HR1:D0HR1: When the sample indicates that DASP- is negated and less than 450ms have elapsed since the negation of RESET, then the device shall transition to the SampleDASP state. When the sample indicates that DASP- is negated and greater than 450 ms but lessthan 5 s have elapsed since the negation of RESET, then the device may transition to theSample DASP state.

Transition D0HR1:D0HR3: When the sample indicates that DASP- is negated and 5 s haveelapsed since the negation of RESET, then the device shall transition to the Clear bit 7 state.When the sample indicates that DASP- is negated and greater than 450 ms but less than 5 shave elapsed since the negation of RESET, then the device may transition to the Clear bit 7state.

State D0HR2 Sample PDIAG: This state is entered when the device has recognized that DASPis asserted.

When in this state, the device shall sample the PDIAG- signal.

Transition D0HR2:D0HR3: When the sample indicates that PDIAG- is asserted, the device shalltransition to the Clear bit 7 state.

Transition D0HR2:D0HR2: When the sample indicates that PDIAG- is negated and less than450 ms have elapsed since the negation of RESET, then the device shall transition to theSample PDIAG state. When the sample indicates that DASP- is negated and greater than 450

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ms but less than 31 s have elapsed since the negation of RESET, then the device may transitionto the Sample PDIAG state.

Transition D0HR2:D0HR4: When the sample indicates that DASP- is negated and 31 s haveelapsed since the negation of RESET, then the device shall transition to the Set bit 7 state.When the sample indicates that DASP- is negated and greater than 450 ms but less than 31 shave elapsed since the negation of RESET, then the device may transition to the Set bit 7 state.

State D0HR3 Clear bit 7: This state is entered when DASP- has not been asserted during theDASP sample state or when PDIAG- has been asserted during the PDIAG sample state.

When in this state, the device shall store whether or not Device 1 exists as this information isneeded to process any future software reset or EXECUTE DEVICE DIAGNOSTIC command.This information shall be saved until the next power on or hardware reset.

When in this state, the device shall clear bit 7 of the Error register to zero.

Transition D0HR3:D0HR5: When bit 7 in the Error register has been cleared to zero, the deviceshall transition to the Set status state.

State D0HR4 Set bit 7: This state is entered when the device has recognized that PDIAG- isasserted.

When in this state, the device shall store the fact that Device 1 exists as this information isneeded to process any future software reset or EXECUTE DEVICE DIAGNOSTIC command.This information shall be saved until the next power on or hardware reset.

When in this state, the device shall set bit 7 of the Error register to one.

Transition D0HR3:D0HR5: When bit 7 in the Error register has been set to one, the device shalltransition to the Set status state.

State D0HR5 Set status: This state is entered when Bit 7 in the Error register has been set orcleared.

When in this state the device shall complete the hardware initialization and self-diagnostictesting begun in the Sample DASP state if not already completed.

Results of the self-diagnostic testing shall be placed in bits 6-0 of the Error register (see table10). The device shall set its signature values (see 9.1). The content of the Features register isundefined.

If the device does not implement the PACKET command feature set, the device shall clear bits3, 2, and 0 in the Status register to zero. If the device implements the PACKET commandfeature set, the device shall clear bits 5, 4, 3, 2, and 0 in the Status register to zero.

If the device implements the PACKET command feature set,, the device shall return itsoperating modes to their specified initial conditions. MODE SELECT conditions shall be restoredto their last saved values if saved values have been established. MODE SELECT conditions forwhich no values have been saved shall be returned to their default values. DRDY shall becleared to zero.

Transition D0HR5:DI1: When hardware initialization and self-diagnostic teating is completedand the status has been set, the device shall transition to the Device idle S state (see figure 8).

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State D1HR0 Set DASP: This state is entered when the device has released the bus, set BSY toone, and determined that it is Device 1.

When in this state, the device shall assert DASP- within 400 ns of the negation of RESET.

When in this state, the device should begin execution of its hardware initialization and self-diagnostic testing to completion. The device may revert to its default condition (the device’ssettings may now be in different conditions than they were before RESET was asserted by thehost). All Ultra DMA modes shall be disabled.

Transition D1HR0:D1HR1: When DASP- has been asserted, the device shall transition to theSet status state.

State D1HR1 Set status: This state is entered when the device has asserted DASP-.

When in this state the device shall complete the hardware initialization and self-diagnostictesting begun in the Set DASP state if not already completed. Results of the self-diagnostictesting shall be placed in the Error register (see table 10). If the device passed its self-diagnostics, the device shall assert PDIAG-.

The device shall set its signature values (see 9.1). The effect on the Features register isundefined.


If the device implements the PACKET command feature set,, the device shall return itsoperating modes to their specified initial conditions. MODE SELECT conditions shall be restoredto their last saved values if saved values have been established. MODE SELECT conditions forwhich no values have been saved shall be returned to their default values. The device shall thenclear BSY to zero. DRDY shall be cleared to zero.

Transition D1HR1:DI2: When hardware initialization and self-diagnostic testing is completedand the status has been set, the device transitions to the Device idle NS state (see figure 8).

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9.3 Software reset protocol

This clause describes the protocol for processing of software resets.

If the host sets SRST in the Device Control register to one while a device is in or going to apower management mode, then the device shall execute its software reset protocol. If the hostasserts RESET- before a device has completed its software reset protocol, then the device shallexecute its hardware reset protocol from the beginning.

The host should not set the SRST bit to one in the Device Control while the BSY bit is set to onein either device Status register as a result of executing the software reset protocol. If the hostsets the SRST bit in the Device Control register to one or issues a DEVICE RESET commandbefore devices have completed execution of the software reset protocol, then the devices shallrestart execution of the software reset protocol from the beginning.

A host should issue an IDENTIFY DEVICE and/or IDENTIFY PACKET DEVICE command afterthe software reset protocol has completed to determine the current status of featuresimplemented by the device(s).

Figure 3 and the text that follows decribes the software reset protocol for the host. Figure 4 andthe text that follows describes the software reset protocol for Device 0. Figure 5 and the text thatfollows describes the software reset protocol for Device 1.

HSR1: Clear wait HSR2: Check statusHSR0: Set SRST

xx:HSR0

SRST asserted

HSR0:HSR1

Timeout complete

HSR1:HSR2

BSY = 1HSR1:HSR1

Software resetrequired

BSY = 0HSR2:HI0

Hostidle

Figure 3 −− Host software reset protocol

State HSR0 Set SRST: This state is entered when the host recognizes that a software reset isrequired.

When in this state, the host sets SRST in the Device Control register to one. The host shallremain in this state with SRST set to one for at least 5 µs. The host shall not set SRST to oneunless it has been cleared to zero for at least 5 µs.

Transition HSR0:HSR1: When the host has had SRST set to one for at least 5 µs, the host shalltransition to the Clear wait state.

State HSR1 Clear wait: This state is entered when SRST has been set to one for at least 5 µs.

When in this state, the host shall clear SRST in the Device Conterol register to zero. The hostshall remain in this state for at least 2 ms.

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Transition HSR1:HSR2: When SRST has been cleared to zero for at least 2 ms, the host shalltransition to the Check status state.

State HSR2 Check status: This state is entered when SRST has been cleared to zero for atleast 2 ms.


Transition HSR2:HSR2: When BSY is set to one, the host shall transition to the Check statusstate.

Transition HSR2:HI0: When BSY is cleared to zero, the host shall transition to the Host idlestate (see figure 6).

D0SR2: Sample PDIAGPDIAG- =R, BSY=1

Resample PDIAG

D0SR2:D0SR2

D0SR1: PDIAG waitPDIAG- =R, BSY=1

Wait completeD0SR1:D0SR2

D0SR3: Clear bit 7PDIAG- =R, BSY=1

Sample timeout

D0SR4: Set bit 7PDIAG- =R, BSY=1

D0SR2:D0SR3

PDIAG asserted

D0SR2:D0SR4

Bit 7 set

Bit 7 clearedD0SR3:D0SR5

D0SR5: Set statusPDIAG- =R, BSY=1

D0SR4:D0SR5

D0SR5:DI1Status set

Device idle S

SRST set to one

D0SR0: SRSTPDIAG- =R, BSY=1

xx:D0SR0

SRST cleared to zero,no Device 1

SRST cleared to zero,Device 1 exists

D0SR0:D0SR3

D0SR0:D0SR1

Figure 4 −− Device 0 software reset protocol

State D0SR0 SRST: This state is entered by Device 0 when the SRST bit is set to one in theDevice Control register.

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When in this state, the device shall release PDIAG-, INTRQ, IORDY, DMARQ, and DD(15:0)within 400 ns after entering this state. The device shall set BSY to one within 400 ns afterentering this state.

If the device does not implement the PACKET command feature set, the device shall beginperforming its hardware initialization and self-diagnostic testing. The device may revert to itsdefault condition (the device’s setting may now be in different conditions than they were beforethe SRST bit was set to one by the host). However, the condition of any Ultra DMA mode (eitherenabled or disabled) shall not be affected by the host setting SRST to one.

If the PACKET command feature set is implemented, the device may begin performing itshardware initialization and self-diagnostic testing and the device is not expected to stop anybackground device activity (e.g., immediate command, see MMC and MMC-2) that was startedprior to the time that SRST was set to one. The device shall not revert to its default condition andthe condition of any Ultra DMA mode (either enabled or disabled) shall not be affected by thehost setting SRST to one.

Transition D0SR0:D0SR1: When SRST is cleared to zero and the assertion of DASP- byDevice 1 was detected during the most recent power on or hardware reset, the device transitionsto the PDIAG wait state.

Transition D0SR0:D0SR3: When SRST is cleared to zero and the assertion of DASP- byDevice 1 was not detected during the most recent power on or hardware reset, the devicetransitions to the Clear bit 7 state.

State D0SR1 PDIAG- wait: This state is entered when SRST has been cleared to zero andDevice 1 exists.

The device shall remain in this state for at least 1 ms.

Transition D0SR1:D0SR2: When at least 1 ms has elapsed since SRST was cleared to zero,the device transitions to the Sample PDIAG state.

State D0SR2 Sample PDIAG: This state is entered when SRST has been cleared to zero for atleast 1 ms.


Transition D0SR2:D0SR3: When the sample indicates that PDIAG- is asserted, the device shalltransition to the Clear bit 7 state.

Transition D0SR2:D0SR2: When the sample indicates that PDIAG- is negated and less than 31s have elapsed since SRST was cleared to zero, then the device shall transition to the SamplePDIAG state.

Transition D0SR2:D0SR4: When the sample indicates that DASP- is negated and 31 s haveelapsed since SRST was cleared to zero, the device shall transition to the Set bit 7 state.

State D0SR3 Clear bit 7: This state is entered when PDIAG- has been asserted during thePDIAG sample state.


Transition D0SR3:D0SR5: When bit 7 in the Error register has been cleared to zero, the devicetransitions to the Set status state.

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State D0SR4 Set bit 7: This state is entered when the device has recognized that PDIAG- wasnot asserted during the PDIAG sample state.


Transition D0SR3:D0SR5: When bit 7 in the Error register has been set to one, the device shalltransition to the Set status state.

State D0SR5 Set status: This state is entered when Bit 7 in the Error register has been set orcleared.

When in this state the device shall complete the hardware initialization and self-diagnostictesting begun in the SRST state if not already completed.

Results of the self-diagnostic testing shall be placed in bits 6-0 of the Error register (see table10). The device shall set its signature values (see 9.1). The effect on the Features register isundefined.


If the device implements the PACKET command feature set, the device shall return its operatingmodes to their specified initial conditions. MODE SELECT conditions shall be restored to theirlast saved values if saved values have been established. MODE SELECT conditions for whichno values have been saved shall be returned to their default values. DRDY shall be cleared tozero.

Transition D0SR5:D0SR6: When hardware initialization and self-diagnostic teating is completedand the status has been set, the device shall transition to the Device idle S state (see figure 8).

SRST set to one

D1SR0: SRSTBSY=1

xx:D1SR0

SRST cleared to zero

D1SR0:D1SR1

D1SR1: Negate PDIAGPDIAG- =N, BSY=1

PDIAG negated

D1SR2:DI2

Status set

D1SR2: Set statusPDIAG- =A, BSY=1

D1SR1:D1SR2

Device idle NS

Figure 5 −− Device 1 software reset protocol

State D1SR0 SRST: This state is entered by Device 1 when the SRST bit is set to one in theDevice Control register.

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When in this state, the device shall release INTRQ, IORDY, DMARQ, and DD(15:0) within 400ns after entering this state. The device shall set BSY to one within 400 ns after entering thisstate.

If the device does not implement the PACKET command feature set, the device shall beginperforming its hardware initialization and self-diagnostic testing. The device may revert to itsdefault condition (the device’s setting may now be in different conditions than they were beforethe SRST bit was set to one by the host). However, the condition of any Ultra DMA mode (eitherenabled or disabled) shall not be affected by the host setting SRST to one.

If the PACKET command feature set is implemented, the device may begin performing itshardware initialization and self-diagnostic testing and the device is not expected to stop anybackground device activity (e.g., immediate command, see MMC and MMC-2) that was startedprior to the time that SRST was set to one. The device shall not revert to its default condition andthe condition of any Ultra DMA mode (either enabled or disabled) shall not be affected by thehost setting SRST to one.

Transition D1SR0:D1SR1: When SRST is cleared to zero, the device shall transition to theNegate PDIAG state.

State D1SR1 : This state is entered when SRST is cleared to zero.

When in this state, the device shall negate PDIAG- within 1 ms of entering this state.

Transition D1SR1:D1SR2: When PDIAG- has been negated, the device shall transition to theSet status state.

State D1SR2 Set status: This state is entered when the device has negated PDIAG-.

When in this state the device shall complete the hardware initialization and self-diagnostictesting begun in the SRST state if not already completed. Results of the self-diagnostic testingshall be placed in the Error register (see table 10). If the device passed its self-diagnostics, thedevice shall assert PDIAG-.

The device shall set its signature values (see 9.1). The contents of the Features register isundefined.



Transition D1SR2:DI2: When hardware initialization and self-diagnostic testing is completedand the status has been set, the device shall transition to the Device idle NS state (see figure 8).

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9.4 Bus idle protocol

When the selected device has BSY cleared to zero and DRQ cleared to zero the bus is idle.When the bus is idle, the device is waiting for a command and the host has no command to sendto the device.

If command overlap is implemented and enabled, the host may be waiting for a service requestfor a released command. In this case, the device is preparing for the data transfer for thereleased command.

If command overlap and command queuing are implemented and enabled, the host may bewaiting for a service request for a number released commands. In this case, the device ispreparing for the data transfer for one of the released commands.

Figure 6 and the text that follows describes the host state during bus idle for hosts notimplementing command overlap and queuing. Figure 7 and the text that follows describes theadditional host state during bus idle required for command overlap and queuing. Figure 8 andthe text that follows describes the device state during bus idle for devices not implementingcommand overlap and queuing. Figure 9 and the text that follows describes the additional devicestate during bus idle required for command overlap and queuing.

HI1: Check Status HI2: Select Device

Commandcompleted orpower-on,hardware, orsoftware reset

HI0: Host Idle

xx:HI0

Command to initiate

HI0:HI1

BSY & DRQ = 0,wrong device selected

HI1:HI2

Device selectedHI2:HI1

BSY or DRQ = 1

HI1:HI1

BSY & DRQ = 0,correct device selected

HI1:HI3

Command protocol

HI3: Write parameters HI4: Write command

Parameters writtenHI3:HI4

Command writtenHI4:xx

Command to initiateHIO2:HI1

Figure 6 −− Host bus idle state without overlap

State HI0 Host Idle: This state is entered when a device completes a command or when apower-on, hardware ,or software reset has occurred.

When in this state, the host waits for a command to be issued to a device.

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Transition HI0:HI1: When the host has a command to issue to a device, the host shall transitionto the Check Status state.

State HI1 Check Status: This state is entered when the host has a command to issue to adevice.

When in this state, the host reads the device Status or Alternate Status register.

Transition HI1:HI2: When the status read indicates that both BSY and DRQ are cleared to zerobut the wrong device is selected, then the host shall transition to the Select Device state.

Transition HI1:HI1: When the status read indicates that either BSY or DRQ is set to one, thehost shall transition to the Check Status state to recheck the status of the selected device.

Transition HI1:HI3: When the status read indicates that both BSY and DRQ are cleared to zeroand the correct device is selected, then the host shall transition to the Write Parameters state.

State HI2 Select Device: This state is entered when the wrong device is selected for issuing anew command.

When in this state, the host shall write to the Device/Head reagister to select the correct device.

Transition HI2:HI1: When the Device/Head register has been written to select thecorrectdevice, then the host shall transition to the Check Status state.

State HI3 Write Parameters: This state is entered when the host has determined that the correctdevice is selected and both BSY and DRQ are cleared to zero.

When in this state, the host writes any required command parameters to the device CommandBlock registers.

Transition HI3:HI4: When all required command parameters have been written to the deviceCommand Block registers, the host shall transition to the Write Command state.

State HI4 Write Command: This state is entered when the host has written all requiredcommand parameters to the device Command Block registers.

When in this state, the host writes the command to the device Command register.

Transition HI4:xx: When the host has written the command to the device Command register,the host shall transition to the command protocol for the command written.

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HIO2:HI1

HIO1: Select device A HIO2: Disable INTRQHIO0: INTRQ wait A

Commandcompleted withnIEN=0, REL=1,and SERV=0

xx:HIO0

Select deviceHIO0:HIO1

nIEN=1

HIO:HIO2New command to initiateBus released

with nIEN=0xx:HIO0

Device selectedHIO1:HIO0

HIO3:HIO2

HIO3: Check status A

Commandcompleted withnIEN=1, REL=1,and SERV=0

xx:HIO3

Bus releasedwith nIEN=1

xx:HIO3

Select deviceHIO3:HIO4

SERV=1

New command to initiate

Device selectedHIO3:HIO4

HIO4: Select device B

INTRQ assertedHIO0:HIO3

HIO6: INTRQ wait B HIO7: Check status BHIO5: Write SERVICE

Commandcompleted withSERV=1

xx:HIO5

Tag checked

Service INTRQ enabledHIO5:HIO6

Command queue

No command queue, noservice INTRQ

Command queueHIO5:HIO7

HIO3:HIO5

HIO6:HIO7

No command queueHIO6:xx

HIO5:xx

HIO7:xx

Service return

Servicereturn

Servicereturn

Figure 7 −− Additional host bus idle state with overlap and queuing

State HIO0 INTRQ wait A: This state is entered when a command has completed with nIENcleared to zero, REL set to one, and SERV cleared to zero. This state is entered when the devicehas released the bus with nIEN cleared to zero. This state is entered when the host is pollingINTRQ for bus released commands.

When in this state, the host waits for INTRQ to be asserted indicating that a device is ready toresume execution of a bus released command.

Transition HIO0:HIO1: When the host has one or more commands outstanding to both devices,the host may transition to the Select device A state to poll INTRQ.

Transition HIO0:HIO2: When the host has a new command to issue to a device and that devicehas no command released or supports command queuing, then the host shall transition to theDisable INTRQ state.

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Transition HIO0:HIO3: When the host detects INTRQ asserted, the host shall transition to theCheck status A state.

State HIO1 Select device A: This state is entered when the host has outstanding, bus releasedcommands to both devices.

When in this state, the host shall disable INTRQ by setting nIEN to one, shall write theDevice/Head register to select the other device, and then, shall enable INTRQ by clearing nIENto zero.

Transition HIO1:HIO0: Having selected the other device, the host shall transition to the INTRQwait A state.

State HIO2 Disable INTRQ: This state is entered when the host has a new command to issue toa device and that device has no outstanding, bus released command or supports commandqueuing.

When in this state, the host shall set nIEN to one.

Transition HIO2:HI1: When nIEN has been set to one, the host shall transition to the Checkstatus state (see figure 6).

State HIO3 Check status A: This state is entered when a command is completed with nIEN setto one, REL set to one, and SERV cleared to zero. This state is entered when the device hasreleased the bus and nIEN is set to one. This state is entered when an interrupt has occuredindicating that a device is requesting service.

When in this state, the host shall read the Status register looking for a device requesting service.

Transition HIO3:HIO4: If SERV is cleared to zero and the host has released commandsoutstanding to both devices, then the host shall transition to the Select device B state.

Transition HIO3:HIO2: If SERV is cleared to zero and the host has a new command to issued toa device, then the host shall transition to the Disable INTRQ state.

Transition HIO3:HIO5: If SERV is set to one, the host shall transition to the Write SERVICEstate.

State HIO4 Select device B: This state is entered when the host has outstanding, bus releasedcommands to both devices.

When in this state, the host shall disable INTRQ by setting nIEN to one, shall write theDevice/Head register to select the other device, and then, shall enable INTRQ by clearing nIENto zero.

Transition HIO4:HIO3: Having selected the other device, the host shall transition to the Checkstatus A state.

State HIO5 Write SERVICE: This state is entered when a device has set SERV to one indicatingthat the device requests service. This state is entered when a command has completed withSERV set to one.

When in this state, the host shall write the SERVICE command to the Command register.

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Transition HIO5:HIO6: When the device is one that implements the PACKET command featureset and the Service interrupt is enabled, then the host shall transition to the INTRQ wait B state.

Transition HIO5:HIO7: When the host has more than one released command outstanding to thedevice and the Service interrupt is disabled, the host shall transition to the Check status B state.

Transition HIO5:xx: When the Service interrupt is disabled and the host has only one releasedcommand outstanding to the device, the host shall transition to the service return for the protocolfor the command outstanding.

State HIO6 INTRQ wait B: This state is entered when the SERVICE command has been writtento a device implementing the PACKET command feature set and the Service interrupt isenabled.

When in this state, the host waits for the assertion of INTRQ.

Transition HIO6:HIO7: When the host has more than one released command outstanding to thedevice and INTRQ is asserted, the host shall transition to the Check status B state.

Transition HIO6:xx: When INTRQ has been asserted and the host has only one releasedcommand outstanding to the device, then the host shall transition to the service return for theprotocol for the command outstanding.

State HIO7 Check status B: This state is entered when the SERVICE command has beenwritten and the host has more than one released command outstanding to the device.

When in this state the host reads the command tag to determine which outstanding commandservice is requested for.

Transition HIO7:xx: When the command for which service is requested has been determined,the host shall transition to the service return for that command protocol.

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Command completed,nIEN=0, interrupt pending

xx:DI1

Power-on, hardware,or software reset ifDevice 0

DI2: Device Idle NSBSY=0, DRQ=0, INTRQ=R

xx:DI2

Power-on, hardware, orsoftware reset if Device 1

DI0:DI2

xx:DI0

DI0: Device Idle SIBSY=0, DRQ=0, INTRQ=A

Command protocol

Command writtenDI0:xx

Status register read

Device/Head registerwritten, device selected

DI0:DI0

DI0:DI1

DI1: Device Idle SBSY=0, DRQ=0, INTRQ=N

Command protocol

Command writtenDI1:xx

Device/Head registerwritten, device selected

DI1:DI1

Device/Head registerwritten, device deselected

Device/Head registerwritten, device deselected

DI1:DI2

Device/Head registerwritten, device selected,nIEN=0, interrupt pending

DI2:DI0

Device/Head registerwritten, device selected,no interrupt pending or nIEN=1

DI2:DI1Command completed,no interrupt pending ornIEN=1

xx:DI1

Figure 8 −− Device bus idle state without overlap

State DI0 Device Idle SI (selected/INTRQ asserted): This state is entered when the device hascompleted the execution of a command protocol with interrupt pending and nIEN=0.

When in this state, the device shall have BSY and DRQ cleared to zero and INTRQ asserted.

Transition DI0:xx: When the Command register is written, the device shall clear the deviceinternal interrupt pending, shall negate or release INTRQ, and shall transition to the commandprotocol indicated by the content of the Command register.

Transition DI0:DI1: When the Status register is read, the device shall clear the device internalinterrupt pending, negate or release INTRQ, and transition to the Device Idle S state.

Transition DI0:DI0: When the Device/Head register is written and the DEV bit selects thisdevice, the device shall transition to the Device Idle SI state.

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Transition DI0:DI2: When the Device/Head register is written and the DEV bit selects the otherdevice, then the device shall release INTRQ and transition to the Device Idle NS state.

State DI1 Device Idle S (selected/INTRQ negated): This state is entered when the device hascompleted the execution of a command protocol with no interrupt pending or nIEN=1, or when apending interrupt is cleared. This state is also entered by Device 0 at the completion of a power-on, hardware, or software reset.

When in this state, the device shall have BSY and DRQ cleared to zero and INTRQ negated orreleased.

When entering this state from a power on, hardware, or software reset, if the device does notimplement the PACKET command feature set, the device shall set DRDY to one within 30 s ofentering this state. When entering this state from a power on, hardware, or software reset, if thedevice does implement the PACKET command feature set, the device shall not set DRDY toone.

Transition DI1:xx: When the Command register is written, the device shall transition to thecommand protocol indicated by the content of the Command register.

Transition DI1:DI1: When the Device/Head register is written and the DEV bit selects thisdevice, the device shall transition to the Device Idle S state.

Transition DI1:DI2: When the Device/Head register is written and the DEV bit selects the otherdevice, the device shall transition to the Device Idle NS state.

State DI2 Device Idle NS (not selected): This state is entered when the device is deselected.This state is also entered by Device 1 at the completion of a power-on, hardware, or softwarereset.

When in this state, the device shall have BSY and DRQ cleared to zero and INTRQ shall bereleased.

When entering this state from a power on, hardware, or software reset, if the device does notimplement the PACKET command feature set, the device shall set DRDY to one within 30 s ofentering this state. When entering this state from a power on, hardware, or software reset, if thedevice does implement the PACKET command feature set, the device shall not set DRDY toone.

Transition DI2:DI0: When the Device/Head register is written, the DEV bit selects this device,the device has an interrupt pending, and nIEN is cleared to zero, then the device shall transitionto the Device Idle SI state.

Transition DI2:DI1: When the Device/Head register is written, the DEV bit selects this device,and the device has no interrupt pending or nIEN is set to one, then the device shall transition tothe Device Idle S state.

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Command completed,interrupt pending andnIEN=0, REL=1, SERV=1

DIO0: Device Idle SIRBSY=0, DRQ=0, INTRQ=1,REL=1, SERV=0

Command completed,interrupt pending andnIEN=0, REL=1, SERV=0

xx:DIO0

Bus released, interruptpending and nIEN=0,REL=1, SERV=0

xx:DIO0

Service required

DIO2: Device Idle SISBSY=0, DRQ=0, INTRQ=1,REL=1, SERV=1

xx:DIO2

Bus released, interruptpending and nIEN=0,REL=1, SERV=1

xx:DIO2

DIO0:DIO2

DIO4: Device Idle NSBSY=0, DRQ=0, INTRQ=R,

Command writtenDIO0:xx Command protocol

Device deselectedDIO0:DIO4

Device selectedDIO4:DIO0

Bus released, nointerrupt pending ornIEN=1, REL=1, SERV=0

DIO1: Device Idle SRBSY=0, DRQ=0, INTRQ=0,REL=1, SERV=0

Command completed, nointerrupt pending ornIEN=1, REL=1, SERV=0

xx:DIO1

xx:DIO1

Status register readDIO0:DIO1

Service required

DIO3: Device Idle SSBSY=0, DRQ=0, INTRQ=0,REL=1, SERV=1

Command completed, nointerrupt pending ornIEN=1, REL=1, SERV=1

xx:DIO3

Bus released, no interruptpending or nIEN=1,REL=1, SERV=1

xx:DIO3

DIO1:DIO3

Commandwritten

DIO1:xx

Commandprotocol



Commandwritten

DIO3b:xx

Commandprotocol



Status register readDIO2:DIO3

Command writtenDIO2b:xx Command protocol



SERVICE writtenDIO2a:xx Service return

SERVICEwritten

DIO3a:xx

Servicereturn

Figure 9 −− Additional device bus idle state with overlap and queuing

State DIO0 Device Idle SIR (selected/INTRQ asserted/RELset to one): This state is enteredwhen the device has completed the execution of a command protocol with interrupt pending,nIEN=0, REL set to one, and SERV cleared to zero. This state is entered when the device has

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released an overlapped with interrupt pending, nIEN=0, REL set to one, and SERV cleared tozero.

When in this state, the device is preparing for completion of a released command. The deviceshall have BSY and DRQ cleared to zero, and INTRQ asserted.

Transition DIO0:xx: When the Command register is written, the device shall clear the deviceinternal interrupt pending, shall negate or release INTRQ, and shall transition to the commandprotocol indicated by the content of the Command register.

Transition DIO0:DIO1: When the Status register is read, the device shall clear the deviceinternal interrupt pending, negate or release INTRQ, and transition to the Device Idle SR state.

Transition DIO0:DIO2: When the Device/Head register is written and the DEV bit selects theother device, then the device shall release INTRQ and transition to the Device Idle NS state.

Transition DIO0:DIO2: When the device is ready to continue the execution of a releasedcommand, the device shall transition to the Device idle SIS state.

State DIO1 Device Idle SR (selected/INTRQ negated/REL set to one): This state is enteredwhen the device has completed the execution of a command protocol with no interrupt pendingor nIEN=1, REL set to one, and SERV cleared to zero. This state is entered when the device hasreleased an overlapped command with no interrupt pending or nIEN=1, REL set to one, andSERV cleared to zero. This state is entered when a pending interrupt is cleared, REL is set toone, and SERV is cleared to zero.

When in this state, the device is preparing for completion of a released command. The deviceshall have BSY and DRQ cleared to zero, and INTRQ negated or released.

Transition DIO1:xx: When the Command register is written, the device shall transition to thecommand protocol indicated by the content of the Command register.

Transition DIO1:DIO4: When the Device/Head register is written and the DEV bit selects theother device, the device shall transition to the Device Idle NS state.

Transition DIO1:DIO3: When the device is ready to continue the execution of a releasedcommand, the device shall transition to the Device idle SS state.

State DIO2 Device Idle SIS (selected/INTRQ asserted/SERV set to one): This state is enteredwhen the device has completed the execution of a command protocol with interrupt pending,nIEN=0, REL set to one, and SERV set to one. This state is entered when the device hasreleased an overlapped with interrupt pending, nIEN=0, REL set to one, and SERV set to one.

Transition DIO2:DIO3: When the Status register is read, the device shall clear the deviceinternal interrupt pending, negate or release INTRQ, and transition to the Device Idle SS state.

Transition DIO2: DIO4: When the Device/Head register is written and the DEV bit selects theother device, the device shall transition to the Device Idle NS state.

Transition DIO2a:xx: When the SERVICE command is written into the Command register, thedevice shall transition to the Service return of the command ready for service.

Transition DIO2b:xx: When any overlapped command other than SERVICE is written to theCommand register, the device shall transition to the protocol for the new command.

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State DIO3 Device Idle SS (selected/INTRQ negated/SERV set to one): This state is enteredwhen the device has completed the execution of a command protocol with no interrupt pendingor nIEN=1, REL set to one, and SERV set to one. This state is entered when the device hasreleased an overlapped with no interrupt pending or nIEN=1, REL set to one, and SERV set toone.

Transition DIO3: DIO4: When the Device/Head register is written and the DEV bit selects theother device, the device shall transition to the Device Idle NS state.

Transition DIO3a:xx: When the SERVICE command is written into the Command register, thedevice shall transition to the Service return of the command ready for service.

Transition DIO3b:xx: When any overlapped command other than SERVICE is written to theCommand register, the device shall transition to the protocol for the new command.

State DIO4 Device Idle NS (not selected): This state is entered when the device is deselectedwith REL or SERV set to one.

When in this state, the device shall have BSY and DRQ cleared to zero and INTRQ shall bereleased.

Transition DIO4:DIO0: When the Device/Head register is written, the DEV bit selects thisdevice, the device has an interrupt pending, nIEN is cleared to zero, REL is set to one, andSERV is cleared to zero, then the device transitions to the Device Idle SIR state.

Transition DIO4:DIO1: When the Device/Head register is written, the DEV bit selects thisdevice, the device has no interrupt pending or nIEN is set to one, REL is set to one, and SERV iscleared to zero, then the device transitions to the Device Idle SIR state.

Transition DIO4:DIO2: When the Device/Head register is written, the DEV bit selects thisdevice, the device has an interrupt pending, nIEN is cleared to zero, REL is set to one, andSERV is set to one, then the device transitions to the Device Idle SIS state.

Transition DIO4:DIO3: When the Device/Head register is written, the DEV bit selects thisdevice, the device has no interrupt pending or nIEN is set to one, REL is set to one, and SERV isset to one, then the device transitions to the Device Idle SIR state.

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9.5 Non-data command protocol

This class includes:

− CFA ERASE SECTORS− CFA REQUEST EXTENDED ERROR CODE− CHECK POWER MODE− FLUSH CACHE− GET MEDIA STATUS− IDLE− IDLE IMMEDIATE− INITIALIZE DEVICE PARAMETERS− MEDIA EJECT− MEDIA LOCK− MEDIA UNLOCK− NOP− READ NATIVE MAX ADDRESS− READ VERIFY SECTOR(S)− SECURITY ERASE PREPARE− SECURITY FREEZE LOCK− SEEK− SET FEATURES− SET MAX ADDRESS− SET MULTIPLE MODE− SLEEP− SMART DISABLE OPERATION− SMART ENABLE/DISABLE AUTOSAVE− SMART ENABLE OPERATION− SMART EXECUTE OFFLINE IMMEDIATE− SMART RETURN STATUS− STANDBY− STANDBY IMMEDIATE

Execution of these commands involves no data transfer. Figure 10 and the text that followsdescribes the host state. Figure 11 and the text that follows decribes the device state.

See the NOP command description in 8.20 and the SLEEP command in 8.40 for additionalprotocol requirements.

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HND0: INTRQ wait HND1: Check Status

Commandwritten &selected devicenIEN = 0

HI4:HND0

INTRQ assertedHND0:HND1

BSY & DRQ = 0HND1:HI0

BSY or DRQ = 1HND1:HND1

Host Idle

Commandwritten &selected devicenIEN = 1

HI4:HND1

Figure 10 −− Host non-data state

State HND0 INTRQ Wait: This state is entered when the host has written a non-data commandto the device and the nIEN bit in the device has been cleared to zero.

When in this state the host shall wait for INTRQ to be asserted by the device.

Transition HND0:HND1: When the device asserts INTRQ, the host shall transition to the CheckStatus state.

State HND1 Check Status: This state is entered when the host has written a non-data commandto the device and the nIEN bit in the device has been set to one, or when INTRQ has beenasserted.

When in this state, the host shall read the device Status register.

Transition HND1:HI0: When the status read indicates both BSY and DRQ are cleared to zero,the host shall transition to the Host Idle state (see figure 6). If status indicates that an error hasoccured, the host shall take appropriate error recovery action.

Transition HND1:HND1: When the status read indicates that either BSY or DRQ is set to one,the host shall transition to the Check Status state to recheck device status.

DND0: Command ExecutionBSY=1, DRQ=0, INTRQ=N

Non-datacommandwritten

DI0:DND0DI1:DND0

Execution complete,nIEN = 1

DND0:DI1 Device Idle S

Execution complete,nIEN = 0

DND0:DI0 Device Idle SI

Figure 11 −− Device non-data state

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State DND0 Command Execution: This state is entered when a non-data command has beenwritten to the device Command register.

When in this state, the device shall set BSY to one, shall execute the requested command, andshall set the device internal interrupt pending.

Transition DND0:DI0: When command execution completes and nIEN is cleared to zero, thenthe device shall set error bits if appropriate, assert INTRQ, and transition to the Device Idle SIstate (see figure 8).

Transition DND0:DI1: When command execution completes and nIEN is set to one, the deviceshall set error bits if appropriate, and transition to the Device Idle S state (see figure 8).

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9.6 PIO data in command protocol


− CFA TRANSLATE SECTOR− IDENTIFY DEVICE− IDENTIFY PACKET DEVICE− READ BUFFER− READ MULTIPLE− READ SECTOR(S)− SMART READ DATA

Execution of this class of command includes the transfer of one or more blocks of data from thedevice to the host. Figure 12 and the following text describes the host states. Figure 13 and thefollowing text describes the device states.

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PIO data incommandwritten & selecteddevice nIEN = 0

HI4:HPIOI0

HPIOI0: INTRQ wait

INTRQ asserted

HPIOI1: Check Status

HPIOI0:HPIOI1BSY & DRQ = 0

HPIOI1:HI0 Host Idle

PIO data incommandwritten & selecteddevice nIEN = 1

HI4:HPIOI1

BSY = 1 & DRQ = 0HPIOI1:HPIOI1

HPIOI2: Transfer DataBSY = 0 & DRQ = 1

HPIOI1:HPIOI2

Data register read, DRQblock transferred, all datafor command nottransferred, nIEN = 1

HPIOI2:HPIOI1

Data registerread, DRQblocktransferred, alldata forcommand nottransferred,nIEN = 0

HPIOI2:HPIOI0 Data register read, DRQblock transfer not complete

HPIOI2:HPIOI2

Data register read, all datafor command transferred

HPIOI2:HI0 Host Idle

Figure 12 −− Host PIO data in state

State HPIOI0 INTRQ Wait: This state is entered when the host has written a PIO data incommand to the device and nIEN is cleared to zero, or at the completion of a DRQ block transferif all the data for the command has not been transferred and nIEN is cleared to zero.

When in this state, the host shall wait for INTRQ to be asserted.

Transition HPIOI0:HPIOI1: When INTRQ is asserted, the host shall transition to the CheckStatus state.

State HPIOI1 Check Status: This state is entered when the host has written a PIO data incommand to the device and nIEN is set to one, or when INTRQ is asserted.

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Transition HPIOI1:HI0: When BSY is cleared to zero and DRQ is cleared to zero, then thedevice has completed the command with an error. The host shall perform appropriate errorrecovery and transition to the Host Idle state (see figure 6).

Transition HPIOI1:HPIOI1: When BSY is set to one and DRQ is cleared to zero, the host shalltransition to the Check Status state.

Transition HPIOI1:HPIOI2: When BSY is cleared to zero and DRQ is set to one, the host shalltransition to the Transfer Data state.

State HPIOI2 Transfer Data: This state is entered when the BSY is cleared to zero, DRQ is setto one, and the DRQ data block transfer has not completed.

When in this state, the host shall read the device Data register to transfer data.

Transition HPIOI2:HPIOI0: When the host has read the device Data register and the DRQ datablock has been transferred, all data for the command has not been transferred, and nIEN iscleared to zero, then the host shall transition to the INTRQ Wait state.

Transition HPIOI2:HPIOI1: When the host has read the device Data register and the DRQ datablock has been transferred, all data for the command has not been transferred, and nIEN is setto one, then the host shall transition to the Check Status state.

Transition HPIOI2:HPIOI2: When the host has read the device status register and the DRQdata block transfer has not completed, then the host shall transition to the Transfer Data state.

Transition HPIOI2:HI0: When the host has read the device Data register and all data for thecommand has been transferred, then the host shall transition to the Host Idle state (see figure 6).

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PIO data incommand written

DI0:DPIOI0DI1:DPIOI0

DPIOI0: Prepare DataBSY=1, DRQ=0, INTRQ=N

Command executionaborted with error,nIEN=0

DPIOI0:DI0

DPIOI1:DI1

Data registerread, DRQ blocktransferred, alldata for commandnot transferred

DPIOI1:DPIOI0

Data register read,DRQ block transfer notcomplete

DPIOI1:DPIOI1

Data ready to transfer,nIEN=0

Data ready to transfer,nIEN=1

Data register read, all datafor command transferred

DPIOI2:DPIOI1

DPIOI0:DPIOI1

DPIOI1: Transfer DataBSY=0, DRQ=1, INTRQ=N


DPIOI0:DPIOI2DPIOI2: Data Rdy INTRQBSY=0, DRQ=1, INTRQ=A

Device Idle S

Command executionaborted with error,nIEN=1

DPIOI0:DI1

Figure 13 −− Device PIO data in state

State DPIOI0 Prepare Data: This state is entered when the device has a PIO data in commandwritten to the Command register.

When in this state, device shall set BSY to one and prepare the requested data for transfer to thehost.

Transition DPIOI0:DI0: When an error is detected that causes the command to abort and nIENis cleared to zero, then the device shall set the appropriate error bits and transition to the DeviceIdle SI state (see figure 8).

Transition DPIOI0:DI1: When an error is detected that causes the command to abort and nIENis set to one, then the device shall set the appropriate error bits and transition to the Device IdleSI state (see figure 8).

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Transition DPIOI0:DPIOI1: When the device has a DRQ block of data ready to transfer andnIEN is set to one, then the device shall transition to the Transfer Data state.

Transition DPIOI0:DPIOI2: When the device has a DRQ block of data ready to transfer andnIEN is cleared to zero, then the device transitions to the Data Ready INTRQ state.

State DPIOI1 Data Transfer: This state is entered when the device is ready to transfer a DRQblock of data and nIEN is set to one, or when the INTRQ indicating that the device is ready totransfer a DRQ block of data has been acknowleged by a read of the Status register.

When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is negated, and the devicehas a data word ready in the Data register for transfer to the host.

Transition DPIOI1:DPIOI1: When the Data register is read and transfer of the DRQ block hasnot completed, then the device shall transition to the Data Transfer state.

Transition DPIOI1:DPIOI0: When the Data register is read and the transfer of the current DRQblock has completed, but all data for this request has not been transferred, then the device shalltransition to the Prepare Data state.

Transition DPIOI1:DI1: When the Data register is read and all data for this request has beentransferred, then the device shall transition to the Device Idle S state (see figure 8). The deviceinternal interrupt pending is not set on this transition.

State DPIOI2 Data Ready INTRQ: This state is entered when the device has a DRQ block ofdata ready to transfer and nIEN is cleared to zero.

When in this state, BSY is cleared to zero, DRQ is set to one, and INTRQ is asserted.

Transition DPIOI2:DPIOI1: When the Status register is read, then the device shall clear thedevice internal interrupt pending, negate INTRQ, and transition to the Data Transfer state.

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9.7 PIO data out command protocol


− CFA WRITE MULTIPLE WITHOUT ERASE− CFA WRITE SECTORS WITHOUT ERASE− DOWNLOAD MICROCODE− SECURITY DISABLE PASSWORD− SECURITY ERASE UNIT− SECURITY SET PASSWORD− SECUITY UNLOCK− WRITE BUFFER− WRITE MULTIPLE− WRITE SECTOR(S)

Execution of this class of command includes the transfer of one or more blocks of data from thehost to the device. Figure 14 and the following text describes the host states. Figure 15 and thefollowing text describes the device states.

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HPIOO0: Check Status

BSY & DRQ = 0HPIOO0:HI0 Host Idle

PIO data outcommandwritten

HI4:HPIOO0

BSY = 1 & DRQ = 0

HPIOO0:HPIOO0

BSY = 0 & DRQ = 1

HPIOO2:HPIOO0

HPIOO2: INTRQ wait

HPIOO1:HPIOO0

HPIOO1:HPIOO2

HPIOO1: Transfer Data

HPIOO0:HPIOO1

Data register written, DRQblock transferred, nIEN = 0

Data registerwritten, DRQblocktransferred,nIEN = 1

Data register written, DRQblock transfer not complete

HPIOO1:HPIOO1

INTRQ asserted

Figure 14 −− Host PIO data out state

State HPIOO0 Check Status: This state is entered when the host has written a PIO data outcommand to the device; when a DRQ data block has been written and nIEN is set to one; orwhen a DRQ data block has been written, nIEN is cleared zero, and INTRQ has been asserted.


Transition HPIOO0:HI0: When BSY is cleared to zero and DRQ is cleared to zero, then thedevice has completed the command and shall transition to the Host Idle state (see figure 6). If anerror is reported, the host shall perform appropriate error recovery.

Transition HPIOO0:HPIOO0: When BSY is set to one and DRQ is cleared to zero, the hostshall transition to the Check Status state.

Transition HPIOO0:HPIOO1: When BSY is cleared to zero and DRQ is set to one, the hostshall transition to the Transfer Data state.

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State HPIOO1 Transfer Data: This state is entered when the BSY is cleared to zero, DRQ is setto one.

When in this state, the host shall write the device Data register to transfer data.

Transition HPIOO1:HPIOO2: When the host has written the device Data register, the DRQ datablock has been transferred, and nIEN is cleared to zero, then the host shall transition to theINTRQ Wait state.

Transition HPIOO1:HPIOO0: When the host has written the device Data register, the DRQ datablock has been transferred, and nIEN is set to one, then the host shall transition to the CheckStatus state.

Transition HPIOO1:HPIOO1: When the host has written the device status register and the DRQdata block transfer has not completed, then the host shall transition to the Transfer Data state.

State HPIOO2 INTRQ Wait: This state is entered when the host has completed a DRQ datablock transfer and nIEN is cleared to zero.


Transition HPIOO2:HPIOO0: When INTRQ is asserted, the host shall transition to the CheckStatus state.

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PIO data outcommand written

DI0:DPIOO0DI1:DPIOO0

DPIOO0: PrepareBSY=1, DRQ=0, INTRQ=N

Data register written,DRQ block transferred,

DPIOO1:DPIOO0

Data register written,DRQ block transfer notcomplete

DPIOO1:DPIOO1

Ready toreceive firstDRQ data block

DPIOO0a:DPIOO1

DPIOO1: Transfer DataBSY=0, DRQ=1, INTRQ=N

DPIOO0:DPIOO2


DPIOO2: Ready INTRQBSY=0, DRQ=1, INTRQ=A

DPIOO2:DPIOO1

All data for commandtransferred, nIEN = 0

Device Idle SIDPIOO0:DI0


Device Idle SDPIOO0:DI1

Ready to receivesusequent DRQ datablock, nIEN=0

Ready to receivesusequent DRQ datablock, nIEN=1

DPIOO0b:DPIOO1

Figure 15 −− Device PIO data out state

State DPIOO0 Prepare: This state is entered when the device has a PIO data out commandwritten to the Command register or when a DRQ data block has been transferred.

When in this state, device shall set BSY to one, shall clear DRQ to zero, and negate INTRQ. Thedevice shall check for errors, determine if the data transfer is complete, and if not, prepare toreceive the next DRQ data block.

Transition DPIOO0a:DPIOO1: When the device is ready to receive the first DRQ block of datafor a command, the device shall transition to the Transfer Data state.

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Transition DPIOO0b:DPIOO1: When the device is ready to receive a subsequent DRQ block ofdata for a command and nIEN is set to one, then the device shall set the device internal interruptpending and transition to the Transfer Data state.

Transition DPIOO0:DPIOO2: When the device is ready to receive a subsequent DRQ block ofdata for a command and nIEN is cleared to zero, then the device shall set the device internalinterrupt pending and transition to the Ready INTRQ state.

Transition DPIOO0:DI0: When all data for the command has been transferred or an erroroccurs that causes the command to abort, and nIEN is cleared to zero, then the device shall setthe device internal interrupt pending, set appropriate error bits, and transition to the Device IdleSI state (see figure 8).

Transition DPIOO0:DI1: When all data for the command has been transferred or an erroroccurs that causes the command to abort, and nIEN is set to one, then the device shall set thedevice internal interrupt pending, set appropriate error bits, and transition to the Device Idle Sstate (see figure 8).

State DPIOO1 Data Transfer: This state is entered when the device is ready to receive a DRQblock of data.

When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is negated, and the devicerecieves a data word in the Data register.

Transition DPIOO1:DPIOO1: When the Data register is written and transfer of the DRQ blockhas not completed, then the device shall transition to the Data Transfer state.

Transition DPIOO1:DPIOO0: When the Data register is written and the transfer of the currentDRQ block has completed, then the device shall transition to the Prepare state.

State DPIOO2 Ready INTRQ: This state is entered when the device is ready to receive a DRQblock of data and nIEN is cleared to zero.

When in this state, BSY is cleared to zero, DRQ is set to one, and INTRQ is asserted.

Transition DPIOO2:DPIOO1: When the Status register is read, the device shall clear the deviceinternal interrupt pending, negate INTRQ, and transition to the Data Transfer state.

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9.8 DMA command protocol


− READ DMA− WRITE DMA

Execution of this class of command includes the transfer of one or more blocks of data from thedevice to the host or from the device to the host using DMA transfer. The host shall initialize theDMA channel prior to transferring data. A single interrupt is issued at the completion of thetransfer. Figure 16 and the following text describes the host states. Figure 17 and the followingtext describes the device states.

HDMA0: Check Status

BSY & DRQ = 0HDMA0:HI0 Host Idle

DMAcommandwritten

HI4:HDMA0

BSY = 1 & DRQ = 0,DMARQ negated

HDMA0:HDMA0

BSY = 0, DRQ = 1, DMARQ asserted orBSY = 1, DRQ = 0, DMARQ asserted

HDMA2:HDMA0

HDMA1:HDMA0

HDMA1: Transfer Data

HDMA0:HDMA1


All data forcommandtransferred,nIEN = 1

HDMA2: INTRQ wait

HDMA1:HDMA2

INTRQ asserted

Figure 16 −− Host DMA state

State HDMA0 Check Status: This state is entered when the host has written a DMA commandto the device; when all data for the command has been transferred and nIEN is set to one; orwhen all data for the command has been transferred, nIEN is cleared zero, and INTRQ has beenasserted.


Transition HDMA0:HI0: When the BSY is cleared to zero and DRQ is cleared to zero, then thedevice has completed the command and shall transition to the Host Idle state (see figure 6). If anerror is reported, the host shall perform appropriate error recovery.

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Transition HDMA0:HDMA0: When BSY is set to one, DRQ is cleared to zero, and DMARQ isneagted, then the host shall transition to the Check Status state.

Transition HDMA0:HDMA1: When BSY is cleared to zero, DRQ is set to one, and DMARQ isasserted; or if BSY is set to one, DRQ is cleared to zero, and DMARQ is asserted, then the hostshall transition to the Transfer Data state.

State HDMA1 Transfer Data: This state is entered when BSY is cleared to zero, DRQ is set toone, and DMARQ is asserted; or BSY is set to one, DRQ is cleared to zero, and DMARQ isasserted. The host shall have initialized the DMA channel prior to entering this state.

When in this state, the host shall perform the data transfer as described in the Multiword DMAtiming or the Ultra DMA protocol.

Transition HDMA1:HDMA2: When the host has transferred all data for the command and nIENis cleared to zero, then the host shall transition to the INTRQ Wait state.

Transition HDMA1:HDMA0: When the host has transferred all data for the command and nIENis set to one, then the host shall transition to the Check Status state.

State HDMA2 INTRQ Wait: This state is entered when the host has completed the transfer of alldata for the command and nIEN is cleared to zero.


Transition HDMA2:HDMA0: When INTRQ is asserted, the host shall transition to the CheckStatus state.

DMA commandwritten

DI0:DDMA0DI1:DDMA0

DDMA0: PrepareBSY=1, DRQ=0, INTRQ=N

Error caused commandabort, nIEN=0

Device Idle SIDDMA0:DI0

Error caused commandabort, nIEN=1

Device Idle SDDMA0:DI1Ready to transfer data

DDMA0:DDMA1

DDMA1: Transfer DataBSY=0, DRQ=1, INTRQ=N,or BSY=1, DRQ=0, INTRQ=N

All data transferred,nIEN=0

Device Idle SIDDMA1:DI0

All data transferred,nIEN=1

Device Idle SDDMA1:DI1

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Figure 17 −− Device DMA stateState DDMA0 Prepare: This state is entered when the device has a DMA command written tothe Command register.

When in this state, device shall set BSY to one, shall clear DRQ to zero, and negate INTRQ. Thedevice shall check for errors, and prepare to transfer data.

Transition DDMA0:DI0: When an error is detected that causes the command to abort and nIENis cleared to zero, the device shall set the appropriate error bits and transition to the Device IdleSI state (see figure 8).

Transition DDMA0:DI: When an error is detected that causes the command to abort and nIENis set to one, then the device shall set the appropriate error bits and transition to the Device IdleS state (see figure 8).

Transition DDMA0:DDMA1: When the device is ready transfer data for the command, thedevice shall transition to the Transfer Data state.

State DDMA1 Data Transfer: This state is entered when the device is ready to transfer data.

When in this state, BSY is cleared to zero, DRQ is set to one, and INTRQ is negated; or BSY isset to one, DRQ is cleared to zero, and INTRQ is negated. Data is transferred as decribed inMultiword DMA timing or Ultra DMA protocol.

Transition DDMA1:DI0: When the data transfer has completed and nIEN is cleared to zero,then the device shall set error bits if appropriate and transition to the Device Idle SI state (seefigure 8).

Transition DDMA2:DI1: When the data transfer has completed and nIEN is set to one, then thedevice shall set error bits if appropriate and transition to the Device Idle S state (see figire 8).

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9.9 PACKET command protocol


− PACKET

The use of the PACKET command uses two different protocols. Figure 18 and the text thatfollows describes the host protocol for the PACKET command when non-data, PIO data in, orPIO data out is requested. Figure 19 and the text that follows describes the device protocol forthe PACKET command when non-data, PIO data in, or PIO data out is requested. Figure 20 andthe text that follows describes the host protocol for the PACKET command when DMA datatransfer is requested. Figure 21 and the text that follows describes the device protocol for thePACKET command when DMA data transfer is requested.

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HP0: Check Status

Host Idle

BSY = 0, DRQ = 0, C/D = 1,I/O = 1, REL=0, SERV=0

HP0:HI0

PACKETcommand written

HI4:HP0

INTRQ assertedHP2:HP0

HP3: Transfer Data

HP0:HP3

Data registerwritten or read,DRQ blocktransferred

Data register written or read,DRQ block transfer not complete

HP3:HP3

BSY = 1 & DRQ = 0HP0:HP0

HP3:HP0

BSY = 0, DRQ = 1, C/D = 0,I/O = 1 for data in, I/O = 0for data out

HP2: INTRQ waitReady to transfer data orcommand compete, nIEN = 0

HP0a:HP2

HP1: Send Packet

BSY = 0, DRQ = 1,C/D = 1, I/O = 0

HP1:HP1HP0:HP1

Data register written,command packet transfernot complete

Data register written,command packettransfer complete

HP1:HP0

Service return

HIOx:HP0

Bus release orcommand complete

BSY = 0, DRQ = 0, REL=1,SERV=0, nIEN=0

HP0:HIO0



HP0:HIO3


BSY = 0, DRQ = 0, REL=1,SERV=1

HP0:HIO5

Packet written and releaseinterrupt enabled

HP0b:HP2

Figure 18 −− PACKET non-data and PIO data command protocol

State HP0 Check Status: This state is entered when the host has written a PACKET commandto the device; when the command packet has been written, when a DRQ data block has been

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written or read; or when the comand is complete and INTRQ has been asserted. This state isentered upon sending a SERVICE command to resume execution of a bus released command.


Transition HP0:HP0: When BSY is set to one and DRQ is cleared to zero, the host shalltransition to the Check Status state.

Transition HP0:HP1: When BSY is cleared to zero, DRQ is set to one, C/D is set ot one, andI/O is cleared to zero, then the host shall transition to the Send Packet state.

Transition HP0a:HP2: When the host is ready to transfer data or the command is complete, andnIEN is cleared to zero, then the host shall transition to the INTRQ Wait state.

Transition HP0b:HP2: When the command packet transfer is complete and the releaseinterrupt is enabled, thrn the shall host transition to the INTRQ wait state.

Transition HP0:HP3: When BSY is cleared to zero, DRQ is set to one, and C/D is cleared tozero, then the host shall transition to the Transfer Data state.

Transition HP0:HI0: When the BSY is cleared to zero, DRQ is cleared to zero, C/D is set toone, and I/O is set to one, REL is cleared to zero, and SERV is cleared to zero, then thecommand is completed and the host shall transition to the Host Idle state (see figure 6). If anerror is reported, the host shall perform appropriate error recovery.

Transitions HP0:HIO0: When the BSY is cleared to zero, DRQ is cleared to zero, REL is set toone, SERV is cleared to zero, and nIEN is cleared to zero, then the host shall transition to theINTRQ wait A state (see figure 7). The command is completed or the bus has been released. Ifthe command was completed, C/D is set to one and I/O is set to one. If an error is reported, thehost shall perform appropriate error recovery.

Transitions HP0:HIO3: When the BSY is cleared to zero, DRQ is cleared to zero, REL is set toone, SERV is cleared to zero, and nIEN is set to one, then the host shall transition to the Checkstatus A state (see figure 7). The command is completed or the bus has been released. If thecommand was completed, C/D is set to one and I/O is set to one. If an error is reported, the hostshall perform appropriate error recovery.

Transitions HP0:HIO5: When the BSY is cleared to zero, DRQ is cleared to zero, REL is set toone, and SERV is set to one, then the host shall transition to the Write SERVICE state (seefigure 7). The command is completed or the bus has been released. If the command wascompleted, C/D is set to one and I/O is set to one. If an error is reported, the host shall performappropriate error recovery.

State HP1 Send Packet: This state is entered when BSY is cleared to zero, DRQ is set to one,C/D is set to one, and I/O is cleared to zero.

When in this state, the host shall write a byte of the command packet to the Data register.

Transition HP1:HP1: When the Data register has been written and the writing of the commandpacket is not completed, the host shall transition to the Send Packet state.

Transition HP1:HP0: When the Data register has been written and the writing of the commandpacket is completed, the host shall transition to the Check Status state.

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State HP2 INTRQ Wait: This state is entered when the host is ready to transfer data or when thecommand has completed, and nIEN is cleared to zero.


Transition HP2:HP0: When INTRQ is asserted, the host shall transition to the Check Statusstate.

State HP3 Transfer Data: This state is entered when the BSY is cleared to zero, DRQ is set toone, and C/D is cleared to zero.

When in this state, the host shall read or write the device Data register to transfer data.

Transition HP3:HP0: When the host has read or written the device Data register and the DRQdata block has been transferred, then the host shall transition to the Check Status state.

Transition HP3:HP3: When the host has read or written the device status register and the DRQdata block transfer has not completed, then the host shall transition to the Transfer Data state.

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xx:DP0

DP0: PrepareBSY=1, DRQ=0, INTRQ=N

Command completed, nIEN=0,no released command

Device Idle SIDP0:DI0

Command completed, nIEN=1, no released command

Device Idle SDP0:DI1

DP1: Recieve packetBSY=0, DRQ=1, INTRQ=N,C/D=1,I/O=0,REL=0

Data register written,command packettransfer not complete

DP1:DP1

Ready to recieve command packetDP0:DP1

Data register written, commandpacket transfer complete

DP1:DP0

DP3: Ready INTRQBSY=0, DRQ=1, INTRQ=A,C/D=0, I/O=a

DP0:DP3

Ready to transfer DRQdata block, nIEN=0Ready to transfer DRQ

data block, nIEN=1

DP0:DP2


DP3:DP2

Service returnxx:DP0

Command completed or bus release with releaseinterrupt enabled, nIEN = 0, released command

Device Idle SIRDP0:DIO0

Command completed or bus release, nIEN = 0, released commandDevice Idle SRDP0:DIO1

Command completed or bus release, nIEN = 0,ready for serviceDevice Idle SSDP0:DIO3

Command completed or bus release with releaseinterrupt enabled, nIEN = 0, ready for service

Device Idle SISDP0:DIO2

SERVICE written, serviceinterrupt enabled

DP3:DP0

DP0:DP3

Service status read

Data registerread/written, DRQblock transferred

DP2:DP0

Data register read/written,DRQ block transfer notcomplete

DP2: Transfer DataBSY=0, DRQ=1, INTRQ=N,C/D=0, I/O=a

DP2:DP2

Figure 19 −− Device PACKET non-data and PIO data command protocol

State DP0 Prepare: This state is entered when the device has a PACKET or SERVICEcommand written to the Command register, when the command packet has been received, whena DRQ data block has been transferred, or when the command has completed.

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When in this state, device shall set BSY to one, clear DRQ to zero, and negate INTRQ. Non-data transfer commands shall be executed while in this state. For data transfer commands, thedevice shall check for errors, determine if the data transfer is complete, and if not, prepare totransfer the next DRQ data block.

If the command is overlapped and the release interrupt is enabled, the device shall bus releaseas soon as the command packet has been received.

Transition DP0:DP1: When the device is ready to receive the command packet for a command,the device shall transition to the Receive Packet state.

Transition DP0:DP2: When the device is ready to transfer a DRQ block of data for a commandand nIEN is set to one, then the device shall set the device internal interrupt pending andtransition to the Transfer Data state.

Transition DP0a:DP3: When the device is ready to transfer a DRQ block of data for acommand and nIEN is cleared to zero, then the device shall set the device internal interruptpending and transition to the Ready INTRQ state.

Transition DP0b:DP3: When the service interrupt is enabled and the device has SERVICEwritten to the Command register, then the device shall transition to the Ready INTRQ state.

Transition DP0:DI0: When the command has completed or an error occurs that causes thecommand to abort, the device has no other command released, and nIEN is cleared to zero,then the device shall set the device internal interrupt pending, set appropriate error bits, andtransition to the Device Idle SI state (see figure 8).

Transition DP0:DI1: When the command has completed or an error occurs that causes thecommand to abort, the device has no other command released, and nIEN is set to one, then thedevice shall set the device internal interrupt pending, set appropriate error bits, and transition tothe Device Idle S state (see figure 8).

Transition DP0:DIO0: When the command has completed or an error occurs that causes thecommand to abort, the device has another command released but not ready for service, andnIEN is cleared to zero, then the device shall set the device internal interrupt pending, setappropriate error bits, and transition to the Device Idle SIR state (see figure 9). When the devicebus releases a command but has no command ready for service, and nIEN is cleared to zero,then the device shall set the device internal interrupt pending and transition to the Device IdleSIR state (see figure 9).

Transition DP0:DIO1: When the command has completed or an error occurs that causes thecommand to abort, the device has another command released but not ready for service, andnIEN is set to one, then the device shall set the device internal interrupt pending, set appropriateerror bits, and transition to the Device Idle SR state (see figure 9). When the device bus releasesa command but has no command ready for service, and nIEN is set to one, then the device shallset the device internal interrupt pending, and transition to the Device Idle SR state (see figure 9).

Transition DP0:DIO2: When the command has completed or an error occurs that causes thecommand to abort, the device has another command ready for service, and nIEN is cleared tozero, then the device shall set the device internal interrupt pending, set appropriate error bits,and transition to the Device Idle SIS state (see figure 9). When the device bus releases acommand, has another command ready for service, and nIEN is cleared to zero, then the deviceshall set the device internal interrupt pending and transition to the Device Idle SIS state (Seefigure 9).

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Transition DP0:DIO3: When the command has completed or an error occurs that causes thecommand to abort, the device has another command ready for service, and nIEN is set to one,then the device shall set the device internal interrupt pending, set appropriate error bits, andtransition to the Device Idle SS state (see figure 9). When the device bus releases a command,has another command ready for service, and nIEN is set to one, then the device shall set thedevice internal interrupt pending and transition to the Device Idle SS state (see figure 9).

State DP1 Receive Packet: This state is entered when the device is ready to recieve thecommand packet.

When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is negated, C/D is set toone, I/O is cleared to zero, and REL is cleared to zero. When in this state, the device Dataregister is written.

Transition DP1:DP1: If the Data register is written and the entire command packet has not beenrecieved, then the device shall transition to the Receive Packet state.

Transition DP1:DP0: When the Data register is written and the entire command packet hasbeen received, then the device shall transition to the Prepare state.

State DP2 Data Transfer: This state is entered when the device is ready to transfer a DRQblock of data.

When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is negated, C/Dis clearedto zero, I/O is set to one for PIO data out or cleared to zero for PIO data in, and a data word isread/written in the Data register.

Transition DP2:DP2: When the Data register is read/written and transfer of the DRQ block hasnot completed, then the device shall transition to the Data Transfer state.

Transition DP2:DP0: When the Data register is read/written and the transfer of the current DRQblock has completed, then the device shall transition to the Prepare state.

State DP3 Ready INTRQ: This state is entered when the device is ready to transfer a DRQblock of data and nIEN is cleared to zero. This state is entered to interrupt upon receipt of aSERVICE command when service interrupt is enabled.

When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is asserted, C/D is clearedto zero, and I/O is set to one for PIO data out or cleared to zero for PIO data in.

Transition DP3:DP0: When the Status register is read to respond to a service interrupt, thedevice shall transition to the Prepare state.

Transition DP3:DP2: When the Status register is read when the device is ready to transfer data,then the device shall clear the device internal interrupt pending, negate INTRQ, and transition tothe Data Transfer state.

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HPD0: Check Status

Host Idle

BSY = 0, DRQ = 0, C/D = 1,I/O = 1, REL=0, SERV=0

HPD0:HI0


HI4:HPD0

INTRQ assertedHPD2:HPD0

HPD3: Transfer Data

HPD0:HPD3

All data forcommandtransferred,nIEN=1

All data for command transferred,nIEN=0

HPD3:HPD2

BSY = 1 & DRQ = 0HPD0:HPD0

HPD3:HPD0

BSY = 0, DRQ = 1, C/D = 0,I/O = 1 for data in, I/O = 0 fordata out, DMARQ asserted

HPD2: INTRQ waitReady to transfer data orcommand compete, nIEN = 0

HPD0a:HPD2

HPD1: Send Packet

BSY = 0, DRQ = 1,C/D = 1, I/O = 0

HPD1:HPD1HPD0:HPD1

Data register written,command packet transfernot complete

Data register written,command packettransfer complete

HPD1:HPD0

Service returnHIOx:HPD0



HPD0:HIO0



HPD0:HIO3


BSY = 0, DRQ = 0, REL=1,SERV=1

HPD0:HIO5

Packet written and releaseinterrupt enabled

HPD0b:HPD2

Figure 20 −− Host PACKET DMA command protocol

State HPD0 Check Status: This state is entered when the host has written a PACKET commandto the device; when the command packet has been written, or when the comand is complete andINTRQ has been asserted. This state is entered upon sending a SERVICE command to resumeexecution of a bus released command.


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Transition HPD0:HPD0: When BSY is set to one and DRQ is cleared to zero, then the hostshall transition to the Check Status state.

Transition HPD0:HPD1: When BSY is cleared to zero, DRQ is set to one, C/D is set ot one, andI/O is cleared to zero, then the host shall transition to the Send Packet state.

Transition HPD0a:HPD2: When the host is ready to transfer data or the command is complete,and nIEN is cleared to zero, then the host shall transition to the INTRQ Wait state.

Transition HPD0b:HPD2: When the command packet transfer is complete and the releaseinterrupt is enabled, then the host shall transition to the INTRQ wait state.

Transition HPD0:HPD3: When BSY is cleared to zero, DRQ is set to one, and C/D is cleared tozero, and DMARQ is asserted, then the host shall transition to the Transfer Data state.

Transition HPD0:HI0: When the BSY is cleared to zero, DRQ is cleared to zero, C/D is set toone, and I/O is set to one, REL is cleared to zero, and SERV is cleared to zero, then thecommand is completed and the host shall transition to the Host Idle state (see figure 6). If anerror is reported, the host shall perform appropriate error recovery.

Transitions HPD0:HIO0: When the BSY is cleared to zero, DRQ is cleared to zero, REL is setto one, SERV is cleared to zero, and nIEN is cleared to zero, then the host shall transition to theINTRQ wait A state (see figure 7). The command is completed or the bus has been released. Ifthe command was completed, C/D is set to one and I/O is set to one. If an error is reported, thehost shall perform appropriate error recovery.

Transitions HPD0:HIO3: When the BSY is cleared to zero, DRQ is cleared to zero, REL is setto one, SERV is cleared to zero, and nIEN is set to one, then the host shall transition to theCheck status A state (see figure 7). The command is completed or the bus has been released. Ifthe command was completed, C/D is set to one and I/O is set to one. If an error is reported, thehost shall perform appropriate error recovery.

Transitions HPD0:HIO5: When the BSY is cleared to zero, DRQ is cleared to zero, REL is setto one, and SERV is set to one, then the host shall transition to the Write SERVICE state (seefigure 7). The command is completed or the bus has been released. If the command wascompleted, C/D is set to one and I/O is set to one. If an error is reported, the host shall performappropriate error recovery.

State HPD1 Send Packet: This state is entered when BSY is cleared to zero, DRQ is set to one,C/D is set to one, and I/O is cleared to zero.

When in this state, the host shall write a byte of the command packet to the Data register.

Transition HPD1:HPD1: When the Data register has been written and the writing of thecommand packet is not completed, then the host shall transition to the Send Packet state.

Transition HPD1:HPD0: When the Data register has been written and the writing of thecommand packet is completed, then the host shall transition to the Check Status state.

State HPD2 INTRQ Wait: This state is entered when the host is ready to transfer data or whenthe command has completed, and nIEN is cleared to zero.


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Transition HPD2:HPD0: When INTRQ is asserted, the host shall transition to the Check Statusstate.

State HPD3 Transfer Data: This state is entered when the BSY is cleared to zero, DRQ is set toone, and C/D is cleared to zero.

When in this state, the host shall read or write the device Data port to transfer data.

Transition HPD3:HPD0: When the data transfer is complete and nIEN is set to one, then thehost shall transition to the Check Status state.

Transition HPD3:HPD2: When the data transfer is complete and nIEN is cleared to zero, thenthe host shall transition to the INTRQ wait state.

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xx:DPD0

DPD0: PrepareBSY=1, DRQ=0, INTRQ=N

Command completed, nIEN=0,no released command

Device Idle SIDPD0:DI0

Command completed, nIEN=1, no released command

Device Idle SDPD0:DI1

DPD1: Recieve packetBSY=0, DRQ=1, INTRQ=N,C/D=1,I/O=0,REL=0

Data register written,command packettransfer not complete

DPD1:DPD1

Ready to recieve command packetDPD0:DPD1

Data register written, commandpacket transfer complete

DPD1:DPD0

DPD3: Ready INTRQBSY=0, DRQ=1, INTRQ=A,C/D=0, I/O=a

DPD0:DPD3

Ready to transfer DRQdata block, nIEN=0

Data transfercompleted orpaused

DPD2:DPD0


Ready to transfer DRQdata block, nIEN=1

DPD0:DPD2

DPD2: Transfer DataBSY=0, DRQ=1, INTRQ=N,C/D=0, I/O=a, DMARQ=A

DPD3:DPD2

Service returnxx:DPD0

Command completed or bus release with releaseinterrupt enabled, nIEN = 0, released command

Device Idle SIRDPD0:DIO0

Command completed or bus release, nIEN = 0, released commandDevice Idle SRDPD0:DIO1

Command completed or bus release, nIEN = 0,ready for serviceDevice Idle SSDPD0:DIO3

Command completed or bus release with releaseinterrupt enabled, nIEN = 0, ready for service

Device Idle SISDPD0:DIO2

SERVICE written, serviceinterrupt enabled

DPD3:DPD0

DPD0:DPD3

Service status read

Figure 21 −− Device PACKET DMA command protocol

State DPD0 Prepare: This state is entered when the device has a PACKET or SERVICEcommand written to the Command register, when the command packet has been received, whena DRQ data block has been transferred, or when the command has completed.

When in this state, device shall set BSY to one, clear DRQ to zero, and negate INTRQ. Non-data transfer commands are executed while in this state. For data transfer commands, thedevice shall check for errors, determine if the data transfer is complete, and if not, shall prepareto transfer the next DRQ data block.

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If the command is overlapped and the release interrupt is enabled, the device shall bus releaseas soon as the command packet has been received.

Transition DPD0:DPD1: When the device is ready to receive the command packet for acommand, the device shall transition to the Receive Packet state.

Transition DPD0:DPD2: When the device is ready to transfer a DRQ block of data for acommand and nIEN is set to one, then the device shall set the device internal interrupt pendingand transition to the Transfer Data state.

Transition DPD0a:DPD3: When the device is ready to transfer a DRQ block of data for acommand and nIEN is cleared to zero, then the device shall set the device internal interruptpending and transition to the Ready INTRQ state.

Transition DPD0b:DPD3: When the service interrupt is enabled and the device has SERVICEwritten to the Command register, then the device shall transition to the Ready INTRQ state.

Transition DPD0:DI0: When the command has completed or an error occurs that causes thecommand to abort, the device has no other command released, and nIEN is cleared to zero,then the device shall set the device internal interrupt pending, set appropriate error bits, andtransition to the Device Idle SI state (see figure 8).

Transition DPD0:DI1: When the command has completed or an error occurs that causes thecommand to abort, the device has no other command released, and nIEN is set to one, then thedevice shall set the device internal interrupt pending, set appropriate error bits, and transition tothe Device Idle S state (see figure 8).

Transition DPD0:DIO0: When the command has completed or an error occurs that causes thecommand to abort, the device has another command released but not ready for service, andnIEN is cleared to zero, then the device shall set the device internal interrupt pending, setappropriate error bits, and transition to the Device Idle SIR state (see figure 9). When the devicebus releases a command but has no command ready for service, and nIEN is cleared to zero,then the device shall set the device internal interrupt pending and transition to the Device IdleSIR state (see figure 9).

Transition DPD0:DIO1: When the command has completed or an error occurs that causes thecommand to abort, the device has another command released but not ready for service, andnIEN is set to one, then the device shall set the device internal interrupt pending, set appropriateerror bits, and transition to the Device Idle SR state (see figure 9). When the device bus releasesa command but has no command ready for service, and nIEN is set to one, then the device shallset the device internal interrupt pending and transition to the Device Idle SR state (see figure 9).

Transition DPD0:DIO2: When the command has completed or an error occurs that causes thecommand to abort, the device has another command ready for service, and nIEN is cleared tozero, then the device shall set the device internal interrupt pending, set appropriate error bits,and transition to the Device Idle SIS state (see figure 9). When the device bus releases acommand, has another command ready for service, and nIEN is cleared to zero, then the deviceshall set the device internal interrupt pending and transition to the Device Idle SIS state (seefigure 9).

Transition DPD0:DIO3: When the command has completed or an error occurs that causes thecommand to abort, the device has another command ready for service, and nIEN is set to one,then the device shall set the device internal interrupt pending, set appropriate error bits, andtransition to the Device Idle SS state (see figure 9). When the device bus releases a command,

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has another command ready for service, and nIEN is set to one, then the device shall set thedevice internal interrupt pending and transition to the Device Idle SS state (see figure 9).

State DPD1 Receive Packet: This state is entered when the device is ready to recieve thecommand packet.

When in this state, BSY is cleared to zero, DRQ is set to one, Intrq is negated, C/C is set to one,I/O is cleared to zero, and REL is cleared to zero. When in this state, the device Data register iswritten.

Transition DPD1:DPD1: When the Data register is written and the entire command packet hasnot been recieved, then the device shall transition to the Receive Packet state.

Transition DPD1:DPD0: When the Data register is written and the entire command packet hasbeen received, then the device shall transition to the Prepare state.

State DPD2 Data Transfer: This state is entered when the device is ready to transfer data.

When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is negated, C/Dis clearedto zero, I/O is set to one for PIO data out or cleared to zero for PIO data in, DMARQ is asserted,and is transferred as described in Multiword DMA timing or Ultra DMA protocol.

Transition DPD2:DPD0: When the data transfer has been completed or is paused, the deviceshall transition to the Prepare state.

State DPD3 Ready INTRQ: This state is entered when the device is ready to transfer a DRQblock of data and nIEN is cleared to zero. This state is entered to interrupt upon receipt of aSERVICE command when service interrupt is enabled.

When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is asserted, C/D is clearedto zero, and I/O is set to one for PIO data out or cleared to zero for PIO data in.

Transition DPD3:DPD0: When the Status register is read to respond to a service interrupt, thedevice shall transition to the Prepare state.

Transition DPD3:DPD2: When the Status register is read when the device is ready to transferdata, the device shall clear the device internal interrupt pending, negate INTRQ, and transition tothe Data Transfer state.

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9.10 READ/WRITE DMA QUEUED command protocol


− READ DMA QUEUED− WRITE DMA QUEUED

Execution of this class of command includes the transfer of one or more blocks of data from thedevice to the host or from the device to the host using DMA transfer. This command may busrelease before transferring data. The host shall initialize the DMA channel prior to transferringdata. Figure 22 and the following text describes the host states. Figure 23 and the following textdescribes the device states.

HDMAQ0: Check Status

BSY=0, DRQ=0, C/D=1, I/O=1, REL=0HDMAQ0:HI0 Host Idle

BSY = 1 & DRQ = 0,DMARQ negated

DMA QUEUED command writtenHI4:HDMAQ0

HDMAQ0:HDMAQ0

BSY = 0, DRQ = 1, C/D=0, I/O=a,DMARQ asserted

HDMAQ2:HDMAQ0

HDMAQ0:HDMAQ1

HDMAQ1:HDMAQ0

HDMAQ1: Transfer Data


All data forcommandtransferred,nIEN = 1

HDMAQ2: INTRQ wait

HDMAQ1:HDMAQ2

INTRQ asserted

BSY=0, DRQ=0, C/D=1, I/O=1 REL=1,SERV=0HDMAQ0:HIO0 INTRQ wait A

DMA QUEUED service returnHIO5:HDMAQ0HIO7:HDMAQ0

BSY=0, DRQ=0, C/D=0, I/O=0, REL=1, SERV=0HDMAQ0:HIO3 Check status A

BSY = 0, DRQ = 0, REL = 1, SERV=1HDMAQ0:HIO5 Write SERVICE

Figure 22 −− Host DMA QUEUED state

State HDMAQ0 Check Status: This state is entered when the host has written a READ/WRITEDMA QUEUED command to the device; when all data for the command has been transferredand nIEN is set to one; or when all data for the command has been transferred, nIEN is clearedzero, and INTRQ has been asserted. It is also enterd when the SERVICE command has beenwritten to continue execution of a bus released command.


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Transition HDMAQ0:HI0: When BSY is cleared to zero, DRQ is cleared to zero, C/D is set toone, I/O is set to one, and REL is cleared to zero, then the host shall transition to the Host Idlestate (see figure 6). If an error is reported, the host shall perform appropriate error recovery.

Transition HDMAQ0:HIO0: When BSY is cleared to zero, DRQ is cleared to zero, C/D is set toone, I/O is set to one, REL is set to one, and SERV is cleared to zero, then the host shalltransition to the INTRQ wait A state (see figure 7). If an error is reported, the host shall performappropriate error recovery.

Transition HDMAQ0:HIO3: When BSY is cleared to zero, DRQ is cleared to zero, C/D iscleared to zero, I/O is cleared to zero, REL is set to one, and SERV is cleared to zero, then thehost shall transition to the Check status A state (see figure 7).

Transition HDMAQ0:HIO5: When BSY is cleared to zero, DRQ is cleared to zero, REL is set toone, and SERV is set to one, then the host shall transition to the Write SERVICE state (seefigure 7). If C/D is set to one and I/O is set to one, a command has completed, and if, an error isreported, the host shall perform appropriate error recovery.

Transition HDMAQ0:HDMAQ0: When BSY is set to one, DRQ is cleared to zero, and DMARQis negated, the host shall transition to the Check Status state.

Transition HDMAQ0:HDMAQ1: When BSY is cleared to zero, DRQ is set to one, and DMARQis asserted; then the host shall transition to the Transfer Data state.

State HDMAQ1 Transfer Data: This state is entered when BSY is cleared to zero, DRQ is set toone, and DMARQ is asserted. The host shall have initialized the DMA channel prior to enteringthis state.

When in this state, the host shall perform the data transfer as described in the Multiword DMAtiming or the Ultra DMA protocol.

Transition HDMAQ1:HDMAQ2: When the host has transferred all data for the command andnIEN is cleared to zero, the host shall transition to the INTRQ Wait state.

Transition HDMAQ1:HDMAQ0: When the host has transferred all data for the command andnIEN is set to one, the host shall transition to the Check Status state.

State HDMAQ2 INTRQ Wait: This state is entered when the host has completed the transfer ofall data for the command and nIEN is cleared to zero.


Transition HDMAQ2:HDMAQ0: When INTRQ is asserted, the host shall transition to the CheckStatus state.

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DMA QUEUEDcommand written

xx:DDMAQ0

DDMAQ0: PrepareBSY=1, DRQ=0, INTRQ=N

Data transfer complete

DDMAQ1:DDMAQ0

Service returnxx:DDMAQ0

Command complete, nIEN=0, no command released

Device Idle SIDDMAQ0:DI0

Command complete, nIEN=1, no command releasedDevice Idle SDDMAQ0:DI1

Command complete, nIEN=0, released command

Device Idle SIRDDMAQ0:DIO0

Command complete, nIEN=1, released commandDevice Idle SRDDMAQ0a:DIO1

Command completed, nIEN=1, ready for serviceDevice Idle SSDDMAQ0a:DIO3

Command completed, nIEN=0, command releasedDevice Idle SISDDMAQ0:DIO2

Bus releasedDevice Idle SRDDMAQ0b:DIO1

Bus released, ready for serviceDevice Idle SSDDMAQ0b:DIO3

DDMAQ0:DDMAQ1

DDMAQ1: Transfer DataBSY=0, DRQ=1, INTRQ=N,C/D=0, I/O=a, DMARQ=A

Ready to transfer data

Figure 23 −− Device DMA QUEUED command protocol

State DDMAQ0 Prepare: This state is entered when the device has a READ/WRITE DMAQUEUED or SERVICE command is written to the Command register, when the data has beentransferred, or when the command has completed.

When in this state, device shall set BSY to one, clear DRQ to zero, and negate INTRQ.

Transition DDMAQ0:DDMAQ1: When the device is ready to transfer the data for a command,then the device shall transition to the Transfer Data state.

Transition DDMAQ0:DI0: When the command has completed or an error occurs that causes thecommand to abort, the device has no other command released, and nIEN is cleared to zero,then the device shall set the device internal interrupt pending, set appropriate error bits, andtransition to the Device Idle SI state (see figure 8).

Transition DDMAQ0:DI1: When the command has completed or an error occurs that causes thecommand to abort, the device has no other command released, and nIEN is set to one, then the

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device shall set the device internal interrupt pending, set appropriate error bits, and transition tothe Device Idle S state (see figure 8).

Transition DDMAQ0:DIO0: When the command has completed or an error occurs that causesthe command to abort, the device has another command released but not ready for service, andnIEN is cleared to zero, then the device shall set the device internal interrupt pending, setappropriate error bits, and transition to the Device Idle SIR state (see figure 9).

Transition DDMAQ0a:DIO1: When the command has completed or an error occurs that causesthe command to abort, the device has another command released but not ready for service, andnIEN is set to one, then the device shall set the device internal interrupt pending, set appropriateerror bits, and transition to the Device Idle SR state (see figure 9).

Transition DDMAQ0b:DIO1: When the device bus releases a command but has no commandready for service, and nIEN is set to one, then the device shall set the device internal interruptpending, and transition to the Device Idle SR state (see figure 9).

Transition DDMAQ0:DIO2: When the command has completed or an error occurs that causesthe command to abort, the device has another command ready for service, and nIEN is clearedto zero, then the device shall set the device internal interrupt pending, set appropriate error bits,and transition to the Device Idle SIS state (see figure 9).

Transition DDMAQa0:DIO3: When the command has completed or an error occurs that causesthe command to abort, the device has another command ready for service, and nIEN is set toone, then the device shall set the device internal interrupt pending, set appropriate error bits, andtransition to the Device Idle SS state (see figure 9).

Transition DDMAQb0:DIO3: When the device bus releases a command, has another commandready for service, and nIEN is set to one, then the device shall set the device internal interruptpending and transition to the Device Idle SS state (see figure 9).

State DDMAQ1 Data Transfer: This state is entered when the device is ready to transfer data.

When in this state, BSY is cleared to zero, DRQ is set to one, INTRQ is negated, C/D is clearedto zero, I/O is set to one for data out or cleared to zero for data in, DMARQ is asserted, and datais transferred as described in the Ultra DMA protocol or the Multiword DMA timing.

Transition DDMAQ1:DDMAQ0: When all data has been transferred, then the device shalltransition to the Prepare state.

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9.11 EXECUTE DEVICE DIAGNOSTIC command protocol


− EXECUTE DEVICE DIAGNOSTIC

If the host asserts RESET- before devices have completed executing their EXECUTE DEVICEDIAGNOSTIC protocol, then the devices shall start executing the power on or hardware resetprotocol from the beginning.

If the host sets SRST to one in the Device Control register before the devices have completedexecution of their EXECUTE DEVICE DIAGNOSTIC protocol, then the devices shall startexecuting their software reset protocol from the beginning.

Figure 24 and the text that follows decribes the EXECUTE DEVICE DIAGNOSTIC protocol forthe host. Figure 25 and the text that follows describes the EXECUTE DEVICE DIAGNOSTICprotocol for Device 0. Figure 26 and the text that follows describes the EXECUTE DEVICEDIAGNOSTIC protocol for Device 1.

HED0: Wait HED1: Check status

EXECUTE DEVICEDIAGNOSTICcommand written

HI4:HED0

Timeout completeHED0:HED1

BSY = 1HED1:HED1

BSY = 0HED2:HI0 Host idle

Figure 24 −− Host EXECUTE DEVICE DIAGNOSTIC protocol

State HED0 Wait: This state is entered when the host has written the EXECUTE DEVICEDIAGNOSTIC command to the devices.

The host shall remain in this state for at least 2 ms.

Transition HED0:HED1: When at least 2 ms has elapsed since the command was written, thehost shall transition to the Check status state.

State HED1 Check status: This state is entered when at least 2 ms since the command waswritten.

When in this state, the host shall read the Status register.

Transition HED1:HED1: When BSY is set to one, the host shall transition to the Check statusstate.

Transition HED1:HI0: When BSY is cleared to zero, the host shall transition to the Host idlestate (see figure 6).

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EXECUTE DEVICE DIAGNOSTICcommand writen

D0ED0: Release busPDIAG- =R, BSY=1

DI0:D0ED0DI1:D0ED0

Bus released, noDevice 1

Bus released, Device1 exists

D0ED0:D0ED3

D0ED0:D0ED1D0ED1: PDIAG waitPDIAG- =R, BSY=1

Wait complete

D0ED2: Sample PDIAGPDIAG- =R, BSY=1

Resample PDIAGD0ED2:D0ED2

D0ED1:D0ED2

Sample timeout

D0ED4: Set bit 7PDIAG- =R, BSY=1

D0ED3:D0ED5

D0ED2:D0ED3

PDIAG asserted

D0ED2:D0ED4

Bit 7 set

D0ED5: Set statusPDIAG- =R, BSY=1

D0ED4:D0ED5

D0ED3: Clear bit 7PDIAG- =R, BSY=1

Bit 7 cleared

Status setD0ED5:DI1 Device idle S

Figure 25 −− Device 0 EXECUTE DEVICE DIAGNOSTIC protocol

State D0ED0 Release bus: This state is entered when the EXECUTE DEVICE DIAGNOSTICcommand has been written to Device 0.

When in this state, the device shall release PDIAG-, INTRQ, IORDY, DMARQ, and DD(15:0)within 400 ns after entering this state. The device shall set BSY to one within 400 ns afterentering this state.

The device should begin performing its self-diagnostic testing.

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Transition D0ED0:D0ED1: When the bus has been released, BSY set to one, and the assertionof DASP- by Device 1 was detected during the most recent power on or hardware reset, then thedevice shall transition to the PDIAG wait state.

Transition D0ED0:D0ED3: When the bus has been released, BSY set to one, and the assertionof DASP- by Device 1 was not detected during the most recent power on or hardware reset, thenthe device shall transition to the Clear bit 7 state.

State D0ED1 PDIAG- wait: This state is entered when the bus has been released, BSY set toone, and Device 1 exists.

The device shall remain in this state until least 1 ms has elapsed since the command waswritten.

Transition D0ED1:D0ED2: When at least 1 ms has elapsed since the command was written, thedevice shall transition to the Sample PDIAG state.

State D0ED2 Sample PDIAG: This state is entered when at least 1 ms has elapsed since thecommand was written.


Transition D0ED2:D0ED3: When the sample indicates that PDIAG- is asserted, the device shalltransition to the Clear bit 7 state.

Transition D0ED2:D0ED2: When the sample indicates that PDIAG- is negated and less than 6 shave elapsed since the command was written, then the device shall transition to the SamplePDIAG state.

Transition D0ED2:D0ED4: When the sample indicates that DASP- is negated and 6 s haveelapsed since the command was written, then the device shall transition to the Set bit 7 state.

State D0ED3 Clear bit 7: This state is entered when PDIAG- has been asserted during thePDIAG sample state.


Transition D0ED3:D0ED5: When bit 7 in the Error register has been cleared to zero, the deviceshall transition to the Set status state.

State D0ED4 Set bit 7: This state is entered when the device has recognized that PDIAG- wasnot asserted during the PDIAG sample state.


Transition D0ED3:D0ED5: When bit 7 in the Error register has been set to one, the device shalltransitions to the Set status state.

State D0ED5 Set status: This state is entered when Bit 7 in the Error register has been set orcleared.

When in this state the device shall complete the self-diagnostic testing begun in the Release busstate if not already completed.

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Results of the self-diagnostic testing shall be placed in bits 6-0 of the Error register (see table10). The device shall set its signature values (see 9.1). The effect on the Features register isundefined.


If the device implements the PACKET command feature set, the device shall return its operatingmodes to their specified initial conditions. MODE SELECT conditions shall be restored to theirlast saved values if saved values have been established. MODE SELECT conditions for whichno values have been saved shall be returned to their default values. DRDY shall be cleared tozero.

Transition D0ED5:D0ED6: When hardware initialization and self-diagnostic testing is completedand the status has been set, then the device shall transition to the Device idle S state (see figure8).

D1ED0:D1ED1

D1ED1: Negate PDIAGPDIAG- =N, BSY=1

PDIAG negated

EXECUTEDEVICEDIAGNOSTICcommand written

D1ED0: Release busBSY=1

DI0:D1ED0DI1:D1ED0

Bus released

D1ED2:DI2Status set

D1ED2: Set statusPDIAG- =A, BSY=1

D1ED1:D1ED2

Device idle NS

Figure 26 −− Device 1 EXECUTE DEVICE DIAGNOSTIC command protocol

State D1ED0 Release bus: This state is entered when the EXECUTE DEVICE DIAGNOSTICcommand is written to Device 1.


The device shall begin performing its self-diagnostic testing.

Transition D1ED0:D1ED1: When the bus has been released and BSY set to one, then thedevice shall transition to the Negate PDIAG state.

State D1ED1 : This state is entered when the bus has been released and BSY set to one.

When in this state, the device shall negate PDIAG- within 1 ms of the receipt of the EXECUTEDEVICE DIAGNOSTIC command.

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Transition D1ED1:D1ED2: When PDIAG- has been negated, the device shall transition to theSet status state.

State D1ED2 Set status: This state is entered when the device has negated PDIAG-.

When in this state the device shall complete the hardware initialization and self-diagnostictesting begun in the Release bus state if not already completed. Results of the self-diagnostictesting shall be placed in the Error register (see table 10). If the device passed its self-diagnostics, the device shall assert PDIAG-.




Transition D1ED2:DI2: When hardware initialization and self-diagnostic testing is completedand the status has been set, then the device shall transition to the Device idle NS state (seefigure 8).

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9.12 DEVICE RESET command protocol


− DEVICE RESET

If the host asserts RESET- before the device has completed executing a DEVICE RESETcommand, then the device shall starts executing its hardware reset protocol from the begining. Ifthe host sets the SRST bit to one in the Device Control register before the device has completedexecuting a DEVICE RESET command, the device shall start executing its software resetprotocol for the beginning.

The host should not issue a DEVICE RESET command while a DEVICE RESET command is inrpogress. If the host issues a DEVICE RESET command while a DEVICE RESET command is inprogress, the results are indeterminant.

Figure 27 and text text that follows describes the DEVICE RESET command protocol for thehost. Figure 28 and the text that follows describes the DEVICE RESET command protocol forthe device.

HDR0: Wait HDR1: Check status

DEVICE RESETcommand written

HI4:HDR0

Timeout complete

HDR0:HDR1

BSY = 1

HDR1:HDR1

BSY = 0HDR2:HI0 Host idle

Figure 27 −− Host DEVICE RESET command protocol

State HDR0 Wait: This state is entered when the host has written the DEVICE RESET commandto the device.

The host shall remain in this state for at least 400 ns.

Transition HDR0:HDR1: When at least 400 ns has elapsed since the command was written, thehost shall transition to the Check status state.

State HDR1 Check status: This state is entered when at least 400 ns since the command waswritten.


Transition HDR1:HDR1: When BSY is set to one, the host shall transition to the Check statusstate.

Transition HDR1:HI0: When BSY is cleared to zero, the host shall transition to the Host idlestate (see figure 6).

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DEVICE RESETcommand written

DDR0: Release busBSY=1

DI0:DDR0DI1:DDR0

Bus released

DDR1:DI1Status set

DDR1: Set statusBSY=1

DDR1:DDR2 Device idle S

Figure 28 −− Device DEVICE RESET command protocol

State DDR0 Release bus: This state is entered when the DEVICE RESET command is written.


Transition DDR0:DDR1: When the bus has been released and BSY set to one, the device shalltransition to the Set status state.

State DDR1 Set status: This state is entered when the device has released the bus and set BSYto one.

When in this state the device should stop execution of any uncompleted command. The deviceshould end background activity (e.g., immediate commands, see MMC and MMC-2).

The device should not revert to its default condition. If the device reverts to its default condition,the device shall report a Unit Attention to a subsequent PACKET command. MODE SELECTconditions shall not be altered.


The device shall clear bit 7 in the ERROR register to zero. The device shall clear bits 6, 5, 4, 3,2, and 0 in the Status register to zero.

Transition DDR1:DI1: When the status has been set, the device shall transition to the Deviceidle state (see figure 8).

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