state of the union - risc-v · state of the union krste asanovic uc berkeley, risc-v foundation,...
TRANSCRIPT
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StateoftheUnionKrsteAsanovic
UCBerkeley,RISC-VFoundation,&SiFive [email protected]
7th RISC-VWorkshopWesternDigital,Milpitas,CA
November28,2017
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WhatisRISC-V?§ Ahigh-quality,license-free,royalty-freeRISCISAspecificationoriginallyfromUCBerkeley
§ Standardmaintainedbynon-profitRISC-VFoundation§ Suitableforalltypesofcomputingsystem,microcontrollerstosupercomputers
§ Numerousproprietaryandopen-sourcecores§ Experiencingrapiduptakeinindustryandacademia§ Supportedbygrowingsharedsoftwareecosystem§ Aworkinprogress…
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What’sDifferentaboutRISC-V?§ Simple
- FarsmallerthanothercommercialISAs§ Clean-slatedesign
- ClearseparationbetweenuserandprivilegedISA- Avoidsµarchitectureortechnology-dependentfeatures
§ Amodular ISAdesignedforextensibility/specialization- SmallstandardbaseISA,withmultiplestandardextensions- Sparseandvariable-lengthinstructionencodingforvastopcode space
§ Stable- Baseandstandardextensionsarefrozen- Additionsviaoptionalextensions,notnewversions
§ Communitydesigned- Developedwithleadingindustry/academicexpertsandsoftwaredevelopers
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RISC-VTimeline
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RISC-VISAprojectbegins
Youarehere
UserISAv1.0,Raven-1tapeout (28nm),RVCMSthesis
1st Rockettapeout,EOS14,45nm
PrivilegedArch,v1.7,RVCv1.7
UserISAv2.0IMAFDHotChips2014
FirstLinux 1stWorksho
p
RISC-VFoundationIncorporated
PrivilegedArch,v1.10
1stCo
mmercialSoC
CommercialSoftcores
7thWorksho
p
RV32E,RVC1.9
Berkeley World
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ModestRISC-VProjectGoal
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Becometheindustry-standardISAforallcomputingdevices
So,how’sitgoing?
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IndustryAdoptionStatus§ LargecompaniesadoptingRISC-VfordeeplyembeddedcontrollersintheirSoCs (“minioncores”)-NVIDIAarepublicwiththis,othersinprogressprivately- Replaceshome-grownandcommercialcores
§ CTOsacrossentirevaluechainofICsuppliers,systemproviders,serviceproviders,areawareandimagining/evaluatingstrategiestoleverageRISC-V
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Replacing2nd-tierISAs§ Smallerproprietary-ISAsoft-coreIPcompaniesswitchingtoRISC-Vstandardtoaccesslargermarket:- Andes- Codasip- Cortus- otherstoannounce
Ifyou’reasoftcore IPprovider,youshouldhaveaRISC-Vproductindevelopment
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GovernmentAdoption§ IndiahasadoptedRISC-VasnationalISA§ USDARPAmandatedRISC-Vinrecentsecuritycallforproposals
§ IsraelInnovationAuthoritycreatingGenPro platformaroundRISC-V
§ Othercountriesatvariousstagesofinvestigation
Ifyourcountrywishestocontrolsecurityofitsowninformationinfrastructure,andfurtheritsown
domesticsemiconductorindustry,sponsorRISC-V8
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Startups§ ManystartupschoosingRISC-Vfornewproducts§ Mostarestealthysowillnotbevisibleforatleastanotheryear
Wehaven’thadtotellstartupsaboutRISC-V;theyfindoutprettyquicklywhenshoppingforprocessorIP
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CommercialEcosystemProviders§ Athemeatthisworkshopismainstreamcommercialecosystemsupport- ExpressLogic,Imperas,Lauterbach,Micrium,Segger,UltraSOC,…
Demandisdrivingsupplyincommercialecosystem
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RISC-VinAcademicResearch§ BecomingstandardISAforacademicresearch- Celerity>500RISC-VcoreSoC in16nmFinFET- FireSim modeling1,024quad-coreRISC-Vserversincloud
§ Recent“1stWorkshoponComputerArchitectureResearchusingRISC-V”(CARRV)at50thMICROinBostonwaslargestworkshop(standingroomonly)–evenbiggerthanmachinelearningtutorial
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RISC-VinEducation
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Booksavailablenow!
AvailableDecember!
RISC-Vspreadingquicklythroughoutcurriculaoftopschools
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Research
EducationIndustry
Openecosystemiskeytokeepingthevirtuouscyclegoing
RISC-V:CompletingtheInnovationCycle
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Foundation:100+Members
RISC-VFoundation
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Q3 2015 Q4 2015 Q1 2016 Q2 2016 Q3 2016 Q4 2016 Q1 2017 Q2 2017 Q3 2017 Q4 2017
RISC-V Foundation Growth HistoryAugust 2015 to November 2017
Platinum Gold Silver Auditor Individual15
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MarketingCommittee§ HiredRacepoint GlobalasFoundationmarketingfirm§ Messaging&MarketingKitreleased§ SocialMediaprogramactive- RegularTwitter&LinkedInupdates
§ MultipleRISC-Vevents(outsidetheFoundation)- CARRV,SoCConf Irvine,EEWorld webinar
§ Websiterefresh– RISC-Vnewsaggregator§ 7th Workshophas15editors/analystsinattendance
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UpcomingEvents§ RISC-VTokyo(Dec18th,2017)§ EmbeddedWorld- HaveRISC-VboothanddaylongRISC-Vseriesoftalks
§ 8th RISC-VworkshopMay2018inBarcelona-Otherregionaleventsbeingconsidered
§ DACJune2018§ HotChips August2018§ LinleyProcessorConferenceOctober2018§ Moretocome…
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RISC-VTechnicalRoadmapfor2017§ PrimarygoalsweretoformallystandardizebaseISA,memorymodel,debug,andstabilizeprivilegedarchitectureforUnixportsandtapeouts
§ Severalcorners/holesofbaseISAfixed,butnotquiteratifiedduetospecversusprofilesclarifications-Noplanstochangeanyinstructionspecificationsversus2.0
§ Unixplatformstableasofpriv 1.10-Onlybackward-compatiblechangesthereafter
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ISASpecificationsandProfiles§ OriginalISAspecsmixedinstructionspecificationswithplatformmandates- butdifficulttoagreegivenwiderangeofplatforms(4KiBmicrocontrollerversus1TiBUnixserver)
§ Nowseparatinginstructionsetspecifications fromplatformprofiles-Maximizereuseofinstructionsetspecificationsfordifferentusecases
- Constrainprofilesmoretightlytosimplifysoftwarecompatibility
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Expandednamingofinstructionsets§ Single-letternameswillrunoutsomeday§ Needfiner-grainnamingofinstructionsetstodescribeprofiles:- someCinstructionsdependonForDbeingpresent- howtoreportmultiplynotdivideimplemented?- needtospecifypotentiallydozensofcryptoextensions
§ UseZxxxx tonamestandardinstructionextensions(Xyyy usedfornon-standardinstructions)
§ Existingsingle-letternamesretainmeaning§ Inactivediscussiononisa-dev mailinglist
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ProfilesforSoftwareCompatibility§ SoftwareABI/SBIdefinesaprofile
- Whatharts,registers,instructions,memoryareavailable- Howprocess/OSisstarted/terminated- HowI/Ohappens- ForUnix,ABI/SBIassumesIMAFDC=GCinstructions
§ NeedprofilesforM-mode-onlymicrocontrollers- ForportablelibrariesinM-mode
§ andprofilesforMU-modemicrocontrollers- ForeachRTOSusingM&Umodes
§ andforbootingMSUplatforms§ Instructionspecsreusedinalltheseprofiles§ AimtohavefirstreadyinQ12018
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MemoryModel§ OriginalmodelwastooweakforC11andalsounderspecified
§ Amazingworkbymanyexpertsovercourseofyear§ Wehavearesolution:- RVWMOisRISC-VbaseISAmemorymodel,weaklyordered- detailedformalspecs,bothaxiomaticandoperational!- mappingfromC11tobaseISAonly,andwithAextension
- alsodefinedRVTSOasoptionalextensionprovidingstrongTSOmemorymodel(RVTSOstrictsubsetofRVWMO)
- seeDanielLustig’s talklaterthismorning
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ABIandCompilers§ CallingconventionandABIhasbeenstabilizedanddocumented
§ GCCandbinutils havebeenupstreamed andreleasedinGCC7.1(SiFive,Andes)
§ LLVMupstreaminprogress(lowRISC,Andes)
§ Othercompilers/languages:CompCert,Go,Rust,OCaml,Jikes JVM,OpenJDK (notJITyet),Forth,Pascal,…
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UnixPlatform§ PrivilegedArchitecture1.10releasedatlastworkshop§ Intentisforfutureadditionstobebackwards-compatiblewith1.10
§ Linuxportacceptedupstreamfor4.15release!§ FreeBSDmainlinesince11.0§ Hypervisorspecreleased- DesignedtosupportrecursivevirtualizationusingenhancedSmode
§ SeeAndrewWaterman’stalknext
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OtherOSPorts§ ManyotherOSportsinprogressorcompleted- FreeRTOS- ZephyrOS- ApacheMyNewt- RIOT- seL4- uC/OS- LiteOS- RTEMS- ThreadX-…
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Run-HaltDebug§ Successfulcollaborationbetweenmanyorganizationshasresultedinastableversionawaitingratification
§ Providesanabstractinterfacetodebugsystemtosupportalternativeimplementationstyles
§ Beingtargetedbycommercialecosystempartners
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Summaryof2017TechnicalRoadmap§ Allplannedmajortechnicaldecisionssettled§ Somemoreworkonratificationprocessneeded
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TechnicalRoadmapGoalsfor2018§ CompleteratificationofbaseISAandfirstprofiles- IMADFC,debugspecifications-UnixABI/SBIprofiles-M,MU,andMSU-modeplatformprofiles
§ Basevectorextensionsproposedandratified- ValidatewithcompilersupportinLLVM,gcc
§ Hypervisorimplemented,specratified- KVMprimary,BeehiveandXen secondary
§ Formalspeccompletedandreleased
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VectorExtensions§ Reconfigurable,vector-length-agnostic,mixed-precision,vectorunitthatreplacesotherISAs’packed-SIMDextensions
§ Idealformachinelearning,DSP,graphics,supercomputing,…§ Considerablemovementondesign,gettingsimpler§ Supportforscalar,1Dvector,and2Dmatrix“shapes”ofvarioustypes(floating,int,8b,16b,32b,..,512b)
§ Cryptoextensionbuildsonwidescalarbitvectors§ “BestVectorISAEver”™§ TalktomorrowbyRogerEspasa
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Security§ ReallytwoseparableeffortsinFoundation:
- Trustedexecutionenvironments(TEE)- Cryptographicinstructionextensions
§ MuchotherworkincludingMITSanctum(enclaves),lowRISC(taggedmemory),CHERI(capabilities),Dover(acceleratedmetadatarules),secureboot(Microsemi,Rambus),…
§ RISC-Visdominatingsecurityresearch§ Everyoneagreessecurityisreallyimportant§ Noindustryagreementonrightsolutionforeverything§ Workinprogress
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Interrupts§ Sofar,wehavefastlocalinterrupts(per-hart)andglobalplatform-levelinterrupts(PLIC)
§ Requestsfrom:§ High-endsystems(manycores,complexdevices),wouldlikeper-hartmessage-signaledinterrupts(MSI)-MSIschemeneedstobedevelopedalongsidehypervisor
§ Low-endembedded(slowcores,dumbdevices)wantpreemptivevectoredprioritizedinterrupts- Shouldnotdisturbexistingschemes
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ImprovingEmbeddedCompression§ Cextensionwasdesignedforgeneral-purposecomputing,withUnixbinaries
§ Seeingsomenon-competitiveRISC-Vcodesizeonpureembeddedworkloads
§ Likelyduetobyte,halfword memoryaccess?-moreresearchneeded
§ ConsideringalternativeCforRV32Esystems?
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JExtension§ Newtaskgroupinitiatedtoexploresupportfordynamicallytranslatedlanguages(JVM,Javascript,etc.)
§ Handlingintegeroverflow?§ Garbagecollection?§ Instructioncachemanagement?
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RISC-VTechnicalPrioritiesfor2018Priorities:§ RatifyingbaseISAandprofiles,withcompliancesuites§ Hypervisorimplementations§ Basevectorspecandimplementations§ Trustedexecutionspecs,cryptosupport§ FormalmodelforbaseISAOthers:§ Message-signaledinterrupts§ Pre-emptivevectoredinterrupts§ Improvedcompressionforembedded§ Tracingsupport§ Jextension 34
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Summary§ CurrentRISC-VecosystemusableforcommercialembeddeddevelopmentandsimplerUnixuses-Multiplesoftcore providers,ecosystemtoolpartners
§ Veryrapiddevelopmentandadoption- Bytimeyoudecidetodoproject,supportwillbethere
§ Manysiliconprojectsinpipeline,butstillnoUnix-capableRISC-VSoC forsale
§ Joincommunityandhelppushalong!
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Questions?
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