static time analysis

8/3/2019 Static Time Analysis

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Biswanath DashAshutosh Mohanty


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Setup and hold concepts

Skew and its effects on setup and hold

Static timing analysis Dynamic simulation vs STA

Tools for STA (Prime time/ Gold time)

How prime time works Prime time commands


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Setup and Hold time

Setup timeis defined as theminimum amount of timeBEFOREthe clocks active edge

by which the data must be stable

for it to be latched correctly

Hold timeis defined as theminimum amount of timeAFTER

the clocks active edge during

which the data must be stable


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Flop to Flop Path


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Hold Evaluation


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Clock Skew

If a clock edge does not arrive at different flip-flops at exactlythe same time, then the clock is said to be skewedbetween theseflip-flops.

clock skew= difference between the times of arrival of clock at

the flip-flops Clock skewis due to different delays on different paths from

the clock generator to the various flip-flops.

Different length wires (wires have delay)

Gates (buffers) on the paths Flip-Flops that clock on different edges (need to invert clock for

some flip-flops)

Gating the clock to control loading of registers (a very bad idea)


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Effect of Skew on Setup


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Effect of Skew on Hold


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Summary of setup and hold

Setup always calculated from launch edge ofFF1 to capture edge of FF2.

Hold always calculated from launch of FF1 to

launch edge of FF2. If there is a setup violation on your silicon, you

can always slow down the clock and still the

circuit will work. If there is a hold violationyou are in

deeeeeeeeeeeeeeeep trouble!!!


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Static timing analysis

Static timing analysis (STA) is a method of

validating the timing performance of a design by

checking all possible paths for timing violations.

Static Timing Analysis is a method of

computing the expected timing of a digital

circuit without requiring simulation.


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Different STA Tools

Synopsys' PrimeTime/PrimeTime-SISTA including delay calculatorPrimeTime-SI is doing crosstalk analysis (CCSM)

Cadence's CTE(common timing engine)

SignalStorm is its delay calculator. (ECSM)Celtic is for noise analysis. (.cdb)

Incentia's TimeCraftDO NOT HAVE ITS OWN delay calculator.

Mentor graphics SST velocity Extreme DAsGold time

Magmas Quartz Timeof


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Dynamic Simulation vs STA

DS uses test patterns (vectors) as the i/p

to perform timing analysis on only those paths that are

activated according to patterns.

STA considers all rises and falls in blocks and traces allpaths thus allowing verification with a higher degree of

accuracy.

DS also checks logical functionality of the circuit. STA does not check the logical functionality.

STA is faster than DS.


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Prime Time/Gold Time

Input file formats

.library format (timing information of a ckt andprimitive delay information)

.netlist format

.delay format (R-C parasitic)


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Prime time top level description


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How Prime time works ???

Breaking the design into a set ofTiming paths

Delay calculation

- cell delay- net delay

Constraint checking

-setup and hold constraint-recovery/removal constraints

-data-to-data constraints

-clock-gating setup/hold constraints

-minimum pulse width for clock signals


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Prime Time Commands

Report_timing :

Provides general or more information about the

timing of the whole design, a group of paths or anindividual path.

Command options specify the types of paths reported,scope of design to search for specified paths and type

of information included in path reports


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Sl no Command Description

1 (Without option) Reports the single path with the worst setup timing slack in

each path group

2 -from and -to Paths contained in this option will be reported

3 -delay{max} Calculate the setup timesfor all paths

-delay{min} Each path is check for hold violations

4 -nets Tells GT to include the nets in the reports

-capacitance Lump capacitance of every net will be reported

-transition reports on all the input driving transition on the pin in the

path

5 -max_paths INT the total number(INT) of paths to be reported per group.(

default is one)

6 -nworst INT The number(INT) of enp points to be reported


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Sl no Command Description

7 -nosplit Prevent line splitting

8 -group GROUP_LIST Select paths in this group

9 -voltage Displays the pin supply voltage

10 -input_pins Displays only the input pins

11 -output_pins Displays the output pins


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Commands

report_clock_timing :

reports the skew,the difference between the longestand shortest clock insertion time, and allow the designto evaluate whether or not the clock tree must besynthesized.

A powerful commandsaves the designer fromnumerous timing closure spins

Eg:


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Commands

-report_bottleneck

Reports on the timing bottlenecks in the design

When design have a large number of timing violations ,

bottleneck analysis helps in finding places in design

most likely to benefit from design changes(gate resizing

or resynthsis under new constarints)


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Commands

report_delay_calculation

Generates a detailed report on how GT/PTcalculates delay for a specified cell or net timing

arc

Used for debugging problem


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static time analysis

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