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STATS AND CONFIGURATION
ZSim Tutorial – MICRO 2015
Core Models
Po-An Tsai
Outline2
Outline
ZSim core simulation techniques
2
Outline
ZSim core simulation techniques
ZSim core structure
Simple IPC 1 core
Timing core
OOO core
2
Core
I1D I1I
Outline
ZSim core simulation techniques
ZSim core structure
Simple IPC 1 core
Timing core
OOO core
Coding examples with demo
Branch predictor
Westmere to Silvermont
2
Core
I1D I1I
Core Simulation Techniques3
Core Simulation Techniques
ZSim simulates the system using Pin
Leverages dynamic binary translation
3
Core Simulation Techniques
ZSim simulates the system using Pin
Leverages dynamic binary translation
ZSim mainly uses 4 types of analysis routine
Basic block
Load and Store
Branch
to cover the simulated program
3
Core Simulation Technique4
Core Simulation Technique
A basic block (BBL) from Pin
4
Core Simulation Technique
A basic block (BBL) from Pin
4
mov (%rbp),%rcx
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
Core Simulation Technique
A basic block (BBL) from Pin
mov (%rbp),%rcx
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
5
Core Simulation Technique
A basic block (BBL) from Pin
1. Simulate core activities with a BBL descriptor that
contains most of the static information
mov (%rbp),%rcx
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
5
Core Simulation Technique
A basic block (BBL) from Pin
1. Simulate core activities with a BBL descriptor that
contains most of the static information
mov (%rbp),%rcx
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
mov (%rbp),%rcx
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
5
Core Simulation Technique
A basic block (BBL) from Pin
1. Simulate core activities with a BBL descriptor that
contains most of the static information
mov (%rbp),%rcx
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
mov (%rbp),%rcx
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
5
Decode BBL into
BBL descriptor
Core Simulation Technique
A basic block (BBL) from Pin
1. Simulate core activities with a BBL descriptor that
contains most of the static information
mov (%rbp),%rcx
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
mov (%rbp),%rcx
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
BblDescriptor:
numInstructions = 4
numBytes = 4
uop[]
5
Decode BBL into
BBL descriptor
Core Simulation Technique
A basic block (BBL) from Pin
1. Simulate core activities with a BBL descriptor that
contains most of the static information
mov (%rbp),%rcx
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
mov (%rbp),%rcx
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
BblDescriptor:
numInstructions = 4
numBytes = 4
uop[]
5
Decode BBL into
BBL descriptorBasicBlock(BblDescriptor)
Core Simulation Technique6
Decode x86 instructions into uops
With different latencies, src/dst pair, function unit ports
Core Simulation Technique7
Core Simulation Technique
2. Simulate memory system operations with addresses
7
Core Simulation Technique
2. Simulate memory system operations with addresses
mov (%rbp),%rcx
add %rax,%rbx
mov %rdx,(%rbp)
BasicBlock(BblDescriptor)
ja 40530a
7
Core Simulation Technique
2. Simulate memory system operations with addresses
mov (%rbp),%rcx
add %rax,%rbx
mov %rdx,(%rbp)
BasicBlock(BblDescriptor)
ja 40530a
7
Load(%rbp)
Store(%rbp)
Core Simulation Technique
2. Simulate memory system operations with addresses
mov (%rbp),%rcx
add %rax,%rbx
mov %rdx,(%rbp)
BasicBlock(BblDescriptor)
ja 40530a
Load(Address addr) {
L1D->load(addr);
}
Store(Address addr) {
L1D->Store(addr);
}
7
Load(%rbp)
Store(%rbp)
Core Simulation Technique8
Core Simulation Technique
Instruction-driven core activity (basic block) simulation
Simulates multiple stages for single instruction at once
Each stage maintains a separate clock
8
Core Simulation Technique
Instruction-driven core activity (basic block) simulation
Simulates multiple stages for single instruction at once
Each stage maintains a separate clock
BasicBlock(BblDescriptor) {
foreach uop {
simulateFetch(uop);
simulateDecode(uop);
simulateIssue(uop);
simulateExecute(uop);
simulateCommit(uop);
}
}
8
Core Simulation Technique
Instruction-driven core activity (basic block) simulation
Simulates multiple stages for single instruction at once
Each stage maintains a separate clock
BasicBlock(BblDescriptor) {
foreach uop {
simulateFetch(uop);
simulateDecode(uop);
simulateIssue(uop);
simulateExecute(uop);
simulateCommit(uop);
}
}
simulateIssue(uop) {
addUopToRob(curRobCycle, uop);
if(rob.isFull()){
nextRobAvailCycle = rob.advance();
}
}
8
Core Simulation Technique9
Event-driven uncore activity simulation
Core Simulation Technique9
Event-driven uncore activity simulation
Request
from core
Core Simulation Technique9
Event-driven uncore activity simulation
Cache
Tag Acc
@50
Request
from core
Core Simulation Technique9
Event-driven uncore activity simulation
Cache
Tag Acc
@50
Cache
Miss
WB
@60
Request
from core
Core Simulation Technique9
Event-driven uncore activity simulation
Cache
Tag Acc
@50
Cache
Miss
WB
@60
Mem
Data
Read
@60
Request
from core
Core Simulation Technique9
Event-driven uncore activity simulation
Cache
Tag Acc
@50
Cache
Miss
WB
@60
Mem
Data
Read
@60
Cache
Data
Write
@160
Request
from core
Core Simulation Technique9
Event-driven uncore activity simulation
Cache
Tag Acc
@50
Cache
Miss
WB
@60
Mem
Data
Read
@60
Cache
Data
Write
@160
Request
from core
Response
to core
Core Simulation Technique9
Event-driven uncore activity simulation
Cache
Tag Acc
@50
Cache
Miss
WB
@60
Mem
Data
Read
@60
Cache
Data
Write
@160
Request
from core
Response
to core
@200Weave phase
General Core Structure10
General Core Structure
ZSim simulates a core with 4 functions using Pin’s APIs
BblFunc
LoadFunc
StoreFunc
BranchFunc
10
General Core Structure
ZSim simulates a core with 4 functions using Pin’s APIs
BblFunc
LoadFunc
StoreFunc
BranchFunc
Current supported core type
Simple IPC1 core
Timing core
OOO core (Westmere-like)
10
Simple IPC1 Core11
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
Simple IPC1 Core11
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
Load(%rbp)
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
Simple IPC1 Core11
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
Load(%rbp)
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
Current cycle = l1d->load(curCycle)
Simple IPC1 Core11
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
Load(%rbp)
add %rax,%rbx
mov %rdx,(%rbp)
Store(%rbp)
ja 40530a
Current cycle = l1d->load(curCycle)
Simple IPC1 Core11
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
Load(%rbp)
add %rax,%rbx
mov %rdx,(%rbp)
Store(%rbp)
ja 40530a
Current cycle = l1d->load(curCycle)
Current cycle = l1d->store(curCycle)
Simple IPC1 Core11
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
Load(%rbp)
add %rax,%rbx
mov %rdx,(%rbp)
Store(%rbp)
BasicBlock(BblDescriptor)
ja 40530a
Current cycle = l1d->load(curCycle)
Current cycle = l1d->store(curCycle)
Simple IPC1 Core11
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
Load(%rbp)
add %rax,%rbx
mov %rdx,(%rbp)
Store(%rbp)
BasicBlock(BblDescriptor)
ja 40530a
Current cycle = l1d->load(curCycle)
Current cycle = l1d->store(curCycle)
Current cycle += 4
Timing Core12
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
Timing Core12
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
Load(%rbp)
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
Timing Core12
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
Load(%rbp)
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
Current cycle = l1d->load(curCycle)
Timing Core12
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
Load(%rbp)
add %rax,%rbx
mov %rdx,(%rbp)
ja 40530a
Current cycle = l1d->load(curCycle)
Tag
Acc
Miss
Write
back
Mem
Data
Read
Data
Write
Request
from core
Response
to core
Timing Core12
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
Load(%rbp)
add %rax,%rbx
mov %rdx,(%rbp)
Store(%rbp)
ja 40530a
Current cycle = l1d->load(curCycle)
Tag
Acc
Miss
Write
back
Mem
Data
Read
Data
Write
Request
from core
Response
to core
Timing Core12
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
Load(%rbp)
add %rax,%rbx
mov %rdx,(%rbp)
Store(%rbp)
ja 40530a
Current cycle = l1d->load(curCycle)
Current cycle = l1d->store(curCycle)
Tag
Acc
Miss
Write
back
Mem
Data
Read
Data
Write
Request
from core
Response
to core
Timing Core12
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
Load(%rbp)
add %rax,%rbx
mov %rdx,(%rbp)
Store(%rbp)
ja 40530a
Current cycle = l1d->load(curCycle)
Current cycle = l1d->store(curCycle)
Tag
Acc
Miss
Write
back
Mem
Data
Read
Data
Write
Request
from core
Response
to core
Timing Core12
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
Load(%rbp)
add %rax,%rbx
mov %rdx,(%rbp)
Store(%rbp)
ja 40530a
Current cycle = l1d->load(curCycle)
Current cycle = l1d->store(curCycle)
Tag
Acc
Data
Write
Request
from core
Tag
Acc
Miss
Write
back
Mem
Data
Read
Data
Write
Request
from core
Response
to core
Timing Core12
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
Load(%rbp)
add %rax,%rbx
mov %rdx,(%rbp)
Store(%rbp)
BasicBlock(BblDescriptor)
ja 40530a
Current cycle = l1d->load(curCycle)
Current cycle = l1d->store(curCycle)
Tag
Acc
Data
Write
Request
from core
Tag
Acc
Miss
Write
back
Mem
Data
Read
Data
Write
Request
from core
Response
to core
Timing Core12
IPC1 Core
I1D I1I
Current cycle = 0
mov (%rbp),%rcx
Load(%rbp)
add %rax,%rbx
mov %rdx,(%rbp)
Store(%rbp)
BasicBlock(BblDescriptor)
ja 40530a
Current cycle = l1d->load(curCycle)
Current cycle = l1d->store(curCycle)
Current cycle += 4
Tag
Acc
Data
Write
Request
from core
Tag
Acc
Miss
Write
back
Mem
Data
Read
Data
Write
Request
from core
Response
to core
OOO Core - BBL13
Simulate all stages at once
Load A
Exec
Store A
Exec
Fetch
OOO Core - BBL13
Simulate all stages at once
Load A
Exec
Store A
Exec
Decode Issue OOO
Execute
Commit
Fetch
OOO Core - BBL14
Simulate all stages at once
Load A
Exec
Store A
Exec
Decode Issue OOO
Execute
Commit
Fetch
OOO Core - BBL15
Simulate all stages at once
Store A
Exec
Decode Issue OOO
Execute
Commit
Load AExec
Fetch
OOO Core - BBL15
Simulate all stages at once
Store A
Exec
Decode Issue OOO
Execute
Commit
Load AExec
Fetch
OOO Core - BBL15
Simulate all stages at once
Store A
Exec
Decode Issue OOO
Execute
Commit
Load AExec
Fetch
OOO Core - BBL15
Simulate all stages at once
Store A
Exec
Decode Issue OOO
Execute
Commit
Load AExec
Fetch
OOO Core - BBL15
Simulate all stages at once
Store A
Exec
Decode Issue OOO
Execute
Commit
Load AExec
Fetch
OOO Core - BBL15
Simulate all stages at once
Store A
Exec
Decode Issue OOO
Execute
Commit
Exec
Fetch
OOO Core - BBL15
Simulate all stages at once
Store A
Exec
Decode Issue OOO
Execute
Commit
Exec
Fetch
OOO Core - BBL15
Simulate all stages at once
Store A
Exec
Decode Issue OOO
Execute
Commit
Exec
Fetch
OOO Core - BBL15
Simulate all stages at once
Store A
Exec
Decode Issue OOO
Execute
Commit
Exec
Fetch
OOO Core - BBL15
Simulate all stages at once
Store A
Exec
Decode Issue OOO
Execute
Commit
Exec
Fetch
OOO Core - BBL15
Simulate all stages at once
Store A
Exec
Decode Issue OOO
Execute
Commit
Fetch
OOO Core - BBL16
Simulate all stages at once
Load A
Decode Issue OOO
Execute
Commit
Fetch
OOO Core - BBL17
Simulate all stages at once
Fetch
wrong ins
Miss prediction
Fetch
whole bbl
Ins Fetch
Load A
Adjust
Fetch clock
Decode Issue OOO
Execute
Commit
Fetch cycle
Fetch
OOO Core - BBL18
Simulate all stages at once
Fetch
wrong ins
Miss prediction
Fetch
whole bbl
Ins Fetch
Load A
Adjust
Fetch clock
Decode Issue OOO
Execute
Commit
uop Queue
Decode cycle
Adjust
Decode clock
Check next
available
cycle
Fetch
OOO Core - BBL19
Simulate all stages at once
Fetch
wrong ins
Miss prediction
Fetch
whole bbl
Ins Fetch
Load A
Adjust
Fetch clock
Decode Issue OOO
Execute
Commit
uop Queue
Dispatch cycle
Adjust
Decode clock
Check next
available
cycle
Check src
available
cycle
Reg Scoreboard
Issue width
RegFile width
Adjust
issue clock
Check next
avail cycle
Rob
Fetch
OOO Core - BBL20
Simulate all stages at once
Fetch
wrong ins
Miss prediction
Fetch
whole bbl
Ins Fetch
Load A
Adjust
Fetch clock
Decode Issue OOO
Execute
Commit
uop Queue
Ins Window
Commit cycle
Adjust
Decode clock
Check next
available
cycleSchedule
uop in the
next cycle
that needed
ports avail
Adjust
issue clock
LS Unit*
Issue
Load/Store
Check src
available
cycle
Reg Scoreboard
Issue width
RegFile width
Adjust
issue clock
Check next
avail cycle
Rob
*Only for load/store
Fetch
OOO Core - BBL21
Simulate all stages at once
Fetch
wrong ins
Miss prediction
Fetch
whole bbl
Ins Fetch
Load A
Adjust
Fetch clock
Decode Issue OOO
Execute
Commit
uop Queue
Adjust
Decode clock
Check next
available
cycle
Adjust
issue clock
Check src
available
cycle
Reg Scoreboard
Issue width
RegFile width
Adjust
issue clock
Check next
avail cycle
Rob
Set dst
available
cycle
Reg Scoreboard
Retire uop
considering
rob width
Rob
Adjust
retire clock
Ins Window
Schedule
uop in the
next cycle
that needed
ports avail
LS Unit*
Issue
Load/Store
OOO Core – Load/Store22
Simulate MLP
Load A
Load B
OOO Core – Load/Store22
Issue A
@ 30
Cache
Hit
@ 50
Dispatch
@ 40
Response
@ 70
Simulate MLP
Load A
Load B
OOO Core – Load/Store23
Issue A
@ 30
Cache
Hit
@ 50
Dispatch
@ 40
Response
@ 70
Issue B
@ 50
Cache
Miss
@ 70
Dispatch
@ 60
Response
@ 110
Mem
Read
@ 90
Mem
WB
@ 110
Cache
Write
@ 100
Simulate MLP
Load A
Load B
OOO Core – Load/Store23
Issue A
@ 30
Cache
Hit
@ 50
Dispatch
@ 40
Response
@ 70
Issue B
@ 50
Cache
Miss
@ 70
Dispatch
@ 60
Response
@ 110
Mem
Read
@ 90
Mem
WB
@ 110
Cache
Write
@ 100
Simulate MLP
Load A
Load B
In weave phase, request B
will not be delayed due to
contentions for A
Simulation Speed for Different Core Type
SPECCPU 2006 suite
24
Simulation Speed for Different Core Type
SPECCPU 2006 suite
24
~3X difference between
IPC1 and OOO-C in Hmean
Not Modeled Core Behaviors25
Not Modeled Core Behaviors
Wrong path execution
Hard to simulate for Pin
Okay to skip for Westmere
25
Not Modeled Core Behaviors
Wrong path execution
Hard to simulate for Pin
Okay to skip for Westmere
Fine-grained message-passing
Need significant changes
25
Not Modeled Core Behaviors
Wrong path execution
Hard to simulate for Pin
Okay to skip for Westmere
Fine-grained message-passing
Need significant changes
TLBs and SMT
Not supported yet
25
Coding Examples26
Coding Examples
Implement a branch predictor for OOO core
26
Coding Examples
Implement a branch predictor for OOO core
Change OOO core type
From Westmere to Silvermont
26
Implement Branch Predictors27
Implement Branch Predictors
Have a new branch predictor class
27
Implement Branch Predictors
Have a new branch predictor class
class GShareBranchPredictor {
27
Implement Branch Predictors
Have a new branch predictor class
class GShareBranchPredictor {
private:
bool lastSeen;
……
}
27
Implement Branch Predictors
Have a new branch predictor class
class GShareBranchPredictor {
private:
bool lastSeen;
……
}
Implement the predict method
27
Implement Branch Predictors
Have a new branch predictor class
class GShareBranchPredictor {
private:
bool lastSeen;
……
}
Implement the predict method
public:
// Predicts and updates; returns false if mispredicted
inline bool predict(Address branchPc, bool taken) {
27
Implement Branch Predictors
Have a new branch predictor class
class GShareBranchPredictor {
private:
bool lastSeen;
……
}
Implement the predict method
public:
// Predicts and updates; returns false if mispredicted
inline bool predict(Address branchPc, bool taken) {
bool prediction = (taken == lastSeen);
27
Implement Branch Predictors
Have a new branch predictor class
class GShareBranchPredictor {
private:
bool lastSeen;
……
}
Implement the predict method
public:
// Predicts and updates; returns false if mispredicted
inline bool predict(Address branchPc, bool taken) {
bool prediction = (taken == lastSeen);
lastSeen = taken;
27
Implement Branch Predictors
Have a new branch predictor class
class GShareBranchPredictor {
private:
bool lastSeen;
……
}
Implement the predict method
public:
// Predicts and updates; returns false if mispredicted
inline bool predict(Address branchPc, bool taken) {
bool prediction = (taken == lastSeen);
lastSeen = taken;
return prediction; // always predict taken
}
27
Implement Branch Predictors
Have a new branch predictor class
class GShareBranchPredictor {
private:
bool lastSeen;
……
}
Implement the predict method
public:
// Predicts and updates; returns false if mispredicted
inline bool predict(Address branchPc, bool taken) {
bool prediction = (taken == lastSeen);
lastSeen = taken;
return prediction; // always predict taken
}
Replace the branch predictor in ooo_core.h
27
Implement Branch Predictors
Have a new branch predictor class
class GShareBranchPredictor {
private:
bool lastSeen;
……
}
Implement the predict method
public:
// Predicts and updates; returns false if mispredicted
inline bool predict(Address branchPc, bool taken) {
bool prediction = (taken == lastSeen);
lastSeen = taken;
return prediction; // always predict taken
}
Replace the branch predictor in ooo_core.h
//BranchPredictorPAg<11, 18, 14> branchPred;
GSharePredictor branchPred;
27
Demo28
Different OOO Micro-architecture29
Different OOO Micro-architecture
The original zsim assumes Westmere OOO core, but what
if I want to simulate a Silvermont/Haswell OOO core?
29
Different OOO Micro-architecture
The original zsim assumes Westmere OOO core, but what
if I want to simulate a Silvermont/Haswell OOO core?
Step 1: obtain the important ooo core parameters
29
Different OOO Micro-architecture
The original zsim assumes Westmere OOO core, but what
if I want to simulate a Silvermont/Haswell OOO core?
Step 1: obtain the important ooo core parameters
Step 2: change the core parameters in ooo_core.h/cpp
29
Different OOO Micro-architecture
The original zsim assumes Westmere OOO core, but what
if I want to simulate a Silvermont/Haswell OOO core?
Step 1: obtain the important ooo core parameters
Step 2: change the core parameters in ooo_core.h/cpp
Step 3: verify it against real system
29
Obtain Important Core Parameters
[1] http://www.realworldtech.com/nehalem/
[2] http://www.realworldtech.com/silvermont/
Westmere[1] Silvermont[2]
Issue width 4 2
F/D/I/E stages 1/4/7/13 1/3/5/8
Fetch width 16B 8B
RF read width 3 2
ROB size 128 32
Ins window 1K * 36 1K * 16
Issue queue 28 8
30
Change OOO Core Parameters31
Change OOO Core Parameters
Change sizes of hardware structures in ooo_core.h
31
Change OOO Core Parameters
Change sizes of hardware structures in ooo_core.h
CycleQueue<28> uopQueue
-> <8>
ReorderBuffer<128, 4> rob
-> <32, 2>
31
Change OOO Core Parameters
Change sizes of hardware structures in ooo_core.h
CycleQueue<28> uopQueue
-> <8>
ReorderBuffer<128, 4> rob
-> <32, 2>
Change the ooo core parameter in ooo_core.cpp
31
Change OOO Core Parameters
Change sizes of hardware structures in ooo_core.h
CycleQueue<28> uopQueue
-> <8>
ReorderBuffer<128, 4> rob
-> <32, 2>
Change the ooo core parameter in ooo_core.cpp
#define FETCH_STAGE 1 -> 1
#define DECODE_STAGE 4 -> 3
#define ISSUE_STAGE 7 -> 5
#define DISPATCH_STAGE 13 -> 8
#define FETCH_BYTES_PER_CYCLE 16 -> 8
#define ISSUES_PER_CYCLE 4 -> 2
#define RF_READS_PER_CYCLE 3 -> 2
31
Demo32
Verify It Against Real System33
IPC traces for Westmere and Silvermont
Westmere (6% performance difference)
Silvermont (9% performance difference)
Summary34
Summary
ZSim uses instruction-driven simulation for core activities
and event-driven simulation for uncore activities
34
Summary
ZSim uses instruction-driven simulation for core activities and
event-driven simulation for uncore activities
ZSim currently supports 3 types of core
Simple IPC1 core (simple_core.h)
Timing core (timing_core.h)
Westmere-like OOO core (ooo_core.h)
34
Summary
ZSim uses instruction-driven simulation for core activities and
event-driven simulation for uncore activities
ZSim currently supports 3 types of core
Simple IPC1 core (simple_core.h)
Timing core (timing_core.h)
Westmere-like OOO core (ooo_core.h)
Extending zsim core model is straightforward
Modify 4 basic analysis routines
Substitute the hardware structure with your implementation
Change the parameters in OOO
34
Hacking Advice
As common Pin programming, functions in the core are
very frequently called in zsim
You should be aware of performance when coding
It’s the main reason why zsim statically allocates hardware
structures and set ooo parameters
35
Thank you!Any questions?
36
