status of integrated preamplifiers for gerda gerda meeting – mpi heidelberg, feb 20-22, 2006 f....
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Status of integrated preamplifiers for GERDA
Status of integrated preamplifiers for GERDA
GERDA meeting – MPI Heidelberg, Feb 20-22, 2006GERDA meeting – MPI Heidelberg, Feb 20-22, 2006
F. Zocca, A. Pullia, S.Riboldi, C. Cattadori
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Proposed circuit structure (from J. Gal*)Proposed circuit structure (from J. Gal*)
*J. Gal et al. “Realization of charge sensitive preamplifiers using current feedback operational amplifier”, Nucl. Instrum. And Meth., Vol. A366, pp. 145-147, 1995
RD CF
BF862
Cdet
detector
Vout
G
new output stage (low impedance &
swinging to negative-rail)
RF 2.5 V
-3.5 V VD
discrete components
ASI C (CMOS 0.8um 5V)
12 V
A = gm RD × G
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Test chipTest chip3.
3 m
m
3.3 mm
MOSFETs
resistors
MOSFETs
MOSFETs
MOSFETs
PREAMP 2pMOS + ext RF + int biasVmax = 550mV (50 Ohm)
PREAMP 1pMOS + ext RF + ext biasVmax = 550mV (50 Ohm)
PREAMP 1PREAMP 2
PREAMP 3pMOS + reset pMOS + shaper
PREAMP 3
PREAMP 4
PREAMP 4pMOS + ext RF + ext biasVmax = 2V (1 kOhm)HIGH VOLTAGE comp’s
TEST struct
TEST struct
CSP+OS simple CC=0pF
CSP+OS simple CC=0.2pF
CSP+OS simple CC=0.6pF
CSP+OS simple CC=1pF
CSP+OS simple CC=1.4pF
CSP+OS cplx CC=0pF
CSP+OS cplx CC=2pF
CSP+OS cplx CC=0.4pF
CSP+OS cplx CC=1.4pF
CSP+OS cplx CC=1pF
OPAMP OPAMP OPAMP OPAMP
CSP + OS simpleCSP with new rail-to-rail output stage. Various comp cap’s
CSP + OS cplxCSP with new rail-to-rail output stage. Various comp cap’s
Tested preamp
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Test chip with wire bondings Test chip with wire bondings in 68LCC packagein 68LCC package
Setup for cryogenic testSetup for cryogenic test
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The output stage must be able to drive a coax/twisted pair cable (or a 100 to 200 load) and must provide the largest negative voltage swing (hole signals)
Output stage & dynamic rangeOutput stage & dynamic range
At T=300°K, with a negative power supply VEE = - 3V, the circuit can drive a 10m coaxial cable of 50 still providing a negative voltage swing of ~ 2.5V
At T=77°K the negative swing reached is of ~ 2.4V
CF = ~ 0.15 pF, Ctest = 1 pF
Cdet = 15 pF
Energy sensitivity (in Ge) at the preamp output = ~ 370 mV/MeV (~185 mV/MeV if 50 terminated)
Input dynamic range = ~ 6.5 MeV
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Rise timeRise timeat T = 300 °K
driving a 50 coaxial cable of different
lengths
~ 13 ns with ~1m cable
~ 15 ns with ~10m cable
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Rise timeRise timeat T = 77 °K
driving a ~2m coaxial cable (50)
A fast rise time of ~ 8 ns to ~ 13 ns has been obtained but a little overshoot has still to be eliminated by a low-pass filter or by reducing the preamp bandwidth a little bit
7.8 ns with no BW limit
13 ns with BW limit (equivalent to Anti-Aliasing filter)
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Decay time constant Decay time constant ~ 200 s both at room temperature and in liquid nitrogen
T = 300 °K
T = 77 °K
~200s
~200s
CF = ~ 0.15 pF
RF = 1.2 G
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Shaping time
T=300°K
ENC (el. r.m.s.)
T=77 °KENC (el. r.m.s.)
0.5 s 178 325
1 s 148 252
2 s 126 191
3 s 118 166
6 s 110 128
10 s 111 112
Noise measurementsNoise measurementsCdet = 15 pF
At T =77 °K the substantial increase of the white series noise is mainly due to the decrease of the JFET tranconductance
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T = 300 °K T = 77 °K
Energy sensitivity
(CF = 0.15pF)~ 370 mV/MeV at preamp output
~ 185 mV/MeV after 50 termination
Negative output voltage swing
~ 2.5 V ~ 2.4 V
Input dynamic range ~ 6.7 MeV ~ 6.5 MeV
Rise time~ 13 ns with 1m coaxial cable
~ 15 ns with 10m coaxial cable
~ 13 ns with 2m coaxial cable (with little overshoot)
~ 15 ns with 10m coaxial cable (with little overshoot)
Loop gain ~ 500 > 500
Minimum ENC (el. r.m.s.) with
Cdet = 15pF110 el. at = 6s 112 el. at = 10s
Power required
~ 177 mW
(VFET = +12V ID = 14mA
VCC= +2.5V VEE = -3V)
~ 22 mW
(VFET = +4V ID = 3mA
VCC= +3V VEE = -3V)
Tested preamp specsTested preamp specs
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Future developmentsFuture developments
• Optimization of tested preamplifier
• Tests with different values of Cdet and with values of CF ranging from 0.2 to 1 pF
• Tests of more preamplifiers (with different values of compensation capacitance)
• Design and test of a miniaturized setup
• Tests with different cable types and lengths
Activity scheduleActivity schedule• March-June 2006: tests/optimization of existing chip. Design/realization of miniaturized PCB. Design of improved new chip.
• June-September 2006: realization of new chip / tests of old chip (continued)
• September-December 2006: tests of new chip