status of the csc track status of the csc track-finder-finderacosta/cms/tridas_may00.pdf · status...
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D. Acosta, University of Florida TriDAS Review May 2000 1
Status of the CSC Track-FinderStatus of the CSC TrackStatus of the CSC Track--FinderFinder
Darin Acosta
University of FloridaMay 2000
D. Acosta, University of Florida TriDAS Review May 2000 2
OutlineOutlineOutline
Overview of the CSC trigger systemSector ReceiverSector ProcessorMuon SorterCSC/DT Interface
D. Acosta, University of Florida TriDAS Review May 2000 3
Strip FE cards
Wire FE cards
Port Card
PC
Sector Receiver
Sector Processor
OPTICAL
SR SP
CSC Track-Finder
CSC Muon Sorter
Global µ Trigger
DTRPC
FE
FE
Global L1
2µ / chamber
3µ / port card
3µ / sector
4µ
4µ
4µ4µ
LCT
Strip LCT + Motherboard card
Wire LCT card
On chamber In peripheral crate
In counting
house
TMB
LCT
RPC Interface Module
RIM
CSC Muon Trigger SchemeCSC Muon Trigger SchemeCSC Muon Trigger Scheme
D. Acosta, University of Florida TriDAS Review May 2000 4
OPTICAL
SP
1 Muon Sorter
3µ / port card
3µ / sector
ME1
ME2-ME3
ME4
SR
DT TF
SP
From CSC Port Cards
MS
MB1
PC
From DT Track-Finder
24 Sector Receivers (+12 for ME4)
12 Sector Processors
To Global Muon Trigger
GMT
RPC
4µ
4µ
8µ
The CSC Track-FinderThe CSC TrackThe CSC Track --FinderFinder
12 sectors
(UCLA) (Florida) (Rice)
(Vienna)
(Vienna)
From DT Track-Finder
3.1.1.2 3.1.1.3,3.1.1.4
3.1.1.153.1.1.1WBS:
D. Acosta, University of Florida TriDAS Review May 2000 5
Sector Receiver FunctionalitySector Receiver FunctionalitySector Receiver Functionality
1. Receive 6 µ segments via 12 optical links from 2 Muon Port Cards• Require 3 Sector Receivers for one 60°
sector2. Synchronize the data3. Reformat the data into track segment
variables• LCT bit pattern → η, ϕ, ϕb, ...
4. Apply corrections for alignment5. Communicate to Sector Processor via
custom backplane (Channel Link)6. Fan out ME1/3 µ segments to DT Track-
Finder
} via LUTs
UC
LA
3.1.1.2
D. Acosta, University of Florida TriDAS Review May 2000 6
Sector Receiver LogicSector Receiver LogicSector Receiver Logic
UC
LA
JTAG interface
Controller FPGA
Front Panel
Optical Receiver
Optical Fiber from MPC
Deserializer
Optical Receiver
Optical Fiber from MPC
Deserializer
Front FPGA
LUTS
LUTS
Back FPGA
To Barrel
To Backplane
VME
Repeat for each Muon
3.1.1.2
D. Acosta, University of Florida TriDAS Review May 2000 7
Sector Receiver LUT SchemeSector Receiver LUT SchemeSector Receiver LUT Scheme
UC
LA
D. Acosta, University of Florida TriDAS Review May 2000 8
Sector ReceiverSector ReceiverSector Receiver
• Fell behind schedule after postdoc departure.
• Personnel added in December/January:• Robert Cousins, physicist, 50% time• Vladislav Sedov, electronics engineer, 90% time
(10% residual work on ALCT board)• Also using paid consultant for some FPGA work
(UCLA CS Ph.D. candidate)
• Schematics now well underway.
• Long-lead-time parts ordered.
• Layout planned by beginning of May.
• Plan to be ready for summer Track Finder test.
UC
LA
3.1.1.2
D. Acosta, University of Florida TriDAS Review May 2000 9
Sector Processor FunctionalitySector Processor FunctionalitySector Processor Functionality
1. Accumulate track segments for possibly more than one B.X.
2. Extrapolate in 3D from one station to another for all possible track segment combinations
3. Assemble tracks from extrapolation results4. Select best 3 tracks and cancel ghosts5. Assign track parameters: p T, ϕ, η, quality
New since last Review:
• Combined DT/CSC overlap region onto same boardas CSC-only region (add MB1–ME2 extrap.)
• Improved P T assignment technique
• Ghost-busting when 2 muons enter 1 CSC chamber (try all combinations)
1 2
1
2
Flor
ida
3.1.1.3, 3.1.1.4
D. Acosta, University of Florida TriDAS Review May 2000 10
To Front panel
EU1-2
EU1-3
EU2-3
EU2-4
EU3-4
EU MB1-2
TAU1
TAU2
TAU3
FSUBXA
FIFO MUX
AU
FromBackplane
Bunch Crossing Analyzer
Track Assembler Units
Final Selection Unit
Extrapolation Units
Assignment Unit
busbus
Sector Processor LogicSector Processor LogicSector Processor Logic
Flor
ida
3.1.1.3, 3.1.1.4
D. Acosta, University of Florida TriDAS Review May 2000 11
Extrapolation LogicExtrapolation LogicExtrapolation Logic
L U T η 1
L U T η 2
L U T ∆ η
SU B η A -η B
“ A N D ”
η (A 1)
A m b(A 1)
A m b(B 1)
“ O R ”
η (B 1)
L U T φ b
-
L U T φ b
+
“ A N D ” SU B φ A -φ B
φ (A 1) φ (B 1)
φ b (A 1)
φ b (B 1)
C M P ∆ φ -φ b
+
L U T φ b
+
L U T φ b
-
C M P ∆ φ -φ b
-
C M P ∆ φ -φ b
+
C M P ∆ φ -φ b
-
L U T ∆ φ h igh
L U T ∆ φ m ed
L U T ∆ φ lo w
C M P ∆ φ h igh
C M P ∆ φ m ed
C M P ∆ φ lo w
A B S ∆ φ
Q ual(A 1)
Q ual(B 1)
L U T E xtra p Q ual
Q η(A 1B 1) Q η(A 2B 1) Q η(A 3B 1)
Q extrap(A 1B 1)
η road finder
ϕ road finder
quality assignm ent un it
L U T ∆ φ
z
ϕ
η road finder
ϕ road finder
quality assignment unit
Flor
ida
D. Acosta, University of Florida TriDAS Review May 2000 12
Track Selection and PT Assignment
Track Selection and Track Selection and PPTT AssignmentAssignment
SUBφ1-φ2
SUBφ2-φ3
LUTφ
LUT η
MUXFIFO
MUX
φ1
φ2
φ3
Mode(From FSU)
φ
η
~2M x 8SRAMLUT
Rank (PT & Quality)
Sign
φ
η
I.D.Comparison
Unit
Track Rank Sorter
MUX
Cancellation Logic and Encoder
9 Track Assembler RAMs
“9 to 3” Sorter with ghost cancellation logic
New: 3-station sagitta measurement using FPGA preprocessing and RAM
(Improves P T resolution from 30% to 20%)
Flor
ida
D. Acosta, University of Florida TriDAS Review May 2000 13
SP Prototype LayoutSP Prototype LayoutSP Prototype Layout
Bunch Crossing Analyzer
Extrapolation Units
Track Assembler Units
Final Selection Unit
Assignment Units
VME/JTAG interface (developed separately)
XCV50BG256 XCV400BG560 XCV150BG352
XCV50BG256
SRAM
SRAM
Cus
tom
Cha
nnel
Link
bac
kpla
neS
tand
ard
VM
E
• Layoutcomplete
• 12 layers
• Tests setfor 6/1/00
Flor
ida
US CMS DOE/NSF Review: April 11-13, 2000 13
Prototype Crate LayoutPrototype Crate LayoutPrototype Crate Layout
One sector is half of Track-Finder crate
SPSRSR SR CCB
Six crates for entire system
Fully routed for summer tests
Flor
ida
Smaller prototype tested already
3.1.1.7
D. Acosta, University of Florida TriDAS Review May 2000 15
Pre-Prototype TestsPrePre--Prototype TestsPrototype Tests
Flor
ida
VME / JTAG interface for SR and SP:
Software & hardware for FPGA and SRAM downloading through VME works
Channel Link backplane and connector tests:
No errors found up to 58 MHz clock (400 MHz on backplane)
D. Acosta, University of Florida TriDAS Review May 2000 16
Muon Sorter FunctionalityMuon Sorter FunctionalityMuon Sorter Functionality
1. Receive 36 muons from 12 Sector Processors• 36 × 18 bits = 648 bits (& control bits)
2. Sort and rank the best 4 muons• Sort is based on 7 bits (5 bits for pT and 2 bits
for quality)3. Send the output to the Global Muon Trigger for
association with RPC and DT triggers• 4 × 22 bits = 88 bits
Ric
e
New since last Review:
• Reduction in muon count from 72 to 36 (inclusion of CSC/DT overlap in Sector Processor)allows sorting to be accomplished in one FPGA
3.1.1.15
D. Acosta, University of Florida TriDAS Review May 2000 17
FF SORTER 4 out of 18
153comparisonsin parallel
SORTER 4 out of 8
28comparisonsin parallel
FF
FF
FF
FF
FF
28
28
28
28
28
28
28
2814
28
7+6
ALTERA EP20K200EFC484-1
10 2 3 4“4 out of 36” SINGLE-CHIP SORTER BLOCK DIAGRAM AND TIMING
FF
FF
FF
28
28
28
28
28 28
7+6
LUT
ADR1
PAT1
LUT
LUT
LUT
ADR2
ADR3
ADR4
PAT2
PAT3
PAT4
SORTER 4 out of 18
153comparisonsin parallel
14
FF
FF
FF
FF
6
6
6
6
7
7
7
7 8
8
8
8
CLK
28
7+6
7+6
7+6
7+6
7+6
7+6
40MHz
6
6
6
6
VME INTERFACE FOR LUT READ/WRITE
28
FF- FLIP-FLOP, LUT - LOOK-UP TABLE RAM
Muon Sorter LogicMuon Sorter LogicMuon Sorter Logic Ric
e
3.1.1.15
D. Acosta, University of Florida TriDAS Review May 2000 18
VMEINTERFACE
VME J1CONNECTOR
SORTERPLD
CONNECTORTO CUSTOM BACKPLANE
252
56
9U * 400 MM BOARD
CCB INTERFACE
CONNECTORSTO GMT
CONNECTOR TORECEIVER BOARDS
GMT LVDSDRIVERS
Sorter Board Block DiagramSorter Board Block DiagramSorter Board Block Diagram Ric
e
3.1.1.15
D. Acosta, University of Florida TriDAS Review May 2000 19
CONNECTORSTO GMT
12 CONNECTORS TORECEIVER BOARDS
S R R R R
Muon Sorter Crate LayoutMuon Sorter Crate LayoutMuon Sorter Crate Layout Ric
e
3.1.1.15
D. Acosta, University of Florida TriDAS Review May 2000 20
CONNECTOR TO SP
CONNECTOR TO SP
Rx
PIPELINEPLD
10K130Eor
20K200E
Rx
CONNECTOR TOSORTER BOARD
CONNECTOR TO SP
RECEIVERS
Rx
21
2121
2760
60
6084
CLOCK
POWER
Sorter Receiver Board Block Diagram
Sorter Receiver Board Sorter Receiver Board Block DiagramBlock Diagram R
ice
3.1.1.15
D. Acosta, University of Florida TriDAS Review May 2000 21
Summer PlansSummer PlansSummer Plans
Crate test with prototype SR, SP, CCB (and TMB, MPC) scheduled for summer 2000
• Bench tests start June 1• Integration tests start July 1• Will test optical link connections and trigger algorithms
at 40 MHz, verify output and latency
All designs are proceeding well, and we should be able to make milestone
• Conceptual design, schematics, and some layouts already exist
Development of test software started
D. Acosta, University of Florida TriDAS Review May 2000 22
Separation of DT/CSC CoverageSeparation of DT/CSC CoverageSeparation of DT/CSC Coverage
• Hard boundary defined η=1.04
• Separate Track-Finders optimized for each system
• Information shared across boundary for maximum efficiency
• Tentative agreement reached on DT/CSC interface Feb’00
Slow simulation of CMS detector in GEANT 3.21
0
100
200
300
400
500
600
700
800
0 200 400 600 800 1000 1200Z (cm)
R (
cm)
η = 1.04
ME1/3
MB2/1
D. Acosta, University of Florida TriDAS Review May 2000 23
Advantages of ProposalAdvantages of ProposalAdvantages of Proposal
• Interconnections are cut in half when track segments from ME 2/2 and MB 2/2 are not shared(only ME 1/3 and MB2/1 are shared)
• The mapping of 60° CSC trigger sectors onto 30° DT ones is avoided (no ME 2/2)• But, ME1 station has 30° or 20° subsectors, so there
may still be a mapping problem
• The RPC data may be used by the GMT to settle any ghosting problem if a single muon is found by both Track-Finders
• φb and η do not need to be sent by the CSC Track-Finder for DT T-F extrapolations
D. Acosta, University of Florida TriDAS Review May 2000 24
Advantages ContinuedAdvantages ContinuedAdvantages Continued
• The DT Track-Finder may trigger on MB1-MB2 type tracks • These track segments and all those sent by
the CSC trigger are assumed to be in barrel region
• The CSC Track-Finder logic is considerably simplified with proposed boundary• Already assumed in present prototype
D. Acosta, University of Florida TriDAS Review May 2000 25
Issues with ProposalIssues with ProposalIssues with Proposal
Must demonstrate acceptable efficiency by simulation
CSC Sector Receiver must be designed to send only 2 track segments (out of 3) for the barrel-overlap region