Status of the digital

readout electronics

Mauro Raggi and F. Gonnella

LNF

Photon Veto WG

CERN 13/12/2011

OUTLINE

New lab, a new collaborator, a new paper!

The wiener crate LAV FEE

• Basic tests of the crates

• Reprogramming crate voltages

The status of the TELL1 readout system in Frascati

New LAV electronic lab at LNF

The lab is equipped with:A NIM and CAMAC cratesA commercial VME 6U Daq system (based on HPTDC)A custom LAV FEE 9U crate + 1TELL1 and 2 TDCb V5A LAV FEE 9U prototype board

Proceedings of twepp available on ArXiv

We have a new 2 year post doc collaborator: F. Gonnella

LAV readout chain

Each LAV FEE boardsGet 32 analog inputs and produce 64 LVDS outputsThe output is sent to the TDC using 2 custom SCSI2 HDCI cables

The LAV 9U FEE board

12

3

4

4

3

Operating voltage ±12V reduced to ±7.5V by onboard voltage regulators

Test of the NA62 FEE TEL62 crates

The LAV 9U crate

With respect to standard TELL1 crates 46A of a voltage in the range 7-16 has been added.

The current Wiener setting we have the voltage set to ±12V for the LAV line.

Being the only user of the line we are free to change the value in the range 7-16V.

The TELL1 into LAV crate BUGCrate Power supply

TELL1 J1 connector

TELL1 J1 TEL62 J1

Basics testsWe performed very basic set of tests on the FEE TEL62 crates.1) Mechanical test is ok2) Electrical test of power supply is ok for both the TELL1 and FEE boards3) Preliminary noise tests:

1) we checked that there is no noise transfer between TELL1 and the FEEA. Same level of noise in the FEE with or without TELL1 in the crateB. No additional noise when accessing the TELL1 using CCPC

connection2) We checked that the noise in the FEE depends on the crates power

supplyA. Increase the current load to the crate power supplyB. Try a new test with V = ±7.5 V to increase the drop on linear

regulators External power supply

Wiener crate power supply

1,7 ms

2mV

0.5ms

7mV

Hacking the LAV crateTo save power the LAV FEE can be operated at ±7V instead of the ±12V just removing the regulators and reprogramming the LAV crate to provide ±7V.

Reprogramming LAV crate by steps

Construct dongle

Connect to WINXP Pc with an RS232 port

Enable rom access

Download PC programUEP6000.exe

Restart Crate

Set new voltage and new defaults

using wiener program

Crate is protected against the use of non standard power supply voltage need to reprogram a ROM inside

the crate

First LAV readout cell!Connection of LAV FEE to TDC just like it will be at the experiment!

Doing the full readout is only adding more FEE and TDCb and routing cables

Cable routing studied has to start to validate cable length before final production

DAQ test is planned for January next year:Pulse 32 ch FEE inputs read them out with Tell1

TELL1 CCPC server installation A FC11 based pc has been setup as server for the TELL1

• Different from standard version with SL4 - SL5

• Few problems with setup of the CCPC due to DHCP settings sitting in different directory in FC11 wrt scientific linux

The CCPC now boots successfully

The TDSPY program is running on the CCPC

TDSPY scripts currently interacting well with the TELL1 FPGA and TDCb:

• FPGA status read and write are all OK

• TDCb Mezzanine on/off

• TDCb tested successfully

Clock provided successfully with AGILENT 81110A

• Clock frequency used 40.080 MHz

LAV firmware2 persons involved in preparing a firmware for the

LAV• Mauro Raggi (LNF)

• Francesco Gonnella (LNF, brand new postdoc)

A computer (dual core, XEON 3.1GHz, 2Gbyte RAM)

running WIN7 has been setup for firmware development

The last version of the TELL1 firmware has been setup, compiled, synthesized

The firmware (.pof file) has been uploaded to the TELL1 using the ROM

Run under Windows seven

• Still to install SVN in local PC. Only works from LXPLUS

Mentor GraphicsHDL Designer

All tools are installed:

Altera Quartus II v. 11

Software installed

DDR control

Data formatter and writer

Data extraction

Trigger handling

Trigger primitivegenerato

r

Core services & monitoring Inter-PP

communication

TD

Cb

com

m

TD

Cb

DDR II memory

Prev PP

Next PP

From SL FPGA

PP-FPGA

firmware

Data

corr

ecti

on

LAV specific

QDR control

Data formatter and writer

Gbithandling

TTCrx & trigger

handling

Core services & monitoring

AUX boardcommunicatio

n

PP

0 P

P1 P

P2

PP

3

QDR

From TTCrx

SL-FPGAFirmware

Data

m

erg

er

Trig

ger

pri

mit

ive

merg

er

Trigger primitivehandling

To Gbit Eth

Prev TEL62

Next TEL62

LAV specific

PlansTry do run data acquisition with present tell1

firmware• Still need some study of the daq software

Start developing a stand alone version of the LAV firmware

• Start with the development of the data correction module

• Produce an independent test bench with proper simulated inputs

• Decide in which FPGA we want to set the module