Status of TIGER test activities

Michela GrecoOn behalf of Torino TIGER test group

CGEM IT

OutlineCGEM

TIGER electrical characterization

First tests with (planar and) cylindrical GEM

Radiation hardness tests

TIGER Front End cards design

M: Greco, CGEM meeting, March 2017

Torino Integrated Gem Electronics for ReadoutContact person: Manuel ROLO-INFN Torino

CGEM

Detector Spatial Resolution ≤130 m using TPC readout

TIGER ASIC Channels-UMC 110 nm technology

10 000 Channels 160 ASICs 40+40 FE cards

64 Channels per ASIC 2 ASICs per FE card

ASIC Requirements

1 – 50 fC Input Charge

signal duration 30-50 ns, 30-40 ns rising time, 10 ns falling time

up to 100 pF sensor capacitance

60 kHz event rate per channel (safety factor of 4 included)

4-5 ns time resolution

<10 mW/channel power consumption (analog+digital)

M: Greco, CGEM meeting, March 2017

Each channelCGEM

front-end Back-end+SEU protection

Time-based readoutsingle or double thresholdtime stamp on rising/falling edge (sub-50 ps binning quad-buffered TDC)charge measurement with Time-over-Threshold

Time and amplitude samplingtime stamp on rising edge (sub-50 ps binning quad-buffered TDC)Sample-and-Hold circuit for peak amplitude sampling:slow shaper output voltage is sampled and digitised with a 10-bit Wilkinson ADC

M: Greco, CGEM meeting, March 2017

First test setupCGEM

M: Greco, CGEM meeting, March 2017

FPGA controlM. Alekseev, M. Gertosio, R. Wheadon

Test boardM. Mignone

Test setups installedFirst data out from Setup #1 by end October 2016Setup #2 installed end November 2016

In summaryR/W Channel/Global configuration registers

Data TX and decoding

(dual-) TDC operation and fine calibrationquantisation error lower than 40 ps r.m.s. after calibration

Front-end performanceinternal calibration circuitryexternal charge injection (channel 63) Charge measurement: Time-over-threshold and Sample/HoldAmplifier baseline shifted, may limit linearity of S/H for big chargeOperation at higher temperature to recover BL shift

Baseline and threshold equalisation

(ongoing) Channel intrinsic noise wrt Cin

(ongoing) Linearity of charge measurements

CGEMCGEM

Characterization runs

M: Greco, CGEM meeting, March 2017

Scan over dynamic range sweeping internal test-pulse phaseCreate LUT with gain and offset correction all channelsAverage TDC quantisation error after calibration ~30 ps r.m.s.

CGEMCGEM

TDC operation

TBD: to quantify intrinsic jitter through test pulse injected to FE

M: Greco, CGEM meeting, March 2017

Injection of Q=8fC with internal test-pulse

Average gain above 10mV/fC (expected 11mV/fC from post-layout simulations)

Results after baseline equalisation: below 25 mV r.m.s. dispersion on the DC operating point(expected residual channel-to-channel dispersion (0.2 mV/fC r.m.s.)

CGEMCGEM

Gain dispersion

M: Greco, CGEM meeting, March 2017

Time –over-ThresholdSample-and Hold

Calibration of dynamic range with an external test-pulse generator

CGEMCGEM

Charge measurements (ongoing)

difficult to measure below 5 fC working on interference noise and grounding

M: Greco, CGEM meeting, March 2017

Noise evaluated for each input capacitance from a typ 50 points threshold -scan with fixed test-pulse (sigmoid fit). Measure repeated typ 100 times

CGEMCGEM

Noise measurements (ongoing)

PSRR, interference and grounding: under study

expecting 1700 e- from post-layout simulations at T=40C

M: Greco, CGEM meeting, March 2017

In summaryTime-based readout working properly

Charge measurement S/H seems to work Baseline dependence on temperatureroot cause: fragility of bias conditions of baseline holder circuit reproduced fairly well in simulationsminor revision activities started

Status of TIGER test activities

Moving towards integration with off-detector electronics

GEM testing for assessing sensitivity to grounding or system-level power integrity

What next

Main result

A second prototype is not needed, minor revisions on engineering run

CGEM

M: Greco, CGEM meeting, March 2017

Tests at Ferrara, 8-10 March

What next

Main result

CGEM

after first trials with planar gems…

M: Greco, CGEM meeting, March 2017

Tests at Ferrara, 8-10 March

What next

Main result

CGEM

TIGER interfaced to Layer 2

M: Greco, CGEM meeting, March 2017

Tests at Ferrara, 8-10 March

What next

Main result

CGEM

First signals acquired from exposition to 90-Sr

Tests at Ferrara, 8-10 March

What next

Main result

CGEM

First signals acquired from exposition to cosmic rays (night acquisition)

M: Greco, CGEM meeting, March 2017

In summary (November 2016)Test board irradiated to about 30 krad to test radiation damage on Voltage Regulators

n runs

Radiation hardness @ GIF++ (CERN)

SEU test request submitted for run at Legnaro Sirad facility (July 2017)Higher dose TID test on planning

What next

Analog power: TPS78601KTTT, TPS78601DCQDigital power: TPS78601DCQ, TPS78625DCQ

PRE (V) POST (V) %

Analog power

T1 1,232 1,222 0,992

T2 1,232 1,222 0,992

Digital power

T3 1,232 1,222 0,992

T4 2,505 2,488 0,993

Top

ASICinside

-0.7/0.8 %ok!

LT3021for Voltage reference

PRE (V) POST (V) %

Vref (T5) 0,835 0,867 1,038

Vblh (T7) 0,301 0,327 1,086

Vout_th 0,575 0,452 0,786

Vout_y 0,506 0,5 0,988

Bottom

we will have resistor voltage dividers

CGEM

M: Greco, CGEM meeting, March 2017

In summary for Layer 3

Board FE1 (56x40 mm2)2 ASICs, biasing and references, filtering ESD protection network for 122 channels 2 Analogue domain power regulators connector towards anode/connector towards FE2Routing done, finalization ongoing

Board FE2 (56x30 mm2)2 Digital domain power regulators 7 LVDS Buffersconnector towards FE1: power, signallingRouting done, finalization ongoing

TIGER Front-end cards designContact person: Marco Mignone-INFN Torino

Board FE1 (56x52.8 mm2) Board FE2 (56x67 mm2)

Layout to be started, Layer 3 FEs as reference

What next for Layer 1 and 2

CGEM

M: Greco, CGEM meeting, March 2017

Conclusions

TIGER electrical characterization ongoing:

a second prototype is not needed,

minor revisions in engineering run

TIGER Front End cards design: on schedule

area/volume constraints overcome for layer 3

Radiation hardness tests:

Good results from first tests on voltage regulators

SEU and TID tests planned

First tests with cylindrical GEM & first signals acquired!

data analysis ongoing and next months activity to be scheduled

CGEM

M: Greco, CGEM meeting, March 2017

Torino TIGER Test GroupFabio Cossio, Marco Mignone,

Manuel Rolo, Richard Wheadon Maxim Alexeev, Martina Gertosio

Michela Greco, Simonetta Marcello